Single-wafer battery protection circuit, battery charging and discharging circuit, and portable electronic device

Abstract

The present application provides a single-wafer battery protection circuit, a battery charging and discharging circuit, and a portable electronic device. The single-wafer battery protection circuit includes: a basic protection circuit, a clamping voltage circuit, a gate-substrate control circuit, and a charging and discharging control MOS transistor; one end of the source or drain of the charging and discharging control MOS transistor is connected to the battery, and the other end is connected to a charger or a load, and the gate and the substrate are connected to the gate-substrate control circuit; the basic protection circuit is coupled to the gate-substrate control circuit; the clamping voltage circuit includes voltage dividing resistors and N unidirectionally series-connected Zener diodes for clamping the supply voltage of the gate-substrate control circuit to prevent damage to the gate-substrate control circuit and the charging and discharging control MOS transistor. The present application can protect the battery protection circuit from being damaged by spike voltages and DC high voltages, and extend the service life of the charging and discharging circuit.

Description

Technical Field

[0001] This application relates to the technical field of battery charging and discharging, and particularly to a single-wafer battery protection circuit, a battery charging and discharging circuit, and a portable electronic device. Background Art

[0002] With the continuous increase in the functions of mobile terminals in recent years, the performance of mobile terminals has also been rapidly improved, which poses greater requirements for terminal batteries. Some application batteries need to be made very small, and some application batteries need to be made at low cost. However, traditional battery protection solutions usually occupy a large board area and are costly, and are increasingly unable to meet the new market demands.

[0003] Traditional battery protection solutions are achieved by discrete devices. A control circuit chip and a chip containing two N-type power MOS transistors are required. The control circuit chip controls the charging and discharging of the battery by controlling the gate voltages of these two power MOS transistors. The control circuit chip is made using CMOS technology, while the power MOS transistor chip is usually made using a vertical structure DMOS or UMOS transistor. Since CMOS and DMOS / UMOS are two completely different technologies, the control circuit chip and the two power MOS transistor chips usually come from two different suppliers and are two independent chips. In addition, the charging and discharging peripheral circuit of this discrete device solution requires two resistors and a capacitor.

[0004] In order to reduce the area of the above discrete device battery protection solution and lower the solution cost, in Chinese Patent CN103474967A, our company proposed a single-wafer battery protection circuit and a charging and discharging circuit. This single-wafer battery protection circuit integrates the control circuit chip, the two power MOS transistor chips, and an external resistor in a semiconductor substrate. The external charging and discharging circuit only requires one resistor and one capacitor. The single-wafer battery protection solution proposed by our company not only integrates the control circuit chip and the two power MOS transistor chips in a semiconductor substrate, but further, our company combines the two power MOS transistor structures in the traditional solution into one power MOS transistor to further reduce the solution area and lower the solution cost.

[0005] Currently, in order to minimize the circuit area and cost, 5V CMOS technology is usually selected for implementation. The breakdown voltage of the MOS transistor in 5V CMOS technology is between 8V and 12V. Since the battery protection circuit may generate a peak voltage of up to 16V and a DC high voltage during charging and discharging and production testing, the single-wafer battery protection circuit made using 5V CMOS technology will be broken down by the peak voltage or DC high voltage, resulting in damage to the single-wafer battery protection circuit.

[0006] An intuitive solution is to select a semiconductor process with a higher breakdown voltage to increase the withstand voltage of the single-wafer battery protection circuit, enabling it to withstand a 16V spike voltage and a high DC voltage. However, doing so will increase the number of process layers and greatly increase the area occupied by semiconductor devices on the chip, significantly driving up the cost of the protection circuit.

[0007] In view of this, the present application provides a single-wafer battery protection circuit, a battery charging and discharging circuit, and a portable electronic device to solve the problem of the single-wafer battery protection circuit being damaged by a high DC voltage and a spike voltage. Summary of the Invention

[0008] The objective of the present application is to provide a single-wafer battery protection circuit, a battery charging and discharging circuit, and a portable electronic device, which can protect the single-wafer battery protection circuit from being damaged by a high DC voltage and a spike voltage during the battery production test process and during charging and discharging use, and extend the service life of the charging and discharging circuit and the battery.

[0009] The technical solution provided by the present application is as follows:

[0010] The present application provides a single-wafer battery protection circuit, including: a basic protection circuit, a clamping circuit, a gate-substrate control circuit, and a charge-discharge control MOS transistor;

[0011] One end of the source and drain of the charge-discharge control MOS transistor is connected to the negative electrode of the battery, and the other end of the source and drain of the charge-discharge control MOS transistor is connected to the negative electrode of the charger or the load; the gate and substrate of the charge-discharge control MOS transistor are respectively connected to the gate-substrate control circuit;

[0012] The basic protection circuit is coupled to the gate-substrate control circuit;

[0013] The clamping circuit is used to clamp the supply voltage of the gate-substrate control circuit. The clamping circuit includes a voltage-dividing resistor and N zener diodes connected in series in one direction, where N≥1;

[0014] One end of the voltage-dividing resistor receives the supply voltage, the other end of the voltage-dividing resistor is connected to the negative electrode of the N zener diodes connected in series in one direction and the input end of the gate-substrate control circuit, and the positive electrode of the N zener diodes connected in series in one direction is coupled to the input end of the gate-substrate control circuit.

[0015] The battery protection circuit in this solution involves a large number of semiconductor devices, which may be damaged by spike voltages or DC high voltages during the battery production test process and during charging and discharging. For example, the breakdown voltage of a MOS transistor in a 5V CMOS process is between 8V and 12V. If the spike voltage generated during the production test process and during charging and discharging exceeds this breakdown voltage, the MOS transistor will be damaged. Generally, the intuitive solution is to increase the breakdown voltage of the MOS transistor, which will increase the number of process layers and the area of the MOS transistor on the chip, increasing the cost of the chip. In order to protect the device from being damaged by spike voltages or DC high voltages while ensuring the cost and chip area, this solution adds a clamping circuit to clamp the voltage within a certain range. Even if there are spike voltages or DC high voltages during the production test process and during charging and discharging, the clamping circuit will clamp the voltage within the safe voltage range to ensure that the protection circuit is not damaged.

[0016] During the production test process of the battery protection circuit, first, the battery protection chip and resistors and capacitors are made into a battery protection board, and then the battery protection board and the battery cell are connected together to form a battery with protection function. During the production test process of the battery, test equipment such as a protection board tester, an integrated tester, and a grading cabinet are often used. The protection board tester is used to detect whether the protection board is qualified, the integrated tester is used to detect whether the battery with protection function is qualified, and the grading cabinet is used to detect the capacity of the battery with protection function. These test equipment often generate spike voltages or DC high voltages up to 16V during the test process. Therefore, in the traditional battery protection solution, the breakdown voltages of the charging control MOS transistor Mc and the discharging control MOS transistor Md need to be made above 16V to prevent the battery with protection function from being broken down by the 16V spike voltage or DC high voltage during the production test process.

[0017] Theoretically, for a single-wafer battery protection circuit, the breakdown voltages of the source and drain of the charge and discharge control MOS transistors need to be made above 16V at the same time to ensure that the battery with protection function is not broken down by the spike voltage or DC high voltage up to 16V generated by the test equipment during the production test process. However, making the breakdown voltage of the charge and discharge control MOS transistor above 16V will result in high costs.

[0018] By using the clamping circuit of this application, the breakdown voltage of the charge and discharge control MOS transistor only needs to be 12V, which is the breakdown voltage of the traditional 5V CMOS process, to prevent the battery with protection function from being broken down by the spike voltage or DC high voltage up to 16V during the production test process and during charging and discharging.

[0019] This application also provides a battery charging circuit, including the above-mentioned single-wafer battery protection circuit, a charger, a battery, and an RC filter circuit, where:

[0020] One end of the first resistor is connected to the power supply voltage terminal of the basic protection circuit, and the other end of the first resistor is connected to the positive electrode of the battery;

[0021] One end of the first capacitor is connected to the power supply voltage terminal of the basic protection circuit, and the other end of the first capacitor is connected to the negative electrode of the battery;

[0022] The positive electrode of the charger is connected to the positive electrode of the battery to provide a charging voltage for the battery.

[0023] This application also provides a battery discharge circuit, including the above-mentioned single-wafer battery protection circuit, RC filter circuit, battery, and load, where:

[0024] One end of the first resistor is connected to the power supply voltage terminal of the basic protection circuit, and the other end of the first resistor is connected to the positive electrode of the battery;

[0025] One end of the first capacitor is connected to the power supply voltage terminal of the basic protection circuit, and the other end of the first capacitor is connected to the negative electrode of the battery;

[0026] The positive electrode of the battery is connected to the positive electrode of the load to provide power for the load, and the negative electrode of the load is connected to the negative electrode of the battery through a charge and discharge control MOS tube.

[0027] This application also provides a portable electronic device, including a single wafer and the above-mentioned single-wafer battery protection circuit. Among them, the portable electronic device can be a device with a lithium battery, such as a mobile phone, a toy, a power bank, an electronic cigarette, a true wireless stereo (TWS) earphone, etc.

[0028] Through a single-wafer battery protection circuit, a charge and discharge circuit, and a portable electronic device provided by this application, at least one of the following beneficial effects can be achieved:

[0029] In this application, by using a clamping circuit, the voltage between the power supply voltage GVDD of the gate-substrate control circuit and the VSS terminal is clamped within a preset range. The voltage withstand of the battery protection circuit chip during production testing and during charge and discharge use is improved, preventing damage to the devices in the battery protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above characteristics, technical features, advantages, and their implementation manners of a single-wafer battery protection circuit and a charge and discharge circuit with improved anti-spike voltage ability will be further described below in a clear and understandable manner in conjunction with the drawings in the preferred embodiments.

[0031] Figure 1 It is a structural diagram of the charging and discharging circuits of a traditional discrete device battery protection circuit;

[0032] Figure 2 is the charging and discharging circuit structure diagram of the existing single-wafer battery protection circuit;

[0033] Figure 3 is a circuit diagram of the gate-substrate control circuit in the existing single-wafer battery protection solution technology;

[0034] Figure 4 is an embodiment of the single-wafer battery protection circuit and the charging and discharging circuit structure diagram for improving the anti-spike voltage ability in the present application;

[0035] Figure 5 is Figure 4 the structure diagram of the basic protection circuit in;

[0036] Figure 6 is Figure 4 the circuit diagram of the over-temperature protection circuit in;

[0037] Figure 7 is Figure 4 a circuit diagram of the gate-substrate control circuit in;

[0038] Figure 8 is Figure 4 another circuit diagram of the gate-substrate control circuit in;

[0039] Figure 9 is a circuit diagram of a clamping voltage circuit in an embodiment of the present application;

[0040] Figure 10 is another circuit diagram of the clamping voltage circuit in an embodiment of the present application;

[0041] Figure 11 is another circuit diagram of the clamping voltage circuit in an embodiment of the present application;

[0042] Figure 12 is another circuit diagram of the clamping voltage circuit in an embodiment of the present application. Detailed implementation manners

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the specific implementation manners of the present application will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings, and other implementation manners can also be obtained.

[0044] To simplify the drawings, only the parts relevant to this application are schematically shown in each figure, and they do not represent the actual structure of the product as a whole. Additionally, to simplify the drawings for easier understanding, for components with the same structure or function in some figures, only one of them is schematically illustrated, or only one of them is labeled. In this article, "one" not only means "only this one" but also can mean "more than one" situation.

[0045] Figure 1 The charging and discharging circuit is for the traditional discrete device battery protection solution. The control circuit A controls the charging and discharging of the battery by controlling the gate voltages of two power MOS transistors (Mc and Md). The control circuit A is made using CMOS technology, while the power MOS transistors (Mc and Md) are usually made using a vertical structure DMOS or UMOS transistor. Since CMOS and DMOS / UMOS are two completely different technologies, the control circuit A and the two power MOS transistors (Mc and Md) usually come from two different suppliers and are two independent chips, and the peripheral circuit requires two resistors R0 and Rvm and a capacitor C0.

[0046] Figure 2 It is the internal block diagram and charging and discharging circuit of the battery protection circuit in the single-wafer battery protection solution technology. When the battery protection circuit enters overcharge voltage protection, overcharge current protection, or overcharge temperature protection, the charging path of the battery protection circuit is turned off, and the voltage of the charger is completely provided by the external charging circuit. The basic protection circuit, over-temperature protection circuit, logic control unit I12, and logic control unit I13 inside the battery protection circuit are powered by the battery and do not have high voltage, so the circuit will not be damaged by high voltage. However, the supply voltage of the gate-substrate control circuit during charging protection is the charger voltage. During the production test process and the charger connection process, this voltage may reach a high voltage of 16V, which will damage the gate-substrate control circuit and may also damage the charging and discharging control MOS transistor M0.

[0047] Figure 3 It is the circuit diagram of the gate-substrate control circuit in the existing single-wafer battery protection solution technology.

[0048] Refer to Figure 3 As shown, it includes a gate control circuit that outputs VGATE and a substrate control circuit that outputs VSUB. Since the low-level VSS voltage and VGND voltage of the gate control circuit are not exactly the same potential, the low potential of the VOD voltage, VOC voltage, and VCHOC1 voltage input to the gate control circuit is the VGND voltage and needs to be converted to the VSS voltage. The VOD voltage, VOC voltage, and VCHOC1 voltage all require a level conversion circuit. Here, the level conversion circuit of the VOD voltage is taken as an example for illustration.

[0049] MOS transistors M7, M8, M9, M10 and logic control unit I6 complete the low-level conversion of the VOD voltage. When the VOD voltage is at the high level VDD, transistor M7 is cut off and transistor M8 is turned on, and the VODP voltage is at the high level VDD; when the VOD voltage is at the low level VGND, transistor M7 is turned on and transistor M8 is cut off, and the VODP voltage is at the low level VSS, completing the conversion from the VGND level to the VSS level. Similarly, the VOC voltage is converted to the VOCP voltage, the VCHOC1 voltage is converted to the VCHOC1P voltage, and the VCHOC1N voltage. When both the VODP voltage and the VOCP voltage are at the high level, the output at the VGATE terminal is at the high level VDD. When either the VODP voltage or the VOCP voltage is at the low level VSS, the output at the VGATE terminal is at the low level VSS. When VOCP is at the high level, VGOC is at the low level, VGOCB is at the high level, MOS transistor M1 is turned on, MOS transistor M2 is cut off, and the output VSUB voltage is equal to the VGND voltage; when VOCP is at the low level, VGOC is at the high level, VGOCB is at the low level, MOS transistor M1 is cut off, MOS transistor M2 is turned on, and the output VSUB voltage is equal to the VM voltage. When the VCHOC1 voltage is at the high level, the VCHOC1P voltage is at the high level and the VCHOC1N voltage is at the low level, MOS transistors M19 are turned on and MOS transistors M20 are cut off, and the VSS voltage is equal to the VGND voltage; when the VCHOC1 voltage is at the low level, the VCHOC1P voltage is at the low level and the VCHOC1N voltage is at the high level, MOS transistors M19 are cut off and MOS transistors M20 are turned on, and the VSS voltage is equal to the VM voltage.

[0050] In the above description, when the VCHOC1P voltage is at the low level, the VSS voltage is equal to the VM voltage, then the voltage difference between the VDD voltage and the VSS voltage is the voltage difference between the VDD voltage and the VM voltage. During the production test process and charge and discharge use, a peak voltage or DC voltage of up to 16V may be generated between VDD and VM, and the breakdown voltage of the 5V CMOS process MOS transistor is between 8V and 12V, which is lower than the generated peak voltage or DC voltage, so the existing gate-substrate control circuit will be damaged or broken down.

[0051] Based on the above analysis conclusion, the present application provides a new battery protection circuit. Figure 4 It is a structural diagram of a single-wafer battery protection circuit and a charge and discharge circuit in an embodiment of the present application. Figure 5 It is Figure 4 a structural diagram of the basic protection circuit in Figure 6 It is Figure 4 a circuit diagram of the overtemperature protection circuit in Figure 7 It is Figure 4 a circuit diagram of a gate-substrate control circuit in Figure 8 It is Figure 4Another circuit diagram of the gate-substrate control circuit in Figure 7 , Figure 8 As shown, the gate-substrate control circuit includes a gate control part and a substrate control part, and the gate control part and the substrate control part have a common circuit. Refer to Figures 4 to 7 As shown, relative to Figure 2 the battery protection circuit in Figure 3 the gate-substrate control circuit in Figure 4 When the battery protection circuit enters overcharge voltage protection, overcharge current protection or overcharge temperature protection, the charging path of the battery protection circuit is turned off, and the voltage of the charger is completely provided by the external charging circuit. Refer to Figure 7 As shown, the positive power supply terminal of the improved gate-substrate control circuit is the output voltage GVDD of the clamping circuit. When the battery protection circuit enters overcharge voltage protection, overcharge current protection or overcharge temperature protection, the voltage of the negative power supply terminal VSS is VM, and in other cases, the voltage of the negative power supply terminal VSS is VGND. The supply voltage of the gate-substrate control circuit is the voltage between GVDD and VM or the voltage between GVDD and VGND, and this supply voltage is clamped and lower than the breakdown voltage of all MOS transistors inside the gate-substrate control circuit, so the gate-substrate control circuit will not be damaged.

[0052] Refer to Figure 4 As shown, the battery charging and discharging circuit 2 includes a battery, an RC filter circuit 3, a single-chip battery protection circuit 1, a charger and a load. The battery is connected in parallel with the RC filter circuit 3, the charger and the load; among them, the single-chip battery protection circuit 1, the charger, the battery and the RC filter circuit 3 form a battery charging circuit; the single-chip battery protection circuit 1, the RC filter circuit 3, the battery and the load form a battery discharging circuit.

[0053] The battery charging circuit includes a single-chip battery protection circuit 1, a charger, a battery and an RC filter circuit 3, where: one end of the first resistor R0 in the RC filter circuit 3 is connected to the power supply voltage VDD terminal of the basic protection circuit 10, and the other end of the first resistor R0 is connected to the positive electrode of the battery; one end of the first capacitor C0 in the RC filter circuit 3 is connected to the power supply voltage VDD terminal of the basic protection circuit 10, and the other end of the first capacitor C0 is connected to the negative electrode of the battery; the positive electrode of the charger is connected to the positive electrode of the battery during charging to provide a charging voltage for the battery, and the negative electrode of the charger is connected to the negative electrode of the battery through the charge and discharge control MOS transistor M0.

[0054] The battery discharge circuit includes a single-wafer battery protection circuit 1, an RC filter circuit 3, a battery, and a load, where: One end of the first resistor R0 in the RC filter circuit 3 is connected to the power supply voltage VDD terminal of the basic protection circuit 10, and the other end of the first resistor R0 is connected to the positive electrode of the battery; One end of the first capacitor C0 in the RC filter circuit 3 is connected to the power supply voltage VDD terminal of the basic protection circuit 10, and the other end of the first capacitor C0 is connected to the negative electrode of the battery; The positive electrode of the battery is connected to one end of the load to provide power to the load, and the negative electrode of the battery is connected to the other end of the load through the charge and discharge control MOS transistor M0.

[0055] The single-wafer battery protection circuit 1 includes: a basic protection circuit 10, a clamping voltage circuit 11, a gate-substrate control circuit 12, an over-temperature protection circuit 13, a first logic control unit I12, a second logic control unit I13, and a charge and discharge control MOS transistor M0; The power supply voltage VDD input terminal of the basic protection circuit 10 is connected between the first resistor R0 and the first capacitor C0; The output terminal of the basic protection circuit 10 is coupled to the gate-substrate control circuit 12. The input terminal of the over-temperature protection circuit 13 is connected to the basic protection circuit 10; The output terminal of the basic protection circuit 10 is respectively coupled to the output terminal of the over-temperature protection circuit 13 through the first logic control unit I12 and the second logic control unit I13 to the gate-substrate control circuit 12; The clamping voltage circuit 11 is coupled to the power supply voltage VDD, and the clamping voltage circuit 11 is coupled to the gate-substrate control circuit 12. One end of the source and drain of the charge and discharge control MOS transistor M0 is connected to the negative electrode of the battery, and the other end of the source and drain of the charge and discharge control MOS transistor M0 is connected to the negative electrode of the charger or the load. For example, the source of the charge and discharge control MOS transistor M0 is connected to the negative electrode of the charger, and the drain of the charge and discharge control MOS transistor M0 is connected to the negative electrode of the battery; The gate and substrate of the charge and discharge control MOS transistor M0 are respectively connected to the gate-substrate control circuit 12; The source of the charge and discharge control MOS transistor M0 is connected to the basic protection circuit 10 and the gate-substrate control circuit 12, and the drain of the charge and discharge control MOS transistor M0 is connected to the basic protection circuit 10 and the gate-substrate control circuit 12.

[0056] The single-wafer battery protection circuit 1 of this embodiment detects the charge and discharge conditions of the battery through the basic protection circuit 10, sends a control signal to the gate-substrate control circuit 12, and enables the gate-substrate control circuit 12 to control the conduction condition of the charge and discharge control MOS transistor M0 according to the control signal, thereby controlling the charge and discharge of the battery. The single-wafer battery protection circuit 1 detects the temperature of the integrated chip of the battery protection circuit through the over-temperature protection circuit 13, and the over-temperature protection circuit 13 and the basic protection circuit 10 jointly control the conduction of the gate-substrate control circuit 12. The single-wafer battery protection circuit 1 clamps the power supply voltage of the gate-substrate control circuit 12 through the clamping voltage circuit 11 to ensure that the single-wafer battery protection circuit 1 is not damaged.

[0057] AsFigure 9 As shown, it is a circuit diagram of the clamping circuit 11 in an embodiment of the present application. The clamping circuit 11 includes a voltage-dividing resistor R5 and N zener diodes connected in series in one direction, where N≥1; one end of the voltage-dividing resistor R5 receives the supply voltage VDD, and the other end of the voltage-dividing resistor R5 is connected to the negative electrode and the input end GVDD of the gate substrate control circuit 12 of the N zener diodes connected in series in one direction, and the positive electrodes of the N zener diodes are coupled to the input end VSS of the gate substrate control circuit 12.

[0058] The principle that the clamping circuit 11 of this embodiment can clamp the voltage between the input voltages GVDD and VSS of the gate substrate control circuit 12 within a preset range is as follows: the resistance of the PN junction of the zener diode is extremely low in the reverse breakdown state. Therefore, when the zener diode is conducting, the voltage between the input voltages GVDD and VSS is equal to the breakdown voltage of the zener diode; when the zener diode is not conducting, the input voltage GVDD is almost equal to the supply voltage VDD.

[0059] When the voltage between VDD and VSS is lower than the conduction voltage of the zener diode, the input voltage GVDD is equal to the supply voltage VDD; when the voltage between VDD and VSS is higher than the conduction voltage of the zener diode, the highest output voltage between the input voltage GVDD and VSS is the zener voltage. Generally, the conduction voltage of the zener diode inside the integrated circuit is between 5.5V and 6.5V. If the voltage between VDD and VSS continues to increase, one or more zener diodes are connected in series for clamping, and the zener voltage is stabilized at the conduction voltage of the zener diode, and the remaining voltage drops on the voltage-dividing resistor R5. The resistance value of the voltage-dividing resistor R5 is greater than or equal to 0, and there is no problem with a voltage drop of dozens of volts on the voltage-dividing resistor R5; therefore, the withstand voltage between the supply voltage VDD and VSS can be as high as dozens of volts without damaging the clamping circuit 11. VSS is connected to the low potential of the gate substrate circuit 12. The voltage between VDD and VSS is clamped at the voltage value of one or more zener diodes. The supply voltage of the gate substrate control circuit 12 is the voltage between GVDD and VSS, and the maximum value is the conduction voltage of the zener diode. It is lower than the breakdown voltage of the MOS transistor M0 between 8V and 12V, so the gate substrate control circuit 12 will not be damaged.

[0060] As Figure 10 shown, it is another circuit diagram of the clamping circuit 11 in an embodiment of the present application, which is the same as Figure 9The differences are as follows: The clamping circuit 11 includes a voltage-dividing resistor R5 and N diodes connected in series in a single direction, where N≥1; one end of the voltage-dividing resistor R5 receives the supply voltage VDD, and the other end of the voltage-dividing resistor R5 is connected to the positive electrodes and the input terminal GVDD of the gate substrate control circuit 12 of the N diodes connected in series in a single direction, and the negative electrodes of the N diodes connected in series in a single direction are coupled to the input terminal VSS of the gate substrate control circuit 12.

[0061] The principle that the clamping circuit 11 in this embodiment can clamp the voltage between the input voltages GVDD and VSS of the gate substrate control circuit 12 within a preset range by connecting multiple diodes in series is as follows: Utilizing the slow-changing characteristic of the forward conduction voltage of the diode, when the diode conducts, the voltage between the input voltages GVDD and VSS is equal to the sum of the conduction voltages of the multiple diodes; when the diode does not conduct, the input voltage GVDD is almost equal to the supply voltage VDD.

[0062] As Figure 11 shown, it is another circuit diagram of the clamping circuit 11 in the embodiment of the present application. Different from Figure 9 this, the differences are as follows: The clamping circuit 11 includes a voltage-dividing resistor R5 and N NMOS transistors connected in series, where N≥1; one end of the voltage-dividing resistor R5 receives the supply voltage VDD, and the other end of the voltage-dividing resistor R5 is connected to one end of the N NMOS transistors and the input terminal GVDD of the gate substrate control circuit 12, and the other ends of the N NMOS transistors are coupled to the input terminal VSS of the gate substrate control circuit 12.

[0063] The principle that the clamping circuit 11 in this embodiment can clamp the voltage between the input voltages GVDD and VSS of the gate substrate control circuit 12 within a preset range by connecting multiple NMOS transistors in series is as follows: The source and gate of the NMOS transistor are shorted together, and the NMOS transistor is equivalent to a diode, and the forward conduction voltage is the threshold voltage Vthn of the NMOS transistor. Therefore, when the NMOS transistor conducts, the input voltage GVDD is equal to the sum of the threshold voltages of the multiple NMOS transistors; when the NMOS transistor does not conduct, the input voltage GVDD is almost equal to the supply voltage VDD.

[0064] As Figure 12 shown, it is another circuit diagram of the clamping circuit 11 in the embodiment of the present application. Different from Figure 9 this, the differences are as follows: The clamping circuit 11 includes a voltage-dividing resistor R5 and N PMOS transistors connected in series, where N≥1; one end of the voltage-dividing resistor R5 receives the supply voltage VDD, and the other end of the voltage-dividing resistor R5 is connected to one end of the N PMOS transistors and the input terminal GVDD of the gate substrate control circuit 12, and the other ends of the N PMOS transistors are coupled to the input terminal VSS of the gate substrate circuit 12.

[0065] The principle that the clamping circuit 11 in this embodiment can clamp the voltage between the input voltage GVDD of the gate-substrate control circuit 12 and VSS within a preset range by connecting multiple PMOS in series is the same as that of connecting multiple NMOS in series to clamp the voltage between GVDD and VSS within a preset range.

[0066] As Figure 5 shown, it is Figure 4 the circuit diagram of the basic protection circuit 10 in the single-wafer battery protection circuit 1, including: a reference circuit, a discharge overcurrent comparator, a discharge short-circuit comparator, a charge overcurrent comparator, an over-discharge voltage comparator, an overcharge voltage comparator, a delay circuit, a charge-discharge detection circuit, a second resistor R1, a third resistor R2, a fourth resistor R3, a fifth resistor R4, a sixth logic control unit I0, a seventh logic control unit I1, an eighth logic control unit I2, a ninth logic control unit I3, and a tenth logic control unit I4.

[0067] The output terminal of the reference circuit is respectively connected to the first input terminal (positive input terminal) of the discharge overcurrent comparator, the first input terminal (positive input terminal) of the discharge short-circuit comparator, the second input terminal (negative input terminal) of the charge overcurrent comparator, the second input terminal (negative input terminal) of the over-discharge voltage comparator, and the first input terminal (positive input terminal) of the overcharge voltage comparator; the second input terminal (negative input terminal) of the discharge overcurrent comparator, the second input terminal (negative input terminal) of the discharge short-circuit comparator, the first input terminal (positive input terminal) of the charge overcurrent comparator, and the second input terminal (negative input terminal) of the charge-discharge detection circuit are respectively connected to the source or drain of the charge-discharge control MOS transistor M0 through the fifth resistor R4; one end of the second resistor R1 is connected to the supply voltage VDD, and the other end of the second resistor R1 is connected to the first input terminal (positive input terminal) of the over-discharge voltage comparator and one end of the third resistor R2; the other end of the third resistor R2 is connected to the second input terminal (negative input terminal) of the overcharge voltage comparator and one end of the fourth resistor R3, and the other end of the fourth resistor R3 is connected to the first input terminal (positive input terminal) of the charge-discharge detection circuit and grounded; the output terminals of the discharge overcurrent comparator, the discharge short-circuit comparator, the charge overcurrent comparator, the over-discharge voltage comparator, and the overcharge voltage comparator are respectively connected to the delay circuit; the output terminal of the charge overcurrent comparator is respectively connected to the delay circuit and the gate-substrate control circuit 12; the output terminal of the charge-discharge detection circuit is connected to the input terminal of the over-temperature comparison circuit 13.

[0068] The output terminal of the delay circuit is connected to the first input terminal of the eighth logic control unit I2 through the sixth logic control unit I0, VDOC1, VDSHORT, and VDODV; the output terminal of the charge and discharge detection circuit is connected to the second input terminal of the eighth logic control unit I2; the output terminal of the eighth logic control unit I2 is coupled to the gate-substrate control circuit 12; the output terminals VDCHOC and VDOCV of the delay circuit are connected to the first input terminal of the ninth logic control unit I3 through the seventh logic control unit I1; the output terminal of the charge and discharge detection circuit is connected to the input terminal of the tenth logic control unit I4; the output terminal of the tenth logic control unit I4 is connected to the second input terminal of the ninth logic control unit I3; the output terminal of the ninth logic control unit I3 is coupled to the gate-substrate control circuit 12.

[0069] Among them, the reference circuit is used to generate the positive input signal VOC1 of the discharge overcurrent comparator, the positive input signal VSHORT of the discharge short-circuit comparator, the negative input signal VCHOC of the charge overcurrent comparator, the reference output voltages VPN, VOTP, the positive input signal VOCV of the overcharge voltage comparator, and the negative input signal VODV of the over-discharge voltage comparator.

[0070] Based on the comparison result of the positive input signal VOC1 and the negative input signal virtual ground voltage VM1, when VOC1 is greater than VM1, the discharge overcurrent comparator outputs a high level VDD, and when VOC1 is lower than VM1, it outputs a low level VGND.

[0071] Based on the comparison result of the positive input signal VSHORT and the negative input signal virtual ground voltage VM1, when VSHORT is greater than VM1, the discharge short-circuit comparator outputs a high level VDD, and when VSHORT is lower than VM1, it outputs a low level VGND.

[0072] Based on the comparison result of the positive input signal virtual ground voltage VM1 and the negative input signal VCHOC, when VM1 is greater than VCHOC, the charge overcurrent comparator outputs a high level VDD, and when VM1 is lower than VCHOC, it outputs a low level VGND.

[0073] Based on the comparison result of the positive input signal VOCV and the negative input signal VROCV after the supply voltage VDD is divided by a resistor, the overcharge voltage comparator outputs a high level VDD or a low level VGND.

[0074] Based on the comparison result of the positive input signal VRODV after the supply voltage VDD is divided by a resistor and the negative input signal VODV, the over-discharge voltage comparator outputs a high level VDD or a low level VGND.

[0075] Based on the comparison result of the magnitudes of the positive input signal VGND and the negative input signal virtual ground voltage VM1, the charge-discharge detection circuit outputs a high level VDD or a low level VGND. When the positive input signal VGND is greater than the negative input signal virtual ground voltage VM1, a high level VDD is output. When the positive input signal VGND is lower than the negative input signal virtual ground voltage VM1, a low level VGND is output.

[0076] The delay circuit is used to delay the output signals VOC1P of the discharge overcurrent comparator, VSHORTP of the discharge short-circuit comparator, VCHOC1 of the charge overcurrent comparator, VODVP of the over-discharge voltage comparator, and VOCVP of the overcharge voltage comparator, and outputs VDOC1, VDSHORT, VDCHOC, VDODV, and VDOCV correspondingly after the delay. VDOC1 is the signal after the delay of VOC1P, VDSHORT is the signal after the delay of VSHORTP, VDCHOC is the signal after the delay of VCHOC1, VDODV is the signal after the delay of VODVP, and VDOCV is the signal after the delay of VOCVP.

[0077] When VDOC1, VDSHORT, and VDODV are all high, the output signal VOD3 of the sixth logic control unit I0 outputs a high level VDD. When at least one of VDOC1, VDSHORT, and VDODV is low, the output signal VOD3 of the sixth logic control unit I0 outputs a low level VGND.

[0078] When VDCHOC and VDOCV are both high, the output signal VOC3 of the seventh logic control unit I1 outputs a high level VDD. When at least one of VDCHOC and VDOCV is low, the output signal VOC3 of the seventh logic control unit I1 outputs a low level VGND.

[0079] When at least one of the output signal VOD3 of the sixth logic control unit I0 and the output signal VCHP of the charge-discharge detection circuit is high, the output signal VOD2 of the eighth logic control unit I2 outputs a high level VDD. When both VOD3 and VCHP are low, VOD2 outputs a low level VGND.

[0080] When at least one of the output signal VOC3 of the seventh logic control unit I1 and the output signal VCHN of the tenth logic control unit I4 is high, the output signal VOC2 of the ninth logic control unit I3 outputs a high level VDD. When both the output signal VOC3 of the seventh logic control unit I1 and the output signal VCHN of the tenth logic control unit I4 are low, the output signal VOC2 of the ninth logic control unit I3 outputs a low level VGND.

[0081] The basic protection circuit 10 of this embodiment detects the charging and discharging conditions of the battery, sends a control signal to the gate-substrate control circuit 12, and enables the gate-substrate control circuit 12 to control the conduction of the charging and discharging control MOS transistor M0 according to the control signal, thereby controlling the charging and discharging of the battery.

[0082] As Figure 6 shown, it is Figure 4 the circuit of the over-temperature protection circuit 13 in the single-wafer battery protection circuit 1.

[0083] The over-temperature protection circuit 13 includes an over-temperature comparator, a third logic control unit I14, a fourth logic control unit I15, and a fifth logic control unit I16.

[0084] The input terminal of the over-temperature comparator is connected to the basic protection circuit 10. The output terminal of the over-temperature comparison circuit 13 is respectively connected to the first input terminal of the fourth logic control unit I15 and the second input terminal of the fifth logic unit I16. The second input terminal of the fourth logic control unit I15 is connected to the output terminal of the third logic control unit I14. The first input terminal of the fifth logic control unit I16 and the input terminal of the third logic control unit I14 are connected to the basic protection circuit 10. The output terminals of the fourth logic control unit I15 and the fifth logic control unit I16 are coupled to the gate-substrate control circuit 12. Specifically, the output terminal VCHOTP of the fourth logic control unit I15 is coupled to the gate-substrate control circuit 12 through the second logic control unit I13, and the output terminal VDISOTP of the fifth logic control unit I16 is coupled to the gate-substrate control circuit 12 through the first logic control unit.

[0085] Based on the comparison result of the positive input terminal voltage VPN and the negative input terminal voltage VOTP, the over-temperature comparator outputs a high level when the positive input terminal voltage VPN is greater than the negative input terminal voltage VOTP, and outputs a low level when the positive input terminal voltage VPN is less than the negative input terminal voltage VOTP.

[0086] When at least one of the output voltage VOTPP of the over-temperature comparator and the output voltage VCHN1 of the third logic control unit I14 is high, the output voltage VCHOTP of the fourth logic control unit I15 outputs a high level VDD. When both the output voltage VOTPP of the over-temperature comparator and the output voltage VCHN1 of the third logic control unit I14 are low, the output voltage VCHOTP of the fourth logic control unit I15 outputs low.

[0087] When at least one of the output voltage VOTPP of the overtemperature comparator and the input voltage VCHP of the third logic control unit I14 is high, the output voltage VDISOTP of the fifth logic control unit I16 outputs a high level VDD. When both the output voltage VOTPP of the overtemperature comparator and the input voltage VCHP of the third logic control unit I14 are low, the output voltage VDISOTP of the fifth logic control unit I16 outputs low.

[0088] The overtemperature protection circuit 13 of this embodiment is used to detect the temperature of the integrated chip of the single-wafer battery protection circuit 1, and jointly control the conduction of the gate-substrate control circuit 12 with the basic protection circuit 10.

[0089] As Figure 7 shown, it is Figure 4 a circuit schematic diagram of the gate-substrate control circuit 12 in the single-wafer battery protection circuit 1.

[0090] Relative Figure 3 to the gate-substrate control circuit, the difference is that the gate-substrate control circuit 12 further includes resistors R11, R12, R13, R14, R15, R16 and MOS transistors M21, M22, M23, M24, M25, M26.

[0091] The gate-substrate control circuit 12 includes a gate control part and a substrate control part, and the gate control part and the substrate control part have a common circuit;

[0092] The gate control part includes resistors R11, R12, R13, R14, R15, R16 and MOS transistors M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, M23, M24, M25, M26 and logic control units I6, I7, I8, I9;

[0093] One end of resistor R11 is connected to the output voltage VOD of the first logic control unit I12; the other end of resistor R11 is connected to the gate of MOS transistor M7, the input terminal of logic control unit I6, and the drain of MOS transistor M21; the source of MOS transistor M21 is connected to the gate of MOS transistor M21, the substrate of MOS transistor M21, the output terminal GVDD of the clamping circuit 11, the substrate of MOS transistor M7, the source of MOS transistor M7, the substrate of MOS transistor M8, the source of MOS transistor M8, the gate of MOS transistor M22, the substrate of MOS transistor M22, and the source of MOS transistor M22; one end of resistor R12 is connected to the drain of MOS transistor M22 and the gate of MOS transistor M8; the other end of resistor R12 is connected to the output terminal of logic control unit I6; the drain of MOS transistor M7 is connected to the drain of MOS transistor M9 and the gate of MOS transistor M10; the drain of MOS transistor M8 is connected to the gate of MOS transistor M9, the drain of MOS transistor M10, and the first input terminal of logic control unit I9; the output terminal of logic control unit I9 is connected to the gate of the charge and discharge control MOS transistor M0; the source of MOS transistor M9, the substrate of MOS transistor M9, the source of MOS transistor M10, the substrate of MOS transistor M10, the source of MOS transistor M13, the substrate of MOS transistor M13, the source of MOS transistor M14, the substrate of MOS transistor M14, the source of MOS transistor M17, the substrate of MOS transistor M17, the source of MOS transistor M18, and the substrate of MOS transistor M18 are connected together and connected to the source of MOS transistor M19, the substrate of MOS transistor M19, the source of MOS transistor M20, and the substrate of MOS transistor M20; the drain of MOS transistor M19 is connected to one end of the source or drain of the charge and discharge control MOS transistor M0 and the negative electrode of the battery; the drain of MOS transistor M20 is connected to the other end of the source or drain of the charge and discharge control MOS transistor M0 and the negative electrode of the charger.

[0094] One end of resistor R13 is connected to the output voltage VOC of the second logic control unit I13; the other end of resistor R13 is connected to the gate of MOS transistor M11, the input terminal of logic control unit I7, and the drain of MOS transistor M23; the source of MOS transistor M23 is connected to the gate of MOS transistor M23, the substrate of MOS transistor M23, the source of MOS transistor M11, the substrate of MOS transistor M11, the output terminal GVDD of the clamping circuit 11, the substrate of MOS transistor M12, the source of MOS transistor M12, the gate of MOS transistor M24, the source of MOS transistor M24, and the substrate of MOS transistor M24; one end of resistor R14 is connected to the drain of MOS transistor M24 and the gate of MOS transistor M12; the other end of resistor R14 is connected to the output terminal of logic control unit I7; the drain of MOS transistor M11 is connected to the drain of MOS transistor M13 and the gate of MOS transistor M14; the drain of MOS transistor M12 is connected to the gate of MOS transistor M13, the drain of MOS transistor M14, the second input terminal of logic control unit I9, and the input terminal of logic control unit I10.

[0095] One end of resistor R15 is connected to the output voltage VCHOC1 of the basic protection circuit 10; the other end of resistor R15 is connected to the gate of MOS transistor M15, the input terminal of logic control unit I8, and the drain of MOS transistor M25; the source of MOS transistor M25 is connected to the gate of MOS transistor M25, the substrate of MOS transistor M25, the source of MOS transistor M15, the substrate of MOS transistor M15, the output terminal GVDD of the clamping circuit 11, the substrate of MOS transistor M16, the source of MOS transistor M16, the gate of MOS transistor M26, the source of MOS transistor M26, and the substrate of MOS transistor M26; one end of resistor R16 is connected to the drain of MOS transistor M26 and the gate of MOS transistor M16; the other end of resistor R16 is connected to the output terminal of logic control unit I8; the drain of MOS transistor M15 is connected to the drain of MOS transistor M17, the gate of MOS transistor M18, and the gate of MOS transistor M20; the drain of MOS transistor M16 is connected to the gate of MOS transistor M17, the drain of MOS transistor M18, and the gate of MOS transistor M19.

[0096] The substrate control part includes resistors R13, R14, R15, R16 and MOS transistors M1, M2, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M23, M24, M25, M26 and logic control units I7, I8, I10, I11;

[0097] The input terminal of logic control unit I10 is connected to the second input terminal of logic control unit I9, the drain of MOS transistor M12, the gate of MOS transistor M13, and the drain of MOS transistor M14; the output terminal of logic control unit I10 is connected to the input terminal of logic control unit I11 and the gate of MOS transistor M2; the output terminal of logic control unit I11 is connected to the gate of MOS transistor M1; the drain of MOS transistor M1 is connected to the drain of MOS transistor M19 and one end of the source or drain of charge and discharge control MOS transistor M0 and the negative electrode of the battery; the source of MOS transistor M1, the substrate of MOS transistor M1, the source of MOS transistor M2, and the substrate of MOS transistor M2 are connected together and connected to the substrate of charge and discharge control MOS transistor M0; the drain of MOS transistor M2 is connected to the drain of MOS transistor M20, the other end of the source or drain of charge and discharge control MOS transistor M0, and the negative electrode of the charger.

[0098] The functions of adding resistors and MOS transistors are illustrated below with R11, R12, M21, and M22: Since the clamping circuit 11 is added, the positive power supply voltage of the gate-substrate control circuit 12 is the output potential GVDD of the clamping circuit 11, and the input voltage VOD may be the high level VDD or the low level VGND. The voltage between the input voltage GVDD and the power supply voltage VDD, and the voltage between the input voltage GVDD and the power supply voltage VGND may exceed the gate breakdown voltage of MOS transistors M7 and M8, thereby damaging MOS transistors M7 and M8. After adding R11, M21, R12, and M22, the maximum voltage from the GATE of M7 and M8 to GVDD is the parasitic diode voltage of M21 and M22, and this parasitic diode voltage will not damage the MOS transistors. Similarly, R13, R14, M23, and M24 protect M11 and M12 from damage; R15, R16, M25, and M26 protect M15 and M16 from damage.

[0099] The gate-substrate control circuit 12 of this embodiment includes a gate control part and a substrate control part; the gate control part is connected to the gate of the charge-discharge control MOS transistor M0, and the substrate control part is connected to the substrate of the charge-discharge control MOS transistor M0; when the battery is charging and discharging, the gate control part outputs a gate control response signal according to the control signal to control the gate voltage of the charge-discharge control MOS transistor M0, and the substrate control part outputs a substrate control response signal according to the control signal to control the substrate voltage of the charge-discharge control MOS transistor M0, thereby controlling the conduction state of the charge-discharge control MOS transistor M0.

[0100] As Figure 8 shown, compared with Figure 3 the gate-substrate control circuit, the difference is that the gate-substrate control circuit 12 further includes resistors R11, R12, R13, R14, R15, R16 and diodes D3, D4, D5, D6, D7, D8 to achieve Figure 9 the same functions as in

[0101] The gate-substrate control circuit 12 includes a gate control part and a substrate control part, and the gate control part and the substrate control part have a common circuit;

[0102] The gate control part includes resistors R11, R12, R13, R14, R15, R16 and MOS transistors M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20 and diodes D3, D4, D5, D6, D7, D8 and logic control units I6, I7, I8, I9;

[0103] One end of resistor R11 is connected to the output voltage VOD of the first logic control unit I12; the other end of resistor R11 is connected to the gate of MOS transistor M7, the input terminal of logic control unit I6, and the positive electrode of diode D3; the negative electrode of diode D3 is connected to the substrate of MOS transistor M7, the source of MOS transistor M7, the output terminal GVDD of the clamping circuit 11, the substrate of MOS transistor M8, the source of MOS transistor M8, and the negative electrode of diode D4; one end of resistor R12 is connected to the positive electrode of diode D4 and the gate of MOS transistor M8; the other end of resistor R12 is connected to the output terminal of logic control unit I6; the drain of MOS transistor M7 is connected to the drain of MOS transistor M9 and the gate of MOS transistor M10; the drain of MOS transistor M8 is connected to the gate of MOS transistor M9, the drain of MOS transistor M10, and the first input terminal of logic control unit I9; the output terminal of logic control unit I9 is connected to the gate of the charge and discharge control MOS transistor M0; the sources and substrates of MOS transistors M9, M9, M10, M10, M13, M13, M14, M14, M17, M17, M18, and M18 are connected together and are also connected to the source and substrate of MOS transistor M19 and the source and substrate of MOS transistor M20; the drain of MOS transistor M19 is connected to one end of the source or drain of the charge and discharge control MOS transistor M0 and the negative terminal of the battery; the drain of MOS transistor M20 is connected to the other end of the source or drain of the charge and discharge control MOS transistor M0 and the negative terminal of the charger;

[0104] One end of resistor R13 is connected to the output voltage VOC of the second logic control unit I13; the other end of resistor R13 is connected to the gate of MOS transistor M11, the input terminal of logic control unit I7, and the positive electrode of diode D5; the negative electrode of diode D5 is connected to the substrate of MOS transistor M11, the source of MOS transistor M11, the output terminal GVDD of the clamping circuit 11, the substrate of MOS transistor M12, the source of MOS transistor M12, and the negative electrode of diode D6; one end of resistor R14 is connected to the positive electrode of diode D6 and the gate of MOS transistor M12; the other end of resistor R14 is connected to the output terminal of logic control unit I7; the drain of MOS transistor M11 is connected to the drain of MOS transistor M13 and the gate of MOS transistor M14; the drain of MOS transistor M12 is connected to the gate of MOS transistor M13, the drain of MOS transistor M14, the second input terminal of logic control unit I9, and the input terminal of logic control unit I10;

[0105] One end of resistor R15 is connected to the output voltage VCHOC1 of the basic protection circuit 10; the other end of resistor R15 is connected to the gate of MOS transistor M15, the input end of logic control unit I8, and the positive electrode of diode D7; the negative electrode of diode D7 is connected to the substrate of MOS transistor M15, the source of MOS transistor M15, the output end GVDD of the clamping circuit 11, the substrate of MOS transistor M16, the source of MOS transistor M16, and the negative electrode of diode D8; one end of resistor R16 is connected to the positive electrode of diode D8 and the gate of MOS transistor M16; the other end of resistor R16 is connected to the output end of logic control unit I8; the drain of MOS transistor M15 is connected to the drain of MOS transistor M17, the gate of MOS transistor M18, and the gate of MOS transistor M20; the drain of MOS transistor M16 is connected to the gate of MOS transistor M17, the drain of MOS transistor M18, and the gate of MOS transistor M19.

[0106] The substrate control part includes resistors R13, R14, R15, R16, MOS transistors M1, M2, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, and diodes D5, D6, D7, D8, and logic control units I7, I8, I10, I11.

[0107] The input end of logic control unit I10 is connected to the second input end of logic control unit I9, the drain of MOS transistor M12, the gate of MOS transistor M13, and the drain of MOS transistor M14; the output end of logic control unit I10 is connected to the input end of logic control unit I11 and the gate of MOS transistor M2; the output end of logic control unit I11 is connected to the gate of MOS transistor M1; the drain of MOS transistor M1 is connected to the drain of MOS transistor M19, one end of the source or drain of charge and discharge control MOS transistor M0, and the negative electrode of the battery; the source of MOS transistor M1, the substrate of MOS transistor M1, the source of MOS transistor M2, and the substrate of MOS transistor M2 are connected together and connected to the substrate of charge and discharge control MOS transistor M0; the drain of MOS transistor M2 is connected to the drain of MOS transistor M20, the other end of the source or drain of charge and discharge control MOS transistor M0, and the negative electrode of the charger.

[0108] The application also provides a portable electronic device, which includes a single wafer and the single wafer battery protection circuit 1 disclosed in the above embodiment. The portable electronic device can be a device with a lithium battery, such as a mobile phone, a toy, a mobile power supply, an electronic cigarette, a true wireless stereo (TWS) earphone, etc.

[0109] It should be noted that the above embodiments can be freely combined as needed. The above are only the preferred embodiments of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A single-wafer battery protection circuit, characterized by comprising: Basic protection circuit, clamping voltage circuit, gate-substrate control circuit, over-temperature protection circuit, and charge-discharge control MOS transistor; One end of the source and drain of the charge-discharge control MOS transistor is connected to the negative electrode of the battery, and the other end of the source and drain of the charge-discharge control MOS transistor is connected to the negative electrode of the charger or the load; the gate and substrate of the charge-discharge control MOS transistor are respectively connected to the gate-substrate control circuit; The basic protection circuit is coupled to the gate-substrate control circuit; The clamping voltage circuit is used to clamp the supply voltage of the gate-substrate control circuit. The clamping voltage circuit includes a voltage-dividing resistor and N zener diodes connected in series in one direction, where N≥1; One end of the voltage-dividing resistor receives the supply voltage, and the other end of the voltage-dividing resistor is connected to the negative electrode of the N zener diodes connected in series in one direction and the input voltage GVDD terminal of the gate-substrate control circuit. The positive electrode of the N zener diodes connected in series in one direction is coupled to the input voltage VSS terminal of the gate-substrate control circuit; The over-temperature protection circuit is respectively coupled to the basic protection circuit and the gate-substrate control circuit, and is used to jointly control the conduction of the gate-substrate control circuit with the basic protection circuit; The over-temperature protection circuit includes an over-temperature comparator, a third logic control unit, a fourth logic control unit, and a fifth logic control unit. Both input terminals of the over-temperature comparator are connected to the basic protection circuit. The output terminal of the over-temperature comparator is respectively connected to the first input terminal of the fourth logic control unit and the second input terminal of the fifth logic control unit. The second input terminal of the fourth logic control unit is connected to the output terminal of the third logic control unit. The first input terminal of the fifth logic control unit and the input terminal of the third logic control unit are connected to the basic protection circuit. The output terminals of the fourth logic control unit and the fifth logic control unit are coupled to the gate-substrate control circuit; Among them, the gate-substrate control circuit includes a gate control part and a substrate control part; the gate control part is connected to the gate of the charge-discharge control MOS transistor, and the substrate control part is connected to the substrate of the charge-discharge control MOS transistor.

2. The single-wafer cell protection circuit according to claim 1, characterized in that , the battery is connected in parallel with the RC filter circuit. The RC filter circuit includes a first resistor and a first capacitor. One end of the first resistor is connected to the positive electrode of the battery, and the other end of the first resistor is connected to the negative electrode of the battery through the first capacitor.

3. The single-wafer cell protection circuit according to claim 1, wherein , The basic protection circuit includes a reference circuit, a discharge over-current comparator, a discharge short-circuit comparator, a charge over-current comparator, an over-discharge voltage comparator, an over-charge voltage comparator, a delay circuit, a charge-discharge detection circuit, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The output terminal of the reference circuit is respectively connected to the first input terminal of the discharge over-current comparator, the first input terminal of the discharge short-circuit comparator, the second input terminal of the charge over-current comparator, the second input terminal of the over-discharge voltage comparator, and the first input terminal of the over-charge voltage comparator; The second input terminal of the discharge overcurrent comparator, the second input terminal of the discharge short - circuit comparator, the first input terminal of the charge overcurrent comparator, and the second input terminal of the charge - discharge detection circuit are respectively connected to the source or drain of the charge - discharge control MOS transistor through the fifth resistor; One end of the second resistor is connected to the supply voltage, and the other end of the second resistor is connected to the first input terminal of the over - discharge voltage comparator and one end of the third resistor; The other end of the third resistor is connected to the second input terminal of the over - charge voltage comparator and one end of the fourth resistor, and the other end of the fourth resistor is connected to the first input terminal of the charge - discharge detection circuit and grounded; The output terminals of the discharge overcurrent comparator, the discharge short - circuit comparator, the charge overcurrent comparator, the over - discharge voltage comparator, and the over - charge voltage comparator are respectively connected to the delay circuit; The output terminal of the charge overcurrent comparator is respectively connected to the delay circuit and the gate - substrate control circuit; The output terminal of the charge - discharge detection circuit is connected to the input terminal of the over - temperature protection circuit.

4. The single-wafer cell protection circuit according to claim 3, wherein ,The basic protection circuit further includes a sixth logic control unit, a seventh logic control unit, an eighth logic control unit, a ninth logic control unit, and a tenth logic control unit; The output terminal VDOC1, the output terminal VDSHORT, and the output terminal VDODV of the delay circuit are connected to the first input terminal of the eighth logic control unit through the sixth logic control unit; the output terminal of the charge - discharge detection circuit is connected to the second input terminal of the eighth logic control unit; the output terminal of the eighth logic control unit is coupled to the gate - substrate control circuit; The output terminal VDCHOC and the output terminal VDOCV of the delay circuit are connected to the first input terminal of the ninth logic control unit through the seventh logic control unit; the output terminal of the charge - discharge detection circuit is connected to the input terminal of the tenth logic control unit; the output terminal of the tenth logic control unit is connected to the second input terminal of the ninth logic control unit; the output terminal of the ninth logic control unit is coupled to the gate - substrate control circuit.

5. A battery charging circuit, characterized in that it includes the single - wafer battery protection circuit according to claim 2, a charger, a battery, and an RC filter circuit, wherein: One end of the first resistor is connected to the power supply voltage terminal of the basic protection circuit, and the other end of the first resistor is connected to the positive electrode of the battery; One end of the first capacitor is connected to the power supply voltage terminal of the basic protection circuit, and the other end of the first capacitor is connected to the negative electrode of the battery. The positive electrode of the charger is connected to the positive electrode of the battery to provide a charging voltage for the battery, and the negative electrode of the charger is connected to the negative electrode of the battery through the charge - discharge control MOS transistor.

6. A battery discharge circuit, characterized in that it includes the single - wafer battery protection circuit according to claim 2, an RC filter circuit, a battery, and a load, wherein: One end of the first resistor is connected to the power supply voltage terminal of the basic protection circuit, and the other end of the first resistor is connected to the positive electrode of the battery; One end of the first capacitor is connected to the power supply voltage terminal of the basic protection circuit, and the other end of the first capacitor is connected to the negative electrode of the battery; The positive electrode of the battery is connected to the positive electrode of the load to provide power for the load, and the negative electrode of the load is connected to the negative electrode of the battery through the charge and discharge control MOS transistor.

7. A portable electronic device, characterized in that, The portable electronic device includes a single wafer and the single wafer battery protection circuit according to any one of claims 1 to 4.

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