Resistive memory devices

Abstract

A resistance-type memory device is provided, comprising: a first conductive line extending in a first direction; a second conductive line extending in a second direction intersecting the first direction; and a memory unit connecting the first conductive line and the second conductive line, wherein the memory unit comprises: a first memory unit comprising a first resistance-type memory layer and a first heating electrode layer, the first heating electrode layer comprising a first contact surface contacting the first resistance-type memory layer, and the first contact surface having a first contact resistance; and a second memory unit comprising a second resistance-type memory layer and a second heating electrode layer, the second heating electrode layer comprising a second contact surface contacting the second resistance-type memory layer, and the second contact surface having a second contact resistance different from the first contact.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0098761 filed on August 23, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a memory device, and more particularly, to a resistance-type memory device having a cross-point array. Background Art

[0004] A resistive memory device is a nonvolatile memory device having a three-dimensional cross-point stacked structure in which memory cells are arranged at the intersection between two electrodes that cross each other. A voltage drop (also called an "IR drop") may occur in the current flow path of a memory cell array of a resistive memory device. As the speed and capacity of resistive memory devices continue to increase, the reliability of resistive memory devices may be reduced due to the IR drop. Summary of the invention

[0005] According to an exemplary embodiment of the present invention, there is provided a resistance type memory device, comprising: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines extending in a second direction intersecting the first direction; and a plurality of memory cells connected to the plurality of first conductive lines and the plurality of second conductive lines, wherein the plurality of memory cells comprise: a first memory cell comprising a first resistance type memory layer and a first heating electrode layer, the first heating electrode layer comprising a first contact surface contacting the first resistance type memory layer, and the first contact surface having a first contact resistance; and a second memory cell comprising a second resistance type memory layer and a second heating electrode layer, the second heating electrode layer comprising a second contact surface contacting the second resistance type memory layer, and the second contact surface having a second contact resistance different from the first contact resistance.

[0006] According to an exemplary embodiment of the present invention, there is provided a resistance memory device, comprising: a first conductive line including an access point to which a voltage is applied; and a plurality of memory cells connected to the first conductive line, wherein the plurality of memory cells include: a first memory cell disposed at a first distance from the access point, the first memory cell including a first resistance memory layer and a first heating electrode layer, the first heating electrode layer including a first contact surface in contact with the first resistance memory layer, and the first contact surface having a first contact resistance; and a second memory cell disposed at a second distance from the access point greater than the first distance, the second memory cell including a second resistance memory layer and a second heating electrode layer, the second heating electrode layer including a second contact surface in contact with the second resistance memory layer, and the second contact surface having a second contact resistance different from the first contact resistance.

[0007] According to an exemplary embodiment of the present invention, there is provided a resistive memory device, comprising: a plurality of first conductive lines extending in a first region and a second region along a first direction, the first region and the second region being spaced apart from each other on a substrate; a plurality of second conductive lines extending in the first region and the second region along a second direction, the second direction intersecting the first direction; and a plurality of memory cells connected to the first conductive lines and the second conductive lines in the first region and the second region, wherein the plurality of memory cells comprise: a first memory cell comprising a first heating electrode layer arranged in the first region and having a first resistance; and a second memory cell comprising a second heating electrode layer arranged in the second region and having a second resistance greater than the first resistance.

[0008] According to an exemplary embodiment of the present invention, there is provided a resistive memory device, comprising: a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction intersecting the first direction; a first memory cell connected to a first word line and a first bit line; and a second memory cell connected to the first word line and the second bit line, wherein the first memory cell is arranged to be closer to an access point of the first word line than the second memory cell, the first memory cell comprises a first heating layer in direct contact with a first resistive material layer, the second memory cell comprises a second heating layer in direct contact with a second resistive material layer, and wherein a contact resistance greater than that between the first heating layer and the first resistive material layer is provided between the second heating layer and the second resistive material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features of the present inventive concept will be more clearly understood by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a memory system including a resistive memory device according to an exemplary embodiment of the inventive concept;

[0011] Figure 2 is a block diagram illustrating a configuration of a resistance type memory device according to an exemplary embodiment of the inventive concept;

[0012] Figure 3 is a circuit diagram illustrating a memory cell array of a resistance-type memory device according to an exemplary embodiment of the inventive concept;

[0013] Figure 4A is a plan layout diagram schematically illustrating a partial configuration of a memory device according to an exemplary embodiment of the inventive concept;

[0014] Figure 4B It is shown Figure 4A A perspective view of the local configuration of

[0015] Figure 4C Shown along Figure 4A A cross-sectional view of the element on a cross section taken along lines X1-X1' and X2-X2';

[0016] Figure 5 Shows FIG. 4A to FIG. 4C An enlarged plan view of a first contact surface of a first heating electrode layer included in a first region and a second contact surface of a second heating electrode layer included in a second region in the memory device shown;

[0017] Figure 6 , Figure 7 , Figure 8 and Fig. 9 is a cross-sectional view illustrating a memory device according to an exemplary embodiment of the inventive concept;

[0018] Fig.10 Shown Fig. 9 An enlarged plan view of a first contact surface of a first heating electrode layer included in a first region and a second contact surface of a second heating electrode layer included in a second region in the memory device shown;

[0019] Fig.11 , Fig.12 and Fig.13 is a cross-sectional view illustrating a memory device according to an exemplary embodiment of the inventive concept;

[0020] Fig.14A , Fig. 14B , Fig. 14C , Fig.14D , Fig.14E , Fig.14F , Figure 14G , 14H , Fig.14I and Fig.14J is a cross-sectional view illustrating a method of manufacturing a memory device according to an exemplary embodiment of the inventive concept; and

[0021] Fig.15A , Fig. 15B , Fig. 15C and Fig.15D is a cross-sectional view illustrating a method of manufacturing a memory device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0022] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the accompanying drawings, in order to clearly understand the inventive concept, the size of the constituent elements may be exaggerated or reduced. In the accompanying drawings, the same reference numerals may be used for the same constituent elements, and their repeated description may be omitted.

[0023] Figure 1 is a block diagram illustrating a memory system 10 including a resistive memory device according to an exemplary embodiment of the inventive concept.

[0024] refer to Figure 1 , the memory system 10 may include a memory device 12 and a memory controller 20. The memory device 12 may include a memory cell array MCA, a row decoder RD, a column decoder CD, and a control logic device CL.

[0025] The memory controller 20 may control the memory device 12 to read data DATA stored in the memory device 12 or write data DATA to the memory device 12 in response to a read / write request from the host HOST. The memory controller 20 may control a program (or, write) operation, a read operation, and an erase operation for the memory device 12 by providing an address ADDR, a command CMD, and a control signal CTRL to the memory device 12. In addition, data DATA to be written and data DATA to be read may be transmitted and received between the memory controller 20 and the memory device 12.

[0026] The memory cell array MCA may include a plurality of memory cells, and the plurality of memory cells are respectively arranged in regions where a plurality of first signal lines and a plurality of second signal lines intersect each other. For example, the memory cell array MCA may include Figure 3In an exemplary embodiment of the present invention, the plurality of first signal lines may be a plurality of bit lines, and the plurality of second signal lines may be a plurality of word lines. In another exemplary embodiment of the present invention, the plurality of first signal lines may be a plurality of word lines, and the plurality of second signal lines may be a plurality of bit lines.

[0027] The plurality of memory cells may each include a single level cell (SLC) storing one bit of data, a multi level cell (MLC) capable of storing at least two bits of data, or a combination thereof.

[0028] The memory cell array MCA may include: a resistance type memory cell including a variable resistance type element (eg, Figure 3 In an exemplary embodiment of the inventive concept, when the variable resistance type element includes a phase change material whose resistance changes with temperature, the memory device 12 may be a phase change random access memory (PRAM) device.

[0029] The row decoder RD may drive a plurality of word lines in the memory cell array MCA, and the column decoder CD may drive a plurality of bit lines in the memory cell array MCA. The row decoder RD may include a decoding unit for decoding a row address, and a conversion unit for controlling conversion in response to various row control signals according to the decoding result. The column decoder CD may include a decoding unit for decoding a column address, and a conversion unit for controlling conversion in response to various column control signals according to the decoding result.

[0030] The control logic device CL can control the overall operation of the memory device 12, and control the row decoder RD and the column decoder CD to perform the operation of selecting the memory cell in the memory cell array MCA. For example, the control logic device CL can process the address ADDR received from the outside and generate the row address and the column address. The memory device 12 may include: a power supply unit for generating various write voltages and read voltages used in write operations and read operations. The write voltage and the read voltage can be provided to the memory cell via the row decoder RD and the column decoder CD under the control of the control logic device CL.

[0031] Figure 2 It is used to illustrate Figure 1 A block diagram of an example configuration of memory device 12 is shown.

[0032] refer to Figure 2 , the memory device 12 may include a memory cell array MCA, a row decoder RD, a column decoder CD, and a control logic device CL. In addition, the memory device 12 may also include a write / read circuit 14, a reference signal generator 16, and a power generator 18. The write / read circuit 14 may include a sense amplifier 14A and a write driver 14B.

[0033] A plurality of memory cells in the memory cell array MCA may be connected to a plurality of word lines WL and a plurality of bit lines BL. When various voltage signals or current signals are provided via the plurality of word lines WL and the plurality of bit lines BL, data may be written to or read from the selected memory cell, and a write operation or a read operation to an unselected memory cell may be prevented.

[0034] The address ADDR for indicating the memory cell to be accessed together with the command CMD may be received by the control logic device CL. The address ADDR may include a row address X_ADDR for selecting a word line WL of the memory cell array MCA, and a column address Y_ADDR for selecting a bit line BL of the memory cell array MCA. The row decoder RD may perform a word line selection operation in response to the row address X_ADDR, and the column decoder CD may perform a bit line selection operation in response to the column address Y_ADDR.

[0035] The write / read circuit 14 may be connected to the bit line BL to write data to the memory cell or read data from the memory cell.

[0036] The power generator 18 may generate a write voltage Vwrite for a write operation and a read voltage Vread for a read operation. The write voltage Vwrite may include a set voltage and a reset voltage. The write voltage Vwrite and the read voltage Vread may be provided to the bit line BL via a column decoder CD, or provided to the word line WL via a row decoder RD, respectively.

[0037] The reference signal generator 16 may generate a reference voltage Vref and a reference current Iref as various reference signals related to a data read operation.

[0038] In the write / read circuit 14, a sense amplifier 14A may be connected to a sense node of the bit line BL to read data based on a reference voltage Vref or a reference current Iref. The write / read circuit 14 may provide a pass / fail signal P / F to the control logic device CL according to a differential result of the read data. The control logic device CL may control the write operation and the read operation of the memory cell array MCA by referring to the pass / fail signal P / F.

[0039] The control logic device CL may be based on the slave memory controller 20 (see Figure 1 ) receives the address ADDR, command CMD and control signal CTRL, and generates various control signals CTRL_RW for reading data from the memory cell array MCA or for writing data to the memory cell array MCA.

[0040] Figure 3 According to an exemplary embodiment of the present invention Figure 2 The circuit diagram of the memory cell array MCA is shown.

[0041] refer to Figure 3 , the memory cell array MCA may include a plurality of cell regions, and represents one cell region among the plurality of cell regions.

[0042] The memory cell array MCA may include 0th to nth word lines WLO, WL1, ..., WLn, 0th to mth bit lines BL0, BL1, ..., BLm, and a plurality of memory cells MC. The 0th to nth word lines WLO, WL1, ..., WLn may correspond to Figure 2 The word line WL in the , and the 0th to mth bit lines BL0, BL1, ..., BLm may correspond to Figure 2 , . . . , WLn. A plurality of memory cells MC may each be arranged at one of the intersections of the 0th to nth word lines WL0, WL1, ..., WLn and the 0th to mth bit lines BLO, BL1, ..., BLm. According to exemplary embodiments of the inventive concept, the number of word lines WL, the number of bit lines BL, and the number of memory cells MC may be changed differently. A plurality of memory cells MC connected to one of the 0th to nth word lines WL0, WL1, ..., WLn may be defined in a page PAGE unit. For example, one PAGE unit may include all memory cells MC connected to the word line WL0.

[0043] A plurality of memory cells MC may each include a variable resistor R for storing information and a selection device D for selecting the memory cell MC. The selection device D may be electrically connected to one of the 0th to nth word lines WLO, WL1, ..., WLn, the variable resistor R may be electrically connected to one of the 0th to mth bit lines BLO, BL1, ..., BLm, and the variable resistor R and the selection device D may be connected in series to each other. However, the inventive concept is not limited thereto, and the variable resistor R may be connected to one of the 0th to nth word lines WLO, WL1, ..., WLn, and the selection device D may be connected to one of the 0th to mth bit lines BLO, BL1, ..., BLm.

[0044] In order to drive the memory device 12 (refer to Figure 2), a voltage may be applied to a variable resistor R of a memory cell MC via a 0th word line to an nth word line WLO, WL1, ..., WLn and a 0th bit line to an mth bit line BLO, BL1, ..., BLm, so that a current flows in the variable resistor R. The variable resistor R may be changed to one of a plurality of resistance states due to an applied electric pulse. In an exemplary embodiment of the inventive concept, the variable resistor R may include: a phase change material, wherein a crystalline state changes according to an amount of current applied to the phase change material. The phase change material may be changed into an amorphous state having a relatively high resistance, or a crystalline state having a relatively low resistance. The phase of the phase change material may be changed by Joule heat generated according to the amount of current applied to the phase change material, and data may be written by using such a phase change.

[0045] Any memory cell MC can be addressed by selecting the 0th to nth word lines WLO, WL1, ..., WLn and the 0th to mth bit lines BLO, BL1, ..., BLm, and any memory cell MC can be programmed by applying a signal between the selected word line and the selected bit line. By measuring the current value flowing through the 0th to mth bit lines BLO, BL1, ..., BLm, information (in other words, programming information) according to the resistance value of the resistive memory layer of the corresponding memory cell MC can be read.

[0046] FIG. 4A to FIG. 4C is a diagram for explaining a memory device 100 according to an exemplary embodiment of the inventive concept. Figure 4A is a plan layout diagram schematically illustrating a partial configuration of a memory device according to an exemplary embodiment of the inventive concept, Figure 4B It is shown Figure 4A A perspective view of a partial configuration of the first area A1 and the second area A2 in FIG. Figure 4C The Figure 4A A cross-sectional view of the element on the cross section taken along the lines X1-X1' and X2-X2'. FIG. 4A to FIG. 4C The memory cell array MCA of the memory device 100 shown in FIG. 1 may have a configuration as shown in FIG. Figure 3 The equivalent circuit configuration described.

[0047] Reference FIG. 4A to FIG. 4C , the memory cell array MCA of the memory device 100 may include a plurality of first conductive lines 110 extending parallel to each other along a first direction (X direction) on a substrate 102, and a plurality of second conductive lines 170 extending parallel to each other in a second direction (Y direction) crossing the first direction (X direction). In the present embodiment, the case where the first direction and the second direction are orthogonal to each other is described as an example, but the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, the plurality of first conductive lines 110 may constitute Figure 3 The 0th word line to the nth word line WL0, WL1, . . . , WLn are shown, and a plurality of second conductive lines 170 may constitute Figure 3 The 0th bit line to the mth bit line BL0, BL1, . . . , BLm are shown. In other exemplary embodiments of the present inventive concept, the plurality of first conductive lines 110 may constitute Figure 3 The 0th bit line to the mth bit line BL0, BL1, ..., BLm are shown, and a plurality of second conductive lines 170 may constitute Figure 3 The 0th to nth word lines are shown as WL0, WL1, . . . , WLn.

[0048] The interlayer insulating layer 104 may be disposed on the substrate 102. The interlayer insulating layer 104 may include an oxide layer, a nitride layer, or a combination thereof.

[0049] The plurality of first conductive lines 110 may be connected to a driver DRV. The driver DRV may be a circuit for applying a voltage to the plurality of first conductive lines 110 and may include, for example, a reference Figure 2 The row decoder RD described. The driver DRV can apply a voltage to the access point AP of each of the plurality of first conductive lines 110 via the wiring 32. In a set write operation, a voltage can be applied through the selected first conductive line 110 and the selected second conductive line 170 connected to the selected memory cell MC. For example, a set high voltage can be applied to the selected first conductive line 110 via the access point AP, and a set low voltage less than the set high voltage can be applied to the selected second conductive line 170. Then, a voltage corresponding to the potential difference between the set high voltage and the set low voltage can be applied to both ends of the selected memory cell MC, and a set current can flow through the selected memory cell MC. Therefore, a current can flow through the plurality of first conductive lines 110 and the plurality of second conductive lines 170.

[0050] In the memory device 100, the memory cell array MCA may include a first area A1 having a relatively small distance from an access point AP of each of the plurality of first conductive lines 110, and a second area A2 having a relatively large distance from the access point AP of each of the plurality of first conductive lines 110. Figure 4A The first region A1 and the second region A2 are shown, therefore, the range and plane shape of the first region A1 and the second region A2 are not limited thereto. The range and plane shape of each of the first region A1 and the second region A2 in the memory cell array MCA can be set differently according to the electrical characteristics required by the memory device 100.

[0051] In an exemplary embodiment of the present inventive concept, Figure 4AA case where the memory cell array MCA includes a first area A1 and a second area A2 is shown. However, the memory cell array MCA may be divided into a plurality of areas (e.g., three or more areas) at different distances from the access point AP. In an exemplary embodiment of the inventive concept, the memory cells MC not included in the first area A1 and the second area A2 may have the same configuration as the plurality of memory cells MC included in the first area A1. In other exemplary embodiments of the inventive concept, the memory cells MC not included in the first area A1 and the second area A2 may have a configuration different from the configuration of the plurality of memory cells MC included in each of the first area A1 and the second area A2.

[0052] A resistance component may exist in each of the plurality of first conductive lines 110 and the plurality of second conductive lines 170. Therefore, when current flows to the selected memory cell MC through the selected first conductive line 110 and the selected second conductive line 170, a voltage drop of the selection voltage applied to the access point AP may be generated by a TR drop, and an IR drop occurs between the access point AP and the selected memory cell MC via the selected first conductive line 110 and the selected second conductive line 170. Since the second area A2 is farther from the access point AP than the first area A1, the voltage drop in the second area A2 may be greater.

[0053] A plurality of first insulating patterns 112 may be disposed between each of the plurality of first conductive lines 110, and a plurality of second insulating patterns 172 may be disposed between each of the plurality of second conductive lines 170. The plurality of first insulating patterns 112 and second insulating patterns 172 may include a silicon oxide layer, a silicon nitride layer, or a combination thereof.

[0054] The plurality of first wires 110 and the plurality of second wires 170 may each include a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In an exemplary embodiment of the present invention, the plurality of first wires 110 and the plurality of second wires 170 may each include W, Ti, Ta, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, TiCSiN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, Au, Ag, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, indium tin oxide (ITO), or a combination thereof. The plurality of first wires 110 and the plurality of second wires 170 may each include a conductive barrier layer. The conductive barrier layer may include, for example, Ti, TiN, Ta, TaN, or a combination thereof.

[0055] Memory cell pillars P1A and P1B constituting memory cells MC may be arranged at a plurality of intersections between the plurality of first conductive lines 110 and the plurality of second conductive lines 170. The memory cell pillars P1A are arranged in the first region A1, and the memory cell pillars P1B are arranged in the second region A2.

[0056] The memory cell pillars P1A and P1B may be insulated from each other by a plurality of first insulating wall portions 116A and a plurality of second insulating wall portions 116B. The plurality of first insulating wall portions 116A and the plurality of second insulating wall portions 116B may each include a silicon nitride layer or a silicon oxide layer.

[0057] In the first region A1, a pair of memory cell pillars P1A may be disposed between each pair of adjacent plurality of first insulating wall portions 116A arranged in a row along the X direction. The plurality of second insulating wall portions 116B may each extend in the X direction, and the plurality of second insulating wall portions 116B and the plurality of memory cell pillars P1A may be alternately arranged in the Y direction.

[0058] In the second region A2, a pair of memory cell pillars P1B may be disposed between each pair of adjacent plurality of first insulating wall portions 116A arranged in a row along the X direction. The plurality of second insulating wall portions 116B may each extend in the X direction, and the plurality of second insulating wall portions 116B and the plurality of memory cell pillars P1B may be alternately arranged in the Y direction.

[0059] In the first area A1, the plurality of memory cell pillars P1A may each include a first heating electrode layer 120A, a resistance type memory layer 130, and an electrode layer 140 sequentially stacked on the first conductive line 110. In the second area A2, the plurality of memory cell pillars P1B may each include a second heating electrode layer 120B, a resistance type memory layer 130, and an electrode layer 140 sequentially stacked on the first conductive line 110.

[0060] The first heating electrode layer 120A and the second heating electrode layer 120B may have a substantially U-shaped cross-sectional shape. One first heating electrode layer 120A may be shared by two adjacent memory cell pillars P1A in the first region A1, and one second heating electrode layer 120B may be shared by two adjacent memory cell pillars P1B in the second region A2. The first insulating spacer 122 and the gap filling insulating layer 124 may be sequentially stacked on the first heating electrode layer 120A and the second heating electrode layer 120B. The first insulating spacer 122 may have a substantially U-shaped cross-sectional shape. Two memory cell pillars P1A sharing one first heating electrode layer 120A may be insulated from each other by the first insulating spacer 122 and the gap filling insulating layer 124. Two memory cell pillars P1B sharing one second heating electrode layer 120B may be insulated from each other by the first insulating spacer 122 and the gap filling insulating layer 124.

[0061] The first insulating spacer 122 may include a material having an etch selectivity different from that of the plurality of first insulating wall portions 116A and the plurality of second insulating wall portions 116B, and the gap-filling insulating layer 124 may include a material having an etch selectivity equal to or similar to that of the plurality of first insulating wall portions 116A and the plurality of second insulating wall portions 116B. For example, the plurality of first insulating wall portions 116A, the plurality of second insulating wall portions 116B, and the gap-filling insulating layer 124 may include a silicon nitride layer, and the first insulating spacer 122 may include a silicon oxide layer. However, the inventive concept is not limited thereto.

[0062] The first heating electrode layer 120A and the second heating electrode layer 120B may perform an operation of heating the resistance type memory layer 130 in a set or reset operation. The first heating electrode layer 120A and the second heating electrode layer 120B may each include a conductive material that does not react with the resistance type memory layer 130 and generates enough heat to cause the resistance type memory layer 130 to undergo a phase change. The first heating electrode layer 120A may contact the resistance type memory layer 130 in the memory cell column P1A, and the second heating electrode layer 120B may contact the resistance type memory layer 130 in the memory cell column P1B.

[0063] The first heating electrode layer 120A may include a pin portion 120P1 extending from the substrate 102 toward the resistance type memory layer 130, and the second heating electrode layer 120B may include a pin portion 120P2 extending from the substrate 102 toward the resistance type memory layer 130. The first heating electrode layer 120A and the second heating electrode layer 120B may have substantially the same or similar thickness. For example, the pin portion 120P1 of the first heating electrode layer 120A and the pin portion 120P2 of the second heating electrode layer 120B may have substantially the same or similar thickness. Here, the thickness of the pin portions 120P1 and 120P2 may correspond to the width of the pin portions 120P1 and 120P2 in the X direction.

[0064] The resistance type memory layer 130 in the plurality of memory cell pillars P1A in the first area A1 may contact an end of the pin portion 120P1 of the first heating electrode layer 120A farthest from the substrate 102. The resistance type memory layer 130 in the plurality of memory cell pillars P1B in the second area A2 may contact an end of the pin portion 120P2 of the second heating electrode layer 120B farthest from the substrate 102.

[0065] exist Figure 5 In the figure, (a) is an enlarged plan view showing a first contact surface 120C1 of the resistive memory layer 130 and the first heating electrode layer 120A in contact with the resistive memory layer 130 in the first area A1, and (b) is an enlarged plan view showing a second contact surface 120C2 of the resistive memory layer 130 and the second heating electrode layer 120B in contact with the resistive memory layer 130 in the second area A2.

[0066] Reference FIG. 4A to FIG. 4C and Figure 5 , the first contact surface 120C1 of the first heating electrode layer 120A and the second contact surface 120C2 of the second heating electrode layer 120B may have substantially the same or similar areas. In the first area A1, the first contact surface 120C1 of the first heating electrode layer 120A may be provided by an end of one pin portion 120P1 of the first heating electrode layer 120A farthest from the substrate 102, and in the second area A2, the second contact surface 120C2 of the second heating electrode layer 120B may be provided by an end of one pin portion 120P2 of the second heating electrode layer 120B farthest from the substrate 102.

[0067] The first heating electrode layer 120A may provide a first contact resistance at the first contact surface 120C1, and the second heating electrode layer 120B may provide a second contact resistance different from the first contact resistance at the second contact surface 120C2. To this end, the first heating electrode layer 120A and the second heating electrode layer 120B may have different compositions. For example, the first heating electrode layer 120A may include a material having a first resistivity, and the second heating electrode layer 120B may include a material having a second resistivity different from the first resistivity.

[0068] In an exemplary embodiment of the inventive concept, a distance from an access point AP of the first conductive line 110 to the second heating electrode layer 120B may be greater than a distance from an access point AP of the first conductive line 110 to the first heating electrode layer 120A. In an exemplary embodiment of the inventive concept, a second current path from an access point AP of the first conductive line 110 to the second heating electrode layer 120B may be greater than a first current path from an access point AP of the first conductive line 110 to the first heating electrode layer 120A. A second contact resistance provided by a second contact surface 120C2 of the second heating electrode layer 120B may be greater than a first contact resistance provided by a first contact surface 120C1 of the first heating electrode layer 120A. A second resistivity of a material of the second heating electrode layer 120B may be greater than a first resistivity of a material of the first heating electrode layer 120A.

[0069] In an exemplary embodiment of the present inventive concept, both the first heating electrode layer 120A and the second heating electrode layer 120B may include a first metal, and a content ratio of the first metal in the second heating electrode layer 120B may be smaller than a content ratio of the first metal in the first heating electrode layer 120 A. The first metal may include Ti, Ta, W, Mo, Nb, Zr, or Al, but is not limited thereto.

[0070] In other exemplary embodiments of the present inventive concept, the first heating electrode layer 120A and the second heating electrode layer 120B may each include a non-metallic element, and a content ratio of the non-metallic element in the second heating electrode layer 120B may be greater than a content ratio of the non-metallic element in the first heating electrode layer 120A. In addition, in other exemplary embodiments of the present inventive concept, the first heating electrode layer 120A and the second heating electrode layer 120B may each include a metalloid element, and a content ratio of the metalloid element in the second heating electrode layer 120B may be greater than a content ratio of the metalloid element in the first heating electrode layer 120A.

[0071] For example, both the first heating electrode layer 120A and the second heating electrode layer 120B may include nitrogen atoms, and the content ratio of the nitrogen atoms in the second heating electrode layer 120B may be greater than the content ratio of the nitrogen atoms in the first heating electrode layer 120A. In another example, both the first heating electrode layer 120A and the second heating electrode layer 120B may include silicon atoms, and the content ratio of the silicon atoms in the second heating electrode layer 120B may be greater than the content ratio of the silicon atoms in the first heating electrode layer 120A.

[0072] In an exemplary embodiment of the present inventive concept, the first heating electrode layer 120A and the second heating electrode layer 120B may each include a metal, a metal nitride, or an alloy, but the compositions of the first heating electrode layer 120A and the second heating electrode layer 120B may be different from each other. For example, the first heating electrode layer 120A and the second heating electrode layer 120B may each include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, TiCN, TaCN, or a combination thereof. However, the components of the first heating electrode layer 120A and the second heating electrode layer 120B may be different from each other.

[0073] For example, the first heating electrode layer 120A and the second heating electrode layer 120B may each include TiSiN, and the content ratio of Ti in the second heating electrode layer 120B may be smaller than the content ratio of Ti in the first heating electrode layer 120A. In another example, the first heating electrode layer 120A and the second heating electrode layer 120B may each include TiSiN, and the content ratio of nitrogen atoms in the second heating electrode layer 120B may be greater than the content ratio of nitrogen atoms in the first heating electrode layer 120A. In yet another example, the first heating electrode layer 120A and the second heating electrode layer 120B may include TiSiN, and the content ratio of silicon atoms in the second heating electrode layer 120B may be greater than the content ratio of silicon atoms in the first heating electrode layer 120A.

[0074] In the plurality of memory cell columns P1A and P1B, the resistance type memory layer 130 may include a phase change material that changes between an amorphous state and a crystalline state according to a heating time. For example, the phase of the resistance type memory layer 130 may be changed by Joule heat generated by a voltage applied to both ends of the resistance type memory layer 130, and may include a material whose resistance changes due to a change in phase. In an exemplary embodiment of the present invention, the resistance type memory layer 130 may include a chalcogenide material as a phase change material. In an exemplary embodiment of the present invention, the resistance type memory layer 130 may include Ge-Sb-Te (GST). For example, the resistance type memory layer 130 may include Ge 2 Sb 2 Te 5 ,Ge 2 Sb 2 Te 7 ,Ge 1 Sb 2 Te 4 Or Ge 1 Sb 4 Te 7 .

[0075] The electrode layer 140 may include a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, the electrode layer 140 may include W, Ti, Ta, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, TiCSiN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, or a combination thereof.

[0076] The multiple memory cell columns P1A and P1B may also each include multiple stacked structures formed by a first interface layer 152, a selection device layer 154, a second interface layer 156 and an electrode layer 160, wherein the first interface layer 152, the selection device layer 154, the second interface layer 156 and the electrode layer 160 are stacked in sequence on the electrode layer 140, and the insulating layer 162 fills the space between the multiple stacked structures.

[0077] Each of the first interface layer 152 and the second interface layer 156 may include a conductive material (eg, carbon (C)). In an exemplary embodiment of the present inventive concept, the first interface layer 152 and the second interface layer 156 may be omitted. The selection device layer 154 may correspond to Figure 3The selection device D shown in . The selection device layer 154 may include an amorphous chalcogenide conversion material. The selection device layer 154 may include a material layer whose resistance varies according to the magnitude of the voltage applied to both ends of the selection device layer 154. For example, the selection device layer 154 may include a bidirectional threshold switching (OTS) material. The OTS material may include a chalcogenide conversion material. In an exemplary embodiment of the present inventive concept, the selection device layer 154 may include Si, Te, As, Ge, In, or a combination thereof. The selection device layer 154 may also include nitrogen atoms. However, the constituent materials of the selection device layer 154 are not limited to the above examples, and various modifications may be made. The detailed configuration of the electrode layer 160 may be substantially the same as the detailed configuration of the electrode layer 140. The insulating layer 162 may include an oxide layer, a nitride layer, or a combination thereof.

[0078] In reference FIG. 4A to FIG. 5 In the memory cell array MCA of the described memory device 100, a plurality of memory cell pillars P1A in a first region A1 having a relatively small distance from an access point AP of each of a plurality of first conductive lines 110 may include a first heating electrode layer 120A. In addition, a plurality of memory cell pillars P1B in a second region A2 having a relatively large distance from an access point AP of each of a plurality of first conductive lines 110 may include: a second heating electrode layer 120B having a different configuration from the first heating electrode layer 120A. Here, the first heating electrode layer 120A and the second heating electrode layer 120B may provide contact resistances of different sizes at a first contact surface 120C1 and a second contact surface 120C2 in contact with the resistive memory layer 130, respectively. For example, a larger contact resistance may be provided at a second contact surface 120C2 of the second heating electrode layer 120B, which is at a position farther away from the access point AP than the first contact surface 120C1 of the first heating electrode layer 120A.

[0079] As shown in Formula 1 below, the heating power provided to the first and second heating electrode layers 120A and 120B may be determined by the product of the square of the current flowing through the first and second heating electrode layers 120A and 120B and the resistance of the first and second heating electrode layers 120A and 120B.

[0080] [Formula 1]

[0081] P=I 2 R

[0082] In Formula 1, P is heating power, I is current, and R is resistance.

[0083] In reference Figure 4A and Figure 5In the memory cell array MCA of the described memory device 100, a voltage drop occurs due to an IR drop of a selection voltage applied to a selected memory cell MC. The IR drop is caused by a resistance component in both the plurality of first conductive lines 110 and the plurality of second conductive lines 170 present in the second area A2 having a relatively large distance from the access point AP. By providing a relatively large contact resistance at the second contact surface 120C2 of the second heating electrode layer 120B in the second area A2 having a relatively large distance from the access point AP, the heating power can be increased in the second heating electrode layer 120B. In this case, the reduction in efficiency caused by the voltage drop due to the IR drop in the second area A2 can be compensated, and therefore, the reduction in the operating margin can be prevented. As described above, by compensating for the voltage drop due to the IR drop at a relatively long distance from the access point AP to which a voltage is applied in the memory cell array MCA of the memory device 100, the heating efficiency can be improved by the first heating electrode layer 120A and the second heating electrode layer 120B in all areas of the memory cell array MCA (regardless of their distances from the access point AP). Therefore, the reliability of the memory device 100 can be increased, and a higher speed and a larger capacity of the memory device 100 can be obtained.

[0084] Figure 6 2 is a cross-sectional view for explaining a memory device 200 according to an exemplary embodiment of the inventive concept. Figure 6 In, with FIG. 4A to FIG. 5 The same reference numerals in the drawings may denote the same elements, and thus, repeated descriptions thereof may be omitted. Figure 6 shows that along with Figure 4A The cross sections taken along the X1-X1' line and the X2-X2' line correspond to the components of the parts.

[0085] refer to Figure 6 , the memory device 200 may have a reference FIG. 4A to FIG. 5 The memory device 100 described above has substantially the same configuration. However, a plurality of memory cell pillars P2A and P2B included in the memory cell array MCA of the memory device 200 may include a first heating electrode layer 220A and a second heating electrode layer 220B instead of the first heating electrode layer 120A and the second heating electrode layer 120B. The first heating electrode layer 220A and the second heating electrode layer 220B may include a first heating electrode layer 220A constituting the memory cell pillar P2A in the first area A1, and a second heating electrode layer 220B constituting the memory cell pillar P2B in the second area A2. The first heating electrode layer 220A may have a pin portion 220P1 in contact with the resistance type memory layer 130 in the first area A1, and the second heating electrode layer 220B may include a pin portion 220P2 in contact with the resistance type memory layer 130 in the second area A2. Reference FIG. 4A to FIG. 5 , more detailed configurations of the first heating electrode layer 220A and the second heating electrode layer 220B may be substantially the same as those described with respect to the first heating electrode layer 120A and the second heating electrode layer 120B.

[0086] In the plurality of memory cell pillars P2A and P2B of the memory device 200, a plurality of stacked structures may be arranged between the plurality of first conductive lines 110 and the plurality of first heating electrode layers 220A and the plurality of second heating electrode layers 220B. Each stacked structure may include a first interface layer 152, a selection device layer 154, a second interface layer 156, and an electrode layer 160 stacked in sequence, and an insulating layer 162 may be provided to fill the space between the plurality of stacked structures. Therefore, the first interface layer 152 and the first conductive line 110 may contact each other, and the electrode layer 140 and the second conductive line 170 may contact each other.

[0087] Figure 7 is a cross-sectional view for explaining a memory device 300 according to an exemplary embodiment of the inventive concept. Figure 7 In, with FIG. 4A to FIG. 5 The same reference numerals in the drawings may denote the same elements, and thus, repeated descriptions thereof may be omitted. Figure 7 shows that along with Figure 4A The cross sections taken along the X1-X1' line and the X2-X2' line correspond to the components of the parts.

[0088] refer to Figure 7 , the memory device 300 may have a reference FIG. 4A to FIG. 5 The memory device 300 may have substantially the same configuration as the memory device 100 described above. Figure 3 The equivalent circuit configuration shown. However, the plurality of memory cell columns P3A and the plurality of memory cell columns P3B included in the memory cell array MCA of the memory device 300 may include a first heating electrode layer 320A and a second heating electrode layer 320B, instead of the first heating electrode layer 120A and the second heating electrode layer 120B. The first heating electrode layer 320A and the second heating electrode layer 320B may include a first heating electrode layer 320A constituting the memory cell column P3A in the first area A1, and a second heating electrode layer 320B constituting the memory cell column P3B in the second area A2. The first heating electrode layer 320A and the second heating electrode layer 320B may not be shared by two adjacent memory cell columns P3A and P3B.

[0089] The first heating electrode layer 320A may have a pin portion 320P1 in contact with the resistance type memory layer 130 in the first area A1, and the second heating electrode layer 320B may include a pin portion 320P2 in contact with the resistance type memory layer 130 in the second area A2. FIG. 4A to FIG. 5 , more detailed configurations of the first heating electrode layer 320A and the second heating electrode layer 320B may be substantially the same as those described with respect to the first heating electrode layer 120A and the second heating electrode layer 120B.

[0090] In addition, the plurality of memory cell pillars P3A and P3B included in the memory cell array MCA of the memory device 300 may include the first insulating spacers 122P and the gap-filling insulating layer 124P instead of the first insulating spacers 122 and the gap-filling insulating layer 124. FIG. 4A to FIG. 4C , a more detailed configuration of the first insulating spacer 122P and the gap-filling insulating layer 124P may be substantially the same as the configuration described for the first insulating spacer 122 and the gap-filling insulating layer 124. However, the first insulating spacer 122P may have a linear cross-sectional structure. The first insulating spacer 122P may be arranged between the first heating electrode layer 320A and the resistive memory layer 130 in the first area A1, and may be arranged between the second heating electrode layer 320B and the resistive memory layer 130 in the second area A2. Two adjacent first heating electrode layers 320A and two adjacent first insulating spacers 122P may be separated from each other by the gap-filling insulating layer 124P in the first area A1, respectively. Two adjacent second heating electrode layers 320B and two adjacent first insulating spacers 122P may be separated from each other by the gap-filling insulating layer 124P in the second area A2, respectively.

[0091] Figure 8 4 is a cross-sectional view for explaining a memory device 400 according to an exemplary embodiment of the inventive concept. Figure 8 In, with FIG. 4A to FIG. 6 The same reference numerals in the drawings may denote the same elements, and thus, repeated descriptions thereof may be omitted. Figure 8 shows that along with Figure 4A The cross sections taken along the X1-X1' line and the X2-X2' line correspond to the components of the parts.

[0092] refer to Figure 8 , the memory device 400 may have a reference Figure 6The memory device 200 described has substantially the same configuration. However, the plurality of memory cell pillars P4A and the plurality of memory cell pillars P4B included in the memory cell array MCA of the memory device 400 may include a first heating electrode layer 420A and a second heating electrode layer 420B instead of the first heating electrode layer 220A and the second heating electrode layer 220B. The first heating electrode layer 420A and the second heating electrode layer 420B may include a first heating electrode layer 420A constituting the memory cell pillar P4A in the first area A1, and a second heating electrode layer 420B constituting the memory cell pillar P4B in the second area A2. The first heating electrode layer 420A and the second heating electrode layer 420B may not be shared by two adjacent memory cell pillars P4A and P4B.

[0093] The first heating electrode layer 420A may have a pin portion 420P1 in contact with the resistance type memory layer 130 in the first area A1, and the second heating electrode layer 420B may include a pin portion 420P2 in contact with the resistance type memory layer 130 in the second area A2. FIG. 4A to FIG. 5 , more detailed configurations of the first heating electrode layer 420A and the second heating electrode layer 420B may be substantially the same as those described with respect to the first heating electrode layer 120A and the second heating electrode layer 120B.

[0094] In addition, the plurality of memory cell pillars P4A and P4B included in the memory cell array MCA of the memory device 400 may include a first insulating spacer 122P and a gap-filling insulating layer 124P instead of the first insulating spacer 122 and the gap-filling insulating layer 124. A more detailed configuration of the first insulating spacer 122P and the gap-filling insulating layer 124P is similar to that of the embodiment of the present invention. Figure 7 Describes the configuration.

[0095] exist Figures 6 to 8 The memory devices 200, 300 and 400 shown (similar to those of reference FIG. 4A to FIG. 5 In the memory device 100 described above, the contact resistance at the contact surface of the second heating electrode layer 220B, 320B and 420B with the resistance type memory layer 130 may be greater than the contact resistance at the contact surface of the first heating electrode layer 220A, 320A, 420A with the resistance type memory layer 130. Therefore, the heating power in the second heating electrode layers 220B, 320B and 420B may be increased, and thus the efficiency drop caused by the voltage drop caused by the IR drop in the second area A2 may be compensated.

[0096] Fig. 9 is a cross-sectional view for explaining a memory device 500 according to an exemplary embodiment of the inventive concept. Fig. 9 In, with FIG. 4A to FIG. 4CThe same reference numerals in the drawings may denote the same elements, and thus, repeated descriptions thereof may be omitted. Fig. 9 shows that along with Figure 4A The cross sections taken along the X1-X1' line and the X2-X2' line correspond to the components of the parts.

[0097] refer to Fig. 9 , the memory device 500 may have a reference FIG. 4A to FIG. 4C The memory device 500 may have substantially the same configuration as the memory device 100 described above. Figure 3 The equivalent circuit configuration shown. However, the plurality of memory cell pillars P5A and the plurality of memory cell pillars P5B included in the memory cell array MCA of the memory device 500 may include a first heating electrode layer 520A and a second heating electrode layer 520B instead of the first heating electrode layer 120A and the second heating electrode layer 120B. The first heating electrode layer 520A and the second heating electrode layer 520B may include a first heating electrode layer 520A constituting the memory cell pillar P5A in the first area A1, and a second heating electrode layer 520B constituting the memory cell pillar P5B in the second area A2. The first heating electrode layer 520A may have a pin portion 520P1 in contact with the resistance type memory layer 130 in the first area A1, and the second heating electrode layer 520B may include a pin portion 520P2 in contact with the resistance type memory layer 130 in the second area A2.

[0098] The first heating electrode layer 520A and the second heating electrode layer 520B may have the same composition. FIG. 4A to FIG. 5, the first heating electrode layer 520A and the second heating electrode layer 520B may each have a configuration substantially the same as that described for the first heating electrode layer 120A. For example, the first heating electrode layer 520A and the second heating electrode layer 520B may each include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, TiCN, TaCN, or a combination thereof. However, the thickness of the second heating electrode layer 520B may be less than the thickness of the first heating electrode layer 520A. For example, the thickness of the pin portion 520P2 of the second heating electrode layer 520B may be less than the thickness of the pin portion 520P1 of the first heating electrode layer 520A. Here, the thickness of the pin portions 520P1 and 520P2 may indicate the size (e.g., width) of the pin portions 520P1 and 520P2 in the X direction. The thickness difference between the first heating electrode layer 520A and the second heating electrode layer 520B may not be limited, and, for example, may be variously selected according to the electrical characteristics required in the memory device 500. For example, the thickness of the pin portion 520P2 of the second heating electrode layer 520B may be about 0.1 to about 0.9 times the thickness of the pin portion 520P1 of the first heating electrode layer 520A, but is not limited thereto.

[0099] The resistance type memory layer 130 in the plurality of memory cell pillars P5A in the first area A1 may contact an end of the pin portion 120P1 of the first heating electrode layer 520A farthest from the substrate 102. The resistance type memory layer 130 in the plurality of memory cell pillars P5B in the second area A2 may contact an end of the pin portion 520P2 of the second heating electrode layer 520B farthest from the substrate 102.

[0100] exist Fig.10 In the figure, (a) is an enlarged plan view showing a first contact surface 520C1 of the resistive memory layer 130 and the first heating electrode layer 520A in contact with the resistive memory layer 130 in the first area A1, and (b) is an enlarged plan view showing a second contact surface 520C2 of the resistive memory layer 130 and the second heating electrode layer 520B in contact with the resistive memory layer 130 in the second area A2.

[0101] Reference Fig. 9 and Fig.10, the area of ​​the second contact surface 520C2 of the second heating electrode layer 520B may be smaller than the area of ​​the first contact surface 520C1 of the first heating electrode layer 520A. Therefore, the contact resistance provided at the second contact surface 520C2 of the second heating electrode layer 520B may be greater than the contact resistance provided at the first contact surface 520C1 of the first heating electrode layer 520A.

[0102] When the current path from the access point AP of the first wire 110 to the second heating electrode layer 520B is longer than the current path from the access point AP to the first heating electrode layer 520A, the heating power in the second heating electrode layer 520B can be increased by providing a relatively large contact resistance, thereby compensating for the efficiency drop caused by the voltage drop caused by the IR drop in the second area A2.

[0103] Fig.11 is a cross-sectional view for explaining a memory device 600 according to an exemplary embodiment of the inventive concept. Fig.11 In, with FIG. 4A to FIG. 9 The same reference numerals in the drawings may denote the same elements, and thus repeated descriptions thereof are omitted. Fig.11 shows that along with Figure 4A The cross sections taken along the X1-X1' line and the X2-X2' line correspond to the components of the parts.

[0104] refer to Fig.11 , the memory device 600 may have a reference Fig. 9 The memory device 500 described above has substantially the same configuration. However, the plurality of memory cell pillars P6A and P6B ​​included in the memory cell array MCA of the memory device 600 may include a first heating electrode layer 620A and a second heating electrode layer 620B, respectively, instead of the first heating electrode layer 520A and the second heating electrode layer 520B. The first heating electrode layer 620A and the second heating electrode layer 620B may include a first heating electrode layer 620A constituting the memory cell pillar P6A in the first area A1, and a second heating electrode layer 620B constituting the memory cell pillar P6B in the second area A2. The first heating electrode layer 620A may have a pin portion 620P1 in contact with the resistance type memory layer 130 in the first area A1, and the second heating electrode layer 620B may include a pin portion 620P2 in contact with the resistance type memory layer 130 in the second area A2. Reference Fig. 9 and Fig.10 , more detailed configurations of the first heating electrode layer 620A and the second heating electrode layer 620B may be substantially the same as those described with respect to the first heating electrode layer 520A and the second heating electrode layer 520B.

[0105] In the plurality of memory cell pillars P6A and P6B ​​of the memory device 600, a plurality of stacked structures may be arranged between the plurality of first conductive lines 110 and the plurality of first heating electrode layers 620A and second heating electrode layers 620B. Each stacked structure includes a first interface layer 152, a selection device layer 154, a second interface layer 156, and an electrode layer 160 stacked in sequence, and an insulating layer 162 may fill the space between the plurality of stacked structures. Therefore, the first interface layer 152 and the first conductive line 110 may contact each other, and the electrode layer 140 and the second conductive line 170 may contact each other.

[0106] Fig.12 7 is a cross-sectional view for explaining a memory device 700 according to an exemplary embodiment of the inventive concept. Fig.12 In, with FIG. 4A to FIG. 9 The same reference numerals in the drawings may denote the same elements, and thus repeated descriptions thereof are omitted. Fig.12 shows that along with Figure 4A The cross sections taken along the X1-X1' line and the X2-X2' line correspond to the components of the parts.

[0107] refer to Fig.12 , the memory device 700 may have a reference Fig. 9 The memory device 700 may have substantially the same configuration as the memory device 500 described above. Figure 3 The equivalent circuit configuration shown. However, the plurality of memory cell columns P7A and the plurality of memory cell columns P7B included in the memory cell array MCA of the memory device 700 may include a first heating electrode layer 720A and a second heating electrode layer 720B, respectively, instead of the first heating electrode layer 520A and the second heating electrode layer 520B. The first heating electrode layer 720A and the second heating electrode layer 720B may include a first heating electrode layer 720A constituting the memory cell column P7A in the first area A1, and a second heating electrode layer 720B constituting the memory cell column P7B in the second area A2. The first heating electrode layer 720A and the second heating electrode layer 720B may not be shared by two adjacent memory cell columns P7A and P7B, respectively.

[0108] The first heating electrode layer 720A may have a pin portion 720P1 in contact with the resistance type memory layer 130 in the first area A1, and the second heating electrode layer 720B may include a pin portion 720P2 in contact with the resistance type memory layer 130 in the second area A2. Fig. 9 and Fig.10 , more detailed configurations of the first heating electrode layer 720A and the second heating electrode layer 720B may be substantially the same as those described with respect to the first heating electrode layer 520A and the second heating electrode layer 520B.

[0109] In addition, the plurality of memory cell pillars P7A and P7B included in the memory cell array MCA of the memory device 700 may include a first insulating spacer 122P and a gap-filling insulating layer 124P instead of the first insulating spacer 122 and the gap-filling insulating layer 124. A more detailed configuration of the first insulating spacer 122P and the gap-filling insulating layer 124P is described with reference to FIG. Figure 7 The configuration described is the same.

[0110] Fig.13 8 is a cross-sectional view for explaining a memory device 800 according to an exemplary embodiment of the inventive concept. Fig.13 In, with FIG. 4A to FIG. 11 The same reference numerals in the drawings may denote the same elements, and thus, repeated descriptions thereof may be omitted. Fig.13 shows that along with Figure 4A The cross sections taken along the X1-X1' line and the X2-X2' line correspond to the components of the parts.

[0111] refer to Fig.13 , the memory device 800 may have a reference Fig.11 The memory device 600 described has substantially the same configuration. However, the plurality of memory cell pillars P8A and the plurality of memory cell pillars P8B included in the memory cell array MCA of the memory device 800 may include a first heating electrode layer 820A and a second heating electrode layer 820B, respectively, instead of the first heating electrode layer 620A and the second heating electrode layer 620B. The first heating electrode layer 820A and the second heating electrode layer 820B may include a first heating electrode layer 820A constituting the memory cell pillar P8A in the first area A1, and a second heating electrode layer 820B constituting the memory cell pillar P8B in the second area A2. The first heating electrode layer 820A and the second heating electrode layer 820B may not be shared by two adjacent memory cell pillars P8A and P8B.

[0112] The first heating electrode layer 820A may have a pin portion 820P1 in contact with the resistance type memory layer 130 in the first area A1, and the second heating electrode layer 820B may include a pin portion 820P2 in contact with the resistance type memory layer 130 in the second area A2. Fig. 9 and Fig.10 , more detailed configurations of the first heating electrode layer 820A and the second heating electrode layer 820B may be substantially the same as those described with respect to the first heating electrode layer 520A and the second heating electrode layer 520B.

[0113] In addition, the plurality of memory cell pillars P8A and P8B included in the memory cell array MCA of the memory device 800 may include first insulating spacers 122P and gap-filling insulating layers 124P, respectively, instead of the first insulating spacers 122 and the gap-filling insulating layers 124. A more detailed configuration of the first insulating spacers 122P and the gap-filling insulating layers 124P is described with reference to FIG. Figure 7 The configuration described is the same.

[0114] exist Figures 11 to 13 The memory devices 600, 700 and 800 shown (similar to those of reference Fig. 9 and Fig.10 In the memory device 500 described above, the contact resistance at the contact surface of the second heating electrode layers 620B, 720B, and 820B with the resistance type memory layer 130 may be greater than the contact resistance at the contact surface of the first heating electrode layers 620A, 720A, 820A with the resistance type memory layer 130. Therefore, the heating power in the second heating electrode layers 620B, 720B, and 820B may be increased, and thus the efficiency drop caused by the voltage drop caused by the IR drop in the second area A2 may be compensated.

[0115] FIG. 14A to FIG. 14J is a cross-sectional view illustrating a method of manufacturing a memory device according to an exemplary embodiment of the inventive concept. FIG. 14A to FIG. 14J Description Manufacturing FIG. 4A to FIG. 4C An example method of the memory device 100 shown in FIG. FIG. 14A to FIG. 14J shows the order of processing along with Figure 4A The components corresponding to the cross sections taken along the X1-X1' line and the X2-X2' line.

[0116] Reference Fig.14A The interlayer insulating layer 104 may be formed on the substrate 102 including the first region A1 and the second region A2, and a plurality of first conductive lines 110 and a plurality of first insulating patterns 112 (see Figure 4B ) may be formed on the interlayer insulating layer 104.

[0117] A plurality of first insulating wall portions 116A may be formed on the plurality of first conductive lines 110 and the plurality of first insulating patterns 112. The plurality of first insulating wall portions 116A may extend parallel to each other in the Y direction. The plurality of first insulating wall portions 116A may each have a first width W1 in the X direction and may be separated from each other by a first gap G1 therebetween. The first gap G1 may be approximately three times the first width W1.

[0118] Reference Fig. 14BIn the first area A1 and the second area A2, a preliminary heating electrode layer 120L may be formed, and the preliminary heating electrode layer 120L conformally covers the respective exposed surfaces of the plurality of first insulating wall portions 116A, the plurality of first conductive lines 110, and the plurality of first insulating patterns 112. The thickness of the preliminary heating electrode layer 120L in the first area A1 and the second area A2 may be substantially the same. The thickness of the preliminary heating electrode layer 120L may be the same as that to be formed in the first area A1 (see Figure 4B and Figure 4C ) have substantially the same thickness.

[0119] In an exemplary embodiment of the present inventive concept, a constituent material of the preliminary heating electrode layer 120L may be the same as a constituent material of the first heating electrode layer 120A to be formed in the first area A1.

[0120] Reference Fig. 14C , the first area A1 may be covered with the mask pattern M1, and in the second area A2, a composition-changed preliminary heating electrode layer 120M may be formed by using the mask pattern M1 as an ion implantation mask and implanting impurities IMP into the preliminary heating electrode layer 120L.

[0121] In an exemplary embodiment of the inventive concept, the mask pattern M1 may have a photoresist pattern. In an exemplary embodiment of the inventive concept, the impurity IMP may include a non-metallic element or a metalloid element. For example, the impurity IMP may include a nitrogen atom or a silicon atom.

[0122] Reference Fig.14D , in execution Fig. 14C After the process of removing the mask pattern M1 covering the first area A1 to expose the preliminary heating electrode layer 120L, a first insulating spacer layer 122L and a preliminary gap filling insulating layer 124L may be formed on the resulting structure. The preliminary gap filling insulating layer 124L may fill the space between the plurality of first insulating wall portions 116A on the first insulating spacer layer 122L. The constituent materials of the first insulating spacer layer 122L and the preliminary gap filling insulating layer 124L are the same as those of the reference FIG. 4A to FIG. 4C The first insulating spacers 122 and the gap-fill insulating layer 124 are described as being composed of the same material.

[0123] Reference Fig.14E , by Fig.14DThe resulting structure removes portions of the top surfaces of the plurality of first insulating wall portions 116A to expose the respective top surfaces of the plurality of first insulating wall portions 116A, and the preliminary heating electrode layer 120L, the preliminary heating electrode layer 120M with a changed composition, the first insulating spacer layer 122L, and the preliminary gap-filling insulating layer 124L may remain between the plurality of first insulating wall portions 116A. While removing the above portions, the thickness of each component arranged between the plurality of first insulating wall portions 116A and the thickness of the plurality of first insulating wall portions 116A may be reduced. In order to remove the above portions, a chemical mechanical polishing (CMP) process or an etch-back process may be performed.

[0124] Next, a plurality of etching mask patterns may be formed on the resulting structure, and the structures exposed by the plurality of etching mask patterns may be etched to form a plurality of linear stacked structures including a first insulating wall portion 116A, a preliminary heating electrode layer 120L, a preliminary heating electrode layer 120M of a changed composition, a first insulating spacer layer 122L, and the remaining portion of the preliminary gap-filling insulating layer 124L. Similar to the plurality of first conductive lines 110, the plurality of etching mask patterns may include a plurality of line patterns extending parallel to each other in the X direction. In an exemplary embodiment of the present inventive concept, the plurality of etching mask patterns may include polysilicon. Next, a plurality of second insulating wall portions 116B (refer to Figure 4B ), and then, the plurality of etching mask patterns may be removed. An insulating layer having a thickness sufficient to fill the linear spaces between the plurality of stacked structures may be formed to form a plurality of second insulating wall portions 116B, and then, portions of the insulating layer may be removed by CMP or an etch-back process. While removing portions of the insulating layer, the heights of the plurality of first insulating wall portions 160A, the preliminary heating electrode layer 120L, the preliminary heating electrode layer 120M with a changed composition, the first insulating spacer layer 122L, and the preliminary gap filling insulating layer 124L may also be reduced. The preliminary gap filling insulating layer 124L with a reduced height may be retained as the gap filling insulating layer 124.

[0125] Reference Fig.14F , by Fig.14EA specific thickness is selectively etched in the respective top surfaces of the first insulating spacer layer 122L, the preliminary heating electrode layer 120L, and the preliminary heating electrode layer 120M with a changed composition in the resulting structure, the first insulating spacer 122 may be formed of the first insulating spacer layer 122L, and the first heating electrode layer 120A and the second heating electrode layer 120B may be formed of the preliminary heating electrode layer 120L and the preliminary heating electrode layer 120M with a changed composition. On the respective top surfaces of the first heating electrode layer 120A and the second heating electrode layer 120B, a plurality of spaces SP1 may be reserved, and the plurality of spaces SP1 are provided between the plurality of first insulating wall portions 116A or the plurality of second insulating wall portions 116B.

[0126] Reference Figure 14G , a resistance type memory layer 130 and an electrode layer 140 may be formed, and the resistance type memory layer 130 and the electrode layer 140 fill the space SP1 on the first heating electrode layer 120A and the second heating electrode layer 120B, respectively.

[0127] Reference Fig.14H In the resulting structure in which the electrode layer 140 is formed, a preliminary first interface layer 152L, a preliminary selection device layer 154L, a preliminary second interface layer 156L, and a preliminary electrode layer 160L may be sequentially formed.

[0128] Reference Fig.14I , by patterning the prepared first interface layer 152L, the prepared selection device layer 154L, the prepared second interface layer 156L and the prepared electrode layer 160L and then filling the insulating layer 162 between the plurality of stacked structures, a plurality of stacked structures can be formed, in which the first interface layer 152, the selection device layer 154, the second interface layer 156 and the electrode layer 160 are sequentially stacked. The plurality of stacked structures can be arranged in a matrix shape on the plurality of memory cells MC on the plurality of electrode layers 140 in a plan view (refer to Figure 4A ) at the corresponding position.

[0129] Reference Fig.14J , can be achieved by Fig.14I A plurality of second conductive lines 170 and a plurality of second insulating patterns 172 are formed on the resulting structure to form the memory device 100 .

[0130] Already referenced FIG. 14A to FIG. 14J Describes the manufacturing FIG. 4A to FIG. 4C However, having Figures 6 to 8 The structures of the memory devices 200, 300, and 400 shown or various other structures of memory devices within the scope of the inventive concept can be obtained by using reference FIG. 14A to FIG. 14J The invention can be manufactured by the described manufacturing process or various other methods within the scope of the present invention.

[0131] For example, to make Figure 6 The memory device 200 shown in FIG. Fig.14A After forming the plurality of first conductive lines 110 and the plurality of first insulating patterns 112 by the method described above, and before forming the plurality of first insulating wall portions 116A, by performing the steps of referring to Fig.14H and Fig.14I The processes described above can form a plurality of stacked structures in which the first interface layer 152, the selection device layer 154, the second interface layer 156 and the electrode layer 160 are directly stacked in sequence on the plurality of first conductive lines 110. Through these processes, the insulating layer 162 is also filled in the space between the plurality of stacked structures. Next, by performing reference Fig.14A The process of forming the plurality of first insulating wall portions 116A described and reference FIG. 14B to FIG. 14G The process described above can form a structure including a first heating electrode layer 120A and a second heating electrode layer 120B, which are arranged in a space defined by a plurality of first insulating wall portions 116A and a plurality of second insulating wall portions 116B in a plurality of stacked structures. The space in which the first heating electrode layer 120A and the second heating electrode layer 120B are arranged can also be defined by the resistive memory layer 130 and the electrode layer 140. Next, by using reference Fig.14J According to the described method, a plurality of second conductive lines 170 and a plurality of second insulating patterns 172 may be formed on the plurality of electrode layers 140 .

[0132] To manufacture Figure 7 The memory device 300 shown in FIG. FIG. 14A to FIG. 14D After the described method completes the process of forming the first insulating spacer layer 122L covering the preliminary heating electrode layer 120L and the preliminary heating electrode layer 120M with a changed composition, an etching process may be performed to separate each of the preliminary heating electrode layer 120L, the preliminary heating electrode layer 120M with a changed composition, and the first insulating spacer layer 122L. Then, the preliminary gap filling insulating layer 124L may fill the space between the preliminary heating electrode layer 120L and the first insulating spacer layer 122L, and the space between the preliminary heating electrode layer 120M with a changed composition and the first insulating spacer layer 122L. Next, the reference etching may be performed. FIG. 14E to FIG. 14J Other processes described.

[0133] To manufacture Figure 8 The memory device 400 shown can be combined and applied Figure 6 The memory device 200 is manufactured by the method and Figure 7 1 and 2. A method for manufacturing the memory device 300 is shown.

[0134] FIG. 15A to FIG. 15D is a cross-sectional view illustrating a method of manufacturing a memory device 500 according to an exemplary embodiment of the inventive concept. FIG. 15A to FIG. 15D describe Fig. 9 An example method of manufacturing the memory device 500 is shown in FIG. FIG. 15A to FIG. 15D shows the order of processing along with Figure 4A The components corresponding to the cross sections taken along the X1-X1' line and the X2-X2' line.

[0135] Reference Fig.15A , you can refer to Fig.14A The described method forms an interlayer insulating layer 104 on a substrate 102, and can form a plurality of first conductive lines 110 and a plurality of first insulating patterns 112 that insulate the plurality of first conductive lines 110 from each other (see Figure 4B ) and a plurality of first insulating wall portions 116A. Then, in accordance with the reference Fig. 14B In a method similar to the method described above, a first preliminary heating electrode layer 520L1 can be formed, which conformally covers the plurality of first insulating wall portions 116A, the plurality of first conductive lines 110, the plurality of first insulating patterns 112 (see Figure 4B ) is exposed to the surface of the first preliminary heating electrode layer 520L1. Fig. 14B The description of the preliminary heating electrode layer 120L is substantially the same. However, the thickness of the first preliminary heating electrode layer 520L1 may be smaller than the first heating electrode layer 520A to be formed in the first area A1 (see Fig. 9 ) required thickness.

[0136] Reference Fig. 15B , the first region A1 may be covered with a mask pattern M2, and the first preliminary heating electrode layer 520L1 may be removed from the second region A2 by using the mask pattern M2 as an etching mask. The mask pattern M2 may have a photoresist pattern. The first preliminary heating electrode layer 520L1 in the second region A2 may be removed using a wet etching process.

[0137] Reference Fig. 15C , through from Fig. 15B After removing the mask pattern M2 covering the first area A1 and exposing the first preliminary heating electrode layer 520L1 in the first area A1, the mask pattern M2 covering the first area A1 is removed to expose the first preliminary heating electrode layer 520L1 in the first area A1. Fig. 14B Similar to the method described for the preliminary heating electrode layer 120L, the second preliminary heating electrode layer 520L2 may be formed in the first area A1 and the second area A2.

[0138] The second preliminary heating electrode layer 520L2 may be formed to conformally cover the first preliminary heating electrode layer 520L1 in the first region A1, and the plurality of first insulating wall portions 116A, the plurality of first conductive lines 110, and the plurality of first insulating patterns 112 in the second region A2 (refer to Figure 4B ) of each of the exposed surfaces. A more detailed configuration of the second preliminary heating electrode layer 520L2 is similar to that of reference Fig. 14B The same is basically the same as described for the preliminary heating electrode layer 120L. However, the thickness of the second preliminary heating electrode layer 520L2 in the first and second regions A1 and A2 may be smaller than the first heating electrode layer 520A to be formed in the first region A1 (see Fig. 9 In the first area A1, the sum of the thickness of the first preliminary heating electrode layer 520L1 and the thickness of the second preliminary heating electrode layer 520L2 may be equal to the thickness of the first heating electrode layer 520A (see Fig. 9 The thickness of the second preliminary heating electrode layer 520L2 may be substantially the same as the thickness of the second heating electrode layer 520B to be formed in the second region A2 (see Fig. 9 )The required thickness is basically the same.

[0139] Reference Fig.15D , by executing the reference Fig.14D and Fig.14E The process described Fig. 15C The resulting structure may form a first insulating spacer layer 122L and a gap-filling insulating layer 124 that cover the second preliminary heating electrode layer 520L2 in the first and second regions A1 and A2.

[0140] Next, you can reference FIG. 14F to FIG. 14J Described process to manufacture Fig. 9 The memory device 500 shown in FIG. Here, Fig. 9 The first heating electrode layer 520A shown may be formed from a Fig.15D The first preliminary heating electrode layer 520L1 and the second preliminary heating electrode layer 520L2 in the first region A1 of the resulting structure are obtained. Fig. 9 The second heating electrode layer 520B shown may be obtained from the Fig.15D A second preliminary heating electrode layer 520L2 in the second area A2 of the resulting structure is obtained.

[0141] To manufacture Figures 11 to 13 The memory devices 600, 700 and 800 shown in FIG. 1 may be used to refer to FIG. 15A to FIG. 15D Process described, reference FIG. 14A to FIG. 14J Described process, and combined manufacturing Figures 6 to 8 The above-described methods of the memory devices 200, 300, and 400 shown in FIG.

[0142] By providing a large contact resistance in a heating electrode layer arranged in an area with a relatively large distance from an access point to which a voltage is applied, even if a voltage drop caused by an IR drop occurs in an area with a relatively large distance from the access point, a resistance-type memory device according to an exemplary embodiment of the inventive concept can increase heating power. Therefore, a decrease in efficiency due to a voltage drop caused by an IR drop can be compensated, and a reduction in an operating margin in an area with a relatively large distance from the access point can be prevented. Therefore, the reliability of the memory device can be increased, and a higher speed and a larger capacity of the memory device can be obtained.

[0143] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, the inventive concept is not limited thereto and various changes and modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the inventive concept as defined in the appended claims.

Claims

1. A resistive memory device, comprising: A plurality of first conductive lines extending in a first direction; A plurality of second conductive lines extending in a second direction intersecting the first direction; as well as a plurality of memory cells connected to the plurality of first conductive lines and the plurality of second conductive lines, Wherein, the plurality of memory units include: a first memory cell including a first resistance type memory layer and a first heating electrode layer, wherein the first heating electrode layer includes a first contact surface contacting the first resistance type memory layer, and the first contact surface has a first contact resistance; and a second memory cell including a second resistance type memory layer and a second heating electrode layer, wherein the second heating electrode layer includes a second contact surface contacting the second resistance type memory layer, and the second contact surface has a second contact resistance different from the first contact resistance, and The thickness of the second heating electrode layer is smaller than that of the first heating electrode layer.

2. The resistive memory device according to claim 1, wherein: An area of ​​the first contact surface is different from an area of ​​the second contact surface.

3. The resistive memory device according to claim 1, wherein: The composition of the first heating electrode layer is different from the composition of the second heating electrode layer.

4. The resistive memory device according to claim 1, wherein: The first heating electrode layer includes a material having a first resistivity, and the second heating electrode layer includes a material having a second resistivity different from the first resistivity.

5. The resistive memory device according to claim 1, further comprising: A driver is configured to apply a voltage to an access point of each of the plurality of first conductive lines, wherein a first current path from the access point to the first memory cell and a second current path from the access point to the second memory cell have different lengths from each other.

6. The resistive memory device according to claim 5, wherein: The second current path is longer than the first current path, and an area of ​​the second contact surface is smaller than an area of ​​the first contact surface.

7. The resistive memory device according to claim 5, wherein: The second current path is longer than the first current path, and the resistivity of the second heating electrode layer is greater than the resistivity of the first heating electrode layer.

8. The resistive memory device according to claim 5, wherein: The second current path is longer than the first current path, the first heating electrode layer and the second heating electrode layer both include a first metal, and a content ratio of the first metal in the second heating electrode layer is smaller than a content ratio of the first metal in the first heating electrode layer.

9. The resistive memory device according to claim 5, wherein: The second current path is longer than the first current path, the first heating electrode layer and the second heating electrode layer both include nitrogen atoms, and a content ratio of the nitrogen atoms in the second heating electrode layer is greater than a content ratio of the nitrogen atoms in the first heating electrode layer.

10. The resistive memory device according to claim 5, wherein: The second current path is longer than the first current path, the first heating electrode layer and the second heating electrode layer both include silicon atoms, and a content ratio of the silicon atoms in the second heating electrode layer is greater than a content ratio of the silicon atoms in the first heating electrode layer.

11. A resistive memory device, comprising: A first conductor includes an access point to which a voltage is applied; as well as a plurality of memory cells connected to the first conductive line, Wherein, the plurality of memory units include: a first memory unit arranged at a first distance from the access point, the first memory unit comprising a first resistance type memory layer and a first heating electrode layer, the first heating electrode layer comprising a first contact surface contacting the first resistance type memory layer, and the first contact surface having a first contact resistance; and a second memory unit arranged at a second distance from the access point, the second distance being greater than the first distance, the second memory unit comprising a second resistance type memory layer and a second heating electrode layer, the second heating electrode layer comprising a second contact surface contacting the second resistance type memory layer, and the second contact surface having a second contact resistance different from the first contact resistance, and The resistivity of the second heating electrode layer is greater than the resistivity of the first heating electrode layer.

12. The resistive memory device according to claim 11, wherein: A content ratio of at least one element selected from nonmetallic elements and metalloid elements in the second heating electrode layer is greater than a content ratio of the at least one element in the first heating electrode layer.

13. The resistive memory device according to claim 11, wherein: An area of ​​the second contact surface is smaller than an area of ​​the first contact surface.

14. A resistive memory device, comprising: A plurality of first conductive lines extending in a first region and a second region along a first direction, the first region and the second region being spaced apart from each other on the substrate; A plurality of second conductive lines extending in the first region and the second region along a second direction, wherein the second direction intersects the first direction; as well as a plurality of memory cells connected to the first conductive line and the second conductive line in the first region and the second region, Wherein, the plurality of memory units include: a first memory cell including a first heating electrode layer disposed in the first region and having a first resistance; and a second memory cell including a second heating electrode layer arranged in the second region and having a second resistance greater than the first resistance, and The plurality of memory cells include: a pair of first memory cells arranged in the first region and configured to share the first heating electrode layer; and a pair of second memory cells arranged in the second region and configured to share the second heating electrode layer.

15. The resistive memory device according to claim 14, wherein: One of the plurality of first conductive lines includes an access point to which a voltage is applied, and a distance from the access point to the second heating electrode layer is greater than a distance from the access point to the first heating electrode layer.

16. The resistive memory device according to claim 14, wherein: A content ratio of at least one element selected from nonmetallic elements and metalloid elements in the second heating electrode layer is greater than a content ratio of the at least one element in the first heating electrode layer.

17. The resistive memory device according to claim 14, wherein: The first heater electrode layer includes a first lead portion extending in a direction away from the substrate, and the second heater electrode layer includes a second lead portion extending in a direction away from the substrate, and a thickness of the second lead portion is smaller than a thickness of the first lead portion.

18. A resistive memory device, comprising: a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction intersecting the first direction; a first memory cell connected to a first word line and a first bit line; as well as a second memory cell connected to the first word line and a second bit line, wherein the first memory cell is arranged closer to the access point of the first word line than the second memory cell, the first memory cell comprises a first heating layer directly in contact with the first resistive material layer, the second memory cell comprises a second heating layer directly in contact with the second resistive material layer, and A contact resistance greater than that between the first heating layer and the first resistive material layer is provided between the second heating layer and the second resistive material layer.

19. The resistive memory device according to claim 18, wherein: A voltage is supplied from a driving circuit to the access point.

20. The resistive memory device according to claim 18, wherein: The first heating layer includes a material having a first resistivity, and the second heating layer includes a material having a second resistivity different from the first resistivity.

21. The resistive memory device according to claim 18, wherein: The first resistive material layer and the second resistive material layer include phase change material.

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