Display device and method of manufacturing the same

Abstract

A display device and a method for manufacturing the display device are provided. The display device may include: an insulating layer; a wiring directly contacting the insulating layer; a first electrode stacked with the insulating layer; an organic light-emitting layer located on the first electrode; and a second electrode located on the organic light-emitting layer. The wiring may include an aluminum alloy including at least one of copper, vanadium and silicon. The first electrode may include silver.

Description

[0001] The technical field relates to a display device and a method of manufacturing the display device. Background Art

[0002] A display device such as an organic light emitting display device may include an organic light emitting element formed in a display area, and may include wiring formed in a peripheral area adjacent to the display area for transmitting signals to the organic light emitting element. The organic light emitting element may include electrodes and an organic light emitting layer disposed between the electrodes.

[0003] When etching the conductive layer to form the electrode of the organic light emitting element, the wiring and the conductive layer are electrochemically corroded. As a result, undesirable conductive particles are formed on the wiring, resulting in an undesirable short circuit between the wiring and the adjacent conductive member. The short circuit adversely affects the performance of the display device. Summary of the invention

[0004] Embodiments may relate to a display device including a wiring that is not significantly corroded during an etching process of a conductive layer.

[0005] Embodiments may relate to a method of manufacturing a display device in which corrosion of wirings may be minimized during etching of a conductive layer.

[0006] According to an embodiment, a display device may include: a wiring located on a substrate, the wiring including an aluminum (Al) alloy including any one of copper (Cu), vanadium (V) and silicon (Si); a first electrode located on the wiring, the first electrode including silver (Ag); an organic light-emitting layer located on the first electrode; and a second electrode located on the organic light-emitting layer.

[0007] In an embodiment, the wiring may include an aluminum-copper alloy, and the aluminum-copper alloy may include about 0.2 at % to about 3.0 at % copper.

[0008] In an embodiment, the wiring may include an aluminum-copper alloy, and the aluminum-copper alloy may include about 0.2 at % to about 1.0 at % copper.

[0009] In an embodiment, the wiring may include an aluminum-vanadium alloy, which may include up to about 4.0 at % vanadium.

[0010] In an embodiment, the display device may further include a thin film transistor located between the substrate and the first electrode, the thin film transistor including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode.

[0011] In an embodiment, the wiring may be located on the same layer as the source electrode and the drain electrode above the substrate.

[0012] In an embodiment, the display device may further include a pad electrode formed integrally with the wiring at an end of the wiring.

[0013] In an embodiment, the wiring may be located on the same layer as the source electrode, the drain electrode, and the pad electrode above the substrate.

[0014] In an embodiment, the wiring may include a first layer, a second layer, and a third layer sequentially stacked, the first layer and the third layer may include titanium (Ti), and the second layer may include an aluminum alloy.

[0015] In an embodiment, the first electrode may include a first layer, a second layer, and a third layer sequentially stacked, the first layer and the third layer may include indium tin oxide (ITO), and the second layer may include silver (Ag).

[0016] According to an embodiment, a display device may include: a wiring located on a substrate, the wiring including an aluminum (Al) alloy containing at least one of indium (In), gallium (Ga), phosphorus (P), and thallium (Tl); a first electrode located on the wiring, the first electrode including silver (Ag); an organic light-emitting layer located on the first electrode; and a second electrode located on the organic light-emitting layer.

[0017] In an embodiment, the wiring may include an aluminum indium gallium phosphide thallium alloy, and the aluminum indium gallium phosphide thallium alloy may include about 0.1 at % indium, about 0.2 at % gallium, about 0.1 at % phosphorus, and about 0.01 at % thallium.

[0018] According to an embodiment, a method for manufacturing a display device may include: forming a wiring on a substrate, the wiring including an aluminum (Al) alloy including any one of copper (Cu), vanadium (V), and silicon (Si); forming a first electrode on the wiring, the first electrode including silver (Ag); forming an organic light-emitting layer on the first electrode; and forming a second electrode on the organic light-emitting layer.

[0019] In an embodiment, the wiring may include an aluminum-copper alloy, and the aluminum-copper alloy may include about 0.2 at % to about 3.0 at % copper.

[0020] In an embodiment, the wiring may include an aluminum-copper alloy, and the aluminum-copper alloy may include about 0.2 at % to about 1.0 at % copper.

[0021] In an embodiment, the wiring may include an aluminum-vanadium alloy, and the aluminum-vanadium alloy may include less than about 4.0 at % vanadium.

[0022] In an embodiment, the step of forming the first electrode may include: forming a first electrode material layer including silver on the wiring; and etching a portion of the first electrode material layer covering the wiring by using an etchant.

[0023] In an embodiment, the first electrode material layer may react with an etchant to form silver ions (Ag +), and the silver ions can come into contact with the wiring.

[0024] In an embodiment, the wiring may include a first layer, a second layer, and a third layer sequentially stacked, the first layer and the third layer may include titanium (Ti), and the second layer may include an aluminum alloy.

[0025] In an embodiment, the silver ions may contact the side of the second layer of the wiring.

[0026] Embodiments may be directed to a display device. The display device may include: an insulating layer; a wiring directly contacting a surface of the insulating layer; a first electrode stacked with the insulating layer; an organic light-emitting layer located on the first electrode; and a second electrode located on the organic light-emitting layer. The wiring may be formed of or include an aluminum alloy including at least one of copper, vanadium, and silicon. The first electrode may be formed of or include silver.

[0027] The wiring may include an aluminum-copper alloy. The aluminum-copper alloy may include copper in a range of 0.2 at % to 3.0 at %.

[0028] The wiring may include an aluminum-copper alloy. The aluminum-copper alloy may include copper in a range of 0.2 at % to 1.0 at %.

[0029] The wiring may include an aluminum-vanadium alloy. The aluminum-vanadium alloy may include up to 4.0 at % vanadium.

[0030] The display device may include a thin film transistor electrically connected to the first electrode. The thin film transistor may include a semiconductor layer, a gate electrode, a source electrode, and a drain electrode.

[0031] A surface of the insulating layer may be in direct contact with each of the source electrode and the drain electrode.

[0032] The display device may include a pad electrode which is integrally formed with the wiring at an end portion of the wiring and is wider than the wiring in a width direction of the wiring.

[0033] A surface of the insulating layer may be in direct contact with each of the source electrode, the drain electrode, and the pad electrode.

[0034] The wiring may include a first layer, a second layer, and a third layer. The second layer may be located between the first layer and the third layer. The first layer and the third layer may each include titanium. The second layer may include an aluminum alloy.

[0035] The first electrode may include a first layer, a second layer and a third layer. The second layer may be located between the first layer and the third layer. The first layer and the third layer may each include indium tin oxide. The second layer may include silver.

[0036] Embodiments may be directed to a display device. The display device may include: a substrate; a wiring, overlapping the substrate; a first electrode, overlapping the substrate and electrically insulated from the wiring; an organic light-emitting layer, located on the first electrode; and a second electrode, located on the organic light-emitting layer. The wiring may include an aluminum alloy containing at least one of indium, gallium, phosphorus, and thallium. The first electrode may include silver.

[0037] The wiring may include an aluminum indium gallium phosphide thallium alloy. The aluminum indium gallium phosphide thallium alloy may include at most 0.1 at% indium, at most 0.2 at% gallium, at most 0.1 at% phosphorus, and at most 0.01 at% thallium.

[0038] Embodiments may be directed to a method of manufacturing a display device. The method may include the following steps: forming a wiring on a substrate, the wiring including an aluminum alloy including at least one of copper, vanadium, and silicon; forming a first electrode on the substrate, the first electrode including silver; forming an organic light-emitting layer on the first electrode; and forming a second electrode on the organic light-emitting layer.

[0039] The wiring may include an aluminum-copper alloy. The aluminum-copper alloy may include copper in a range of 0.2 at % to 3.0 at %.

[0040] The wiring may include an aluminum-copper alloy. The aluminum-copper alloy may include copper in a range of 0.2 at % to 1.0 at %.

[0041] The wiring may include an aluminum-vanadium alloy. The aluminum-vanadium alloy may include up to 4.0 at % vanadium.

[0042] The step of forming the first electrode may include the steps of: forming a first electrode material layer including silver on a planarization layer, wherein the planarization layer is located on a substrate; and etching a portion of the first electrode material layer using an etchant, wherein the planarization layer exposes the wiring during etching.

[0043] The first electrode material layer reacts with the etchant to form silver ions, which can directly contact the wiring.

[0044] The wiring may include a first layer, a second layer, and a third layer. The second layer may be located between the first layer and the third layer. The first layer and the third layer may each include titanium. The second layer may include an aluminum alloy.

[0045] The silver ions may be in direct contact with the side of the second layer of the wiring.

[0046] The display device according to the embodiment may include a wiring including an aluminum alloy so that the wiring is not significantly corroded and / or a minimum amount of undesirable silver particles may be formed on the wiring. Advantageously, undesirable short circuits between adjacent wirings may be prevented.

[0047] In the method of manufacturing a display device according to an embodiment, the wiring may be formed of an aluminum alloy so that the wiring is not significantly corroded and / or a minimum amount of undesirable silver particles may be formed on the wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a plan view showing a display device according to an embodiment.

[0049] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A plan view of a display area and a non-display area of ​​a display device in FIG.

[0050] Figure 3 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A cross-sectional view of a display area and a non-display area of ​​a display device in FIG.

[0051] Figure 4 is a graph showing the corrosion potential of an aluminum-copper alloy according to an embodiment according to the copper content.

[0052] Figure 5 is a graph showing resistivity of an aluminum-copper alloy according to an embodiment according to copper content.

[0053] Figure 6 is a graph showing the corrosion potential of an aluminum-copper alloy according to an embodiment according to the copper content.

[0054] Figure 7 is a graph showing the pitting potential of the aluminum-vanadium alloy according to the embodiment according to the vanadium content.

[0055] Figure 8 , Fig. 9 , Fig.10 and Fig.11 is a cross-sectional view illustrating a structure formed in a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0056] Example embodiments are described with reference to the accompanying drawings. Although the terms "first", "second", etc. can be used here to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, without departing from the teaching of one or more embodiments, the first element can be called the second element. Describing an element as a "first" element may not require or mean the existence of a second element or other elements. Here, the terms "first", "second", etc. can also be used to distinguish different types or different groups of elements. For simplicity, the terms "first", "second", etc. can represent "first type (or first group)", "second type (or second group)", etc. respectively.

[0057] The term “comprising” may mean “formed by…”; the term “contacting” may mean “directly contacting” or “directly contacting”; and the term “connecting” may mean “electrically connected”.

[0058] Figure 1 is a plan view showing a display device according to an embodiment.

[0059] Reference Figure 1 , the display device may include a display area DA and a non-display area NDA. A plurality of pixels PX may be disposed in the display area DA. The display area DA may display an image based on light emitted from each pixel PX.

[0060] The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may be located on at least one side of the display area DA. For example, the non-display area NDA may surround the display area DA. The non-display area NDA may include a pad area PA in which a plurality of conductive pads (or "pads") may be disposed.

[0061] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A plan view of a display area DA and a non-display area NDA of a display device in FIG. Figure 2 It can be shown Figure 1 Area A of the display device. Figure 3 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A cross-sectional view of a display area DA and a non-display area NDA of a display device in FIG. Figure 3 It can be shown Figure 2 A cross-sectional view of the display device taken along line II' and line II-II'.

[0062] Reference Figure 2 and Figure 3 The display device may include a substrate 110 , a thin film transistor TFT, a wiring 160 , a pad electrode 170 , a first electrode 180 , an organic light emitting layer 210 , and a second electrode 220 .

[0063] The substrate 110 may be a transparent or opaque insulating substrate. For example, the substrate 110 may include glass or plastic such as at least one of polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyacrylate, etc.

[0064] The buffer layer 115 may be disposed on the substrate 110. The buffer layer 115 may be located in the display area DA and the non-display area NDA. The buffer layer 115 may block impurities such as oxygen, moisture, etc. from affecting the thin film transistor TFT. In addition, the buffer layer 115 may provide a planarized surface on the substrate 110. The buffer layer 115 may include silicon nitride, silicon oxide, silicon oxynitride, etc. In an embodiment, the buffer layer 115 may be optional.

[0065] The thin film transistor TFT may be disposed on the buffer layer 115. The thin film transistor TFT may be located in the display area DA. The thin film transistor TFT may include a semiconductor layer 120, a gate electrode 130, a source electrode 140, and a drain electrode 150. In an embodiment, the thin film transistor TFT may have a top gate structure in which the gate electrode 130 is located above the semiconductor layer 120 with reference to the substrate 110. In an embodiment, the thin film transistor TFT may have a bottom gate structure in which the gate electrode is located below the semiconductor layer with reference to the substrate 110.

[0066] The semiconductor layer 120 may be disposed on the buffer layer 115. The semiconductor layer 120 may include amorphous silicon, polycrystalline silicon, an oxide semiconductor, etc. The semiconductor layer 120 may include a source region, a drain region, and a channel region formed between the source region and the drain region.

[0067] A gate insulating layer 125 covering the semiconductor layer 120 may be disposed on the buffer layer 115. The gate insulating layer 125 may be located in the display area DA and the non-display area NDA. The gate insulating layer 125 may insulate the gate electrode 130 from the semiconductor layer 120. The gate insulating layer 125 may include silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0068] The gate electrode 130 may be disposed on the gate insulating layer 125. The gate electrode 130 may overlap the channel region of the semiconductor layer 120. The gate electrode 130 may include a metal or an alloy such as at least one of molybdenum (Mo), aluminum (Al), and copper (Cu).

[0069] An insulating interlayer 135 covering the gate electrode 130 may be disposed on the gate insulating layer 125. The insulating interlayer 135 may be located in the display area DA and the non-display area NDA. The insulating interlayer 135 may insulate the source electrode 140 and the drain electrode 150 from the gate electrode 130. The insulating interlayer 135 may include silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0070] The source electrode 140 and the drain electrode 150 may be disposed on the insulating interlayer 135. Through contact holes formed in the insulating interlayer 135 and the gate insulating layer 125, the source electrode 140 and the drain electrode 150 may be connected to a source region and a drain region of the semiconductor layer 120, respectively.

[0071] The wiring 160 may be disposed on the insulating interlayer 135. The wiring 160 may be located in the non-display area NDA.

[0072] In an embodiment, the wiring 160 may be disposed on substantially the same layer as the source electrode 140 and the drain electrode 150 over the substrate 110. For example, the source electrode 140, the drain electrode 150, and the wiring 160 may be disposed on the same surface of the insulating interlayer 135 and may be in direct contact with the same surface of the insulating interlayer 135.

[0073] The pad electrode 170 may be disposed on the insulating interlayer 135. The pad electrode 170 may be located in the non-display area NDA. The pad electrode 170 may be integrally formed with the wiring 160 at an end of the wiring 160 and may be formed of the same material as the wiring 160.

[0074] In an embodiment, the wiring 160 may be disposed on substantially the same layer as the source electrode 140, the drain electrode 150, and the pad electrode 170 over the substrate 110. For example, the source electrode 140, the drain electrode 150, the wiring 160, and the pad electrode 170 may be disposed on the same surface of the insulating interlayer 135 and may be in direct contact with the same surface of the insulating interlayer 135.

[0075] The wiring 160 may include an aluminum (Al) alloy. Since the wiring 160 includes an aluminum alloy, although silver ions (Ag + ) will be in direct contact with wiring 160, but wiring 160 will not be significantly corroded.

[0076] In an embodiment, the source electrode 140, the drain electrode 150, the wiring 160, and the pad electrode 170 may include substantially the same material. In an embodiment, like the wiring 160, the source electrode 140, the drain electrode 150, and the pad electrode 170 may include an aluminum alloy.

[0077] In an embodiment, the aluminum alloy included in the wiring 160 may include at least one of copper (Cu), vanadium (V), and silicon (Si).

[0078] In an embodiment, the wiring 160 may include an aluminum-copper (Al—Cu) alloy.

[0079] The corrosion potential of silver (Ag) can be between about -0.2V and about -0.1V, and the corrosion potential of aluminum (Al) can be between about -1.0V and about -0.8V. When two materials with significantly different corrosion potentials come into contact with each other, the reaction between the two materials will proceed rapidly and cause significant corrosion of the materials. For example, when aluminum and silver ions (Ag + ) contact, the aluminum particles will be oxidized to form aluminum ions (Al 3+), and silver ions (Ag + ) will be reduced to form silver particles. 3+ ) is formed, so aluminum will be significantly corroded.

[0080] The corrosion potential of the aluminum-copper alloy may be higher than that of aluminum, and therefore, the difference between the corrosion potentials of the aluminum-copper alloy and silver may be smaller than the difference between the corrosion potentials of aluminum and silver. + ) contact, but the reaction will not be large, or may be slow. Therefore, the corrosion of the wiring 160 can be substantially prevented or minimized.

[0081] Figure 4 is a graph showing the corrosion potential of an aluminum-copper alloy according to an embodiment according to the copper content. Figure 5 is a graph showing resistivity of an aluminum-copper alloy according to an embodiment according to copper content. Figure 6 is a graph showing the corrosion potential of an aluminum-copper alloy according to an embodiment according to the copper content.

[0082] In an embodiment, the aluminum-copper alloy included in the wiring 160 may include copper in a range of about 0.2 at % to about 3.0 at %.

[0083] Reference Figure 4 , the corrosion potential of the aluminum-copper alloy can increase as the copper content of the aluminum-copper alloy increases. If the aluminum-copper alloy has a copper content less than about 0.2 at%, then the corrosion potential of the aluminum-copper alloy will only increase slightly relative to the corrosion potential of aluminum. Therefore, when the aluminum-copper alloy is combined with silver ions (Ag + ) will corrode. If the aluminum-copper alloy has a copper content greater than about 0.2 at%, the corrosion potential of the aluminum-copper alloy can be significantly increased relative to the corrosion potential of aluminum. + ) contact, the aluminum-copper alloy is not substantially corroded. According to an embodiment, the copper content of the aluminum-copper alloy included in the wiring 160 may be at least about 0.2 at %, so that the corrosion of the wiring 160 can be substantially prevented or minimized.

[0084] Reference Figure 5 , when the copper content of the aluminum-copper alloy increases, the resistivity of the aluminum-copper alloy increases. If the resistivity of the wiring increases, the signal transmitted through the wiring will be delayed. In order to prevent the increase in wiring resistance, it is necessary to increase the thickness of the wiring. If the increase in wiring resistance is greater than about 10%, the wiring will not be suitable for transmitting signals. According to an embodiment, the copper content of the aluminum-copper alloy included in the wiring 160 can be up to about 3.0at%, so that a significant increase in the resistivity of the wiring 160 can be prevented.

[0085] In an embodiment, the aluminum-copper alloy included in the wiring 160 may include copper in a range of about 0.2 at % to about 1.0 at % for minimal corrosion and sufficient conductivity.

[0086] Reference Figure 6 , the increase in the corrosion potential of the aluminum-copper alloy relative to the increase in the copper content of the aluminum-copper alloy can vary. When the copper content of the aluminum-copper alloy is less than about 1.0 at%, the slope of the increase in the corrosion potential of the aluminum-copper alloy relative to the increase in the copper content of the aluminum-copper alloy can be large. When the copper content of the aluminum-copper alloy is greater than about 1.0 at%, the slope of the increase in the corrosion potential of the aluminum-copper alloy relative to the increase in the copper content of the aluminum-copper alloy can be small. Figure 5 and Figure 6 When the copper content of the aluminum-copper alloy is greater than about 1.0 at%, although the resistivity increases significantly with the increase of the copper content of the aluminum-copper alloy, the corrosion potential does not increase significantly with the increase of the copper content of the aluminum-copper alloy. According to an embodiment, the copper content of the aluminum-copper alloy included in the wiring 160 may be in the range of about 0.2 at% to about 1.0 at%, so that the corrosion of the wiring 160 may be substantially prevented or minimized, and a significant increase in the resistance of the wiring 160 may be prevented.

[0087] In an embodiment, the wiring 160 may include an aluminum-vanadium (Al—V) alloy.

[0088] The corrosion potential of the aluminum-vanadium alloy may be higher than that of aluminum; therefore, the difference between the corrosion potentials of the aluminum-vanadium alloy and silver may be smaller than the difference between the corrosion potentials of aluminum and silver. + ) contact, but the reaction does not occur in large quantities, or may be slow. Therefore, corrosion of the wiring 160 can be substantially prevented or minimized.

[0089] Figure 7 is a graph showing the pitting potential of the aluminum-vanadium alloy according to the embodiment according to the vanadium content.

[0090] In an embodiment, the aluminum-vanadium alloy included in wiring 160 may include up to about 4.0 at % vanadium.

[0091] Reference Figure 7, the increase in the pitting potential of the aluminum-vanadium alloy relative to the increase in the vanadium content of the aluminum-vanadium alloy can vary. When the vanadium content of the aluminum-vanadium alloy is less than about 4.0at%, the slope of the increase in the pitting potential of the aluminum-vanadium alloy relative to the increase in the vanadium content of the aluminum-vanadium alloy can be large. When the vanadium content of the aluminum-vanadium alloy is greater than about 4.0at%, the slope of the increase in the pitting potential of the aluminum-vanadium alloy relative to the increase in the vanadium content of the aluminum-vanadium alloy can be small. Therefore, when the vanadium content of the aluminum-vanadium alloy is greater than about 4.0at%, the pitting potential will not increase significantly. According to an embodiment, the vanadium content of the aluminum-vanadium alloy included in the wiring 160 can be up to about 4.0at%, so that the corrosion of the wiring 160 can be substantially prevented or minimized without undesirably causing a significant increase in the resistivity of the wiring 160.

[0092] In yet another embodiment, the wiring 160 may include an aluminum-silicon (Al—Si) alloy.

[0093] The corrosion potential of the aluminum silicon alloy may be higher than that of aluminum, and therefore, the difference between the corrosion potentials of the aluminum silicon alloy and silver may be smaller than the difference between the corrosion potentials of aluminum and silver. + ) contact, but the reaction will not be large, or may be slow. Therefore, the corrosion of the wiring 160 can be substantially prevented or minimized.

[0094] In an embodiment, the aluminum alloy included in the wiring 160 may include at least one of indium (In), gallium (Ga), phosphorus (P), and thallium (Tl).

[0095] In an embodiment, the wiring 160 may include an aluminum-indium-gallium-phosphide-thallium (Al—In—Ga—P—Tl) alloy.

[0096] In an embodiment, the aluminum indium gallium phosphide thallium alloy included in wiring 160 may include up to about 0.1 at % indium, up to about 0.2 at % gallium, up to about 0.1 at % phosphorus, and up to about 0.01 at % thallium.

[0097] Table 1 below shows the corrosion rate of aluminum and the corrosion rate of aluminum-indium-gallium-phosphorus-thallium alloy.

[0098] [Table 1]

[0099]

[0100] As shown in Table 1, the corrosion rate of the aluminum indium gallium phosphide alloy may be lower than the corrosion rate of aluminum. For example, when the aluminum indium gallium phosphide alloy includes about 0.1 at% indium, about 0.2 at% gallium, about 0.1 at% phosphorus, and about 0.01 at% thallium, the corrosion rate of the aluminum indium gallium phosphide alloy may be about 1 / 10 of the corrosion rate of aluminum. Although the wiring 160 including the aluminum indium gallium phosphide alloy is not easily etched with silver ions (Ag + ) contact, but the reaction may be slow. Therefore, the corrosion of the wiring 160 can be substantially prevented or minimized. The content of each of indium, gallium, phosphorus and thallium in the alloy is configured to ensure the desired conductivity of the wiring 160.

[0101] Reference Figure 3 , the wiring 160 may include a first layer 161, a second layer 162, and a third layer 163 sequentially stacked. For example, the first layer 161 may be disposed on a lower surface of the second layer 162, and the third layer 163 may be disposed on an upper surface of the second layer 162.

[0102] The first layer 161, the second layer 162, and the third layer 163 of the wiring 160 may include titanium (Ti), aluminum alloy, and titanium, respectively. The second layer 162 of the wiring 160 may be used as a main wiring layer, and the first layer 161 and the third layer 163 of the wiring 160 may be used as auxiliary wiring layers for protecting the lower surface and the upper surface of the second layer 162, respectively.

[0103] A planarization layer 175 covering the source electrode 140 and the drain electrode 150 may be disposed on the insulating interlayer 135. The planarization layer 175 may be located in the display area DA. The wiring 160 and the pad electrode 170 may not be covered by the planarization layer 175. The planarization layer 175 may provide a planarized surface over the thin film transistor TFT. The planarization layer 175 may include an organic material such as an acrylic resin, an epoxy resin, a polyimide resin, a polyester resin, etc.

[0104] The first electrode 180 may be disposed on the planarization layer 175 . The first electrode 180 may be located in the display area DA. The first electrode 180 may be connected to the drain electrode 150 of the thin film transistor TFT through a contact hole formed in the planarization layer 175 .

[0105] The first electrode 180 may include silver (Ag). In an etching process for forming the first electrode 180, the silver included in the first electrode 180 may react with an etchant so that silver ions (Ag + ). Silver ion (Ag + ) will come into contact with the wiring 160 that is not covered by the planarization layer 175.

[0106] In an embodiment, the first electrode 180 may include a first layer 181, a second layer 182, and a third layer 183 sequentially stacked. For example, the first layer 181 may be disposed on a lower surface of the second layer 182, and the third layer 183 may be disposed on an upper surface of the second layer 182.

[0107] The first layer 181, the second layer 182, and the third layer 183 of the first electrode 180 may include indium tin oxide (ITO), silver, and indium tin oxide, respectively. The second layer 182 of the first electrode 180 may be used as a main electrode layer, and the first layer 181 and the third layer 183 of the first electrode 180 may be used as auxiliary electrode layers for protecting the lower surface and the upper surface of the second layer 182, respectively.

[0108] A pixel defining layer 190 partially covering the first electrode 180 may be disposed on the planarization layer 175. The pixel defining layer 190 may be located in the display area DA. The pixel defining layer 190 may insulate the second electrode 220 from the first electrode 180. The pixel defining layer 190 may include an opening exposing a portion of the upper surface of the first electrode 180, thereby defining an emission area. The pixel defining layer 190 may include an organic material such as an acrylic resin, an epoxy resin, a polyimide resin, a polyester resin, etc.

[0109] The organic light emitting layer 210 may be disposed on the first electrode 180. The organic light emitting layer 210 may be located in the display area DA. The organic light emitting layer 210 may include a low molecular organic compound or a high molecular organic compound.

[0110] In an embodiment, the organic light emitting layer 210 may emit red light, green light or blue light. In an embodiment, the organic light emitting layer 210 may emit white light; the organic light emitting layer 210 may have a multilayer structure including a red light emitting layer, a green light emitting layer and a blue light emitting layer, or may have a single layer structure including a red light emitting material, a green light emitting material and a blue light emitting material.

[0111] The second electrode 220 may be disposed on the organic light emitting layer 210. The second electrode 220 may be disposed on the pixel defining layer 190 and may cover the organic light emitting layer 210. The second electrode 220 may include at least one of lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), and magnesium (Mg).

[0112] Figure 8 , Fig. 9 , Fig.10 and Fig.11 is a cross-sectional view illustrating a structure formed in a method of manufacturing a display device according to an embodiment.

[0113] Reference Figure 8, a thin film transistor TFT, a wiring 160 and a pad electrode 170 may be formed on the substrate 110 .

[0114] The buffer layer 115 may be formed on the substrate 110 in the display area DA and the non-display area NDA. For example, the buffer layer 115 may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, etc. using chemical vapor deposition, sputtering, etc.

[0115] Then, a semiconductor layer 120 may be formed on the buffer layer 115 in the display area DA. For example, a material layer including at least one of silicon, an oxide semiconductor, etc. may be formed on the entire surface of the buffer layer 115, and then the material layer may be patterned to form the semiconductor layer 120. In an embodiment, an amorphous silicon layer may be formed on the entire surface of the buffer layer 115, and then the amorphous silicon layer may be crystallized to form a polycrystalline silicon layer. The polycrystalline silicon layer may be patterned, and impurities may be doped at opposite ends of the patterned polycrystalline silicon layer to form the semiconductor layer 120 including a source region, a drain region, and a channel region therebetween.

[0116] Then, a gate insulating layer 125 covering the semiconductor layer 120 may be formed on the buffer layer 115 in the display area DA and the non-display area NDA. For example, the gate insulating layer 125 may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0117] Then, a gate electrode 130 may be formed on the gate insulating layer 125 in the display area DA. The gate electrode 130 may overlap the semiconductor layer 120. For example, the gate electrode 130 may be formed of a metal or an alloy.

[0118] Then, an insulating interlayer 135 covering the gate electrode 130 may be formed on the gate insulating layer 125 in the display area DA and the non-display area NDA. For example, the insulating interlayer 135 may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0119] Then, contact holes exposing a portion of the semiconductor layer 120 may be formed in the insulating interlayer 135 and the gate insulating layer 125. For example, the contact holes may expose a source region and a drain region of the semiconductor layer 120, respectively.

[0120] Then, the source electrode 140 and the drain electrode 150 may be formed on the insulating interlayer 135 in the display area DA, and the wiring 160 and the pad electrode 170 may be formed on the insulating interlayer 135 in the non-display area NDA. For example, a conductive layer may be formed on the entire surface of the insulating interlayer 135 and then patterned, thereby substantially simultaneously forming the source electrode 140, the drain electrode 150, the wiring 160, and the pad electrode 170.

[0121] The wiring 160 may be formed of an aluminum (Al) alloy, or may include an aluminum alloy. The wiring 160 may include an aluminum alloy so that although the wiring 160 is etched with silver ions (Ag) during the etching process of forming the first electrode 180, + ) contact, but wiring 160 will not be significantly corroded.

[0122] In an embodiment, the aluminum alloy included in the wiring 160 may include at least one of copper (Cu), vanadium (V) and silicon (Si). For example, the wiring 160 may include an aluminum-copper (Al-Cu) alloy, an aluminum-vanadium (Al-V) alloy, or an aluminum-silicon (Al-Si) alloy.

[0123] In an embodiment, the aluminum alloy included in the wiring 160 may include at least one of indium (In), gallium (Ga), phosphorus (P), and thallium (Tl). For example, the wiring 160 may include an aluminum indium gallium phosphorus thallium (Al-In-Ga-P-Tl) alloy.

[0124] In an embodiment, the wiring 160 may include a first layer 161, a second layer 162, and a third layer 163 that are sequentially stacked. For example, a layer including titanium (Ti), a layer including an aluminum alloy, and a layer including titanium (Ti) may be sequentially formed on the insulating interlayer 135 and then patterned to form the source electrode 140, the drain electrode 150, the wiring 160, and the pad electrode 170 each having a stacked structure of Ti—Al alloy—Ti.

[0125] Reference Fig. 9 , Fig.10 and Fig.11 , the first electrode 180 may be formed on the source electrode 140 and the drain electrode 150 and over the wiring 160 and the pad electrode 170 .

[0126] Reference Fig. 9 , a planarization layer 175 covering the source electrode 140 and the drain electrode 150 may be formed on the insulating interlayer 135 in the display area DA. The planarization layer 175 may not cover the wiring 160 and the pad electrode 170. For example, the planarization layer 175 may be formed of at least one of a polyimide-based resin, a photoresist, an acrylic resin, a polyamide-based resin, a siloxane-based resin, etc. A contact hole exposing a portion of the drain electrode 150 may be formed in the planarization layer 175.

[0127] Then, a first electrode material layer 180' may be formed on the planarization layer 175 in the display area DA and on the insulating interlayer 135, the wiring 160, and the pad electrode 170 in the non-display area NDA. The first electrode material layer 180' may be formed of silver (Ag) using at least one of chemical vapor deposition, sputtering, etc.

[0128] The first electrode material layer 180' may be formed with a substantially uniform thickness along the contours of the planarization layer 175, the insulating interlayer 135, the wiring 160, and the pad electrode 170. The first electrode material layer 180' may contact the drain electrode 150 in the display area DA, and may contact the wiring 160 and the pad electrode 170 in the non-display area NDA.

[0129] In an embodiment, the first electrode material layer 180' may include a first layer 181', a second layer 182', and a third layer 183' stacked sequentially. For example, a layer including indium tin oxide (ITO), a layer including silver, and a layer including indium tin oxide may be sequentially deposited to form the first electrode material layer 180' having a stacked structure of ITO-Ag-ITO.

[0130] Then, refer to Fig.10 , a portion of the first electrode material layer 180' covering the wiring 160 and the pad electrode 170 may be etched away. For example, a photoresist pattern may be formed in a region of the first electrode material layer 180' where the first electrode 180 is to be formed, and the first electrode material layer 180' may be etched using the photoresist pattern as a mask and an etchant.

[0131] When the first electrode material layer 180' including silver reacts with the etchant, silver ions (Ag + ) 185. For example, the etchant may include nitric acid (HNO 3 ). Silver included in the first electrode material layer 180' reacts with nitric acid included in the etchant, so that silver ions 185 are formed according to the following Chemical Formula 1.

[0132] [Chemical formula 1]

[0133] 3Ag+4HNO 3 →3Ag + +3NO 3 - +2H 2 O+NO

[0134] The silver ions 185 may come into contact with the wiring 160. For example, the silver ions 185 may come into contact with the side of the second layer 162 of the wiring 160 including the aluminum alloy.

[0135] If the wiring consists only of aluminum, then when silver ions (Ag + ) comes into contact with the wiring, the aluminum included in the wiring will react with the silver ions (Ag + ) reaction, so that silver particles are formed. If the silver particles are formed between adjacent wirings, the wirings may be short-circuited unexpectedly. Therefore, the performance of the display device may be adversely affected and / or the display device may be damaged.

[0136] In the method of manufacturing a display device according to an embodiment, the wiring 160 may be formed of an aluminum alloy, or may include an aluminum alloy, so that corrosion of the wiring 160 may be substantially prevented or minimized. Although the wiring 160 is in contact with the silver ions 185, the reaction may not be large or may be slow. Advantageously, an undesirable short circuit may be prevented.

[0137] Reference Fig.11 , the silver ions 185 remaining on the insulating interlayer 135, the wiring 160, the pad electrode 170, and the planarization layer 175 may be removed. For example, the silver ions 185 may be removed together with the etchant remaining on the substrate 110 through a cleaning process.

[0138] Reference Figure 3 , a pixel defining layer 190 partially covering the first electrode 180 may be formed on the planarization layer 175 in the display area DA. For example, the pixel defining layer 190 may be formed of at least one of a polyimide-based resin, a photoresist, an acrylic resin, a polyamide-based resin, a siloxane-based resin, etc. An opening exposing the upper surface of the first electrode 180 may be formed in the pixel defining layer 190.

[0139] The organic light emitting layer 210 may be formed on the first electrode 180. The organic light emitting layer 210 may be formed in the opening of the pixel defining layer 190. For example, the organic light emitting layer 210 may be formed of a low molecular organic compound or a high molecular organic compound using screen printing, inkjet printing, deposition, or the like.

[0140] The second electrode 220 may be formed on the pixel defining layer 190 and the organic light emitting layer 210. For example, the second electrode 220 may be formed of at least one of lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), and the like.

[0141] The display device according to the embodiment may be included in a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, an MP3 player, and the like.

[0142] Although example embodiments have been described with reference to the accompanying drawings, modifications and changes may be made to the described embodiments by those skilled in the relevant art without departing from the scope defined in the claims.

Claims

1. A display device, comprising: Insulation layer; a wiring directly contacting a surface of the insulating layer, the wiring comprising an aluminum alloy including at least one of copper, vanadium and silicon to reduce a difference between corrosion potentials of the wiring and silver; a first electrode, overlapping the insulating layer, wherein the first electrode comprises silver; An organic light-emitting layer, located on the first electrode; as well as The second electrode is located on the organic light-emitting layer.

2. The display device according to claim 1, wherein: The wiring includes an aluminum-copper alloy, and The aluminum-copper alloy includes copper in the range of 0.2 at % to 3.0 at %.

3. The display device according to claim 1, wherein: The wiring includes an aluminum-copper alloy, and The aluminum-copper alloy includes copper in the range of 0.2 at % to 1.0 at %.

4. The display device according to claim 1, wherein: The wiring includes an aluminum-vanadium alloy, and The aluminum-vanadium alloy includes at most 4.0 at % vanadium.

5. The display device according to claim 1, wherein: The wiring includes a first layer, a second layer and a third layer, The second layer is located between the first layer and the third layer, The first layer and the third layer each include titanium, and The second layer includes the aluminum alloy.

6. A display device, comprising: substrate; a wiring, overlapping the substrate, the wiring comprising an aluminum alloy including at least one of indium, gallium, phosphorus, and thallium to reduce a difference between corrosion potentials of the wiring and silver; a first electrode overlapping the substrate and electrically insulated from the wiring, the first electrode comprising silver; An organic light-emitting layer, located on the first electrode; as well as The second electrode is located on the organic light-emitting layer.

7. A method for manufacturing a display device, the method comprising the following steps: forming a wiring on a substrate, the wiring comprising an aluminum alloy including at least one of copper, vanadium and silicon to reduce a difference between corrosion potentials of the wiring and silver; forming a first electrode on the wiring, wherein the first electrode comprises silver; forming an organic light-emitting layer on the first electrode; as well as A second electrode is formed on the organic light emitting layer.

8. The method according to claim 7, wherein: The wiring includes an aluminum-copper alloy, and The aluminum-copper alloy includes copper in the range of 0.2 at % to 3.0 at %.

9. The method according to claim 7, wherein: The wiring includes an aluminum-vanadium alloy, and The aluminum-vanadium alloy includes at most 4.0 at % vanadium.

10. The method according to claim 7, wherein: The step of forming the first electrode comprises: forming a first electrode material layer including silver on the planarization layer, wherein the planarization layer is located on the substrate; and A portion of the first electrode material layer is etched using an etchant, wherein the planarization layer exposes the wiring during the etching.

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