Memory controller and operating method thereof

Abstract

A memory controller and an operating method thereof are provided. The memory controller is configured to control a memory device including a plurality of memory banks. The memory controller may determine whether the number of write commands queued in a command queue of the memory controller exceeds a reference value; when the number of write commands queued exceeds the reference value, calculate a level of write power consumed by the memory device in response to at least some of the write commands in the queue; and schedule an interleaved command for performing an interleaved operation of the memory device from the write commands in the queue based on the calculated level of write power.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0104780 filed on September 3, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a memory device, and more particularly, to a memory controller for controlling the memory device and an operating method of the memory controller. Background Art

[0004] As nonvolatile memory devices, resistive memory devices such as phase change random access memory (PRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM) have used variable resistance elements as memory cells, which store data by changing the resistance state. The commonality of the materials of the resistive memory devices is that the resistance value changes according to the magnitude and / or direction of the current or voltage, and the material has a nonvolatile characteristic of maintaining the resistance value even when the current or voltage is blocked.

[0005] In recent years, fields using large amounts of data, such as image processing and big data processing, have increased, and therefore it has become important to increase the data processing speed. As a method for increasing the data processing speed of a memory device, a bank interleaving technique that controls data to use a plurality of banks simultaneously is being used. Therefore, the data processing speed can be improved compared to the case of using a single bank. Summary of the invention

[0006] The inventive concept provides a memory controller capable of controlling the number of memory banks that can be used simultaneously according to a power consumption level of a write operation and an operating method thereof.

[0007] According to one aspect of the inventive concept, there is provided an operating method of a memory controller for controlling a memory device including a plurality of memory bodies, the operating method comprising: determining whether the number of write commands queued in a command queue of the memory controller exceeds a reference value; in response to the number of write commands queued exceeding the reference value, calculating a level of write power consumed by the memory device in response to at least some of the write commands from the queued write commands; and scheduling, from the queued write commands, an interleaving command for executing a first interleaving operation of the memory device based on the calculated level of write power.

[0008] According to another aspect of the inventive concept, a memory controller for controlling an interleaved operation of a memory device including a plurality of memory bodies is provided, the memory controller comprising: a power level calculator configured to calculate a level of write power to be consumed in the memory device in response to at least some of a plurality of write commands to be provided to the memory device; and a command scheduler configured to schedule, from the plurality of write commands, interleaved commands for performing the interleaved operation of the memory device based on the calculated level of write power, wherein the power level calculator calculates the level of write power in response to the number of the plurality of write commands exceeding a reference value.

[0009] According to another aspect of the inventive concept, there is provided a memory system, comprising: a memory device, comprising a plurality of memory bodies, and configured to perform a data comparison write operation; and a memory controller, configured to control an interleaved operation of the memory device, wherein the memory controller comprises: a power level calculator, configured to calculate a level of write power to be consumed in the memory device in response to at least some of a plurality of write commands to be provided to the memory device, and a command scheduler, configured to schedule an interleaved command for performing the interleaved operation of the memory device from among the plurality of write commands based on the calculated level of write power, wherein the power level calculator calculates the level of write power in response to the number of the plurality of write commands exceeding a reference value. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a memory system according to an example embodiment;

[0012] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an example of a memory device included in a memory system of;

[0013] Figure 3 yes Figure 2 A circuit diagram of an example embodiment of a memory cell array in;

[0014] FIG. 4A to FIG. 4C It is shown Figure 3 A circuit diagram of an example of a change in a memory cell in FIG.

[0015] Figure 5 is included in Figure 1 A block diagram of an example embodiment of a memory controller in a memory system of;

[0016] Figure 6 is a flowchart illustrating an operating method of a memory controller according to an example embodiment;

[0017] Figure 7 is a flowchart illustrating an operating method of a memory controller according to an example embodiment;

[0018] Fig. 8A It is shown Figure 5 A table of example embodiments of command queues in;

[0019] Figure 8B is a table illustrating an example embodiment of a command queue for pre-read command queuing;

[0020] Fig. 9 Yes Description Figure 6 S30 and Figure 7 FIG. 10 is a diagram of an example embodiment of S40 in FIG. 10 ;

[0021] Fig.10 is a diagram showing an operation method of a memory controller according to an example embodiment and showing Figure 6 A flowchart of an example embodiment of S50 in FIG.

[0022] Fig.11 It is used to illustrate Fig.10 A timing diagram of an example embodiment of S50 in FIG. 1 ;

[0023] Fig. 12A It is used to illustrate Fig.10 A timing diagram of an example embodiment of S50 in FIG. 1 ; and

[0024] Fig. 12B yes Figure 5 A table of example embodiments of a command queue in FIG. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a block diagram illustrating a memory system 10 according to an example embodiment.

[0027] refer to Figure 1 , the memory system 10 may include a memory device 100 and a memory controller 200 .

[0028] The memory controller 200 may control the memory device 100 to write data to the memory device 100 or read data stored in the memory device 100 in response to a write / read request from the host HOST. For example, the memory controller 200 may provide the memory device 100 with an address ADDR, a command CMD (e.g., a write command WCMD and a read command RCMD), and a control signal CTRL to control programming (or registration) and reading operations on the memory device 100. In addition, data DATA to be written and data DATA to be read may be transmitted and received between the memory controller 200 and the memory device 100.

[0029] The memory device 100 may include a memory cell array 110 and a control circuit 130. The memory cell array 110 may include a plurality of memory cells MC respectively arranged in regions where a plurality of first signal lines and a plurality of second signal lines intersect. In an embodiment, the plurality of first signal lines may be a plurality of word lines, and the plurality of second signal lines may be a plurality of bit lines. In another embodiment, the plurality of first signal lines may be a plurality of bit lines, and the plurality of second signal lines may be a plurality of word lines.

[0030] In an embodiment, the plurality of memory cells MC may include a resistance memory cell including a variable resistance element. For example, when the variable resistance element is a phase change material Ge-Sb-Te (GST) and the resistance changes according to temperature, the memory device 100 may be a phase change memory (PRAM). For example, when the variable resistance element includes an upper electrode, a lower electrode, and a composite metal oxide between the upper electrode and the lower electrode, the memory device 100 may be a PRAM. For example, when the variable resistance element includes an upper electrode of a magnetic material, a lower electrode of a magnetic material, and a dielectric between the upper electrode and the lower electrode, the memory device 100 may be a magnetoresistive or magnetic random access memory (MRAM). Therefore, the memory device 100 may be referred to as a resistance memory device, and the memory system 10 may be referred to as a resistance memory system.

[0031] In an embodiment, each of the plurality of memory cells MC may be a single-level cell (SLC) capable of storing one bit of data. At this point, the memory cell MC may have two different resistance distributions depending on the stored data. In an embodiment, each of the plurality of memory cells MC may be a multi-level cell (MLC) capable of storing two bits of data. At this point, the memory cell MC may have four resistance distributions depending on the stored data. In an embodiment, each of the plurality of memory cells MC may be a three-level cell (TLC) capable of storing three bits of data. At this point, the memory cell MC may have eight resistance distributions depending on the stored data. However, the inventive concept is not limited thereto. In an embodiment, the memory cell array 110 may include memory cells MC capable of storing four or more bits of data, respectively. The memory cell array 110 may include SLC, MLC, or TLC together.

[0032] The control circuit 130 may control the operation of the memory device 100. In the present embodiment, the control circuit 130 may control the timing or voltage level of the voltage applied to the first signal line and the second signal line connected to the memory cell array 110. Here, the voltage may include an operating voltage applied to the selected first signal line and the second signal line, and a prohibition voltage applied to the unselected first signal line and the second signal line.

[0033] The memory controller 200 may include an interleaving controller 210. When data is written to the memory device 100, the interleaving controller 210 may control to perform an interleaving operation. For example, the interleaving controller 210 may precalculate the power level to be consumed when writing data to different memory banks at the same time. The interleaving controller 210 may determine the number of write commands WCMD corresponding to the interleaving operation based on the calculated power level to be consumed, and select the write command WCMD corresponding to the interleaving operation. Therefore, according to the operating method of the memory device 100 conceived according to the present invention, the number of accessible memory banks that can be used simultaneously can be increased by effectively controlling the interleaving operation, and the time spent performing the write operation can be reduced.

[0034] Figure 2 It is shown Figure 1 1 is a block diagram of an example of a memory device 100 included in a memory system 10 of FIG. 1 .

[0035] refer to Figure 2 , the memory device 100 may include a memory cell array 110, a write / read circuit 120, a control circuit 130, a reference signal generating circuit 140, a voltage generating circuit 150, a row decoder (X-DEC) 160 and a column decoder (Y-DEC) 170, wherein the write / read circuit 120 may include a sense amplifier (SA) 121 and a write driver (WD) 122.

[0036] The memory cells MC included in the memory cell array 110 may be connected to a plurality of first signal lines and a plurality of second signal lines. In an embodiment, the plurality of first signal lines may be a plurality of word lines WL, and the plurality of second signal lines may be a plurality of bit lines BL. When various voltage signals or current signals are provided through the plurality of word lines WL and the plurality of bit lines BL, data is written or read with respect to the selected memory cell MC, and writing or reading with respect to the remaining unselected memory cells MC may be prevented from being performed.

[0037] The memory cells MC included in the memory cell array 110 may be divided into different memory banks BANK. Each memory bank BANK may include a plurality of pages PAGE, wherein one page PAGE may indicate memory cells MC having the same row address RA in the memory bank BANK. The memory bank BANK may be a unit for performing an interleaving operation, and the page PAGE may be a unit for performing a read or write operation.

[0038] An address ADDR indicating a memory cell MC to be accessed may be received in the memory device 100 together with the command CMD, wherein the address ADDR may include a row address RA for selecting a word line WL of the memory cell array 110 and a column address CA for selecting a bit line BL of the memory cell array 110. The row decoder 160 may respond to the row address RA to perform a word line selection operation. The column decoder 170 may respond to the column address CA to perform a bit line selection operation.

[0039] The write / read circuit 120 may be connected to the first signal line and / or the second signal line of the memory cell array 110 to write data into the memory cell MC or read data from the memory cell MC. The voltage generating circuit 150 may generate a write voltage Vwrite for performing a write operation and a read voltage Vread for performing a read operation. The write voltage Vwrite may include a set pulse and a reset pulse as various voltages related to the write operation. The write voltage Vwrite and the read voltage Vread may be provided to the bit line BL via the column decoder 170, or may be provided to the word line WL via the row decoder 160.

[0040] The reference signal generating circuit 140 may generate a reference voltage Vref and a reference current Iref as various reference signals related to a data reading operation. For example, the sense amplifier 121 may be connected to a node (e.g., a sensing node) of the bit line BL to distinguish data. The sense amplifier 121 may distinguish data values ​​via a comparison operation with respect to the reference voltage Vref and the voltage at the sensing node. Alternatively, when a current sensing method is applied, the reference signal generating circuit 140 may generate a reference current Iref and provide the reference current Iref to the memory cell array 110. The data value may be distinguished by comparing the voltage and the reference voltage Vref of the sensing node caused by the reference current Iref.

[0041] The write / read circuit 120 may provide a distinction result on read and written data to the control circuit 130. The control circuit 130 may control write and read operations of the memory cell array 110 with reference to the distinction result.

[0042] The control circuit 130 may output various control signals CTRL_RW to write or read data to or from the memory cell array 110 based on the command CMD, address ADDR, and control signal CTRL received from the memory controller 200. The control circuit 130 may generally control various operations in the memory device 100.

[0043] The control circuit 130 may perform an interleaving operation with respect to different memory banks BANK included in the memory cell array 110. When the control circuit 130 performs an interleaving operation with respect to the first memory bank BANK and the second memory bank BANK, word line addressing of the first memory bank BANK and the second memory bank BANK may be changed.

[0044] The control circuit 130 may perform a data comparison write (DCW) operation. When the control circuit 130 receives a write command WCMD and write data from the memory controller 200, the control circuit 130 may compare the existing data stored in the address corresponding to the write command WCMD with the write data, and perform an overwrite operation only on the memory cell MC having data different from the existing data in the write data. For example, when the existing data is "00000000" and the write data is "00000001", an overwrite operation may be performed only on the memory cell MC corresponding to the eighth bit. Therefore, the closer the similarity between the already stored data and the data to be written, that is, the smaller the number of memory cells MC having data different from each other, the lower the power consumed when performing the write operation.

[0045] Figure 3 yes Figure 21. The memory cell array 110 may include a plurality of memory banks BANK, and Figure 3 One memory bank BANK can be displayed.

[0046] refer to Figure 3 , the memory bank BANK may include a plurality of memory cells MC. Here, according to example embodiments, the number of word lines WL connected to the plurality of memory cells MC, the number of bit lines BL, and the number of memory cells MC may be variously changed. Figure 3 The number of word lines WL in the memory is shown to be equal to the number of bit lines BL, but the present embodiment is not limited thereto. The number of word lines WL may be different from the number of bit lines BL. The memory bank BANK may include a plurality of pages PAGE. One page PAGE may indicate memory cells MC connected to the same word line WL in the memory bank BANK.

[0047] According to an embodiment, each of the plurality of memory cells MC may include a variable resistor R and a selection element D. Here, the variable resistor R may be referred to as a variable resistance element or a variable resistance material. The selection element D may be referred to as a switching element.

[0048] In an embodiment, the variable resistor R may be connected between one of the plurality of bit lines BL0 to BLm and the selection element D. The selection element D may be connected between one of the plurality of word lines WL0 to WLm and the variable resistor R. However, the present embodiment is not limited thereto. The selection element D may be connected between one of the plurality of bit lines BL0 to BLm and the variable resistor R. The variable resistor R may be connected between one of the plurality of word lines WL0 to WLm and the selection element D.

[0049] The selection element D may be connected between one of the plurality of word lines WL0 to WLm and the variable resistor R, and may control the current supply to the variable resistor R according to the voltage applied to the connected word line WL and the bit line BL. In an embodiment, the selection element D may be a PN junction or a PIN junction diode, wherein the anode of the diode may be connected to the variable resistor R, and the cathode of the diode may be connected to one of the plurality of bit lines BL0 to BLm. At this time, when the voltage difference between the anode and the cathode of the diode is greater than the threshold voltage of the diode, the diode may be turned on and current may be supplied to the variable resistor R.

[0050] FIG. 4A to FIG. 4C It is shown Figure 3 A circuit diagram of an example of a variation of a memory cell MC.

[0051] refer to Figure 4A, the memory cell MCa may include a variable resistor Ra, and the variable resistor Ra may be connected between the bit line BL and the word line WL. The memory cell MCa may store data as voltages applied to the bit line BL and the word line WL, respectively.

[0052] refer to Figure 4B , the memory cell MCb may include a variable resistor Rb and a bidirectional diode Db. The variable resistor Rb may include a resistance material for storing data. The bidirectional diode Db may be connected between the variable resistor Rb and the bit line BL. The variable resistor Rb may be connected between the word line WL and the bidirectional diode Db. The positions of the bidirectional diode Db and the variable resistor Rb may be switched with each other. The leakage current flowing through the unselected memory cell MC may be cut off via the bidirectional diode Db.

[0053] refer to Figure 4C , the memory cell MCc may include a variable resistor Rc and a transistor TR. The transistor TR may be a selection element, that is, a switching element that provides or cuts off current to the variable resistor Rc according to the voltage of the word line WL. Figure 4C In the embodiment, in addition to the word line WL, a source line SL for adjusting the voltage level at both ends of the variable resistor Rc may be additionally included. The transistor TR may be connected between the variable resistor Rc and the bit line BL. The variable resistor Rc may be connected between the source line SL and the transistor TR. The positions of the transistor TR and the variable resistor Rc may be switched with each other. The memory cell MCc may be selected or not selected depending on whether the transistor TR is driven on or off by the word line WL.

[0054] Figure 5 is included in Figure 1 1 is a block diagram of an example embodiment of a memory controller 200 in a memory system 10 of FIG.

[0055] refer to Figure 5 , the memory controller 200 may include an interleave controller 210 , a processor 220 , a random access memory (RAM) 230 , a host interface 240 , and a memory interface 250 .

[0056] The interleaving controller 210 may include a power level calculator 211 and a command scheduler 212. The power level calculator 211 may calculate a level of write power to be consumed as a plurality of write commands are provided to the memory device 100 in response to each write command. For example, the power level calculator 211 may calculate a power level to be consumed due to a write operation with respect to a memory bank corresponding to each of the plurality of write commands. Figure 7 A method of calculating the power consumption level of the write operation by the power level calculator 211 is described.

[0057] The command scheduler 212 may manage write / read requests received from the host to improve the performance of the memory device 100. For example, a plurality of write commands may be queued in the command queue 231 according to the write requests received from the host. The command scheduler 212 may provide the plurality of queued write commands to the memory device 100 in a sequential or unordered manner. According to an embodiment, the command scheduler 212 may schedule the plurality of queued write commands based on the level of write power calculated by the power level calculator 211. The command scheduler 212 may adjust the timing of providing the plurality of queued write commands to the memory device 100. The scheduling method of the command scheduler 212 may be referred to later. Fig.10 describe.

[0058] The processor 220 may include a central processing device or a microprocessor, and may control the overall operation of the memory controller 200. For example, the processor 220 may be configured to drive software or firmware that controls the memory controller 200. The software or firmware may be loaded into the RAM 230 and driven. The RAM 230 may be used as an operating memory, a cache memory, or a buffer memory of the processor 220. In the RAM 230, write data to be written to the memory device 100 may be temporarily stored, and read data read from the memory device 100 may also be temporarily stored.

[0059] In an embodiment, the command queue 231 may be stored in the RAM 230. According to a write request received from the host, a plurality of commands may be queued in the command queue 231. For example, a write command and a read command may be queued. In addition, a pre-read command generated by the interleaving controller 210 may be queued in the command queue 231. The command queue 231 will be referred to later. Fig. 8A Give a description.

[0060] The host interface 240 interfaces with the host to receive a request for a memory operation from the host. For example, the host interface 240 may receive various requests for reading and writing data from the host HOST, and generate various internal signals for the memory device 100 to perform a memory operation in response to the request.

[0061] The memory interface 250 may provide an interface between the memory controller 200 and the memory device 100. For example, write data may be sent to the memory device 100 and read data may be received from the memory device 100 via the memory interface 250. In addition, the memory interface 250 may provide commands and addresses to the memory device 100. The memory interface 250 may also receive various information from the memory device 100 and provide the information to the memory controller 200.

[0062] Figure 6is a flowchart illustrating an operating method of the memory controller 200 according to example embodiments.

[0063] refer to Figure 1 and Figure 6 In S10, the memory controller 200 may receive a write request and write data from the host HOST. Based on the received write request, the memory controller 200 may queue a plurality of write commands in a command queue.

[0064] In S20, the interleave controller 210 of the memory controller 200 may determine whether the number of queued write commands exceeds a reference value. In an embodiment, the interleave controller 210 may determine whether the number of write commands corresponding to different memory banks exceeds a reference value.

[0065] At this time, assuming that the level of write power consumed in one memory bank when performing a write operation according to a write command is the maximum, the reference value may indicate the maximum value of the number of memory banks that can be accessed simultaneously according to the interleaving operation. For example, when the maximum level of power consumed by the memory device 100 in the interleaving operation of the write operation is 32, and the maximum level of write power consumed by writing one memory bank according to the write command is 8, the reference value is 4.

[0066] In S30 , when the number of queued write commands does not exceed a reference value, the interleave controller 210 may control the memory device 100 to perform an interleave operation according to the queued write commands.

[0067] The interleave controller 210 may control the memory device 100 to perform an interleave operation with respect to the queued write commands without calculating the power consumption in advance according to the write operation. For example, when the number of queued write commands does not exceed a reference value, the interleave controller 210 may send the queued write commands to the memory device 100 in parallel, and the memory device 100 may not exceed the upper limit of the power level that may be consumed in the interleave operation, regardless of the level of write power actually consumed in different memory banks in the write operation in response to each write command.

[0068] In S40, when the number of queued write commands exceeds the reference value, the interleave controller 210 may calculate the level of write power consumed in the memory device 100 in response to at least some of the write commands. For example, the number of queued write commands may be 10, and the number of at least some of the write commands may be 6, as shown in FIG. Fig. 9 As shown. We will refer to Figure 7 S40 is described in detail.

[0069] In S50, the interleaving controller 210 may schedule interleaving commands for performing interleaving operations based on the level of write power calculated in S40. The interleaving commands may be at least some of the queued write commands. Fig.10 S50 is described in detail. In the figure, it is shown that S40 and S50 are performed sequentially, but the operation method of the memory controller 200 according to the inventive concept is not limited thereto. S40 and S50 may overlap and be performed in parallel.

[0070] In S60, the memory controller 200 may control the memory device 100 to perform the interleaving operation on the write command based on the scheduled interleaving command to perform the interleaving operation. For example, the memory controller 200 may send the scheduled interleaving commands to the memory device 100 one after another.

[0071] According to the operating method of the memory controller 200 of the embodiment of the inventive concept, the memory controller 200 can determine whether to execute S40 and S50 according to the number of queued write commands. Therefore, the operating time of the memory controller 200 can be reduced (by avoiding unnecessary execution of S40 and S50).

[0072] In addition, when the number of queued write commands exceeds a reference value, the memory controller 200 can schedule the write operations according to the power to be consumed due to the write operations, so that the number of write commands performing interleaved operations can be increased, and the power consumption of the memory device 100 caused by the write operations can be more effectively managed.

[0073] Figure 7 is a diagram showing a method used by the memory controller 200 according to an example embodiment, and showing Figure 6 Flowchart of an example embodiment of S40 in FIG.

[0074] refer to Figures 5 to 7 In S410, the interleave controller 210, for example, the power level calculator 211 may select at least some write commands from the queued write commands to calculate the power. In S410, the following operations (S420 to S490) may be performed with respect to each of the selected some write commands. In an example embodiment, the power level calculator 211 may calculate the write power only for the selected write commands from the queued write commands. Therefore, the write speed and / or power consumption of the memory device 100 may be improved.

[0075] In S420, the power level calculator 211 may check whether there is a read command with respect to the target storage bank, which is before the selected write command. For example, the power level calculator 211 may check whether a read command with respect to the target storage bank is currently pending or whether the memory device 100 is performing a read operation according to the read command. At this time, the target storage bank may indicate a target storage bank of one of the selected write commands. In S420, the power level calculator 211 may check whether there is a read command with respect to each selected write command.

[0076] In S430, when there is no read command with respect to the target storage body, the read command precedes the selected write command, the power level calculator 211 may check whether there is another write command with respect to the target storage body of the selected write command, which precedes the selected write command. When there is no read command or other write command with respect to the target storage body, the read or write command precedes the selected write command, S440 and S450 may be executed.

[0077] In S440, the power level calculator 211 may generate a pre-read command. At this time, the pre-read command may be a read command regarding an address where write data corresponding to the selected write command is to be written.

[0078] In S450 , the power level calculator 211 may compare the pre-read data read by the pre-read command with the write data corresponding to the selected write command to calculate the level of write power to be consumed.

[0079] Since the memory device 100 performs a data comparison write (DCW) operation, when a write command is received, the memory device 100 can compare the previously written and existing data with the write data to be written, and perform an overwrite operation only on the memory cells having other data. The amount of power consumed due to the write operation may be different depending on the difference between the existing data and the write data. Therefore, the power level calculator 211 can compare the pre-read data with the write data after generating and providing the pre-read command to the memory device 100, and calculate the power level to be consumed by the write operation based on the difference between the pre-read data and the write data.

[0080] When there is another write command before the selected write command, S460 may be performed. In S460, the power level calculator 211 may calculate the level of write power to be consumed due to the write operation by assuming that the level of the write power is a maximum value without generating a pre-read command. When another write operation has been performed with respect to the target storage body to perform the write operation, the write operation of the selected write command may be performed after the execution of the write operation is completed. Therefore, in order to improve the write latency or data bandwidth of the memory device 100, the interleaving controller 210 may calculate the level of the write power in the power level calculation S40 by assuming that the level of the write power has a maximum value without generating a pre-read command, in which case there is a possibility of a storage body conflict.

[0081] When there is a read command before the selected write command, S470 may be performed. In S470, the power level calculator 211 may confirm whether the row address corresponding to the read command is the same as the row address corresponding to the selected write command. For example, in S470, the power level calculator 211 may confirm whether the page corresponding to the read command is the same as the target page corresponding to the selected write command. When the page corresponding to the read command is the same as the target page corresponding to the selected write command, it may be referred to as a "page hit".

[0082] In S480, when the row address corresponding to the read command is different from the row address corresponding to the selected write command, the power level calculator 211 may assume that the level of write power to be consumed due to the write operation is the maximum value without generating a pre-read command. When another read operation has been performed with respect to the target storage body to perform the read operation, the write operation with respect to the selected write command may be performed after the read operation that has been performed is completed. Therefore, in order to improve the write latency or data bandwidth of the memory device 100, the interleaving controller 210 may assume in the power level calculation S40 that the power consumption level has the maximum value without generating a pre-read command, in which case there is a possibility of a storage body conflict, and may perform a command scheduling operation (e.g., based on the power level having the maximum value) in a subsequent operation. Figure 6 S50 in ).

[0083] When the row address corresponding to the selected write command is the same as the row address corresponding to the read command, S490 may be executed. For example, when the target page of the selected write command is the same as the page corresponding to the read command, S490 may be executed. In S490, the power level calculator 211 may compare the read data read in response to the read command with the write data to calculate the level of write power to be consumed due to the write operation. Since the read command with respect to the target page corresponding to the selected write command has been previously executed, the power level calculator 211 may not need to generate a separate pre-read command to calculate the write power level. The power level calculator 211 may use the read data to calculate the power level to be consumed due to the write operation of the selected write command. In an embodiment, when the read data read due to the read command is stored in the RAM 230 of the memory controller 200, S490 may be executed immediately after executing S480. In an embodiment, when a read command regarding a target page is pending in the command queue 231 or when a read command is provided to the memory device 100 but read data has not yet been received by the memory controller 200 , S490 may be executed after waiting for a period of time after S480 is completed.

[0084] In an example embodiment, the command scheduler 212 may perform scheduling of queued write commands based on the level of write power calculated by the power level calculator 211 before finishing calculating the levels of write power of all selected write commands by the power level calculator 211. For example, the command scheduler 212 may perform scheduling of some write commands while the power level calculator 211 calculates the levels of write power corresponding to some write commands.

[0085] Fig. 8A It is shown Figure 5 0046] A table of an example embodiment of command queue 231 in FIG. Figure 8B It is shown that by executing Figure 7 The S440 in Figure 5 1. A table of an example embodiment of a command queue of a pre-read command queue generated by the interleave controller 210 in FIG.

[0086] refer to Figure 5 and 8A According to a write request received from the host, a plurality of commands may be queued in the command queue 231. The command queue 231 may include a write command queue 231_1 in which write commands are queued and a read command queue 231_2 in which read commands are queued.

[0087] In an embodiment, commands may be queued in the write command queue 231_1 and the read command queue 231_2 in the order in which write requests and read requests are received from the host. For example, the first write command WCMD0 to the tenth write command WCMD9 may be queued sequentially in the write command queue 231_1 according to the order in which write requests are received from the host. The first read command RCMD0 and the second read command RCMD1 may be queued sequentially in the read command queue 231_2 according to the order in which read requests are received from the host. Fig. 8A The write command queue 231_1 and the read command queue 231_2 shown in FIG. 2 are merely examples for explaining the operation of the interleaving controller 210 included in the memory controller 200. The operation method of the memory controller of the present invention is not limited to Fig. 8A .Although Fig. 8A It is shown that the write command queue 231_1 and the read command queue 231_2 are configured separately, but it is not limited thereto. As an example, the read command and the write command can be combined into one command queue 231 .

[0088] The write command WCMD0 may be executed with respect to the write command from among the first write command WCMD0 to the tenth write command WCMD9. Figure 6 In S30, the first write command WCMD0 to the tenth write command WCMD9 are queued in the write command queue 231_1 and do not exceed the reference value. In addition, the write command exceeding the reference value may be executed Figure 6 For example, when the reference value is 4, S30 may be performed on the first to fourth write commands WCMD0 to WCMD3 queued relatively early, and S40 to S60 may be performed on the remaining write commands WCMD5 to WCMD9.

[0089] refer to FIG. 8A to FIG. 8B , the interleaving controller 210 may perform S440 and S450 in conjunction with a write command without a previous read command or other previous write command (e.g., the fifth write command WCMD4, the eighth write command WCMD7, the ninth write command WCMD8, and the tenth write command WCMD9). Pre-read commands pre_RCMD0, pre_RCMD1, pre_RCMD2, and pre_RCMD3 corresponding to the write commands WCMD4, WCMD7, WCMD8, and WCMD9, respectively, may be generated when performing S440. The pre-read commands pre_RCMD0, pre_RCMD1, pre_RCMD2, and pre_RCMD3 may be arranged in the pre-read command queue 231_2' in the order of the corresponding write commands WCMD4, WCMD7, WCMD8, and WCMD9. Therefore, Figure 5 The command queue 231 in may also include a pre-read command queue 231_2 ′.

[0090] Fig. 9 It is used to illustrate Figure 6 S30 and Figure 7 2 and 3. The exemplary embodiment of S40 in FIG. 2 is shown in FIG. 2 and is a graph showing the value of the level of write power corresponding to each write command calculated by the power level calculator 211.

[0091] refer to Fig. 8A , Figure 8B and Fig. 9 , for example, the level of write power caused by a write operation may be divided into 8 levels (level 1 to level 8), and the higher the level, the higher the power consumption. However, this is only an example, and the level of write power may be subdivided differently.

[0092] The power level calculator (e.g., Figure 5 The power level calculator 211 may calculate the levels of write power of the write commands WCMD0 to WCMD3 that do not exceed the reference value (for example, assuming that the reference value is 4) among the first write command WCMD0 to the tenth write command WCMD9 queued in the command queue as the maximum value (level 8). For example, the power level calculator 211 may calculate the levels of write power that correspond to the write commands WCMD0 to WCMD3, respectively, by assuming that the levels of write power are the maximum value (level 8), without performing a calculation on the first write command WCMD0 to the fourth write command WCMD3. Figure 6 S40 to S60 in.

[0093] The power level calculator 211 may calculate the level of write power regarding at least some of the write commands WCMD4 to WCMD9 exceeding the reference value. For example, the level of write power regarding all the write commands WCMD4 to WCMD9 exceeding the reference value may be calculated.

[0094] The power level calculator 211 may generate pre-read commands pre_RCMD0, pre_RCMD1, pre_RCMD2, and pre_RCMD3 corresponding to the fifth write command WCMD4, the eighth write command WCMD7, the ninth write command WCMD8, and the tenth write command WCMD9, which do not have a previous read command or other previous write commands ( Figure 7S440 in the above description). The pre-read commands pre_RCMD0, pre_RCMD1, pre_RCMD2, and pre_RCMD3 are provided to the memory device 100 before the fifth write command WCMD4, the eighth write command WCMD7, the ninth write command WCMD8, and the tenth write command WCMD9, and the power level calculator 211 can compare the write data with the pre-read data received by the pre-read commands pre_RCMD0, pre_RCMD1, pre_RCMD2, and pre_RCMD3 to calculate the level of write power. For example, the levels of write power corresponding to the fifth write command WCMD4, the eighth write command WCMD7, the ninth write command WCMD8, and the tenth write command WCMD9 can be calculated in 3, 4, 4, and 3 levels, respectively.

[0095] The power level calculator 211 may assume that the level of the write power with respect to the sixth write command WCMD5 (in which there is another previous write command with respect to the target memory bank) is the maximum value (level 8) to calculate the level of the write power ( Figure 7 S460 in the ).

[0096] In addition, when there is a previous read command RCMD1, and the memory bank BANK 6 corresponding to the read command RCMD1 is the same as the target memory bank BANK 6 corresponding to the seventh write command WCMD6, and in particular, when the page corresponding to the read command RCMD1 is the same as the target page corresponding to the seventh write command WCMD6, the power level calculator 211 may compare the read data read by the read command RCMD1 with the write data corresponding to the seventh write command WCMD6 to calculate the level of the write power ( Figure 7 For example, the level of the write power corresponding to the seventh write command WCMD6 may be calculated as Level 6.

[0097] However, with Figure 7 Unlike that shown in S490 of FIG. 1 , when the memory bank corresponding to the previous read command is the same as the target memory bank corresponding to the seventh write command WCMD6, but the page corresponding to the previous read command RCMD1 is different from the target page corresponding to the seventh write command WCMD6, the power level calculator 211 may assume the level of the write power to be the maximum value (level 8) to calculate the level of the write power ( Figure 7 S480 in the ).

[0098] Fig.10 is a diagram showing an operation method of the memory controller 200 according to an example embodiment, and Figure 6 Flowchart of an example embodiment of S50 in FIG.

[0099] refer to Figure 5 and Fig.10 In S510, the interleaving controller 210 (eg, Figure 5 The command scheduler 212 in the command queue 231 may select an interleaved command from the write commands queued in the command queue 231 to perform an interleaved operation. For example, the interleaved command may be at least a portion of the queued write commands.

[0100] In S520, the command scheduler 212 may calculate an interleaving power level to be consumed due to the interleaving operation according to the interleaving command. For example, the command scheduler 212 may sum the level of write power to be consumed in the memory device 100 due to the write operation according to each interleaving command to calculate the interleaving power level.

[0101] In S530, the command scheduler 212 may determine whether the calculated interleaving power level exceeds a reference power level. The reference power level may be set to a maximum power level available when the memory device 100 performs a write operation on a plurality of memory banks according to the interleaving operation.

[0102] When the interleaving power level does not exceed the reference power level, in S540 , the command scheduler 212 may schedule the interleaving commands. For example, the command scheduler 212 may schedule the interleaving commands so that the interleaving commands can be sent to the memory device 100 sequentially.

[0103] Meanwhile, when the interleaving power level exceeds the reference power level, the command scheduler 212 may reselect an interleaving command that performs an interleaving operation among the write commands queued in the command queue 231 to meet the reference power level when returning to S510. For example, the command scheduler 212 may exclude at least one of the previously selected interleaving commands to select other interleaving commands. Alternatively, for example, the command scheduler 212 may exclude at least one of the previously selected interleaving commands and select another write command that is not selected as the interleaving command.

[0104] In S550, the command scheduler 212 may check whether there is an unscheduled queued write command. When there is an unscheduled queued write command, the command scheduler 212 may perform S510 to S540 again.

[0105] The operating method of the memory controller 200 according to the present invention can control the interleaving operation in consideration of the interleaving power level caused by the interleaving operation of a plurality of write commands after preliminarily calculating the level of write power according to each write command. Therefore, the number of write commands used to perform the interleaving operation can be increased to reduce the time required for the write operation, and the power consumption of the memory device 100 caused by the write operation can be effectively managed.

[0106] Fig.11It is used to illustrate Fig.10 A timing diagram of an example embodiment of S50 in FIG. Fig.11 is a diagram showing a time at which a target memory bank performs a write operation or a read operation according to a command to be transmitted to the memory device 100 .

[0107] refer to Fig. 9 , Fig.10 and Fig.11 , command scheduler (e.g., Figure 5 The command scheduler 212 may schedule the first write command WCMD0 to the fourth write command WCMD3 of the first write command WCMD0 to the tenth write command WCMD9 queued in the command queue, which does not exceed the reference value (e.g., 4), to perform an interleaved operation. For example, the command scheduler 212 may schedule the first write command WCMD0 to the fourth write command WCMD3 so that the memory controller 200 may sequentially send the first write command WCMD0 to the fourth write command WCMD3 to the memory device 100, and the memory device 100 may simultaneously perform write operations according to the first write command WCMD0 to the fourth write command WCMD3 during a period of time.

[0108] In S510, the command scheduler 212 may select the fifth write command WCMD4 together with the first write command WCMD0 to the fourth write command WCMD3. In S520, the calculated interleaving power level is level 35 (8+8+8+8+3) and exceeds the reference power level (e.g., level 32). Therefore, the command scheduler 212 may schedule the fifth write command WCMD4 to be provided to the memory device after the time point t1 at which the write operation according to the first write command WCMD0 ends. For example, the command scheduler 212 may schedule the second write command WCMD1 to the fifth write command WCMD4 so that the memory controller 200 may sequentially send the second write command WCMD1 to the fifth write command WCMD4 to the memory device 100, and after the time point t1, the memory device 100 may simultaneously perform write operations according to the second write command WCMD1 to the fifth write command WCMD4 during a period of time.

[0109] Again in S510, the command scheduler 212 may select the sixth write command WCMD5 together with the second write command WCMD1 to the fifth write command WCMD4. In S520, the calculated interleaving power level is level 35 (8+8+8+3+8) and exceeds the reference power level 32. After the time point t2 at which the write operation according to the second write command WCMD1 ends, the memory device 100 may perform the interleaving operation together with the sixth write command WCMD5 according to the third write command WCMD2 to the fifth write command WCMD4. Therefore, the command scheduler 212 may schedule the sixth write command WCMD5 to be provided to the memory device after the time point t2 at which the write operation according to the second write command WCMD1 ends. For example, the command scheduler 212 can schedule the third write command WCMD2 to the sixth write command WCMD5, so that the memory controller 200 can sequentially send the third write command WCMD2 to the sixth write command WCMD5 to the memory device 100, and after time point t2, the memory device 100 can simultaneously perform write operations according to the third write command WCMD2 to the sixth write command WCMD5 during a period of time.

[0110] Again in S510, the command scheduler 212 may select the seventh write command WCMD6 together with the third write command WCMD2 to the sixth write command WCMD5. In S520, the calculated interleaving power level is level 33 (8+8+3+8+6) and exceeds the reference power level 32. After the time point t3 at which the write operation according to the third write command WCMD2 ends, the memory device 100 may perform the interleaving operation according to the fourth write command WCMD3 to the sixth write command WCMD5 together with the seventh write command WCMD6. Therefore, the command scheduler 212 may schedule the seventh write command WCMD6 to be provided to the memory device 100 after the time point t3 at which the write operation according to the third write command WCMD2 ends.

[0111] Again in S510, the command scheduler 212 may select the eighth write command WCMD7 together with the fourth write command WCMD3 to the seventh write command WCMD6. In S520, the calculated interleaving power level is level 29 (8+3+8+6+4) and has a power level equal to or less than the reference power level 32. Therefore, after the time point t3 at which the write operation according to the third write command WCMD2 ends, the command scheduler 212 may schedule the seventh write command WCMD6 and the eighth write command WCMD7 to be provided to the memory device. For example, the command scheduler 212 may schedule the fourth write command WCMD3 to the eighth write command WCMD7 so that the memory controller 200 may sequentially send the fourth write command WCMD3 to the eighth write command WCMD7 to the memory device 100, and after the time point t3, the memory device 100 may simultaneously perform write operations according to the fourth write command WCMD3 to the eighth write command WCMD7 during a period of time.

[0112] Again in S510, the command scheduler 212 may select the ninth write command WCMD8 together with the fourth write command WCMD3 to the eighth write command WCMD7. In S520, the calculated interleaving power level is level 33 (8+3+8+6+4+4) and exceeds the reference power level 32. After the time point t4 at which the write operation according to the fourth write command WCMD3 ends, the memory device 100 may perform the interleaving operation according to the fifth write command WCMD4 to the eighth write command WCMD7 together with the ninth write command WCMD8. Therefore, the command scheduler 212 may schedule the ninth write command WCMD8 to be provided to the memory device after the time point t4 at which the write operation according to the fourth write command WCMD3 ends.

[0113] Again in S510, the command scheduler 212 may select the tenth write command WCMD9 together with the fifth write command WCMD4 to the ninth write command WCMD8. In S520, the calculated interleaving power level is level 28 (3+8+6+4+4+3) and has a power level equal to or less than the reference power level 32. Therefore, after the time point t4 at which the write operation according to the fourth write command WCMD3 ends, the command scheduler 212 may schedule the ninth write command WCMD8 and the tenth write command WCMD9 to be provided to the memory device 100. For example, the command scheduler 212 may schedule the fifth write command WCMD4 to the tenth write command WCMD9 so that the memory controller 200 may sequentially send the fifth write command WCMD4 to the tenth write command WCMD9 to the memory device 100, and after the time point t4, the memory device 100 may simultaneously perform write operations according to the fifth write command WCMD4 to the tenth write command WCMD9 during a period of time.

[0114] Fig. 12A It is used to illustrate Fig.10 A timing diagram of an example embodiment of S50 in FIG. Fig. 12A is a diagram showing a time at which a target memory bank performs a write operation or a read operation according to a command to be transmitted to the memory device 100 .

[0115] refer to Fig. 9 , Fig.10 and Fig. 12A , command scheduler (e.g., Figure 5 The command scheduler 212 may schedule the first write command WCMD0 to the fourth write command WCMD3 of the first write command WCMD0 to the tenth write command WCMD9 queued in the command queue, which does not exceed the reference value (e.g., 4), to perform an interleaved operation. For example, the command scheduler 212 may schedule the first write command WCMD0 to the fourth write command WCMD3 so that the memory controller 200 may sequentially send the first write command WCMD0 to the fourth write command WCMD3 to the memory device 100, and the memory device 100 may simultaneously perform write operations according to the first write command WCMD0 to the fourth write command WCMD3 during a period of time.

[0116] In S510, the command scheduler 212 may select the fifth write command WCMD4 together with the first to fourth write commands WCMD0 to WCMD3. In S520, the calculated interleaving power level is level 35 (8+8+8+8+3) and exceeds the reference power level 32. Therefore, the command scheduler 212 may schedule the fifth write command WCMD4 to be provided to the memory device 100 after the time point t1 at which the write operation according to the first write command WCMD0 ends.

[0117] Again in S510, the command scheduler 212 may select the eighth write command WCMD7 together with the second to fifth write commands WCMD1 to WCMD4. In S520, the calculated interleaving power level is level 31 (8+8+8+3+4) and has a power level equal to or less than the reference power level 32. Therefore, after the time point t1 at which the write operation according to the first write command WCMD0 ends, the command scheduler 212 may schedule the fifth write command WCMD4 and the eighth write command WCMD7 to be provided to the memory device. For example, the command scheduler 212 can schedule the second write command WCMD1 to the fifth write command WCMD4 and the eighth write command WCMD7, so that the memory controller 200 can sequentially send the second write command WCMD1 to the fifth write command WCMD4 and the eighth write command WCMD7 to the memory device 100, and after time point t1, the memory device 100 can simultaneously perform write operations according to the second write command WCMD1 to the fifth write command WCMD4 and the eighth write command WCMD7 during a period of time.

[0118] Again in S510, when the write operation of the second write command WCMD1 ends at the time point t2, the command scheduler 212 may also select the ninth write command WCMD8 and the tenth write command WCMD9 together with the third write command WCMD2, the fourth write command WCMD3, the fifth write command WCMD4, and the eighth write command WCMD7. In S520, the calculated interleaving power level is level 30 (8+8+3+4+4+3) and has a power level equal to or less than the reference power level 32. Therefore, the command scheduler 212 may schedule the ninth write command WCMD8 and the tenth write command WCMD9 to be provided to the memory device 100 after the time point t2 at which the write operation according to the second write command WCMD1 ends. For example, the command scheduler 212 can schedule the third write command WCMD2 to the fifth write command WCMD4 and the eighth write command WCMD7 to the tenth write command WCMD9, so that the memory controller 200 can sequentially send the third write command WCMD2 to the fifth write command WCMD4 and the eighth write command WCMD7 to the tenth write command WCMD9 to the memory device 100, and after time point t2, the memory device 100 can simultaneously perform write operations according to the third write command WCMD2 to the fifth write command WCMD4 and the eighth write command WCMD7 to the tenth write command WCMD9 during a period of time.

[0119] Again in S510, when the write operation according to the third write command WCMD2 ends at time point t3, the command scheduler 212 may further select the seventh write command WCMD6 together with the fourth write command WCMD3, the fifth write command WCMD4, the eighth write command WCMD7, the ninth write command WCMD8, and the tenth write command WCMD9. In S520, the calculated interleaving power level is level 28 (8+3+4+4+3+6) and has a power level equal to or less than the reference power level 32. Therefore, the command scheduler 212 may schedule the seventh write command WCMD6 to be provided to the memory device after time point t3 at which the write operation according to the third write command WCMD2 ends. For example, the command scheduler 212 can schedule the fourth write command WCMD3 and the fifth write command WCMD4, the eighth write command WCMD7 to the tenth write command WCMD9, and the seventh write command WCMD6, so that the memory controller 200 can sequentially send the fourth write command WCMD3 and the fifth write command WCMD4, the eighth write command WCMD7 to the tenth write command WCMD9, and the seventh write command WCMD6 to the memory device 100, and after time point t3, the memory device 100 can simultaneously perform write operations according to the fourth write command WCMD3 and the fifth write command WCMD4, the eighth write command WCMD7 to the tenth write command WCMD9, and the seventh write command WCMD6 during a period of time.

[0120] Again in S510, when the write operation according to the fourth write command WCMD3 ends at time point t4, the command scheduler 212 may further select the sixth write command WCMD5 together with the fifth write command WCMD4, the eighth write command WCMD7 to the tenth write command WCMD9, and the seventh write command WCMD6. In S520, the calculated interleaving power level is level 28 (3+4+4+3+6+8) and has a power level equal to or less than the reference power level 32. Therefore, the command scheduler 212 may schedule the sixth write command WCMD5 to be provided to the memory device after time point t4 at which the write operation according to the fourth write command WCMD3 ends. For example, the command scheduler 212 can schedule the fifth write command WCMD4, the eighth write command WCMD7 to the tenth write command WCMD9, the seventh write command WCMD6, and the sixth write command WCMD5, so that the memory controller 200 can sequentially send the fifth write command WCMD4, the eighth write command WCMD7 to the tenth write command WCMD9, the seventh write command WCMD6, and the sixth write command WCMD5 to the memory controller 100, and after time point t4, the memory device 100 can simultaneously perform write operations according to the fifth write command WCMD4, the eighth write command WCMD7 to the tenth write command WCMD9, the seventh write command WCMD6, and the sixth write command WCMD5 during a period of time.

[0121] refer to Fig.11 and Fig. 12A , the operating method of the memory controller 200 according to the present invention can control the interleaving operation by considering the interleaving power level caused by the interleaving operation of multiple write commands after preliminarily calculating the level of write power according to each write command. Therefore, the number of accessible memory banks used simultaneously by the interleaving operation can be increased without being limited to a specific value. In addition, the power consumption of the memory device 100 caused by the write operation can be effectively managed.

[0122] Fig. 12B yes Figure 5 The table of example embodiments of the command queue 231 is shown in FIG. Fig. 12A The operation of the command scheduler is described in the diagram of the command queue that changes.

[0123] refer to Fig. 8A , Fig. 12A and Fig. 12B , the command scheduler 212 can pre-calculate the interleaving power level to be consumed and schedule the interleaving commands. The command scheduler 212 can control Fig. 12B The write command queue 231_1' in Fig. 8AThe order of at least some of the write commands included in the write command queue 231_1 is changed. Fig. 8A The write command queue 231_1 in FIG. 2 may be a write command queue that sequentially stores the first write command WCMD0 to the tenth write command WCMD9 according to the order in which the write request is received from the host. Alternatively, Fig. 12B The write command queue 231_1′ in the memory controller 200 may be newly stored to send the seventh write command WCMD6 after sending the tenth write command WCMD9 to the memory device 100, and to send the sixth write command WCMD5 after sending the seventh write command WCMD6 to the memory device 100. The memory controller 200 may be based on Fig. 12B The write commands are sent to the memory device 100 according to the order of the write commands queued in the write command queue 231_1′ in FIG.

[0124] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An operating method for controlling a memory controller of a memory device including a plurality of memory banks, the operating method comprising: queuing a plurality of write commands in a command queue of the memory controller according to an order in which write requests are received from a host; determining whether the number of write commands queued in a command queue of the memory controller exceeds a reference value; responsive to the number of queued write commands exceeding a reference value, calculating a level of write power consumed by the memory device in response to at least some of the queued write commands; as well as scheduling an interleaved command to perform a first interleaved operation of the memory device from the queued write commands based on the calculated level of write power, The calculation of the write power level includes: selecting at least some of the write commands from the queued write commands to calculate a power level corresponding to each selected write command; checking whether there is a read command corresponding to a target memory bank of a first selected write command and preceding the first selected write command; generating a pre-read command before the first selected write command when both the read command and the write command do not exist before the first selected write command; and comparing pre-read data read from a target memory bank of the memory device in response to the pre-read command with write data corresponding to a first selected write command to calculate a level of write power of the first selected write command, and Wherein, scheduling the staggered commands includes changing an order of a plurality of write commands queued in a command queue based on the calculated level of write power.

2. The operating method according to claim 1, further comprising: When the number of queued write commands does not exceed a reference value, a second interleaving operation of the memory device is controlled by sequentially sending the queued write commands to the memory device.

3. The operating method according to claim 1, wherein: The reference value is a maximum value of the number of memory banks that can be accessed simultaneously when a level of write power consumed in one memory bank according to a write operation has a maximum value.

4. The operating method according to claim 1, wherein: Determining whether the number of queued write commands exceeds a reference value includes determining whether the number of write commands respectively corresponding to different memory banks as target memory banks for writing data among the queued write commands exceeds a reference value.

5. The operating method according to claim 1, wherein: Calculation of write power levels also includes: In response to determining that there is no read command, checking whether there is a second write command corresponding to a target memory bank of the first selected write command and preceding the first selected write command; and When a second write command exists before the first selected write command, the level of write power corresponding to the first selected write command is calculated to have a maximum value.

6. The operating method according to claim 1, wherein: Calculation of write power levels also includes: When there is a read command before the first selected write command, it is checked whether a row address corresponding to the first selected write command and a row address corresponding to the read command are identical to each other.

7. The operating method according to claim 6, wherein: Calculation of write power levels also includes: When a row address corresponding to a write command of the first selection is different from a row address corresponding to a read command, a level of write power corresponding to the write command of the first selection is calculated to have a maximum value.

8. The operating method according to claim 6, wherein: Calculation of write power levels also includes: When a row address corresponding to a first selected write command is the same as a row address corresponding to a read command, read data read from a target storage body of the memory device in response to the read command is compared with write data corresponding to the first selected write command to calculate a level of write power of the first selected write command.

9. The operating method according to claim 1, wherein: Scheduling interleaving commands include: selecting an interleaved command to perform a first interleaved operation from the queued write commands; calculating, based on the selected interleave command, a level of interleave power to be consumed in the memory device due to the first interleave operation; determining whether the level of the interleaved power exceeds a reference power level; and When the level of the interleaving power is equal to or less than the reference power level, the interleaving command is scheduled.

10. The operating method according to claim 9, wherein: Scheduling interleaving commands also includes: When the level of the interleaving power in the first interleaving operation exceeds the reference power level, an interleaving command for performing a third interleaving operation is selected.

11. The operating method according to claim 9, wherein: The reference power level is a maximum value of a power level available when the memory device performs a write operation on the memory bank according to the first interleaving operation.

12. A memory controller for controlling an interleaved operation of a memory device including a plurality of memory banks, the memory controller comprising: a power level calculator configured to calculate a level of write power to be consumed in the memory device in response to at least some of a plurality of write commands to be provided to the memory device; as well as a command scheduler configured to schedule an interleaved command for performing an interleaved operation of the memory device from among the plurality of write commands based on the calculated level of write power, wherein the power level calculator calculates a level of write power in response to the number of the plurality of write commands exceeding a reference value, and Wherein, the power level calculator is further configured to: checking whether there is a read command corresponding to a target memory bank of a first selected write command and preceding the first selected write command, generating a pre-read command before the first selected write command when both the read command and the write command do not exist before the first selected write command, and comparing pre-read data read from a target memory bank of the memory device in response to the pre-read command with write data corresponding to a first selected write command to calculate a level of write power of the first selected write command, wherein the memory controller queues a plurality of write commands in a command queue of the memory controller according to an order of write requests from a host, and Therein, the command scheduler is configured to schedule the interleaved commands by changing an order of a plurality of write commands queued in the command queue based on a calculated level of write power.

13. The memory controller of claim 12, wherein: The reference value is a maximum value of the number of memory banks that can be accessed simultaneously when a level of write power consumed in one memory bank according to a write operation has a maximum value.

14. The memory controller of claim 12, wherein: When there is another write command corresponding to a target memory bank of the first selected write command and preceding the first selected write command, the power level calculator calculates a level of write power corresponding to the first selected write command to have a maximum value.

15. The memory controller of claim 12, wherein: When there is a read command corresponding to a target page of a first selected write command and preceding the first selected write command, the power level calculator compares read data read from the target page of the memory device with write data corresponding to the first selected write command to calculate a level of write power.

16. A memory system comprising: A memory device including a plurality of memory banks and configured to perform a data comparison write operation; as well as a memory controller configured to control interleaved operations of the memory devices, The memory controller includes: a power level calculator configured to calculate a level of write power to be consumed in the memory device in response to at least some of a plurality of write commands to be provided to the memory device, and a command scheduler configured to schedule an interleaved command for performing an interleaved operation of the memory device from the plurality of write commands based on the calculated level of write power, wherein the power level calculator calculates a level of write power in response to the number of the plurality of write commands exceeding a reference value, and Wherein, the power level calculator is further configured to: checking whether there is a read command corresponding to a target memory bank of a first selected write command and preceding the first selected write command, generating a pre-read command before the first selected write command when both the read command and the write command do not exist before the first selected write command, and comparing pre-read data read from a target memory bank of the memory device in response to the pre-read command with write data corresponding to a first selected write command to calculate a level of write power of the first selected write command, wherein the memory controller queues a plurality of write commands in a command queue of the memory controller according to an order of write requests from a host, and Therein, the command scheduler is configured to schedule the interleaved commands by changing an order of a plurality of write commands queued in the command queue based on a calculated level of write power.

17. The memory system of claim 16, wherein: The memory device includes a plurality of resistive memory cells.

Images