semiconductor packages

Abstract

The present invention can provide a semiconductor package, comprising: a first device layer, comprising a first semiconductor device, a first covering insulating layer and a first through-electrode passing through at least a portion of the first device layer; a second device layer, comprising a second semiconductor device, a second covering insulating layer and a second through-electrode passing through at least a portion of the second device layer, the second semiconductor devices vertically overlap with the first semiconductor devices, respectively, and the second covering insulating layer is in contact with the first covering insulating layer; a third device layer, comprising an upper semiconductor chip, the upper semiconductor chip vertically overlaps with at least two of the first semiconductor devices and at least two of the second semiconductor devices; and a device bonding pad, passing through the first covering insulating layer and the second covering insulating layer, the device bonding pad electrically connecting the first through-electrode and the second through-electrode to the upper semiconductor chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2018-0104702 filed on September 3, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to semiconductor packages, and more particularly, to semiconductor packages including a plurality of semiconductor chips. Background Art

[0004] With the development of the electronics industry and growing user demands, electronic devices are being manufactured with more compact designs, more functionality, and / or higher storage capacity. Consequently, there is a need for semiconductor packages that contain two or more types of semiconductor chips, and printed circuit boards (PCBs) or interposers can be used to electrically connect the different types of semiconductor chips. However, achieving fine pitches is difficult when using PCBs, while increased manufacturing costs are unavoidable when using interposers. Summary of the Invention

[0005] At least one or more of the present inventive concepts provide a semiconductor package including a plurality of semiconductor chips having a relatively small form factor, a relatively fine pitch, and / or a relatively low cost.

[0006] According to an example embodiment, a semiconductor package includes: a first device layer, including a plurality of first semiconductor devices, a first covering insulating layer, and a plurality of first through-electrodes passing through at least a portion of the first device layer; a second device layer, including a plurality of second semiconductor devices, a second covering insulating layer, and a plurality of second through-electrodes passing through at least a portion of the second device layer, the plurality of second semiconductor devices vertically overlapping with the plurality of first semiconductor devices, respectively, and the second covering insulating layer contacting the first covering insulating layer; a third device layer, including an upper semiconductor chip, the upper semiconductor chip vertically overlapping with at least two of the plurality of first semiconductor devices and vertically overlapping with at least two of the plurality of second semiconductor devices; and a plurality of device bonding pads passing through the first covering insulating layer and the second covering insulating layer, the plurality of device bonding pads electrically connecting the plurality of first through-electrodes and the plurality of second through-electrodes to the upper semiconductor chip.

[0007] According to an example embodiment, a semiconductor package includes a first device layer, a second device layer, a third device layer, and a plurality of device bonding pads. The first device layer may include: (1) a first semiconductor substrate; (2) a plurality of first through-electrodes located in a plurality of first semiconductor chip regions and passing through the first semiconductor substrate; and (3) a first covering insulating layer covering the active surface of the first semiconductor substrate. The first semiconductor substrate may have an active surface and may include one or more first scribe lines and a plurality of first semiconductor chip regions, the plurality of first semiconductor chip regions being separated from each other by one or more first scribe line regions therebetween, each of the plurality of first semiconductor chip regions being provided with a first semiconductor device on the active surface of the first semiconductor substrate. The second device layer may include: (1) a second semiconductor substrate; (2) a plurality of second through-electrodes located in a plurality of second semiconductor chip regions and passing through the second semiconductor substrate; and (3) a second insulating layer covering the active surface of the second semiconductor substrate and contacting the first covering insulating layer. The second semiconductor substrate has an active surface and may include one or more second scribe line regions and a plurality of second semiconductor chip regions, the plurality of second semiconductor chip regions being separated from each other by the one or more second scribe line regions therebetween. Each of the plurality of second semiconductor chip regions has a second semiconductor device disposed on the active surface of the second semiconductor substrate, the second semiconductor device being of the same type as the first semiconductor device. The third device layer may include an upper semiconductor chip, the upper semiconductor chip being located on the second device layer and electrically connected to the plurality of second through-electrodes. A plurality of device bonding pads may pass through the first and second cover insulating layers and electrically connect the first device layer to the second device layer.

[0008] According to an example embodiment, a semiconductor package includes: a first semiconductor substrate having an active surface and including a plurality of scribe line regions and a plurality of first semiconductor chip regions, the plurality of first semiconductor chip regions being spaced apart from each other by corresponding scribe line regions among the plurality of scribe line regions therebetween, each of the plurality of first semiconductor chip regions being provided with at least one first semiconductor device on the active surface of the first semiconductor substrate; a plurality of first through electrodes located in the plurality of first semiconductor chip regions and passing through the first semiconductor substrate; a first cover insulating layer covering the active surface of the first semiconductor substrate; a plurality of lower semiconductor chips located on the first semiconductor substrate and corresponding to the plurality of first semiconductor devices, respectively. A first semiconductor chip region, each of the plurality of lower semiconductor chips includes a second semiconductor substrate having an active surface on which a second semiconductor device is positioned, the second semiconductor substrate includes a plurality of second through-electrodes passing therethrough and a second covering insulating layer covering the active surface of the second semiconductor substrate and in contact with the first covering insulating layer; a plurality of device bonding pads passing through the first covering insulating layer and the second covering insulating layer and electrically connecting the plurality of first through-electrodes to the plurality of second through-electrodes; and an upper semiconductor chip including a third semiconductor device and vertically overlapping at least two of the plurality of lower semiconductor chips and electrically connected to the plurality of second through-electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figures 1A to 1I are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0011] Figure 2 is a cross-sectional view of a semiconductor package according to example embodiments.

[0012] Figures 3A to 3C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0013] Figure 4 According to an example embodiment, Figures 3A to 3C A cross-sectional view of a semiconductor package formed by the method shown in FIG.

[0014] Figures 5A to 5D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0015] Figure 6 According to an example embodiment, Figures 5A to 5D A cross-sectional view of a semiconductor package formed by the method shown in FIG.

[0016] Figures 7A to 7C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0017] Figure 8 According to an example embodiment, Figures 7A to 7C A cross-sectional view of a semiconductor package formed by the method shown in FIG.

[0018] Figures 9A to 9C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0019] Figure 10 According to an example embodiment, Figures 9A to 9C A cross-sectional view of a semiconductor package formed by the method shown in FIG.

[0020] Figures 11A to 11E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0021] Figure 12 According to an example embodiment, Figures 11A to 11E A cross-sectional view of a semiconductor package formed by the method shown in FIG.

[0022] Figure 13A and Figure 13B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0023] Figure 14 According to an example embodiment, FIG. 13A to FIG. 13B A cross-sectional view of a semiconductor package formed by the method shown in FIG.

[0024] Figure 15A and Figure 15B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0025] Figure 16 According to an example embodiment, Figure 15A and Figure 15B A cross-sectional view of a semiconductor package formed by the method shown in FIG.

[0026] Figure 17A and Figure 17B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0027] Figure 18 According to an example embodiment, Figure 17A and Figure 17B A cross-sectional view of a semiconductor package formed by the method shown in FIG.

[0028] Figures 19A to 19C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0029] Figure 20 and Figure 21 is a plan view illustrating a layout of a plurality of semiconductor chips of a semiconductor package according to some example embodiments.

[0030] Figure 22(a) to Figure 24(d) is a cross-sectional view for conceptually describing a process of forming a device bonding pad, a chip bonding pad, and an additional bonding pad according to a method of manufacturing a semiconductor package according to an embodiment.

[0031] Explanation of Figure Numbers

[0032] 1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 2, 2a: semiconductor packages;

[0033] 10: carrier substrate;

[0034] 20: Adhesion film;

[0035] 100: a first semiconductor substrate;

[0036] 110: a first semiconductor device;

[0037] 120: Wiring structure;

[0038] 130: device bonding pad;

[0039] 132: first internal connection pad;

[0040] 134: second internal connection pad;

[0041] 135, 135d: additional bonding pads;

[0042] 136, 136d: first additional connection pad;

[0043] 138, 138d: second additional connection pad;

[0044] 142: first covering insulating layer;

[0045] 144: second covering insulating layer;

[0046] 150: through the electrode;

[0047] 152, 152d: additional penetrating electrodes;

[0048] 160: upper connection pad;

[0049] 162, 162d: additional upper connection pads;

[0050] 170: third covering insulating layer;

[0051] 180, 180f: plastic hole;

[0052] 190, 190e, 190f, 190h: filling molded member;

[0053] 195, 195f: through hole;

[0054] 200: second semiconductor substrate;

[0055] 210: second semiconductor device;

[0056] 250: Chip connection terminal;

[0057] 252, 252d, 252e, 252f: additional chip connection terminals;

[0058] 260, 260a: chip connection pads;

[0059] 262, 262d: additional chip connection pads;

[0060] 265: chip bonding pad;

[0061] 270: Chip covered with insulating layer;

[0062] 300, 300g: Molded components;

[0063] 510, 510c, 510d: rewiring conductive pattern;

[0064] 520, 520c, 520d: rewiring via pattern;

[0065] 530: Rewire insulation;

[0066] 550: external connection terminal;

[0067] 552, 552d: additional external connection terminals;

[0068] CR, CR-1, CR-2: semiconductor chip area;

[0069] DC: lower semiconductor chip;

[0070] DL1, DL1c, DL1d, DL1e, DL1h: first device layer;

[0071] DL2, DL2a, DL2b, DL2c, DL2d, DL2e, DL2f, DL2g: second device layer;

[0072] DL3, DL3a, DL3c, DL3d, DL3e, DL3f: third device layer;

[0073] IR, IR-2: intermediate region;

[0074] RS, RSh: concave space;

[0075] RDS, RDSc, RDSd, RDSe: rewiring structure;

[0076] SL, SLd, SL-1, SL-2: marked areas;

[0077] SLR: residual scribe region;

[0078] UC, UCa, UCc, UCd, UC-1, UC-2: upper semiconductor chip;

[0079] W1: first width;

[0080] W2: second width;

[0081] WF1, WF1c, WF1d: first wafer;

[0082] WF2, WF2c, WF2d: second wafer. DETAILED DESCRIPTION

[0083] Figures 1A to 1I are cross-sectional views sequentially illustrating a method of manufacturing the semiconductor package 1 according to example embodiments. Figure 2 is a cross-sectional view of a semiconductor package 1 according to example embodiments.

[0084] See Figure 1A , preparing a first wafer WF1 and a second wafer WF2. Each of the first wafer WF1 and the second wafer WF2 may include a plurality of semiconductor chip regions CR divided by scribe lines SL. The plurality of semiconductor chip regions CR refer to portions separated from the first wafer WF1 or the second wafer WF2 by a sawing process performed along the scribe lines SL and may be handled as separate semiconductor chips.

[0085] In some example embodiments, the first wafer WF1 and the second wafer WF2 may be manufactured using the same or substantially similar processes. Therefore, elements of the first wafer WF1 and the second wafer WF2, except for elements to be distinguished from each other or different elements, may be labeled with the same reference numerals.

[0086] Each of the first wafer WF1 and the second wafer WF2 may include a first semiconductor substrate 100 including a plurality of semiconductor chip regions CR and a scribe line region SL. A first semiconductor device 110, a wiring structure 120, a plurality of first internal connection pads 132, a first cover insulating layer 142, and a plurality of through-electrodes 150 may be located in each of the plurality of semiconductor chip regions CR of the first wafer WF1. The first semiconductor device 110, the wiring structure 120, a plurality of second internal connection pads 134, a second cover insulating layer 144, and a plurality of through-electrodes 150 may be located in each of the plurality of semiconductor chip regions CR of the second wafer WF2.

[0087] The first semiconductor substrate 100 may include a semiconductor (e.g., silicon (Si) or germanium (Ge)) or a compound semiconductor (e.g., silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). The first semiconductor substrate 100 may have an active surface and an inactive surface opposite to the active surface. For example, the first semiconductor device 110 and the wiring structure 120 may be located on the active surface of the first semiconductor substrate 100.

[0088] The first semiconductor device 110 may be, for example, a memory device. In some embodiments, the first semiconductor device 110 may be a high-bandwidth memory (HBM) or dynamic random access memory (DRAM) device. The first semiconductor devices 110 in the plurality of semiconductor chip regions CR of the first wafer WF1 and the second wafer WF2 may be the same type of semiconductor chips.

[0089] The wiring structure 120 may be electrically connected to the first semiconductor device 110 and / or the through-electrode 150. The wiring structure 120 may include at least one metal wiring layer and at least one via plug connected to the at least one metal wiring layer.

[0090] The first and second cover insulating layers 142 and 144 may cover the sidewalls of the first and second internal connection pads 132 and 134, respectively, but may not cover and may expose the top surfaces of the first and second internal connection pads 132 and 134, respectively. The first and second cover insulating layers 142 and 144 may cover the first semiconductor substrate 100 even in the scribe line regions SL of the first wafer WF1 and the scribe line regions SL of the second wafer WF2. Each of the first and second cover insulating layers 142 and 144 may be formed of SiO, SiN, SiCN, SiCO, or a polymer material. Examples of polymer materials include benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), silicone, acrylate, and epoxy resin.

[0091] In some example embodiments, after forming the plurality of first internal connecting pads 132 and the plurality of second internal connecting pads 134, the first cover insulating layer 142 and the second cover insulating layer 144 may be formed. In other example embodiments, after forming the first cover insulating layer 142 and the second cover insulating layer 144 having a plurality of holes corresponding to the plurality of first internal connecting pads 132 and the plurality of second internal connecting pads 134, the plurality of first internal connecting pads 132 and the plurality of second internal connecting pads 134 filling the plurality of holes may be formed. Each of the plurality of first internal connecting pads 132 and the plurality of second internal connecting pads 134 may be formed of a material including, for example, copper (Cu).

[0092] In some example embodiments, the top surfaces of the plurality of first internal connecting pads 132, the top surface of the first cover insulating layer 142, the top surfaces of the plurality of second internal connecting pads 134, and the top surface of the second cover insulating layer 144 may be on the same plane (e.g., may be coplanar). In other example embodiments, one of the first internal connecting pads 132 or the second internal connecting pads 134 may protrude from the corresponding top surface of the top surface of the first cover insulating layer 142 or the top surface of the second cover insulating layer 144, and the other of the first internal connecting pads 132 or the second internal connecting pads 134 may be recessed from the corresponding top surface of the top surface of the first cover insulating layer 142 or the top surface of the second cover insulating layer 144. The widths of the plurality of first internal connecting pads 132 and the widths of the plurality of second internal connecting pads 134 may be the same in some example embodiments, and may be different in other example embodiments.

[0093] The through-electrode 150 may have a first end connected to the wiring structure 120 and a second end extending into the first semiconductor substrate 100. The through-electrode 150 may have at least a columnar portion. The through-electrode 150 may include a barrier film formed on a surface of the columnar portion and a buried conductive layer filling the barrier film, and an insulating film may be located between the first semiconductor substrate 100 and the through-electrode 150.

[0094] See Figure 1B The second wafer WF2 is attached to the first wafer WF1 such that the first cover insulating layer 142 and the second cover insulating layer 144 are in contact with each other, and the plurality of first internal connection pads 132 and the plurality of second internal connection pads 134 correspond to each other. The first cover insulating layer 142 and the second cover insulating layer 144 can be adhered to each other by applying heat and / or pressure during the process of attaching the second wafer WF2 to the first wafer WF1. For example, heat at a first temperature can be applied during the process of attaching the second wafer WF2 to the first wafer WF1.

[0095] See Figure 1B and Figure 1C , the plurality of first internal connection pads 132 and the plurality of second internal connection pads 134 may be bonded to correspond to each other by applying heat at a second temperature higher than the first temperature to obtain a plurality of device bonding pads 130. The plurality of first internal connection pads 132 and the corresponding second internal connection pads of the plurality of second internal connection pads 134 may expand due to the heat to contact each other, and then metal atoms may diffuse and become one, thereby forming the plurality of device bonding pads 130.

[0096] See Figure 1D , a portion of the first semiconductor substrate 100 of the second wafer WF2 is removed to expose the through-electrodes 150 of the second wafer WF2. In some example embodiments, after removing a portion of the edge of the first semiconductor substrate 100 of the second wafer WF2, an upper portion of the first semiconductor substrate 100 of the second wafer WF2 may be removed to expose the through-electrodes 150 of the second wafer WF2.

[0097] See Figure 1E , a plurality of upper connection pads 160 electrically connected to each of the plurality of through electrodes 150 are formed on the first semiconductor substrate 100 of the second wafer WF2. In some exemplary embodiments, a protective insulating layer (not shown) may be further formed, the protective insulating layer covering the top surface of the first semiconductor substrate 100 of the second wafer WF2 and exposing the plurality of upper connection pads 160. Figure 1EThe plurality of upper connection pads 160 are directly connected to the plurality of through electrodes 150, but example embodiments are not limited thereto. In some example embodiments, the plurality of upper connection pads 160 and the plurality of through electrodes 150 may be electrically connected to each other via a conductive rewiring pattern (not shown).

[0098] See Figure 1F Attached to the second wafer WF2 are upper semiconductor chips UC, each of which includes a plurality of chip connection pads 260 electrically connected to the plurality of upper connection pads 160. One upper semiconductor chip UC can be attached to the second wafer WF2 to correspond to at least two semiconductor chip regions CR of each of the first wafer WF1 and the second wafer WF2. In other words, one upper semiconductor chip UC can correspond to at least four semiconductor chip regions CR of the first wafer WF1 and the second wafer WF2.

[0099] Each upper semiconductor chip UC may include a second semiconductor substrate 200, a second semiconductor device 210, and a plurality of chip connection pads 260. The second semiconductor substrate 200 may include a semiconductor or a compound semiconductor. The second semiconductor substrate 200 may have an active surface and an inactive surface opposite the active surface. For example, the second semiconductor device 210 and the plurality of chip connection pads 260 may be located on the active surface of the second semiconductor substrate 200.

[0100] The second semiconductor device 210 may be, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0101] The plurality of chip connection terminals 250 may be located between the plurality of upper connection pads 160 and corresponding chip connection pads among the plurality of chip connection pads 260. The plurality of chip connection terminals 250 may be, for example, bumps or solder balls.

[0102] A molding member 300 surrounding the upper semiconductor chip UC is formed on the second wafer WF2. The molding member 300 may be formed, for example, from an epoxy molding compound (EMC). The molding member 300 may surround the top surface of the second wafer WF2 and the side surfaces of the upper semiconductor chip UC. In some example embodiments, the molding member 300 may not cover and may expose the top surface of the upper semiconductor chip UC.

[0103] See Figure 1G , in making Figure 1FAfter the resulting structure is inverted (e.g., flipped) so that the first wafer WF1 is located above (e.g., on) the second wafer WF2, a portion of the first semiconductor substrate 100 of the first wafer WF1 is removed to expose the through-electrodes 150 of the first wafer WF1. In some example embodiments, after removing a portion of the edge of the first semiconductor substrate 100 of the first wafer WF1, an upper portion of the first semiconductor substrate 100 may be removed to expose the through-electrodes 150 of the first wafer WF1.

[0104] See Figure 1H A rewiring structure RDS is formed on the first wafer WF1. The rewiring structure RDS may include a plurality of rewiring insulating layers 530, a plurality of rewiring conductive patterns 510, and a plurality of rewiring via patterns 520. The plurality of rewiring conductive patterns are located on at least one of the top and bottom surfaces of the plurality of rewiring insulating layers 530. The plurality of rewiring via patterns respectively pass through at least one of the plurality of rewiring insulating layers 530 and connect to corresponding one or more rewiring conductive patterns in the plurality of rewiring conductive patterns 510. Each of the plurality of rewiring conductive patterns 510 and the plurality of rewiring via patterns 520 may include a seed layer in contact with the rewiring insulating layer 530 and a conductive material layer on the seed layer.

[0105] Each of the plurality of rewiring conductive patterns 510 and the plurality of rewiring via patterns 520 may include, but is not limited to, a metal, a metal alloy, or a metal nitride. Each of the plurality of rewiring insulating layers 530 may include, for example, an organic compound. In some example embodiments, each of the plurality of rewiring insulating layers 530 may include an organic polymer material (e.g., photosensitive polyimide (PSPI)).

[0106] The rewiring conductive pattern 510 and the rewiring via pattern 520 may be electrically connected to the through-electrodes 150 of the first wafer WF1. External connection terminals 550 contacting the rewiring conductive pattern 510 and electrically connected to the through-electrodes 150 of the first wafer WF1 may be attached to the rewiring structure RDS.

[0107] In some example embodiments, before forming the rewiring structure RDS, a plurality of lower connection pads (not shown) electrically connected to the plurality of through electrodes 150 and / or a protective insulating layer (not shown) covering the top surface of the first semiconductor substrate 100 and exposing the plurality of lower connection pads may be formed on the first semiconductor substrate 100 of the first wafer WF1. The plurality of lower connection pads may be formed in the same or substantially similar manner as that used to form the plurality of upper connection pads 160. In other example embodiments, when some of the plurality of rewiring conductive patterns 510 and some of the plurality of rewiring insulating layers 530 perform the functions of the plurality of lower connection pads and the protective insulating layer, the plurality of lower connection pads and the protective insulating layer may not be additionally formed.

[0108] See Figure 1H and Figure 1I A plurality of semiconductor packages 1 spaced apart from one another are formed by dicing a rewiring structure RDS, a first wafer WF1, a second wafer WF2, and a molding member 300 along scribe line regions SL that do not vertically overlap with the upper semiconductor chip UC. In each semiconductor package 1, a rewiring structure RDS, a first device layer DL1 (a portion of the first wafer WF1 spaced apart by dicing to have at least two semiconductor chip regions CR), a second device layer DL2 (a portion of the second wafer WF2 spaced apart by dicing to have at least two semiconductor chip regions CR), and a third device layer DL3 (the third device layer including the upper semiconductor chip UC) may be stacked in sequence.

[0109] See Figure 2 In the semiconductor package 1, a rewiring structure RDS, a first device layer DL1 including at least two semiconductor chip regions CR, a second device layer DL2 including at least two semiconductor chip regions CR, and a third device layer DL3 including an upper semiconductor chip UC may be stacked in sequence. Corresponding semiconductor chip regions in the at least two semiconductor chip regions CR of the first device layer DL1 and the at least two semiconductor chip regions CR of the second device layer DL2 may vertically overlap each other.

[0110] The first device layer DL1 may include a first semiconductor substrate 100, a first semiconductor device 110, a wiring structure 120, a plurality of through-electrodes 150 extending through the first semiconductor substrate 100, and a first cover insulating layer 142. The second device layer DL2 may include the first semiconductor substrate 100, the first semiconductor device 110, the wiring structure 120, a plurality of through-electrodes 150 extending through the first semiconductor substrate 100, and a second cover insulating layer 144. The second device layer DL2 may be located on the first device layer DL1 such that the first cover insulating layer 142 and the second cover insulating layer 144 are in contact with each other. The device bonding pad 130 may pass through the first cover insulating layer 142 and the second cover insulating layer 144 and may electrically connect the wiring structure 120 of the first device layer DL1 to the wiring structure 120 of the second device layer DL2. Therefore, the device bonding pad 130 may electrically connect the through-electrodes 150 of the first device layer DL1 to the through-electrodes 150 of the second device layer DL2. A plurality of upper connection pads 160 electrically connected to the plurality of through-electrodes 150 of the second device layer DL2 may be located on the second device layer DL2. At least some of the plurality of through-electrodes 150 of each of the first device layer DL1 and the second device layer DL2 may be electrically connected to the first semiconductor device 110 of each of the first device layer DL1 and the second device layer DL2. In some example embodiments, at least some of the plurality of through-electrodes 150 of each of the first device layer DL1 and the second device layer DL2 may be used only for electrical connection to the second semiconductor device 210.

[0111] Each of the first device layer DL1 and the second device layer DL2 may include a scribe line region SL separating at least two semiconductor chip regions CR (a first semiconductor device 110 is positioned in each of the at least two semiconductor chip regions), and may include a residual scribe line region SLR surrounding the at least two semiconductor chip regions CR at an edge of each of the first device layer DL1 and the second device layer DL2.

[0112] By segmentation, see Figure 1H and Figure 1I In the described process of forming a plurality of semiconductor packages 1 spaced apart from each other using the rewiring structure RDS, the first wafer WF1 , the second wafer WF2 , and the molding member 300 , the residual scribe line region SLR refers to a portion of the scribe line region SL remaining after dicing.

[0113] For example, when a wafer is cut into a plurality of semiconductor chips spaced apart from each other along the scribe line regions, only a portion of the scribe line regions may remain as residual scribe line regions SLR along the edge of each semiconductor chip.

[0114] However, in the semiconductor package 1 according to example embodiments, since each of the first device layer DL1 and the second device layer DL2 includes at least two semiconductor chip regions CR, the unpartitioned scribe line region SL may be located between the at least two semiconductor chip regions CR, and the parted residual scribe line region SLR may be located at the edge of each of the first device layer DL1 and the second device layer DL2. The first width W1 (which is the width of the scribe line region SL of each of the first device layer DL1 and the second device layer DL2) may be greater than the second width W2 (which is the width of each of the parted residual scribe line regions SLR). In some example embodiments, the first width W1 may be greater than twice the second width W2.

[0115] The rewiring structure RDS may include a plurality of rewiring insulating layers 530, a plurality of rewiring conductive patterns 510, and a plurality of rewiring via patterns 520. The plurality of rewiring conductive patterns are located on at least one of the top and bottom surfaces of the plurality of rewiring insulating layers 530. The plurality of rewiring via patterns each penetrate at least one of the plurality of rewiring insulating layers 530 and connect to a corresponding one or more of the plurality of rewiring conductive patterns 510. The rewiring conductive patterns 510 and the rewiring via patterns 520 may be electrically connected to the through-electrodes 150 of the first device layer DL1. External connection terminals 550 electrically connected to the rewiring conductive patterns 510 may be attached to the rewiring structure RDS facing the first device layer DL1. The external connection terminals 550 may be attached to the bottom surface of the rewiring structure RDS, and the first device layer DL1 may be located on the top surface of the rewiring structure RDS.

[0116] The third device layer DL3 includes an upper semiconductor chip UC, which includes a plurality of chip connection pads 260 electrically connected to the plurality of upper connection pads 160. The upper semiconductor chip UC may vertically overlap at least two semiconductor chip regions CR of the first device layer DL1 and the second device layer DL2. In other words, the upper semiconductor chip UC may correspond to at least four semiconductor chip regions CR of the first device layer DL1 and the second device layer DL2. A plurality of chip connection terminals 250 may be located between the plurality of upper connection pads 160 and corresponding ones of the plurality of chip connection pads 260.

[0117] A molding member 300 surrounding the upper semiconductor chip UC may be located on the second device layer DL2. The molding member 300 may surround the top surface of the second device layer DL2 and the side surfaces of the upper semiconductor chip UC. In some example embodiments, the molding member 300 may not cover and may expose the top surface of the upper semiconductor chip UC. In some example embodiments, the top surface of the molding member 300 and the top surface of the upper semiconductor chip UC may be on the same plane (e.g., may be coplanar).

[0118] In some embodiments, a heat dissipation member (not shown) may be attached to the top surface of the upper semiconductor chip UC. A thermal interface material (TIM) layer may be located between the top surface of the upper semiconductor chip UC and the heat dissipation member. In some embodiments, an electromagnetic interference (EMI) shielding layer (not shown) may be formed on the side surfaces and top surface of the semiconductor package 1.

[0119] In a semiconductor package 1 according to an example embodiment of the present inventive concepts, active surfaces of first semiconductor substrates 100 of first and second device layers DL1 and DL2 are adhered to each other via face-to-face bonding, and a third device layer DL3 including an upper semiconductor chip UC is positioned over the first and second device layers DL1 and DL2. Furthermore, at least two semiconductor chip regions CR each including a first semiconductor device 110 may be positioned horizontally in each of the first and second device layers DL1 and DL2, and an upper semiconductor chip UC including a second semiconductor device 210 different from the first semiconductor device 110 may be positioned above the at least two semiconductor chip regions CR in each of the first and second device layers DL1 and DL2.

[0120] In the semiconductor package 1 according to the example embodiment of the present inventive concepts, since the upper semiconductor chip UC is attached to the second device layer DL2, which has a larger area than the upper semiconductor chip UC, a relatively fine pitch can be achieved without using an additional interposer, thereby reducing the manufacturing cost of the semiconductor package. Furthermore, in the semiconductor package 1 according to the example embodiment of the present inventive concepts, since the rewiring structure RDS to which the external connection terminals 550 are connected is formed on the first device layer DL1, which has a larger area than the upper semiconductor chip UC, an additional printed circuit board can be eliminated, thereby achieving a relatively small form factor.

[0121] In the present invention, the semiconductor chip region CR, scribe line region SL, first semiconductor substrate 100, first semiconductor device 110, and through-electrode 150 of the first device layer DL1 may be referred to as the first semiconductor chip region, the first scribe line region, the first semiconductor substrate, the first semiconductor device, and the first through-electrode, respectively. The semiconductor chip region CR, scribe line region SL, first semiconductor substrate 100, first semiconductor device 110, and through-electrode 150 of the second device layer DL2 may be referred to as the second semiconductor chip region, the second scribe line region, the second semiconductor substrate, the second semiconductor device, and the second through-electrode, respectively. The second semiconductor substrate 200 and the second semiconductor device 210 of the third device layer DL3 may be referred to as the third semiconductor substrate and the third semiconductor device, respectively.

[0122] Figures 3A to 3C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments. Figure 4 According to an example embodiment, Figures 3A to 3C A cross-sectional view of a semiconductor package formed by the method shown in FIG. 1 is not given again with reference to FIG. Figures 1A to 2 The same description is carried out. In detail, Figure 3A Show Figure 1D The next steps.

[0123] See Figure 3A A plurality of upper connection pads 160 and a third cover insulating layer 170 are formed on the first semiconductor substrate 100 of the second wafer WF2. The plurality of upper connection pads are electrically connected to the plurality of through electrodes 150, respectively. The third cover insulating layer covers the sidewalls of the plurality of upper connection pads 160 but does not cover the top surfaces of the plurality of upper connection pads 160. The plurality of upper connection pads 160 and the third cover insulating layer 170 can be formed using the same or substantially similar method as used to form the first internal connection pads 132 and the first cover insulating layer 142 or the plurality of second internal connection pads 134 and the second cover insulating layer 144.

[0124] See Figure 3B , an upper semiconductor chip UCa including a plurality of chip connection pads 260a is attached to the second wafer WF2. The upper semiconductor chip UCa may be attached to the second wafer WF2 such that the plurality of chip connection pads 260a correspond to the plurality of upper connection pads 160. The upper semiconductor chip UCa may include a second semiconductor substrate 200, a second semiconductor device 210, a plurality of chip connection pads 260a, and a chip covering insulating layer 270. The chip covering insulating layer 270 may cover the sidewalls of the plurality of chip connection pads 260a, but may not cover the top surfaces of the plurality of chip connection pads 260a on the second semiconductor substrate 200.

[0125] The third cover insulating layer 170 and the chip cover insulating layer 270 can be adhered to each other by applying heat and / or pressure during the process of attaching the upper semiconductor chip UCa to the second wafer WF2. For example, heat at a third temperature can be applied during the process of attaching the upper semiconductor chip UCa to the second wafer WF2. A molding member 300 surrounding the upper semiconductor chip UCa is formed on the second wafer WF2.

[0126] See Figure 3B and Figure 3C , a plurality of die bonding pads 265 are formed by applying heat at a fourth temperature higher than the third temperature. The plurality of die bonding pads are obtained by bonding the plurality of upper connection pads 160 to corresponding die bonding pads among the plurality of die bonding pads 260a. The plurality of upper connection pads 160 and the corresponding die bonding pads among the plurality of die bonding pads 260a may expand due to the heat until they come into contact with each other, and then metal atoms from the plurality of upper connection pads 160 and the corresponding die bonding pads among the plurality of die bonding pads 260a diffuse and become one, thereby forming the plurality of die bonding pads 265.

[0127] See Figure 4 , by Figure 3C The above is performed on the resulting structure Figure 1G to Figure 1I In the semiconductor package 1a, a rewiring structure RDS, a first device layer DL1 including at least two semiconductor chip regions CR, a second device layer DL2 including at least two semiconductor chip regions CR, and a third device layer DL3a including an upper semiconductor chip UCa may be stacked in sequence.

[0128] The third device layer DL3a may be positioned on the second device layer DL2 such that the third cover insulating layer 170 and the chip cover insulating layer 270 are in contact with each other. The chip bonding pad 265 may pass through the third cover insulating layer 170 and the chip cover insulating layer 270 and may electrically connect the through-electrode 150 of the second device layer DL2 to the second semiconductor device 210 of the upper semiconductor chip UCa.

[0129] Figures 5A to 5D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments. Figure 6 According to an example embodiment, Figures 5A to 5D A cross-sectional view of a semiconductor package formed by the method shown in FIG. 1 and therefore will not be given again with reference to FIG. Figures 1A to 2 The same description is carried out. In detail, Figure 5A Show Figure 1A The next steps.

[0130] See Figure 1A and Figure 5A, the second wafer WF2 can be cut along the scribe line region SL to separate the plurality of semiconductor chip regions CR into a plurality of lower semiconductor chips DC. Figure 5A The lower semiconductor chip DC does not include the scribe line region SL, but example embodiments are not limited thereto, and the lower semiconductor chip DC may further include a portion of the scribe line region SL, such as Figure 2 The residual scribe line region SLR.

[0131] A plurality of lower semiconductor chips DC are attached to the first wafer WF1 to correspond to the plurality of semiconductor chip regions CR of the first wafer WF1, respectively. Each of the lower semiconductor chips DC may include a first semiconductor substrate 100, a first semiconductor device 110, a wiring structure 120, a plurality of first internal connection pads 132, a first cover insulating layer 142, and a plurality of through electrodes 150.

[0132] The plurality of lower semiconductor chips DC may be attached to the first wafer WF1 such that the first cover insulating layer 142 and the second cover insulating layer 144 contact each other and the plurality of first internal connection pads 132 and the plurality of second internal connection pads 134 correspond to each other. The first cover insulating layer 142 and the second cover insulating layer 144 may be adhered to each other by applying heat and / or pressure in a process of attaching the plurality of lower semiconductor chips DC to the first wafer WF1.

[0133] See Figure 5A and Figure 5B , a plurality of device bonding pads 130 are formed, which are obtained by bonding the plurality of first internal connection pads 132 and corresponding second internal connection pads of the plurality of second internal connection pads 134 .

[0134] See Figure 5C A filling molding member 190 that fills spaces between and covers the plurality of lower semiconductor chips DC is formed on the first wafer WF1. The filling molding member 190 may include, for example, EMC.

[0135] See Figure 5D , a portion of the first semiconductor substrate 100 of the second wafer WF2 and a portion of the filling molding member 190 are removed in the plurality of lower semiconductor chips DC to expose the through electrodes 150 of the plurality of lower semiconductor chips DC.

[0136] See Figure 6 , by Figure 5D The above is performed on the resulting structure Figure 1E to Figure 1IThe semiconductor package 1b is formed by a process. In the semiconductor package 1b, a rewiring structure RDS, a first device layer DL1 (the first device layer includes at least two semiconductor chip regions CR separated from each other by a scribe line region SL), a second device layer DL2b (the second device layer includes at least two lower semiconductor chips DC separated from each other by a filling molding member 190 therebetween), and a third device layer DL3 (the third device layer includes an upper semiconductor chip UC) may be stacked in sequence.

[0137] Different from Figure 2 A semiconductor package 1 in which a second device layer DL2 is formed on a first device layer DL1 by using a wafer-to-wafer (W2W) bonding method, Figure 6 The semiconductor package 1 b may form the second device layer DL2 b on the first device layer DL1 by using a chip-to-wafer / die-to-wafer (C2W / D2W) bonding method.

[0138] Figures 7A to 7C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments. Figure 8 According to an example embodiment, Figures 7A to 7C A cross-sectional view of a semiconductor package formed by the method shown in FIG. Figures 1A to 2 The same description is carried out.

[0139] See Figure 7A , preparing a first wafer WF1c and a second wafer WF2c. Each of the first wafer WF1c and the second wafer WF2c may include a plurality of semiconductor chip regions CR and a plurality of intermediate regions IR separated from each other by scribe line regions SL. In each of the first wafer WF1c and the second wafer WF2c, a plurality of intermediate regions IR are positioned, replacing Figure 1A The number of the plurality of semiconductor chip regions CR of each of the first wafer WF1c and the second wafer WF2c may be less than Figure 1A The number of the plurality of semiconductor chip regions CR of each of the first wafer WF1 and the second wafer WF2 is .

[0140] The size (area) of each of the intermediate regions IR may be the same as the size (area) of each of the semiconductor chip regions CR in some example embodiments, and may be smaller than the size (area) of the semiconductor chip regions CR in other example embodiments. Therefore, the sum of the number of the plurality of semiconductor chip regions CR and the number of the plurality of intermediate regions IR in each of the first wafer WF1c and the second wafer WF2c may be the same as the size (area) of each of the semiconductor chip regions CR in some example embodiments. Figure 1A The total number of the plurality of semiconductor chip regions CR in each of the first wafer WF1 and the second wafer WF2 is the same, and in other example embodiments may be greater than Figure 1A The total number of the plurality of semiconductor chip regions CR in each of the first wafer WF1 and the second wafer WF2 .

[0141] Each of the intervening regions IR of the first wafer WF1c includes a plurality of first additional connection pads 136 and a plurality of additional through-electrodes 152 connected to the plurality of first additional connection pads 136, and each of the intervening regions IR of the second wafer WF2c includes a plurality of second additional connection pads 138 and a plurality of additional through-electrodes 152 connected to the plurality of second additional connection pads 138. The first cover insulating layer 142 and the second cover insulating layer 144 may cover sidewalls of the plurality of first additional connection pads 136 and the plurality of second additional connection pads 138, and may not cover and may expose top surfaces of the plurality of first additional connection pads 136 and the plurality of second additional connection pads 138 in the intervening regions IR of the first wafer WF1c and the second wafer WF2c.

[0142] Although Figure 7A For ease of explanation, the first additional connection pads 136 and the second additional connection pads 138 are thicker than the first and second internal connection pads 132 and 134, but example embodiments are not limited thereto. For example, the thickness of the first additional connection pads 136 and the second additional connection pads 138 may be the same as the thickness of the first and second internal connection pads 132 and 134. The wiring structure 120 may be located between the first additional connection pads 136 and the additional through-electrode 152, and between the second additional connection pads 138 and the additional through-electrode 152.

[0143] See Figure 7B , the second chip WF2c is attached to the first chip WF1c so that the first cover insulating layer 142 and the second cover insulating layer 144 are in contact with each other, the plurality of first internal connection pads 132 and the plurality of second internal connection pads 134 correspond to each other and the plurality of first additional connection pads 136 and the plurality of second additional connection pads 138 correspond to each other.

[0144] See Figure 7B and Figure 7C, forming a plurality of device bonding pads 130 and a plurality of additional bonding pads 135, wherein the plurality of device bonding pads are obtained by bonding a plurality of first internal connection pads 132 and corresponding second internal connection pads among a plurality of second internal connection pads 134, and the plurality of additional bonding pads are obtained by bonding a plurality of first additional connection pads 136 and corresponding second additional connection pads among a plurality of second additional connection pads 138 to form an integral structure through diffusion bonding.

[0145] See Figure 8 , by Figure 7C The resulting structure is implemented as above Figure 1D to Figure 1I The semiconductor package 1c may be formed using a process that is the same as or substantially similar to the process of the semiconductor package 1c. In the semiconductor package 1c, a rewiring structure RDSc, a first device layer DL1c including at least two semiconductor chip regions CR and at least one intervening region IR, a second device layer DL2c including at least two semiconductor chip regions CR and at least one intervening region IR, and a third device layer DL3c including an upper semiconductor chip UCc may be stacked in sequence.

[0146] The first device layer DL1c may include a first semiconductor substrate 100 (the first semiconductor substrate includes at least two semiconductor chip regions CR and at least one intervening region IR), a wiring structure 120, a first cover insulating layer 142, a first semiconductor device 110 in the semiconductor chip region CR, and a plurality of through-electrodes 150, as well as a plurality of additional through-electrodes 152 in the intervening region IR. The second device layer DL2c may include the first semiconductor substrate 100 (the first semiconductor substrate includes at least two semiconductor chip regions CR and at least one intervening region IR), a wiring structure 120, a second cover insulating layer 144, the first semiconductor device 110 in the semiconductor chip region CR, and a plurality of through-electrodes 150, as well as a plurality of additional through-electrodes 152 in the intervening region IR. The second device layer DL2c may be located on the first device layer DL1c such that the first cover insulating layer 142 and the second cover insulating layer 144 contact each other. The device bonding pad 130 may pass through the first cover insulating layer 142 and the second cover insulating layer 144 in the semiconductor chip region CR and may electrically connect the through-electrodes 150 of the first device layer DL1c to the through-electrodes 150 of the second device layer DL2c. The additional bonding pad 135 may pass through the first and second capping insulating layers 142 and 144 in the intervening region IR and may electrically connect the additional through-electrode 152 of the first device layer DL1 c to the additional through-electrode 152 of the second device layer DL2 c .

[0147] A plurality of upper connection pads 160 electrically connected to the plurality of through electrodes 150 and a plurality of additional upper connection pads 162 electrically connected to the plurality of additional through electrodes 152 may be located on the second device layer DL2 c .

[0148] The upper semiconductor chip UCc may include a second semiconductor substrate 200, a second semiconductor device 210, a plurality of chip connection pads 260, and a plurality of additional chip connection pads 262. The plurality of chip connection terminals 250 may be located between the plurality of upper connection pads 160 and the plurality of chip connection pads 260 corresponding to each other, and the plurality of additional chip connection terminals 252 may be located between the plurality of additional upper connection pads 162 and the plurality of additional chip connection pads 262 corresponding to each other.

[0149] The rewiring structure RDSc may include a plurality of rewiring insulating layers 530, a plurality of rewiring conductive patterns 510c located on at least one of the top and bottom surfaces of the plurality of rewiring insulating layers 530, and a plurality of rewiring via patterns 520c passing through at least one of the plurality of rewiring insulating layers 530 and connected to the plurality of rewiring conductive patterns 510c.

[0150] The rewiring conductive pattern 510c and the rewiring via pattern 520c may be electrically connected to the through-electrodes 150 and the additional through-electrodes 152 of the first device layer DL1c. External connection terminals 550 and additional external connection terminals 552 may be attached to the rewiring structure RDSc, the external connection terminals contacting the rewiring conductive pattern 510c and electrically connected to the plurality of through-electrodes 150 of the first device layer DL1c, and the additional external connection terminals electrically or thermally connected to the plurality of additional through-electrodes 152.

[0151] In the semiconductor package 1c according to an example embodiment of the present inventive concept, when the number of electrical paths required for the upper semiconductor chip UCc is relatively large, the intermediate region IR including a plurality of additional through-electrodes 152 may be located in each of the first device layer DL1c and the second device layer DL2c, and the plurality of additional through-electrodes 152 may be used as additional electrical paths.

[0152] Alternatively, in the semiconductor package 1c according to an example embodiment of the present inventive concept, when the heat generated in the upper semiconductor chip UCc is relatively large, multiple additional chip connection pads 262, multiple additional through electrodes 152, and multiple additional external connection terminals 552 can be used as heat transfer paths, and the heat generated in the upper semiconductor chip UCc can be discharged outward.

[0153] Figures 9A to 9C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an embodiment. Figure 10is a cross-sectional view of a semiconductor package according to an example embodiment, and Figures 9A to 10 The reference will no longer be given Figures 1A to 2 as well as Figures 7A to 8 The same description is carried out.

[0154] See Figure 9A , prepare a first wafer WF1d and a second wafer WF2d. Each of the first wafer WF1d and the second wafer WF2d may include a plurality of semiconductor chip regions CR divided by a scribe line region SLd. Replace the scribe line region SLd of each of the first wafer WF1d and the second wafer WF2d with Figure 1A The scribe line region SLd of each of the first wafer WF1 and the second wafer WF2 is shown in FIG. 1 , and thus the description will focus on the scribe line region SLd.

[0155] Each of the scribe line regions SLd of the first wafer WF1d includes a plurality of first additional connection pads 136d and a plurality of additional through-electrodes 152d connected to the plurality of first additional connection pads 136d, and each of the scribe line regions SLd of the second wafer WF2d includes a plurality of second additional connection pads 138d and a plurality of additional through-electrodes 152d connected to the plurality of second additional connection pads 138d. The first cover insulating layer 142 and the second cover insulating layer 144 may cover side surfaces of the plurality of first additional connection pads 136d and the plurality of second additional connection pads 138d, and may not cover and expose top surfaces of the plurality of first additional connection pads 136d and the plurality of second additional connection pads 138d in the scribe line regions SLd of the first wafer WF1d and the second wafer WF2d.

[0156] Although Figure 9A For convenience of explanation, the first and second additional connection pads 136d and 138d are thicker than the first and second internal connection pads 132 and 134, but example embodiments are not limited thereto.

[0157] See Figure 9B , the second chip WF2d is attached to the first chip WF1d so that the first cover insulating layer 142 and the second cover insulating layer 144 contact each other, the plurality of first internal connection pads 132 and the plurality of second internal connection pads 134 correspond to each other, and the plurality of first additional connection pads 136d and the plurality of second additional connection pads 138d correspond to each other.

[0158] See Figure 9B and Figure 9C, forming a plurality of device bonding pads 130 and a plurality of additional bonding pads 135d, wherein the plurality of device bonding pads are obtained by bonding a plurality of first internal connection pads 132 with corresponding second internal connection pads in a plurality of second internal connection pads 134, and the plurality of additional bonding pads are obtained by bonding a plurality of first additional connection pads 136d with a plurality of second additional connection pads 138d.

[0159] See Figure 10 , by Figure 9C The resulting structure is implemented as above Figure 1D to Figure 1I The semiconductor package 1d is formed by a process that is the same as or substantially similar to the process of the semiconductor package 1d. In the semiconductor package 1d, a rewiring structure RDSd, a first device layer DL1d including at least two semiconductor chip regions CR divided by a scribe line region SLd, a second device layer DL2d including at least two semiconductor chip regions CR divided by the scribe line region SLd, and a third device layer DLdc including an upper semiconductor chip UCd may be stacked in sequence.

[0160] The first device layer DL1d may include a first semiconductor substrate 100 (the first semiconductor substrate includes at least two semiconductor chip regions CR divided by a scribe line region SLd), a wiring structure 120, a first covering insulating layer 142, a first semiconductor device 110 and a plurality of through-electrodes 150 in the semiconductor chip region CR, and a plurality of additional through-electrodes 152d in the scribe line region SLd, and the second device layer DL2d may include a first semiconductor substrate 100 (the first semiconductor substrate includes at least two semiconductor chip regions CR divided by a scribe line region SLd), a wiring structure 120, a second covering insulating layer 144, a first semiconductor device 110 and a plurality of through-electrodes 150 in the semiconductor chip region CR, and a plurality of additional through-electrodes 152d in the scribe line region SLd, and the second device layer DL2d may be located on the first device layer DL1d so that the first covering insulating layer 142 and the second covering insulating layer 144 are in contact with each other. The device bonding pad 130 may pass through the first and second cover insulating layers 142 and 144 in the semiconductor chip region CR and may electrically connect the through-electrode 150 of the first device layer DL1d to the through-electrode 150 of the second device layer DL2d. The additional bonding pad 135d may pass through the first and second cover insulating layers 142 and 144 in the scribe line region SLd and may electrically connect the additional through-electrode 152d of the first device layer DL1d to the additional through-electrode 152d of the second device layer DL2d.

[0161] A plurality of upper connection pads 160 electrically connected to the plurality of through electrodes 150 and a plurality of additional upper connection pads 162 d electrically connected to the plurality of additional through electrodes 152 d may be located on the second device layer DL2 d .

[0162] The upper semiconductor chip UCd may include a second semiconductor substrate 200, a second semiconductor device 210, a plurality of chip connection pads 260, and a plurality of additional chip connection pads 262d. The plurality of chip connection terminals 250 may be located between the corresponding plurality of upper connection pads 160 and the plurality of chip connection pads 260, and the plurality of additional chip connection terminals 252d may be located between the corresponding plurality of additional upper connection pads 162d and the plurality of additional chip connection pads 262d.

[0163] The rewiring structure RDSd may include a plurality of rewiring insulating layers 530, a plurality of rewiring conductive patterns 510d located on at least one of the top and bottom surfaces of the plurality of rewiring insulating layers 530, and a plurality of rewiring via patterns 520c that pass through at least one of the plurality of rewiring insulating layers 530 and are connected to the plurality of rewiring conductive patterns 510d. The rewiring conductive patterns 510d and the rewiring via patterns 520d may be electrically connected to the through-electrodes 150 and the additional through-electrodes 152 of the first device layer DL1d. Attached to the rewiring structure RDSd may be external connection terminals 550 and additional external connection terminals 552d. The external connection terminals contact the rewiring conductive patterns 510d and are electrically connected to the plurality of through-electrodes 150 of the first device layer DL1d. The additional external connection terminals are electrically or thermally connected to the plurality of additional through-electrodes 152d.

[0164] Although Figure 10 Only one additional bonding pad 135d, one additional through-electrode 152d for each of the first device layer DL1d and the second device layer DL2d, one additional upper connection pad 162d, one additional chip connection terminal 252d, one additional chip connection pad 262d, and one additional external connection terminal 552d are shown, but the example embodiments are not limited thereto, and multiple elements may be located between the two semiconductor chip regions CR in the direction in which the scribe line region SLd extends or in the direction between the two semiconductor chip regions CR.

[0165] Figures 11A to 11E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments. Figure 12 According to an example embodiment, Figures 11A to 11E A cross-sectional view of a semiconductor package formed by the method shown in FIG. 1 is not given again with reference to FIG. Figures 5A to 6 as well as Figures 7A to 8 The same description is carried out.

[0166] See Figure 11A, a plurality of lower semiconductor chips DC are attached to the first wafer WF1c to correspond to the plurality of semiconductor chip regions CR of the first wafer WF1c. The first wafer WF1c and the lower semiconductor chips DC are connected to Figure 7A The first wafer WF1c and Figure 5A The lower semiconductor chip DC is substantially the same, and thus a detailed explanation thereof will not be given.

[0167] See Figure 11A and Figure 11B , a plurality of device bonding pads 130 are formed, which are obtained by bonding a plurality of first internal connection pads 132 and a plurality of second internal connection pads 134 corresponding to each other.

[0168] See Figure 11C A filling molding member 190e that fills the spaces between the plurality of lower semiconductor chips DC and covers the plurality of lower semiconductor chips DC is formed on the first wafer WF1c. The filling molding member 190e may be formed of, for example, EMC.

[0169] See Figure 11D , a portion of the first semiconductor substrate 100 and a portion of the filling molding member 190 e are removed in the plurality of lower semiconductor chips DC to expose the through electrodes 150 of the plurality of lower semiconductor chips DC.

[0170] Next, a plurality of upper connection pads 160, each electrically connected to the plurality of through electrodes 150, are formed on the first semiconductor substrate 100 of the plurality of lower semiconductor chips DC. After a plurality of through holes 195 (through which the plurality of first additional connection pads 136 are exposed) are formed in the intermediate region IR of the first wafer WF1c by further removing a portion of the filling molding member 190e, a plurality of through-mold vias 180 are formed to fill at least a portion of the plurality of through holes 195 and connect to the plurality of first additional connection pads 136.

[0171] See Figure 11E The upper semiconductor chip UCc is attached to the plurality of lower semiconductor chips DC and the filling molding member 190e. The upper semiconductor chip UCc may include a second semiconductor substrate 200, a second semiconductor device 210, a plurality of chip connection pads 260, and a plurality of additional chip connection pads 262. The plurality of chip connection terminals 250 may be located between the corresponding plurality of upper connection pads 160 and the plurality of chip connection pads 260, and the plurality of additional chip connection terminals 252e may be located between the corresponding plurality of through-molding vias 180 and the plurality of additional chip connection pads 262. A molding member 300 surrounding the upper semiconductor chip UCc is formed on the plurality of lower semiconductor chips DC and the filling molding member 190e.

[0172] See Figure 12 , by Figure 11E The above is performed on the resulting structure Figure 1G to Figure 1I The semiconductor package 1e is formed by using the second device layer DL2e of the semiconductor package 1e. Figure 8 The second device layer DL2c of the semiconductor package 1c is replaced with the additional chip connection terminal 252e of the third device layer DL3e of the semiconductor package 1e. Figure 8 The additional chip connection terminal 252 of the third device layer DL3 c is not provided, so the description will focus on the difference.

[0173] In the semiconductor package 1e, a rewiring structure RDSe, a first device layer DL1e including at least two semiconductor chip regions CR and at least one intermediate region IR, a second device layer DL2e including at least two lower semiconductor chips DC, and a third device layer DL3e including an upper semiconductor chip UCc may be stacked in sequence. The second device layer DL2e of the semiconductor package 1e includes at least two lower semiconductor chips DC (instead of Figure 8 The semiconductor package 1e may include at least two semiconductor chip regions CR of the second device layer DL2c, and include a filling molding member 190e (rather than an intermediate region IR) having a plurality of through-holes 195 and a plurality of through-molding holes 180 formed in the plurality of through-holes 195. The plurality of additional chip connection terminals 252e may be located between the plurality of through-molding holes 180 and the plurality of additional chip connection pads 262, and the plurality of through-molding holes 180 and the plurality of additional chip connection terminals 252e corresponding to each other may be directly connected to each other. Therefore, the semiconductor package 1e may not include Figure 8 The additional upper connection pads 162 of the semiconductor package 1c.

[0174] Figure 13A and Figure 13B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments, and Figure 14 According to an example embodiment, FIG. 13A to FIG. 13B The cross-sectional view of the semiconductor package formed by the method shown in FIG. Figures 1A to 2 、 Figures 5A to 6 as well as Figures 9A to 10 The same description is carried out.

[0175] See Figure 13A , a plurality of lower semiconductor chips DC are attached to the first wafer WF1d to correspond to the plurality of semiconductor chip regions CR of the first wafer WF1d. The first wafer WF1d and the lower semiconductor chips DC are connected to Figure 9A The first wafer WF1d and Figure 5A The lower semiconductor chip DC is the same or substantially similar to that of FIG. 1 , and thus a detailed explanation thereof will not be given.

[0176] See Figure 13B , by executing the above Figure 11B The process is used to form a plurality of device bonding pads 130, and by performing Figure 11C and Figure 11D A similar process is used to form a plurality of upper connection pads 160 electrically connected to the plurality of through electrodes 150 on the first semiconductor substrate 100 of the plurality of lower semiconductor chips DC. Furthermore, a filling molding member 190f having a plurality of through holes 195f is formed on the first wafer WF1d, filling the spaces between the plurality of lower semiconductor chips DC. A plurality of through-molded vias 180f are formed to fill at least a portion of the plurality of through holes 195f and connect to the plurality of first additional connection pads 136d.

[0177] Next, the upper semiconductor chip UCd is attached to the plurality of lower semiconductor chips DC and the filling molding member 190f. The upper semiconductor chip UCd may include a second semiconductor substrate 200, a second semiconductor device 210, a plurality of chip connection pads 260, and a plurality of additional chip connection pads 262d. The plurality of chip connection terminals 250 may be located between the corresponding plurality of upper connection pads 160 and the plurality of chip connection pads 260, and the plurality of additional chip connection terminals 252f may be located between the corresponding plurality of through-molding holes 180f and the plurality of additional chip connection pads 262d. A molding member 300 surrounding the upper semiconductor chip UCd is formed on the plurality of lower semiconductor chips DC and the filling molding member 190f.

[0178] See Figure 14 , by Figure 13B The above is performed on the resulting structure Figure 11E as well as Figure 1G to Figure 1I The semiconductor package 1f is formed by using a process. The second device layer DL2f of the semiconductor package 1f is replaced Figure 10 The second device layer DL2d of the semiconductor package 1d is replaced with the additional chip connection terminal 252f of the third device layer DL3f. Figure 10 The additional chip connection terminal 252d of the third device layer DL3d is shown in FIG. 2 , and thus the description will focus on the difference.

[0179] In the semiconductor package 1f, a rewiring structure RDSd, a first device layer DL1d including at least two semiconductor chip regions CR divided by a scribe line region SLd, a second device layer DL2f including at least two lower semiconductor chips DC, and a third device layer DL3f including an upper semiconductor chip UCd may be stacked in sequence. The second device layer DL2f of the semiconductor package 1f includes at least two lower semiconductor chips DC (instead of the upper semiconductor chip UCd). Figure 10The semiconductor package 1f may include at least two semiconductor chip regions CR of the second device layer DL2d, and include a filling molding member 190f having a plurality of through-holes 195f and a plurality of through-molding holes 180f formed in the plurality of through-holes 195f (instead of the scribe line region SLd). The plurality of additional chip connection terminals 252f may be located between the plurality of through-molding holes 180f and the plurality of additional chip connection pads 262d, and the plurality of through-molding holes 180f and the plurality of additional chip connection terminals 252f corresponding to each other may be directly connected to each other. Therefore, the semiconductor package 1f may not include Figure 10 The additional upper connection pads 162d of the semiconductor package 1d are shown.

[0180] Figure 15A and Figure 15B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments, and Figure 16 is a cross-sectional view of a semiconductor package according to an example embodiment, and reference will not be given again. Figures 3A to 4 The same description is carried out. In detail, Figure 15A Show Figure 3A The next steps.

[0181] See Figure 15A , a recess space RS is formed by removing a portion of the third cover insulating layer 170 of the second wafer WF2 and an upper portion of the first semiconductor substrate 100. The recess space RS can be formed by forming a mask pattern covering the remaining portion of the third cover insulating layer 170 and the plurality of upper connection pads 160 on the second wafer WF2 and then removing a portion of the third cover insulating layer 170 of the second wafer WF2 and an upper portion of the first semiconductor substrate 100 by using the mask pattern as an etching mask. The width of the mask pattern may be equal to or greater than Figure 15B The width of the upper semiconductor chip UCa.

[0182] See Figure 15B , the upper semiconductor chip UCa including the plurality of chip connection pads 260a is attached to the second wafer WF2 including the recessed space RS. The upper semiconductor chip UCa may be attached to the second wafer WF2 such that the plurality of chip connection pads 260a correspond to the plurality of upper connection pads 160. The upper semiconductor chip UCa may be attached to the second wafer WF2 so as to be aligned with respect to the recessed space RS, and the third cover insulating layer 170 and the chip cover insulating layer 270 may be adhered to each other.

[0183] See Figure 16 , by Figure 15B The above is performed on the resulting structure Figure 3CThe plurality of chip bonding pads 265 and the molding member 300g are formed by bonding the plurality of upper connection pads 160 and the plurality of chip connection pads 260a corresponding to each other, and the molding member fills the recess RS in the second wafer WF2 and surrounds the upper semiconductor chip UCa. Next, by performing the above Figure 1G to Figure 1I The semiconductor package 1g is formed by the process of replacing the second device layer DL2g and the molding member 300g of the semiconductor package 1g. Figure 4 The second device layer DL2 and the molding member 300 of the semiconductor package 1 a are shown in FIG. 1 , and thus the description will focus on the differences.

[0184] In semiconductor package 1g, a rewiring structure RDS, a first device layer DL1 including at least two semiconductor chip regions CR divided by a scribe line region SL, a second device layer DL2g including at least two lower semiconductor chips DC, and a third device layer DL3a including an upper semiconductor chip UCa are stacked in sequence. The first semiconductor substrate 100 of the second device layer DL2g of semiconductor package 1g may include a recessed space RS, which may be filled with a molding member 300g. The upper semiconductor chip UCa may be attached to a protrusion defined by the recessed space RS of the first semiconductor substrate 100 of the second device layer DL2g.

[0185] Figure 17A and Figure 17B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to example embodiments. Figure 18 According to an example embodiment, Figure 17A and Figure 17B A cross-sectional view of a semiconductor package formed by the method shown in FIG. 1 is not given again with reference to FIG. Figures 5A to 6 The same description is carried out. In detail, Figure 17A Shown in Figure 5A A step before the plurality of lower semiconductor chips DC are attached to the first wafer WF1.

[0186] See Figure 17A , a recessed space RSh is formed in the first wafer WF1 by removing a portion of the first cover insulating layer 142 and an upper portion of the first semiconductor substrate 100. The recessed space RSh can be formed by forming a mask pattern covering the remaining portion of the first cover insulating layer 142 and the plurality of first internal connection pads 132 on the first wafer WF1, and then removing a portion of the first cover insulating layer 142 and an upper portion of the first semiconductor substrate 100 using the mask pattern as an etching mask. The width of the mask pattern can be equal to or greater than the width of each of the lower semiconductor chips DC.

[0187] See Figure 17B , a plurality of lower semiconductor chips DC are attached to the first wafer WF1 including the recessed spaces RSh to correspond to the plurality of semiconductor chip regions CR of the first wafer WF1. The plurality of lower semiconductor chips DC may be attached to the first wafer WF1 such that the first cover insulating layer 142 and the second cover insulating layer 144 are in contact with each other and the plurality of first internal connection pads 132 and the plurality of second internal connection pads 134 correspond to each other.

[0188] The lower semiconductor chip DC may be attached to the first wafer WF1 to be aligned with respect to the recess space RSh, and the first cover insulating layer 142 and the second cover insulating layer 144 may be adhered to each other.

[0189] See Figure 18 , by Figure 17B The above is performed on the resulting structure Figure 5C and Figure 5D The semiconductor package 1h is formed by the process of replacing the first device layer DL1h and the filling molding member 190h of the semiconductor package 1h. Figure 6 1 and 190 of the semiconductor package 1 b , and thus the description will focus on the differences.

[0190] In the semiconductor package 1h, a rewiring structure RDS, a first device layer DL1h, a second device layer DL2b, and a third device layer DL3 may be stacked in sequence. The first semiconductor substrate 100 of the first device layer DL1h of the semiconductor package 1h may include a recessed space RSh, which may be filled with a molding member 190h. A lower semiconductor chip DC is attached to a protrusion defined by the recessed space RSh of the first semiconductor substrate 100 of the first device layer DL1h.

[0191] Figures 19A to 19C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment, and reference will not be given again. Figures 1A to 2 The same description is carried out. In detail, Figures 19A to 19C Show Figure 1D The next steps.

[0192] See Figure 19A , by Figure 1D The above is performed on the resulting structure Figure 1HA rewiring structure RDS is formed on the first wafer WF1 using a process. The rewiring structure RDS may include a plurality of rewiring insulating layers 530, a plurality of rewiring conductive patterns 510 located on at least one of the top and bottom surfaces of the plurality of rewiring insulating layers 530, and a plurality of rewiring via patterns 520 passing through at least one of the plurality of rewiring insulating layers 530 and connected to the plurality of rewiring conductive patterns 510. A plurality of external connection terminals 550 contacting the rewiring conductive patterns 510 and electrically connected to the plurality of through electrodes 150 of the first wafer WF1 may be attached to the rewiring structure RDS.

[0193] See Figure 19B , in making Figure 19B After the resulting structure is inverted so that the rewiring structure RDS faces downward, the first wafer WF1 on which the rewiring structure RDS is formed is attached to the carrier substrate 10 with an adhesive film 20 therebetween. The adhesive film 20 may fill the space between the rewiring structure RDS and the carrier substrate 10 and may surround the external connection terminals 550.

[0194] See Figure 19C , by executing the above Figure 1E and Figure 1F The upper semiconductor chip UC is formed by a process of forming a plurality of upper connection pads 160 and attaching the upper semiconductor chip UC, which includes a plurality of chip connection pads 260 electrically connected to the plurality of upper connection pads 160. The plurality of chip connection terminals 250 may be located between the plurality of upper connection pads 160 and the plurality of chip connection pads 260 corresponding to each other. The molding member 300 surrounding the upper semiconductor chip UC is formed on the second wafer WF2. Next, the upper semiconductor chip UC may be formed by performing the above Figure 1I The process is formed Figure 2 A semiconductor package 1.

[0195] In addition, those skilled in the art will appreciate that by using the above Figures 19A to 19C The process is formed Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 12 、 Figure 14 、 Figure 16 as well as Figure 18 any of the semiconductor package 1a, semiconductor package 1b, semiconductor package 1c, semiconductor package 1d, semiconductor package 1e, semiconductor package 1f, semiconductor package 1g, and semiconductor package 1h, and therefore no detailed explanation will be given.

[0196] Figure 20 and Figure 21is a plan view illustrating a layout of a plurality of semiconductor chips of a semiconductor package according to some example embodiments.

[0197] See Figure 20 , the semiconductor package 2 may include an upper semiconductor chip UC- 1 located above a plurality of semiconductor chip regions CR- 1 divided by a scribe line region SL- 1 . Figure 20 Each of the plurality of semiconductor chip regions CR-1 includes two stacked semiconductor chip regions, or lower semiconductor chips stacked on the semiconductor chip regions. Figure 20 There are 16 semiconductor chip regions CR- 1 in the semiconductor package 2 , but example embodiments are not limited thereto, and the semiconductor package 2 may include two or more semiconductor chip regions CR- 1 .

[0198] The semiconductor chip region CR-1 may be Figure 2 、 Figure 4 、 Figure 6 、 Figure 10 、 Figure 14 、 Figure 16 or Figure 18 The upper semiconductor chip UC-1 may be a semiconductor chip region CR of the first device layer DL1, the first device layer DL1d or the first device layer DL1h and a semiconductor chip region CR of the second device layer DL2, the second device layer DL2a or the second device layer DL2d or a lower semiconductor chip DC of the second device layer DL2b. Figure 2 、 Figure 4 、 Figure 6 、 Figure 10 、 Figure 14 、 Figure 16 or Figure 18 The upper semiconductor chip UC, the upper semiconductor chip UCa or the upper semiconductor chip UCd. The scribe line area SL-1 may be Figure 2 、 Figure 4 、 Figure 6 、 Figure 10 、 Figure 14 、 Figure 16 or Figure 18 The scribe line region SL or scribe line region SLd of the first device layer DL1, the first device layer DL1d or the first device layer DL1h, and the scribe line region SL or scribe line region SLd of the second device layer DL2, the second device layer DL2a or the second device layer DL2d.

[0199] See Figure 21 The semiconductor package 2a may include a plurality of semiconductor chip regions CR-2 divided by a scribe line region SL-2 and an upper semiconductor chip UC-2 located above the plurality of intermediate regions IR-2. Figure 21Each of the plurality of semiconductor chip regions CR-2 includes two stacked semiconductor chip regions, or lower semiconductor chips stacked on the semiconductor chip regions. Figure 21 The semiconductor package 2a includes 16 semiconductor chip regions CR-2 and 4 intermediate regions IR-2, but the example embodiment is not limited thereto, and the semiconductor package 2a may include two or more semiconductor chip regions CR-1 and one or more intermediate regions IR-2.

[0200] The semiconductor chip region CR-2 may be Figure 8 or Figure 12 The semiconductor chip region CR of the first device layer DL1c and the semiconductor chip region CR of the second device layer DL2c or the second device layer DL2e or the lower semiconductor chip DC. The intermediate region IR-2 may be Figure 8 or Figure 12 The scribe line region SL-2 may be a first device layer DL1c intermediate region IR and a second device layer DL2c intermediate region IR. Figure 8 or Figure 12 The scribe line region SL of the first device layer DL1 c and the scribe line region SL of the second device layer DL2 c are shown in FIG.

[0201] Figure 22(a) to Figure 24(d) is a cross-sectional view for conceptually describing a process of forming a device bonding pad, a chip bonding pad, and an additional bonding pad according to a method of manufacturing a semiconductor package according to an example embodiment. Figure 22(a) to Figure 24(d) as well as Figure 1A and Figure 1C The process of forming the device bond pad 130 is described.

[0202] See Figure 22(a) to Figure 22(c) 22( a), the top surfaces of the first and second internal connection pads 132 and 134 and the top surfaces of the first and second cover insulating layers 142 and 144 may be on the same plane (e.g., they may be coplanar). As shown in FIG22( b), the first and second cover insulating layers 142 and 144 may be brought into contact with each other by applying heat of a first temperature. As shown in FIG22( c), when heat of a second temperature is applied, the metal atoms of the first and second internal connection pads 132 and 134 may be diffused and integrated, thereby forming a plurality of device bonding pads 130.

[0203] See Figure 23(a) to Figure 23(d), as shown in FIG23( a), by adjusting the conditions of the planarization process for forming the first internal connection pad 132 and the second internal connection pad 134, the top surface of one of the first internal connection pad 132 and the second internal connection pad 134 may protrude, while the top surface of the other may be recessed. As shown in FIG23( b), when heat of a first temperature is applied, the first cover insulating layer 142 and the second cover insulating layer 144 may contact each other. As shown in FIG23( c), when heat of a second temperature is applied, the first internal connection pad 132 and the second internal connection pad 134 may expand to contact each other. Next, as shown in FIG23( d), the metal atoms of the first internal connection pad 132 and the second internal connection pad 134 may be diffused and integrated, thereby forming a plurality of device bonding pads 130.

[0204] See Figure 24(a) to Figure 24(d) , as shown in FIG24( a), the first internal connection pad 132 and the second internal connection pad 134 may have different widths. As shown in FIG24( b), when heat of a first temperature is applied, the first cover insulating layer 142 and the second cover insulating layer 144 may contact each other. As shown in FIG24( c), when heat of a second temperature is applied, the first internal connection pad 132 and the second internal connection pad 134 may expand to contact each other. Next, as shown in FIG24( d), the metal atoms of each of the first internal connection pad 132 and the second internal connection pad 134 may be diffused and integrated, thereby forming a plurality of device bonding pads 130.

[0205] Since semiconductor packages according to some example embodiments of the present inventive concepts can achieve a relatively fine pitch without using an additional interposer, the manufacturing cost of the semiconductor package can be reduced. Since the semiconductor package has a rewiring structure connected to external connection terminals, an additional printed circuit board can be eliminated, thereby making it possible to have a relatively small form factor.

Claims

1. A semiconductor package, comprising: a first device layer comprising a first semiconductor substrate, a plurality of first semiconductor devices, a first capping insulating layer, and a plurality of first through-electrodes passing through at least a portion of the first device layer, wherein the first semiconductor substrate comprises an active surface on which the plurality of first semiconductor devices are positioned, and the first capping insulating layer covers the active surface of the first semiconductor substrate; a second device layer comprising a second semiconductor substrate, a plurality of second semiconductor devices, a second covering insulating layer, and a plurality of second through-electrodes passing through at least a portion of the second device layer, wherein the second semiconductor substrate comprises an active surface on which the plurality of second semiconductor devices are positioned, the second covering insulating layer covers the active surface of the second semiconductor substrate, the plurality of second semiconductor devices respectively vertically overlap with the plurality of first semiconductor devices, and the second covering insulating layer is in contact with the first covering insulating layer; a third device layer comprising an upper semiconductor chip vertically overlapping at least two of the plurality of first semiconductor devices and vertically overlapping at least two of the plurality of second semiconductor devices; as well as A plurality of device bonding pads pass through the first cover insulating layer and the second cover insulating layer, and the plurality of device bonding pads electrically connect the plurality of first through-electrodes and the plurality of second through-electrodes to the upper semiconductor chip.

2. The semiconductor package according to claim 1, wherein The first semiconductor substrate includes a plurality of first semiconductor chip regions and one or more first scribe line regions, wherein the plurality of first semiconductor chip regions are spaced apart from each other by the one or more first scribe line regions therebetween.

3. The semiconductor package according to claim 2, wherein The second semiconductor substrate includes a plurality of second semiconductor chip regions and one or more second scribe line regions, wherein the plurality of second semiconductor chip regions are spaced apart from each other by the one or more second scribe line regions therebetween.

4. The semiconductor package according to claim 3, wherein The upper semiconductor chip includes: a third semiconductor substrate having an active surface on which a third semiconductor device is positioned, and A chip covering insulating layer covers the active surface of the third semiconductor substrate, and The semiconductor package further includes: a third cover insulating layer covering a surface of the second semiconductor substrate facing the third device layer and contacting the chip cover insulating layer; and A plurality of chip bonding pads pass through the third cover insulating layer and the chip cover insulating layer and electrically connect the third semiconductor device to the plurality of second through electrodes. 5 . The semiconductor package according to claim 4 , wherein the second semiconductor substrate has a recess on a surface facing the third device layer, and the upper semiconductor chip is attached to a protrusion of the second semiconductor substrate defined by the recess of the second semiconductor substrate. 6 . The semiconductor package according to claim 1 , wherein the second device layer comprises a plurality of lower semiconductor chips and a filling molding member, the plurality of lower semiconductor chips being spaced apart from each other with the filling molding member therebetween, each of the plurality of lower semiconductor chips including the second semiconductor substrate.

7. The semiconductor package according to claim 6, wherein The filling molding member has a through hole that receives a through-mold via connected to the upper semiconductor chip, and The semiconductor package further includes an additional through-electrode located in a corresponding first scribe line region among the one or more first scribe line regions, passing through the first semiconductor substrate, and connected to the through-molded via.

8. The semiconductor package according to claim 7, wherein the first semiconductor substrate further comprises a plurality of intermediate regions, wherein the plurality of intermediate regions are respectively arranged between a pair of the one or more first scribe line regions, and each of the plurality of intermediate regions comprises an additional connection pad, wherein the additional connection pad connects the through-molded via to the additional through-electrode.

9. The semiconductor package according to claim 6, wherein The first semiconductor substrate further includes at least two intervening regions, the at least two intervening regions being separated from each other by at least one corresponding first scribe line in the one or more first scribe line regions therebetween. The filling molding member has a plurality of through holes in the at least two intermediate regions, the plurality of through holes accommodating a plurality of through-mold vias connected to the upper semiconductor chip, and The at least two intermediate regions include a plurality of additional through-electrodes passing through the first semiconductor substrate and connected to the plurality of through-hole vias.

10. The semiconductor package according to claim 6, wherein The first semiconductor substrate has a recessed portion on a surface facing the second device layer, and The plurality of lower semiconductor chips are attached to protrusions of the first semiconductor substrate defined by the recesses of the first semiconductor substrate.

11. The semiconductor package according to claim 1 , further comprising: a rewiring structure located on a first surface of the first device layer, the first surface of the first device layer being opposite to a second surface of the first device layer facing the second device layer, the rewiring structure comprising: Multiple rewiring insulation layers, a plurality of rewiring conductive patterns respectively located on one of the top surface or the bottom surface of one of the plurality of rewiring insulating layers, and a plurality of rewiring via patterns respectively connecting a pair of vertically adjacent rewiring conductive patterns of the plurality of rewiring conductive patterns and passing through at least one of the plurality of rewiring insulating layers; The plurality of rewiring conductive patterns and the plurality of rewiring via patterns are electrically connected to the plurality of first through-electrodes.

12. A semiconductor package, comprising: The first device layer comprises: A first semiconductor substrate having an active surface, the first semiconductor substrate comprising: one or more first scribe regions, and a plurality of first semiconductor chip regions, spaced apart from each other by the one or more first scribe line regions therebetween, each of the plurality of first semiconductor chip regions being provided with a first semiconductor device on the active surface of the first semiconductor substrate, a plurality of first through electrodes located in the plurality of first semiconductor chip regions and passing through the first semiconductor substrate, and a first cover insulating layer covering the active surface of the first semiconductor substrate; The second device layer comprises: a second semiconductor substrate comprising an active surface, the second semiconductor substrate comprising: one or more second scribe areas, and a plurality of second semiconductor chip regions, spaced apart from each other by the one or more second scribe line regions therebetween, each of the plurality of second semiconductor chip regions being provided with a second semiconductor device on the active surface of the second semiconductor substrate, the second semiconductor device being of the same type as the first semiconductor device, a plurality of second through electrodes located in the plurality of second semiconductor chip regions and passing through the second semiconductor substrate, and a second cover insulating layer, covering the active surface of the second semiconductor substrate and contacting the first cover insulating layer; a third device layer comprising an upper semiconductor chip, the upper semiconductor chip being located on the second device layer and electrically connected to the plurality of second through-electrodes; as well as A plurality of device bonding pads pass through the first and second capping insulating layers and electrically connect the first device layer to the second device layer.

13. The semiconductor package according to claim 12, wherein The upper semiconductor chip includes a plurality of chip connection pads, and The semiconductor package further comprises, a plurality of upper connection pads located on a first surface of the second semiconductor substrate, the first surface of the second semiconductor substrate being opposite to a second surface of the second semiconductor substrate facing the first device layer, and the plurality of upper connection pads being connected to corresponding through-electrodes of the plurality of second through-electrodes, a plurality of chip connection terminals located between the plurality of chip connection pads and corresponding upper connection pads of the plurality of upper connection pads, and A packaging member is located on the second semiconductor substrate and surrounds side surfaces of the upper semiconductor chip.

14. The semiconductor package according to claim 12, wherein The first semiconductor substrate further includes a first residual scribe line region, the first residual scribe line region surrounding the plurality of first semiconductor chip regions at an edge of the first semiconductor substrate. The second semiconductor substrate further includes a second residual scribe line region surrounding the plurality of second semiconductor chip regions at an edge of the second semiconductor substrate, and Each of the one or more first scribe line regions and the one or more second scribe line regions has a first width, and each of the first residual scribe line region and the second residual scribe line region has a second width that is smaller than the first width.

15. The semiconductor package according to claim 12, further comprising: a first additional through-electrode located in a corresponding first scribe line region among the one or more first scribe line regions and passing through the first semiconductor substrate; a second additional through-electrode located in a corresponding second scribe line region among the one or more second scribe line regions, passing through the second semiconductor substrate, and electrically connected to the upper semiconductor chip; as well as An additional bonding pad passes through the first cover insulating layer and the second cover insulating layer and electrically connects the first additional through-electrode to the second additional through-electrode. 16 . The semiconductor package of claim 15 , wherein each of the plurality of device bond pads or the additional bond pad is a diffusion-bonded, unitary structure of two substructures.

17. The semiconductor package according to claim 12, wherein The first semiconductor substrate further includes a first intervening region separated from a corresponding first semiconductor chip region among the plurality of first semiconductor chip regions by a corresponding first scribe line region among the one or more first scribe line regions interposed therebetween, and The second semiconductor substrate further includes a second intervening region separated from a corresponding second semiconductor chip region in the plurality of second semiconductor chip regions by a corresponding second scribe line region in the one or more second scribe line regions interposed therebetween. The first intermediate region includes a plurality of first additional through-electrodes passing through the first semiconductor substrate, and The second intervening region includes a plurality of second additional through-electrodes that pass through the second semiconductor substrate and electrically connect the plurality of first additional through-electrodes to the upper semiconductor chip. The semiconductor package further includes a plurality of additional bonding pads that pass through the first cover insulating layer and the second cover insulating layer and electrically connect the plurality of first additional through-electrodes to the plurality of second additional through-electrodes.

18. A semiconductor package, comprising: a first semiconductor substrate comprising an active surface, said first semiconductor substrate comprising, Multiple lined areas, and a plurality of first semiconductor chip regions spaced apart from each other by corresponding scribe line regions among the plurality of scribe line regions therebetween, each of the plurality of first semiconductor chip regions being provided with at least one first semiconductor device on the active surface of the first semiconductor substrate; a plurality of first through electrodes, located in the plurality of first semiconductor chip regions and passing through the first semiconductor substrate; a first cover insulating layer covering the active surface of the first semiconductor substrate; A plurality of lower semiconductor chips are located on the first semiconductor substrate and correspond to the plurality of first semiconductor chip regions respectively, each of the plurality of lower semiconductor chips comprising: a second semiconductor substrate having an active surface on which at least one second semiconductor device is positioned, the second semiconductor substrate including a plurality of second through-electrodes therethrough, and a second cover insulating layer, covering the active surface of the second semiconductor substrate and contacting the first cover insulating layer; a plurality of device bonding pads passing through the first cover insulating layer and the second cover insulating layer and electrically connecting the plurality of first through-electrodes to the plurality of second through-electrodes; as well as An upper semiconductor chip includes a third semiconductor device, vertically overlaps at least two of the plurality of lower semiconductor chips, and is electrically connected to the plurality of second through-electrodes.

19. The semiconductor package according to claim 18, further comprising: A filling molding member is located on the first semiconductor substrate, the filling molding member filling spaces between the plurality of lower semiconductor chips.

20. The semiconductor package according to claim 18, wherein the first semiconductor device and the second semiconductor device are of the same type, and The third semiconductor device is of a different type from the first semiconductor device and the second semiconductor device.

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