Three-dimensional semiconductor memory device and method of manufacturing the same, integrated circuit device

Abstract

Integrated circuit devices and methods of forming the same are provided. A device can include a substrate including a cell region and an extension region, and a conductive layer stacked on the cell region in a vertical direction. The conductive layer can extend onto the extension region and can have a stepped structure on the extension region. The device can also include vertical structures on the substrate. Each vertical structure can extend in the vertical direction, and the vertical structures can include first vertical structures on the cell region and second vertical structures on the extension region. The first vertical structures can extend through the conductive layer and can include first channel layers, the second vertical structures can be in the stepped structure and can include second channel layers, and the second channel layers can be spaced apart from the substrate in the vertical direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0105507, filed on September 4, 2018, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of electronics, and more specifically, to semiconductor devices. Background Technology

[0004] Integration density in semiconductor devices has increased to achieve high performance and low manufacturing costs. Since integration density is often a major factor determining price, increasing it can be beneficial. The integration density of two-dimensional or planar semiconductor memory devices can largely depend on the area occupied by a single memory cell, making it susceptible to the level of technology used to form intricate patterns.

[0005] Because expensive equipment can be used to form fine patterns, three-dimensional semiconductor memory devices have been developed to overcome the limitations of two-dimensional semiconductor memory devices. Summary of the Invention

[0006] Some exemplary embodiments of the present invention provide three-dimensional semiconductor memory devices manufactured using simplified manufacturing processes.

[0007] Some exemplary embodiments of the present invention provide a method for manufacturing a three-dimensional semiconductor memory device, which can be performed through a simplified manufacturing process.

[0008] According to some embodiments of the present invention, an integrated circuit device may include: a substrate including cell regions and extension regions arranged in a horizontal direction; and a plurality of conductive layers stacked on the cell regions in a vertical direction perpendicular to the horizontal direction. The plurality of conductive layers may extend onto the extension regions and may have a stepped structure on the extension regions. The integrated circuit device may also include a plurality of vertical structures on the substrate. Each of the plurality of vertical structures may extend in a vertical direction, and the plurality of vertical structures may include a first vertical structure on the cell regions and a second vertical structure on the extension regions. The first vertical structure may extend through the plurality of conductive layers and may include a first channel layer; the second vertical structure may be located within a stepped structure of the plurality of conductive layers and may include a second channel layer, and the second channel layer may be spaced apart from the substrate in the vertical direction.

[0009] According to some embodiments of the present invention, an integrated circuit device may include: a substrate including a first region and a second region arranged in a horizontal direction; and a stacked structure located on the substrate. The stacked structure may include a plurality of conductive layers stacked on the first region of the substrate in a vertical direction perpendicular to the horizontal direction, and the plurality of conductive layers may extend onto the second region of the substrate and may have a stepped structure on the second region of the substrate. The integrated circuit device may also include a plurality of vertical structures on the substrate. Each of the plurality of vertical structures may extend in a vertical direction. The plurality of vertical structures may include: a first vertical structure located on the first region of the substrate and extending through the plurality of conductive layers; a second vertical structure located on the second region of the substrate and extending through the stepped structure of the plurality of conductive layers; and a third vertical structure overlapping with and spaced apart from the second vertical structure in a vertical direction.

[0010] According to some embodiments of the present invention, an integrated circuit device may include: a substrate including cell regions and extension regions arranged in a horizontal direction; and a stacked structure located on the substrate. The stacked structure may include a plurality of conductive layers stacked on the cell regions in a vertical direction perpendicular to the horizontal direction, and the plurality of conductive layers may extend onto the extension regions and may have a stepped structure on the extension regions. The integrated circuit device may also include a plurality of vertical structures on the substrate. The plurality of vertical structures may include a first vertical structure extending through the plurality of conductive layers on the cell regions and a second vertical structure extending through the stepped structure of the plurality of conductive layers, the second vertical structure including a lower portion and an upper portion sequentially stacked on the substrate, and the upper portion of the second vertical structure may include a material different from the lower portion of the second vertical structure.

[0011] According to some embodiments of the present invention, a method of forming an integrated circuit device may include forming a lower stacked structure on a substrate including a first region and a second region. The lower stacked structure may include a plurality of lower sacrificial layers alternating with a plurality of lower insulating layers. The method may further include forming a plurality of lower sacrificial vertical structures extending through the lower stacked structure on the first region and forming a plurality of lower virtual vertical structures extending through the lower stacked structure on the second region, and forming an upper stacked structure on the plurality of lower sacrificial vertical structures and the plurality of lower virtual vertical structures. The upper stacked structure may include a plurality of upper sacrificial layers alternating with a plurality of upper insulating layers. The method may further include forming a stepped structure on the second region by etching portions of the upper and lower stacked structures on the second region, and forming a plurality of upper sacrificial vertical structures extending through the upper stacked structure on the first region and forming a plurality of upper virtual vertical structures on the second region. The plurality of upper sacrificial vertical structures may respectively directly contact the plurality of lower sacrificial vertical structures, and the plurality of upper virtual vertical structures may respectively overlap with the plurality of lower virtual vertical structures. Alternatively, the method may include removing multiple lower sacrificial vertical structures and multiple upper sacrificial vertical structures to form multiple channel holes extending through the upper and lower stacked structures, and forming multiple channel structures in the multiple channel holes respectively. Attached Figure Description

[0012] Figure 1A Equivalent circuit diagrams of three-dimensional semiconductor memory devices according to some exemplary embodiments of the present invention are shown.

[0013] Figure 1B A plan view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0014] Figures 2A to 2L It shows along Figure 1B The cross-sectional views taken by line II illustrate methods for manufacturing three-dimensional semiconductor memory devices according to some exemplary embodiments of the present invention.

[0015] Figures 2M to 2Q It shows along Figure 1B The cross-sectional view taken from line II, and Figures 2M to 2Q Each of these illustrates a three-dimensional semiconductor memory device according to some exemplary embodiments of the concept of the present invention.

[0016] Figures 3A to 3D It shows along Figure 1B The cross-sectional views taken by line II illustrate methods for manufacturing three-dimensional semiconductor memory devices according to some exemplary embodiments of the present invention.

[0017] Figures 4A to 4F It shows along Figure 1BThe cross-sectional views taken by line II illustrate methods for manufacturing three-dimensional semiconductor memory devices according to some exemplary embodiments of the present invention.

[0018] Figures 5A to 5D It shows along Figure 1B The cross-sectional views taken by line II illustrate methods for manufacturing three-dimensional semiconductor memory devices according to some exemplary embodiments of the present invention. Detailed Implementation

[0019] A three-dimensional semiconductor memory device and a method for manufacturing the same, based on some exemplary embodiments of the present invention, will be described.

[0020] As used in this document, the term “and / or” includes any and all combinations of one or more of the relevant listed items.

[0021] It should be understood that "component A covers component B" (or similar language) means that component A is on top of component B, but does not necessarily mean that component A completely covers component B. It should also be understood that "concurrently formed" means formed at approximately (but not necessarily precisely) the same time in the same manufacturing steps.

[0022] Figure 1A Equivalent circuit diagrams of three-dimensional semiconductor memory devices according to some exemplary embodiments of the present invention are shown.

[0023] refer to Figure 1A The three-dimensional semiconductor memory device 1 may include a common source line CSL, multiple bit lines BL0 to BL2, and multiple cell strings CSTRs between the common source line CSL and the bit lines BL0 to BL2. The three-dimensional semiconductor memory device 1 may be, for example, a vertical NAND flash memory device.

[0024] Bit lines BL0 to BL2 can be arranged in a two-dimensional configuration, and multiple cell strings CSTRs can be connected in parallel to one of the bit lines BL0 to BL2. The cell strings CSTRs can be connected together to a common source line CSL. Multiple cell strings CSTRs can be positioned between the common source line CSL and each of the bit lines BL0 to BL2. Multiple common source lines CSLs can be provided and arranged in a two-dimensional configuration. The common source lines CSLs can be supplied with the same voltage or can be electrically controlled independently of each other.

[0025] Each cell string (CSTR) may include a ground select transistor (GST) connected to a common source line (CSL), a string select transistor (SST) connected to one of the bit lines (BL0 to BL2), and a plurality of memory cell transistors (MCTs) disposed between the ground select transistor (GST) and the string select transistor (SST). The ground select transistor (GST), the string select transistor (SST), and the memory cell transistors (MCTs) may be connected in series.

[0026] The common source line CSL can be connected to the ground select transistor GST. Multiple ground select lines GSL, multiple word lines WL0 to WL3, and multiple string select lines SSL between the common source line CSL and the bit lines BL0 to BL2 can be used as the gate electrodes of the ground select transistor GST, the memory cell transistor MCT, and the string select transistor SST, respectively. Each memory cell transistor MCT may include data storage elements, such as an insulator capable of trapping charge carriers (e.g., electrons). Although Figure 1A The diagram shows four word lines WL0 to WL3 located between the ground select line GSL and the serial select line SSL; however, it should be understood that more than four word lines may be provided between the ground select line GSL and the serial select line SSL.

[0027] Figure 1B A plan view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0028] refer to Figure 1B The three-dimensional semiconductor memory device 1 may include a plurality of stacked structures ST extending along a first direction X on a semiconductor substrate 100, a plurality of vertical channels 350 and virtual vertical channels 450 penetrating each stacked structure ST along a third direction Z, a plurality of bit lines 630 electrically connected to the vertical channels 350 and extending along a second direction Y, a plurality of metal lines 650 electrically connected to the stacked structures ST via metal contacts 550 and extending along the second direction Y, and a plurality of common source plugs 676 extending along the first direction X between the stacked structures ST and electrically insulated from the stacked structures ST.

[0029] The first direction X and the second direction Y can be horizontal directions that are substantially perpendicular to each other and extend along the semiconductor substrate 100. The first direction X and the second direction Y can be parallel to the upper surface of the semiconductor substrate 100. The third direction Z can be a vertical direction that is substantially perpendicular to both the first direction X and the second direction Y and extends vertically from the semiconductor substrate 100.

[0030] The three-dimensional semiconductor memory device 1 can be divided into a cell array region (CAR) and an extended region (EXT). A vertical channel 350 can be disposed on the cell array region (CAR), and a virtual vertical channel 450 can be disposed on the extended region (EXT). Bit lines 630 can extend along a second direction Y on the cell array region (CAR), and metal lines 650 can extend along the second direction Y on the extended region (EXT). In some embodiments, each bit line 630 and each metal line 650 can extend longitudinally along the second direction Y, such as... Figure 1BAs shown. The stacked structure ST and the common source plug 676 may extend along the common source 672 disposed in the semiconductor substrate 100 in a first direction X. In some embodiments, each of the stacked structure ST and the common source plug 676 may extend longitudinally along the first direction X, as shown. Figure 1B As shown.

[0031] The vertical channel 350 may have a continuous vertical column shape along the third direction Z. The virtual vertical channel 450 may have a continuous or discontinuous vertical column shape along the third direction Z. In some embodiments, the vertical channel 350 may have a U-shaped shape or a curved tube shape when viewed in cross-section. Although Figure 1B The vertical channel 350 and the virtual vertical channel 450 are shown to have the same shape and size in the plan view, but the inventive concept is not limited thereto. In some embodiments, the vertical channel 350 and the virtual vertical channel 450 may have different shapes and sizes.

[0032] Figures 2A to 2L It shows along Figure 1B The cross-sectional views taken by line II illustrate methods for manufacturing three-dimensional semiconductor memory devices according to some exemplary embodiments of the present invention.

[0033] refer to Figure 2A The semiconductor substrate 100 may include a cell array region CAR and an extended region EXT. The semiconductor substrate 100 may be a silicon wafer having a first conductivity type (e.g., P-type). A plurality of molding sacrificial layers 110 and a plurality of molding dielectric layers 120 may be alternately and repeatedly stacked on the semiconductor substrate 100, and may form a first stack S1. A dielectric buffer layer 105 may also be formed between the semiconductor substrate 100 and the bottommost molding sacrificial layer 110. The molding sacrificial layer 110 and the molding dielectric layer 120 may be formed of dielectric materials having etch selectivity relative to each other. The dielectric buffer layer 105 may be formed of the same or similar dielectric material as the dielectric material of the molding dielectric layer 120. For example, the molding sacrificial layer 110 may include silicon nitride, and the molding dielectric layer 120 and the dielectric buffer layer 105 may include silicon oxide.

[0034] Referring to Figures 2B_1 and 2B_2, a plurality of first sacrificial pillars 150 may be formed to penetrate (e.g., extend through) the first stack S1. For example, an etching process may be performed on the first stack S1 to form one or more first vertical holes 130 that vertically penetrate the first stack S1, and one or more first dummy vertical holes 140 that vertically penetrate the first stack S1. Then, the first sacrificial pillars 150 may be formed to fill the first vertical holes 130 and the first dummy vertical holes 140. The first vertical holes 130 may be disposed on the cell array region CAR, and the first dummy vertical holes 140 may be disposed on the extension region EXT. The first vertical holes 130 and the first dummy vertical holes 140 may have a hollow pillar shape, such as a hollow cylinder, a hollow elliptical cylinder, or a hollow polygonal cylinder, and may expose the semiconductor substrate 100. The first sacrificial pillar 150 can be formed by depositing a material with etch selectivity relative to the molded sacrificial layer 110 and the molded dielectric layer 120 in the first vertical hole 130 and the first virtual vertical hole 140. For example, the first sacrificial pillar 150 may comprise a semiconductor material such as polycrystalline silicon or a metallic material such as tungsten. It should be understood that the term "pillar" as used herein refers to a vertical structure having various shapes.

[0035] In some embodiments, each of the first vertical hole 130 and the first virtual vertical hole 140 may have a side surface perpendicular to the upper surface of the semiconductor substrate 100 and may have a uniform width in a first direction X along the third direction Z, as shown in FIG2B_1. In some embodiments, each of the first vertical hole 130 and the first virtual vertical hole 140 may have a side surface inclined relative to the upper surface of the semiconductor substrate 100 and may have a non-uniform width in the first direction X, which increases along the third direction Z, as shown in FIG2B_2.

[0036] refer to Figure 2CThe first sacrificial pillar 150 on the extended region EXT can be replaced by a first passive pillar 155. For example, a mask pattern 50 can be formed on a first stack S1 on the cell array region CAR, and an etching process can be performed using the mask pattern 50 as an etching mask to remove the first sacrificial pillar 150 from the first virtual vertical aperture 140. Dielectric material can be deposited in the empty first virtual vertical aperture 140 where the first sacrificial pillar 150 has been removed, and this deposition can form the first passive pillar 155 on the extended region EXT. The mask pattern 50 may include, for example, a photoresist or other material having etch selectivity relative to the molding sacrificial layer 110 and the molding dielectric layer 120. The first passive pillar 155 may include a dielectric material that has no etch selectivity or low etch selectivity relative to the molding sacrificial layer 110 and / or the molding dielectric layer 120. In some embodiments, the molding sacrificial layer 110 may include silicon nitride, the molding dielectric layer 120 may include silicon oxide, and the first passive pillar 155 may include silicon oxide, silicon nitride, or a combination thereof. After the first passive pillar 155 is formed, the mask pattern 50 can be removed by, for example, an ashing process or a stripping process.

[0037] It should be understood that if two materials do not have etch selectivity or have low etch selectivity, they can be etched by an etching process at the same or similar etch rate.

[0038] refer to Figure 2D A second stack S2 can be formed on a semiconductor substrate 100. The second stack S2 can be stacked on a first stack S1. The second stack S2 can be the same as or similar to the first stack S1. For example, a plurality of molding sacrificial layers 110 and a plurality of molding dielectric layers 120 can be alternately and repeatedly stacked on the first stack S1, and can form the second stack S2. The molding sacrificial layers 110 and molding dielectric layers 120 of the second stack S2 can include materials that are the same as or similar to the materials of the molding sacrificial layers 110 and molding dielectric layers 120 of the first stack S1. For example, the molding sacrificial layer 110 of the second stack S2 can include silicon nitride, and the molding dielectric layer 120 of the second stack S2 can include silicon oxide. The bottommost molding dielectric layer 120 of the second stack S2 can be used as a buffer layer. In some embodiments, the bottommost molding dielectric layer 120 of the second stack S2 can be formed to be thicker than the adjacent other molding dielectric layers 120, such as Figure 2D As shown.

[0039] refer to Figure 2E A stepped structure 300 can be formed on the semiconductor substrate 100. Multiple etching processes can be performed on the first stack S1 and the second stack S2, and on an etching mask (e.g., ...). Figure 2EMultiple trimming processes are performed on the mask pattern 60 to form the stepped structure 300. For example, a photoresist layer may be coated on the second stack S2, and then the photoresist layer may be patterned to form the mask pattern 60. An etching process may be performed in which the mask pattern 60 is used as an etching mask to first etch the uppermost molding dielectric layer 120 and the uppermost molding sacrificial layer 110. The mask pattern 60 may undergo a trimming process to reduce the size of the mask pattern 60, and the reduced mask pattern 60 may be used as an etching mask to second etch the already etched uppermost molding dielectric layer 120 and the uppermost molding sacrificial layer 110. In this case, the uppermost molding dielectric layer 120 and the uppermost molding sacrificial layer 110 may be used as etching masks to etch the second uppermost molding dielectric layer 120 and the second uppermost molding sacrificial layer 110.

[0040] The trimming and etching processes can be performed multiple times to reduce (e.g., gradually reduce) the size of the mask pattern 60 and to repeatedly etch the molding dielectric layer 120 and the molding sacrificial layer 110. As described above, since the first passive pillar 155 has no etch selectivity or low etch selectivity relative to the molding dielectric layer 120 and the molding sacrificial layer 110, the first passive pillar 155 can also be etched together with the molding dielectric layer 120 and the molding sacrificial layer 110 of the first stack S1. In some embodiments, the first passive pillar 155 can be etched at the same or similar etch rate as the molding dielectric layer 120 and the molding sacrificial layer 110 of the first stack S1, and therefore the upper surface of the first passive pillar 155 can be coplanar with the upper surface of the molding dielectric layer 120, such as... Figure 2E As shown.

[0041] In this specification, a stepped process can refer to a series of finishing and etching processes. A single stepped process may use a single mask pattern throughout the entire process (e.g., Figure 2E The mask pattern 60 in the process can be removed after the single step process is completed. The step process is discussed, for example, in U.S. Patent Application Publication No. , the entire contents of which are incorporated herein by reference. In some example embodiments, a single step process can be performed to form a step structure 300 extending continuously along the first stack S1 and the second stack S2, such as... Figure 2E As shown. For example, as referenced in Figure 2B and Figure 2CAs the first sacrificial pillar 150 on the extended region EXT is replaced by a first passive pillar 155 comprising the same or similar material as the molded dielectric layer 120 and / or the molded sacrificial layer 110, an etching process can be easily performed on the extended region EXT of the first stack S1. Therefore, the stepped structure 300 can be formed by performing a single step process on the first stack S1 and the second stack S2 instead of performing two separate step processes on the first stack S1 and the second stack S2. Even when two or more first stacks S1 are provided between the semiconductor substrate 100 and the second stack S2, the stepped structure 300 can be formed by a single step process. After forming the stepped structure 300, the mask pattern 60 can be removed by, for example, an ashing process or a stripping process.

[0042] refer to Figure 2F A planarized dielectric layer 301 may be formed on the semiconductor substrate 100, covering the stepped structure 300. The planarized dielectric layer 301 may include, for example, silicon oxide, silicon nitride, or a combination thereof. The stepped structure 300 may have a downwardly sloping shape along a direction from the cell array region CAR toward the extension region EXT (corresponding to...). Figure 1B The molding sacrificial layer 110 extends in the first direction (X). In the extended region EXT, the molding sacrificial layer 110 may have an end not covered by the molding sacrificial layer 110 immediately superimposed thereon. For example, in the extended region EXT, each molding sacrificial layer 110 may protrude beyond the end of the molding sacrificial layer 110 immediately superimposed thereon, such as... Figure 2F As shown.

[0043] When performing a stepped process, the etching process can etch the tops of some of the first passive pillars 155. The height of the etched first passive pillars 155 can be less than their initial height. The height can refer to the vertical direction starting from the semiconductor substrate 100 (corresponding to...). Figure 1B The length in the third direction Z). The height of the etched first passive pillar 155 may decrease (e.g., gradually decrease) as the distance between the etched first passive pillar 155 and the cell array region CAR in the first direction X increases, such as Figure 2F As shown. The first passive pillar 155, which is not etched during the step process, can maintain its initial height. Similarly, the first sacrificial pillar 150 can maintain its initial height.

[0044] Referring to Figures 2G_1 and 2G_2, a second vertical hole 230 and a second virtual vertical hole 240 can be formed. The second vertical hole 230 can be disposed on the cell array region CAR, and the second virtual vertical hole 240 can be disposed on the extension region EXT. For example, the second stack S2 can undergo an etching process to form the second vertical hole 230 vertically aligned with the first vertical hole 130. The second stack S2 and the planarized dielectric layer 301 can undergo an etching process to form the second virtual vertical hole 240 vertically aligned with the first virtual vertical hole 140. The second vertical hole 230 and the second virtual vertical hole 240 can be formed simultaneously. The second vertical hole 230 and the second virtual vertical hole 240 can have a hollow cylindrical shape, such as a hollow cylindrical, hollow elliptical cylindrical, or hollow polygonal cylindrical. In some embodiments, the second vertical hole 230 and the second virtual vertical hole 240 can be formed concurrently.

[0045] In some embodiments, each of the second vertical hole 230 and the second virtual vertical hole 240 may have a side surface perpendicular to the upper surface of the semiconductor substrate 100 and may have a uniform width in a first direction X along a third direction Z, as shown in FIG2G_1. In some embodiments, each of the second vertical hole 230 and the second virtual vertical hole 240 may have a side surface inclined relative to the upper surface of the semiconductor substrate 100 and may have a non-uniform width in a first direction X, which increases along a third direction Z, as shown in FIG2G_2.

[0046] The second vertical hole 230 and the second virtual vertical hole 240 may be formed such that their depth is equal to or greater than the height of the second stack S2. For example, each of the second vertical holes 230 is penetrable (e.g., extends through) the second stack S2 and may be continuously connected to a corresponding one of the first vertical holes 130 below the second vertical hole 230. In this case, each of the second vertical holes 230 may expose (e.g., reveal) a corresponding one of the first sacrificial pillars 150 in the first vertical hole 130 corresponding to the second vertical hole 230. Some of the second virtual vertical holes 240 are penetrable through the stepped structure 300 of the second stack S2 and may be continuously connected to the first virtual vertical holes 140 below said some of the second virtual vertical holes 240. In this case, some of the second virtual vertical holes 240 may expose (e.g., reveal) the first passive pillars 155 in the first virtual vertical holes 140 corresponding to said some of the second virtual vertical holes 240. Some of the other virtual vertical holes 240 may partially penetrate the planarized dielectric layer 301 and may discontinuously connect to the first virtual vertical hole 140 below the other virtual vertical holes 240. In this case, the other virtual vertical holes 240 may not expose the first passive pillar 155 in the first virtual vertical hole 140 corresponding to the other virtual vertical holes 240.

[0047] In some embodiments, some of the second virtual vertical holes 240 may extend through the second stack S2 and may expose the underlying first passive pillars 155, as shown in Figures 2G_1 and 2G_2. In some embodiments, some of the second virtual vertical holes 240 may not extend through the planarized dielectric layer 301 and may be spaced apart from the underlying first passive pillars 155 in the third direction Z, as shown in Figures 2G_1 and 2G_2.

[0048] refer to Figure 2H The second sacrificial post 250 may be formed in the second vertical hole 230, and the second passive post 255 may be formed in the second virtual vertical hole 240. For example, the second sacrificial post 250 may be formed in both the second vertical hole 230 and the second virtual vertical hole 240, and then can be performed with reference to Figure 2C The process described is the same as or similar to that used to form a second passive pillar 255 that replaces the second sacrificial pillar 250 in the second virtual vertical hole 240. The second sacrificial pillar 250 may comprise a semiconductor material such as polysilicon or a metallic material such as tungsten. In some embodiments, the second sacrificial pillar 250 may comprise a material that is the same as or similar to that of the first sacrificial pillar 150. The second passive pillar 255 may comprise a material such as silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the second passive pillar 255 may comprise a material that is the same as or similar to that of the first passive pillar 155.

[0049] A continuous unit may be defined as comprising a first sacrificial post 150 and a second sacrificial post 250 continuously connected to each other in a first vertical hole 130 and a second vertical hole 230. Another continuous unit may be defined as comprising a first passive post 155 and a second passive post 255 continuously connected to each other in a first virtual vertical hole 140 and a second virtual vertical hole 240. A discontinuous unit may be defined as comprising a first passive post 155 and a second passive post 255 not connected to each other in a first virtual vertical hole 140 and a second virtual vertical hole 240. A one-to-one correspondence may be established between the first passive post 155 and the second passive post 255. For example, the number of first passive posts 155 may be the same as the number of second passive posts 255.

[0050] In some embodiments, each of the second sacrificial pillars 250 may overlap with a corresponding one of the first sacrificial pillars 150 in the third direction Z, and each of the second passive pillars 255 may overlap with a corresponding one of the first passive pillars 155 in the third direction Z, such as Figure 2H As shown. It should be understood that "element A overlaps with element B in one direction" (or similar language) means that there exists at least one line extending in that direction and intersecting both element A and element B.

[0051] refer to Figure 2I Multiple vertical channels 350 may be formed to penetrate the first stack S1 and the second stack S2 and be electrically connected to the semiconductor substrate 100. For example, an etching process may be performed to selectively remove the first sacrificial pillar 150 and the second sacrificial pillar 250 from the first vertical hole 130 and the second vertical hole 230, and then the vertical channels 350 may fill the empty first vertical hole 130 and the second vertical hole 230 from which the first sacrificial pillar 150 and the second sacrificial pillar 250 have been removed. As described above, since the first sacrificial pillar 150 and the second sacrificial pillar 250 may comprise materials that are etch-selective relative to the molding sacrificial layer 110 and the molding dielectric layer 120, the first sacrificial pillar 150 and the second sacrificial pillar 250 may be selectively removed without etch loss of the molding sacrificial layer 110 and the molding dielectric layer 120.

[0052] Each vertical channel 350 may include a channel layer 352 and a memory layer 354 surrounding the channel layer 352. The memory layer 354 may include one or more dielectric layers. For example, the memory layer 354 may include a tunnel dielectric layer surrounding the channel layer 352, a barrier dielectric layer away from the channel layer 352, and a charge storage layer located between the tunnel dielectric layer and the barrier dielectric layer. The channel layer 352 may include, for example, polysilicon. The channel layer 352 may have a block shape or a hollow tube shape. When the channel layer 352 has a hollow tube shape, the dielectric layer may fill the empty interior of the hollow tube shape. Pads 356 may be formed at the top of each vertical channel 350. The pads 356 may be doped regions where conductors or impurities (e.g., N-type impurities) are implanted.

[0053] A pair of first passive pillars 155 and second passive pillars 255 vertically aligned with each other can form a virtual vertical channel 450. For example, a vertical channel 350 can be provided on a cell array region CAR, and a virtual vertical channel 450 can be provided on an extension region EXT. Some of the virtual vertical channels 450 can each be continuous units, while others can each be discontinuous units. For example, at least one adjacent cell array region CAR in the virtual vertical channel 450 can be a continuous unit where the first passive pillar 155 and the second passive pillar 255 are physically in contact with each other. Conversely, at least one unit away from the cell array region CAR in the virtual vertical channel 450 can be a discontinuous unit where the first passive pillar 155 and the second passive pillar 255 are physically spaced apart from each other. A virtual vertical channel 450 having such discontinuous units can include isolated passive pillars (also called floating passive pillars) or second passive pillars 255 spaced apart from the first passive pillar 155 in a third direction Z. In some embodiments, the pair of first passive pillars 155 and second passive pillars 255 furthest from the cell array region CAR can be spaced apart from each other in the third direction Z, such as Figure 2I As shown.

[0054] The first passive post 155 and the second passive post 255 may have the same dielectric bulk structure. In some embodiments, each of the first passive post 155 and the second passive post 255 may be a solid structure. In some embodiments, each of the first passive post 155 and the second passive post 255 may have a unitary structure formed by a single material layer (e.g., a single insulating layer) without interfaces.

[0055] Still referencing Figure 2IThe second passive pillar 255 may have a uniform height. Conversely, the first passive pillar 155 may have a non-uniform height. For example, some of the first passive pillars 155 may have the same or similar height, while others may have a height that decreases (e.g., gradually decreases) as the distance between the first passive pillar 155 and the cell array region CAR increases. The first passive pillars 155 with decreasing heights may be spaced apart from their corresponding second passive pillars 255. The spacing between the first passive pillars 155 and the second passive pillars 255 in the third direction Z may increase as the distance between the first passive pillars 155 and the cell array region CAR increases.

[0056] Some of the second passive pillars 255 can penetrate the planarized dielectric layer 301 and the stepped structure 300, while others of the second passive pillars 255 can penetrate the planarized dielectric layer 301 but not the stepped structure 300. The second passive pillars 255 that penetrate the stepped structure 300 can directly contact the corresponding first passive pillar 155. The second passive pillars 255 that do not penetrate the stepped structure 300 can be spaced apart from the corresponding first passive pillar 155.

[0057] refer to Figure 2J A space 115 can be formed between the molded dielectric layers 120. For example, the molded sacrificial layer 110 can be removed by an etching process using an etchant that selectively etches the molded sacrificial layer 110, which can form the space 115 between the molded dielectric layers 120. When the molded sacrificial layer 110 comprises silicon nitride, it can be selectively removed by an etchant containing, for example, phosphoric acid (H3PO4). Although the first stack S1 and the second stack S2 have weaknesses due to the formation of the space 115 between the molded dielectric layers 120 (e.g., partial susceptibility to effects such as sagging or collapse), the virtual vertical channel 450 can be used as a support to overcome these weaknesses.

[0058] refer to Figure 2K Electrodes 400 may be formed between the molded dielectric layers 120, thus forming a stacked structure ST. For example, a conductive material may be deposited to form electrodes 400 filling space 115. Electrodes 400 may include, for example, polysilicon or metal. For example, electrodes 400 may include tungsten. When a process is performed to fill space 115 with electrodes 400, virtual vertical channels 450 may support the stepped structure 300, and the first stack S1 and the second stack S2 may not collapse.

[0059] Each electrode can be 400. Figure 1AThe diagram shows one of the ground select line GSL, word lines WL0 to WL3, and serial select line SSL. Each electrode 400 may include a pad 405 disposed on the extension region EXT or an end of the electrode 400. The pad 405 of the electrode 400 may form a stepped structure 300 on the extension region EXT and may be supported by a virtual vertical channel 450.

[0060] like Figure 1B As shown, a common source 672 can be formed by implanting an impurity (e.g., an N-type impurity) into a semiconductor substrate 100 between adjacent stacked structures ST, and a common source plug 676 can be formed to be electrically connected to the common source 672 and extend along the common source 672 between the stacked structures ST.

[0061] refer to Figure 2L Bit lines 630 may be formed on the cell array region CAR, and metal lines 650 may be formed on the extension region EXT. For example, an interlayer dielectric layer 303 may be formed on the semiconductor substrate 100 and may cover the second stack S2 and the planarized dielectric layer 301. The interlayer dielectric layer 303 may be formed by deposition, for example, silicon oxide, silicon nitride, or a combination thereof. On the cell array region CAR, bit line contacts 530 may be formed to penetrate the interlayer dielectric layer 303 and connect to pads 356. On the extension region EXT, metal contacts 550 may be formed to penetrate the interlayer dielectric layer 303 and the planarized dielectric layer 301 and connect to pads 405 of the electrode 400. The metal contacts 550 may further penetrate the molded dielectric layer 120 on the pads 405 of the electrode 400. Conductive materials may be deposited and patterned to form bit lines 630 and metal lines 650 on the interlayer dielectric layer 303. Bit line 630 can be electrically connected to vertical channel 350 via bit line contact 530. Metal line 650 can be electrically connected to pad 405 of electrode 400 via metal contact 550. Through the above process, a three-dimensional semiconductor memory device 1 can be manufactured.

[0062] The first passive pillar 155 has a lower portion adjacent to the semiconductor substrate 100 and an upper portion opposite to the lower portion of the first passive pillar 155. In some embodiments, the lower portion of the first passive pillar 155 has a first width W1 in a first direction X, and the upper portion of the first passive pillar 155 has a second width W2 in the first direction X, the second width W2 being greater than the first width W1, such as... Figure 2L As shown. The second passive post 255 has a lower portion adjacent to the first passive post 155 and an upper portion opposite to the lower portion of the second passive post 255. In some embodiments, the lower portion of the second passive post 255 has a third width W3 in a first direction X, and the upper portion of the second passive post 255 has a fourth width W4 in the first direction X, the fourth width W4 being greater than the third width W3, as shown. Figure 2LAs shown. In some embodiments, the second width W2 of the first passive post 155 may be greater than the third width W3 of the second passive post 255.

[0063] Figures 2M to 2Q It shows along Figure 1B The cross-sectional view taken from line II, and Figures 2M to 2Q Each of the examples shows a different instance of the three-dimensional semiconductor memory device 1.

[0064] refer to Figure 2M When passing through Figure 2G to Figure 2I In the process shown, when forming a vertical channel 350 on the cell array region CAR, the second virtual vertical via 240 can be filled with second passive pillars 255, each of which has a structure identical or similar to that of the vertical channel 350. Therefore, the three-dimensional semiconductor memory device 1 can include virtual vertical channels 450, each of which has a heterogeneous structure. For example, the first passive pillar 155 can have a dielectric structure, and the second passive pillar 255 can have the same structure as the vertical channel 350. In some embodiments, the second passive pillar 255 can include a material different from the first passive pillar 155. In some embodiments, the first passive pillar 155 can be formed before the second passive pillar 255 is formed, as shown in the reference. Figure 2C and 2H It should be understood that the first passive column 155 and the second passive column 155 can be formed by different processes.

[0065] In some embodiments, the channel layer 352 and the memory layer 354 may be formed in each of the second virtual vertical holes 240, such as Figure 2M As shown. In some embodiments, the channel layer 352 and memory layer 354 formed in the second virtual vertical aperture 240 furthest from the cell array region CAR may be spaced apart from both the underlying first passive pillar 155 and the semiconductor substrate 100 in the third direction Z, as... Figure 2M As shown. Conversely, the channel layer 352 of the vertical channel 350 on the cell array region CAR can directly contact the semiconductor substrate 100. In some embodiments, the channel layer 352 and memory layer 354 formed in the second virtual vertical aperture 240 furthest from the second cell matrix region CAR can also be spaced apart from both the underlying first passive pillar 155 and the semiconductor substrate 100 in the third direction Z, as shown. Figure 2M As shown. In some embodiments, the first passive pillar 155 may not include the channel layer 352.

[0066] refer to Figure 2NWhen the second vertical via 230 and the second virtual vertical via 240 are formed using the processes shown in Figures 2G_1 and 2G_2, all the second virtual vertical vias 240 can be formed with a depth sufficient to expose the first passive pillar 155 below the corresponding second virtual vertical via 240. In this case, the second passive pillar 255 can directly contact the first passive pillar 155, while having a dielectric structure that is the same as or similar to that of the first passive pillar 155. Then, the three-dimensional semiconductor memory device 1 may include virtual vertical channels 450, each virtual vertical channel 450 having a continuous unit where the first passive pillar 155 and the second passive pillar 255 are in direct contact with each other.

[0067] refer to Figure 2O For reference Figure 2M The second virtual vertical hole 240 may be filled with second passive pillars 255, each of which has a structure identical or similar to that of the vertical channel 350. Then, the semiconductor memory device 1 may include virtual vertical channels 450, each of which has a heterogeneous structure and is a continuous unit where the first passive pillar 155 and the second passive pillar 255 are in direct contact with each other.

[0068] In some embodiments, the channel layer 352 and the memory layer 354 may be formed in each of the second virtual vertical holes 240, such as Figure 2O As shown. In some embodiments, the channel layer 352 formed in the second virtual vertical aperture 240 furthest from the cell array region CAR may include the lowest end at the first horizontal level, and the channel layer 352 formed in the second virtual vertical aperture 240 furthest from the cell array region CAR may include the lowest end at a second horizontal level above the first horizontal level, such as... Figure 2O As shown. In some embodiments, the uppermost end of the channel layer 352 formed in the second virtual vertical aperture 240 furthest from the cell array region CAR and the uppermost end of the channel layer 352 formed in the second virtual vertical aperture 240 furthest from the cell array region CAR may be at the same level, as shown. Figure 2O As shown.

[0069] refer to Figure 2P The three-dimensional semiconductor memory device 1 may include a virtual vertical channel 450, and the number of first passive pillars 155 constituting the virtual vertical channel 450 may be greater than the number of second passive pillars 255 constituting the virtual vertical channel 450. The difference in number may result in at least one of the virtual vertical channels 450 having a dual-pillar or multi-pillar structure, and at least one of the virtual vertical channels 450 having a single-pillar structure.

[0070] For example, when the second virtual vertical via 240 is formed using the process described in Figures 2G_1 and 2G_2, it is possible to avoid forming a second virtual vertical via 240 that only penetrates the planarized dielectric layer 301 without penetrating the stepped structure 300 of the second stack S2. Therefore, at least one of the virtual vertical channels 450 may have a double-pillar structure in which the first passive pillar 155 and the second passive pillar 255 are continuously connected to each other, and at least one of the virtual vertical channels 450 may have a single-pillar structure that includes only the first passive pillar 155 and not the second passive pillar 255. Each of the first passive pillar 155 and the second passive pillar 255 may have a dielectric structure.

[0071] refer to Figure 2Q ,and Figure 2P As shown or similarly, the three-dimensional semiconductor memory device 1 may include at least one virtual vertical channel 450 having a dual-pillar structure and at least one virtual vertical channel 450 having a single-pillar structure. The virtual vertical channel 450 with a dual-pillar structure may include a first passive pillar 155 having a dielectric structure, and may also include a second passive pillar 255 having the same structure as the vertical channel 350. The virtual vertical channel 450 with a single-pillar structure may include a single first passive pillar 155 having a dielectric structure.

[0072] Figures 3A to 3D It shows along Figure 1B The cross-sectional views taken by line II illustrate methods for manufacturing three-dimensional semiconductor memory devices according to some exemplary embodiments of the present invention.

[0073] refer to Figure 3A An additional molding sacrificial layer 112 may be further formed on the stepped structure 300. For example, it can be implemented with reference to Figures 2A to 2D The processes described are identical or similar to those used to form a first stack S1 and a second stack S2 on a semiconductor substrate 100, and then can be performed with reference to Figure 2E The step process described herein is the same as or similar to a step process used to pattern the first stack S1 and the second stack S2, which can form a step structure 300. In some example embodiments, when performing the step process, the etching target can be controlled to form the step structure 300 with the ends of the molding sacrificial layer 110 exposed on the extension region EXT. Each additional molding sacrificial layer 112 can respectively cover the exposed ends of each molding sacrificial layer 110, such as Figure 3A As shown.

[0074] The additional molding sacrificial layer 112 may comprise a material that is the same as or similar to that of the molding sacrificial layer 110. For example, the additional molding sacrificial layer 112 may comprise, for example, silicon nitride. In some example embodiments, since the stepped structure 300 is formed by performing a single stepped process, it is not necessary to perform the formation of the additional molding sacrificial layer 112 on the first stack S1 and the formation of the additional molding sacrificial layer 112 on the second stack S2 separately. Therefore, the additional molding sacrificial layer 112 covering the stepped structure 300 can be formed by a single process (e.g., a single deposition process) performed on the first stack S1 and the second stack S2.

[0075] refer to Figure 3B Executable and Reference Figures 2F to 2I The processes described are identical or similar, used to form a planarized dielectric layer 301 covering the stepped structure 300 and to form vertical channels 350 and virtual vertical channels 450 on the cell array region CAR and the extended region EXT. At least one adjacent cell array region CAR in the virtual vertical channel 450 may have continuous cells with the first passive pillar 155 and the second passive pillar 255 in direct contact with each other, and at least one cell distant from the cell array region CAR in the virtual vertical channel 450 may have discontinuous cells with the first passive pillar 155 and the second passive pillar 255 spaced apart from each other in the third direction Z. The first passive pillar 155 and the second passive pillar 255 may have the same dielectric structure.

[0076] refer to Figure 3C Executable and Reference Figure 2J and Figure 2K The processes described are the same as or similar to those described. The molding sacrificial layer 110 can be selectively removed to form the space 115, and an electrode 400 can be formed to fill the space 115. Since the additional molding sacrificial layer 112 comprises the same or similar material as the molding sacrificial layer 110, the additional molding sacrificial layer 112 can also be removed together with the molding sacrificial layer 110. See reference... Figure 3A As the additional molding sacrificial layer 112 is formed at the end of the molding sacrificial layer 110, the space 115 may have an extended end corresponding to the end of the molding sacrificial layer 110. Therefore, the pad 405 of the electrode 400 may have an increased thickness. For example, compared to other portions of the electrode 400, the pad 405 may have a raised top surface, such as... Figure 3C As shown.

[0077] refer to Figure 3D Executable and Reference Figure 2LThe aforementioned processes are identical or similar to form bit lines 630, which are electrically connected to the vertical channel 350 via bit line contacts 530 penetrating the interlayer dielectric layer 303. Furthermore, this process can form metal lines 650, which are electrically connected to the pads 405 of the electrode 400 via metal contacts 550 penetrating the interlayer dielectric layer 303. Because the pads 405 of the electrode 400 have increased thickness, the pads 405 can have improved resistance to over-etching when an etching process is performed to form contact holes in which the metal contacts 550 are formed. Therefore, contact holes can be prevented from penetrating the corresponding pads 405 and can be prevented from extending to other pads 405 immediately below a penetrated pad 405.

[0078] The virtual vertical channel 450 can have the same characteristics as... Figures 2M to 2Q The virtual vertical channel 450 shown has the same structure. For example, the virtual vertical channel 450 may have... Figure 2M The heterostructure shown Figure 2N The continuous monomers shown, or Figure 2O Both heterogeneous structures and continuous monomers are shown. In some embodiments, at least one of the virtual vertical channels 450 may have Figure 2P or Figure 2Q The single-column structure shown.

[0079] Figures 4A to 4F It shows along Figure 1B The cross-sectional views taken by line II illustrate methods for manufacturing three-dimensional semiconductor memory devices according to some exemplary embodiments of the present invention.

[0080] refer to Figure 4A Executable and Reference Figures 2A to 2D The processes described are the same or similar, used to form a first stack S1 and a second stack S2 on a semiconductor substrate 100, and to form a second vertical hole 230 and a second virtual vertical hole 240, respectively, vertically aligned with the first vertical hole 130 and the first virtual vertical hole 140. The second vertical hole 230 may expose (e.g., reveal) the first sacrificial pillar 150 in the first vertical hole 130, and the second virtual vertical hole 240 may expose (e.g., reveal) the first passive pillar 155 in the first virtual vertical hole 140.

[0081] refer to Figure 4B The second sacrificial post 250 may be formed in the second vertical hole 230, and the second passive post 255 may be formed in the second virtual vertical hole 240. For example, the second sacrificial post 250 may be formed in both the second vertical hole 230 and the second virtual vertical hole 240, and then can be performed with reference to Figure 2CThe processes described are the same or similar, such that the second passive pillar 255 can replace the second sacrificial pillar 250 in the second virtual vertical aperture 240. Therefore, the cell array region CAR can have vertically aligned and contacting first sacrificial pillars 150 and second sacrificial pillars 250 thereon, and the extended region EXT can have vertically aligned and contacting first passive pillars 155 and second passive pillars 255 thereon. The first sacrificial pillars 150 and second sacrificial pillars 250 may comprise the same or similar materials, such as polysilicon. The first passive pillars 155 and second passive pillars 255 may comprise the same or similar materials, such as silicon oxide, silicon nitride, or combinations thereof.

[0082] refer to Figure 4C Executable and Reference Figure 2E The process described is the same as or similar to the process described above. A step process can be performed to pattern the first stack S1 and the second stack S2 to form a step structure 300 on the semiconductor substrate 100. When etching the molding dielectric layer 120 and the molding sacrificial layer 110, the first passive pillar 155 and the second passive pillar 255 can be etched at an etch rate that is the same as or similar to the etch rate of the molding dielectric layer 120 and the molding sacrificial layer 110. Therefore, the step structure 300 can be formed by a single step process that patterns both the first stack S1 and the second stack S2, and this single step process can also form a virtual vertical channel 450 that can support the step structure 300.

[0083] At least one of the virtual vertical channels 450 may consist only of a first passive post 155. For example, the virtual vertical channel 450 furthest from the cell array region CAR may consist only of a first passive post 155. At least one of the virtual vertical channels 450 may include a pair of first passive posts 155 and second passive posts 255 vertically aligned with each other. For example, the virtual vertical channel 450 closest to the cell array region CAR may include first passive posts 155 and second passive posts 255 vertically aligned with each other, and may have continuous units where the first passive posts 155 and second passive posts 255 are in direct contact with each other. The first passive posts 155 and second passive posts 255 may have the same dielectric structure.

[0084] In some embodiments, the virtual vertical channel 450 furthest from the cell array region CAR may consist of only a single first passive pillar 155 and may not include the second passive pillar 255, such as Figure 4C As shown. In some embodiments, the virtual vertical channel 450 closest to the cell array region CAR may include both a first passive pillar 155 and a second passive pillar 255, as shown. Figure 4C As shown, the second passive post 255 can overlap with the first passive post 155 in the third direction Z and can directly contact the first passive post 155, as... Figure 4C As shown.

[0085] The virtual vertical channels 450 can have different heights from each other. For example, the height of the virtual vertical channels 450 can be along the direction from the cell array region CAR to the extension region EXT (corresponding to...). Figure 1B The height of the virtual vertical channel 450 decreases (e.g., gradually decreases) in the first direction X. In some embodiments, the virtual vertical channel 450 closest to the cell array region CAR may have the largest height, and the virtual vertical channel 450 farthest from the cell array region CAR may have the smallest height, such as... Figure 4C As shown.

[0086] refer to Figure 4D The planarized dielectric layer 301 can be formed to cover a stepped structure 300 on the semiconductor substrate 100, and a plurality of vertical channels 350 can be formed to penetrate the first stack S1 and the second stack S2 and be electrically connected to the semiconductor substrate 100. For example, an etching process can be performed to selectively remove the first sacrificial pillar 150 and the second sacrificial pillar 250 from the first vertical hole 130 and the second vertical hole 230, and then the vertical channels 350 can fill the empty first vertical hole 130 and the second vertical hole 230 where the first sacrificial pillar 150 and the second sacrificial pillar 250 have been removed.

[0087] refer to Figure 4E Executable and Reference Figure 2J and Figure 2K The processes described are identical or similar, involving the selective removal of the molding sacrificial layer 110 to form space 115 and filling space 115 with a conductive material (e.g., tungsten) to form electrode 400. A stacked structure ST in which electrodes 400 are stacked between molding dielectric layers 120 is then obtained. The virtual vertical channel 450 may not protrude beyond the stepped structure 300.

[0088] refer to Figure 4F Executable and Reference Figure 2L The processes described are identical or similar to form the interlayer dielectric layer 303 and bit line contacts 530 that penetrate the interlayer dielectric layer 303 and are coupled (e.g., electrically connected) to the pads 356 of the vertical channel 350. Furthermore, these processes can form metal contacts 550 that penetrate the interlayer dielectric layer 303 and the planarized dielectric layer 301 and are coupled (e.g., electrically connected) to the pads 405 of the electrode 400. On the interlayer dielectric layer 303, bit lines 630 can be formed to connect (e.g., electrically connected) to the bit line contacts 530, and metal lines 650 can be formed to connect (e.g., electrically connected) to the metal contacts 550.

[0089] Figures 5A to 5D It shows along Figure 1BThe cross-sectional views taken by line II illustrate methods for manufacturing three-dimensional semiconductor memory devices according to some exemplary embodiments of the present invention.

[0090] refer to Figure 5A For reference Figures 4A to 4C The process described above involves performing a single step process to pattern the first stack S1 and the second stack S2. A step structure 300 can then be formed on the extended region EXT, and simultaneously, a virtual vertical channel 450 can be formed so as not to protrude from the step structure 300. In some embodiments, the upper portion of the virtual vertical channel 450 may not protrude beyond the upper surface of the step structure 300, such as... Figure 5A As shown, the entire virtual vertical channel 450 can therefore be situated within the stepped structure 300. The cell array region CAR can be provided with a first sacrificial pillar 150 and a second sacrificial pillar 250 vertically aligned with each other. In some example embodiments, when the stepped structure 300 is formed, the ends of the molded sacrificial layer 110 can be exposed on the extension region EXT.

[0091] After the stepped structure 300 is formed, an additional molding sacrificial layer 112 may be disposed thereon. The additional molding sacrificial layer 112 comprises a material that is the same as or similar to that of the molding sacrificial layer 110. The additional molding sacrificial layer 112 may be formed by a single process (e.g., a deposition process) performed on the first stack S1 and the second stack S2. The additional molding sacrificial layer 112 may cover the exposed ends of the molding sacrificial layer 110. The additional molding sacrificial layer 112 may also cover the virtual vertical channel 450.

[0092] refer to Figure 5B For reference Figure 4C and Figure 4D The planarized dielectric layer 301 can be formed to cover the stepped structure 300, and the vertical channel 350 can be formed on the cell array region CAR. For example, an etching process can be performed to selectively remove the first sacrificial pillar 150 and the second sacrificial pillar 250 from the first vertical hole 130 and the second vertical hole 230, and then the vertical channel 350 can fill the empty first vertical hole 130 and the second vertical hole 230 where the first sacrificial pillar 150 and the second sacrificial pillar 250 have been removed.

[0093] refer to Figure 5C For reference Figure 4EThe molding sacrificial layer 110 can be selectively removed to form space 115. When space 115 is filled with a conductive material (e.g., tungsten) to form electrode 400, a stacked structure ST in which electrode 400 is disposed between molding dielectric layers 120 is obtained. When molding sacrificial layer 110 is removed, an additional molding sacrificial layer 112 can also be removed to extend the ends of space 115, thus the pads 405 of electrode 400 can have increased thickness.

[0094] refer to Figure 5D For reference Figure 4F After forming the interlayer dielectric layer 303, bit line contacts 530 may be formed to penetrate the interlayer dielectric layer 303 and be connected (e.g., electrically connected) to the pads 356 of the vertical channel 350, and metal contacts 550 may be formed to penetrate the interlayer dielectric layer 303 and the planarized dielectric layer 301 and be connected (e.g., electrically connected) to the pads 405 of the electrode 400. On the interlayer dielectric layer 303, bit lines 630 may be formed to be connected (e.g., electrically connected) to the bit line contacts 530, and metal lines 650 may be formed to be connected (e.g., electrically connected) to the metal contacts 550.

[0095] According to the present invention, although the number of stacked components formed on the semiconductor substrate is increased, a single step process can form a step structure. Since the step structure is formed by a single step process, the simplification of the process due to the reduction in the number of processes can reduce manufacturing costs.

[0096] The advantages of the inventive concept compared to the prior art will become apparent from the appended claims and the description with reference to the accompanying drawings. The inventive concept is expressly claimed and specifically pointed out in the claims. However, the inventive concept can be best understood by referring to this description in conjunction with the accompanying drawings. Throughout the description, the same reference numerals denote the same components.

[0097] This specific embodiment of the inventive concept should not be construed as limited to the embodiments set forth herein, and is intended to cover various combinations, modifications, and variations of the invention without departing from the spirit and scope of the inventive concept. The appended claims should be interpreted to include other embodiments.

Claims

1. An integrated circuit device, comprising: The substrate includes a cell region and an extension region arranged in a horizontal direction; Multiple conductive layers are stacked on the unit region in a vertical direction perpendicular to the horizontal direction, wherein the multiple conductive layers extend into the extended region and have a stepped structure in the extended region; and A plurality of vertical structures are located on the substrate, wherein each of the plurality of vertical structures extends in the vertical direction, and the plurality of vertical structures includes a first vertical structure on the unit region and a second and a third vertical structure on the extended region. The first vertical structure extends through the plurality of conductive layers and includes a first channel layer. The second vertical structure comprises an upper part and a lower part, the upper part comprising a second channel layer, and the lower part comprising a first passive pillar, the lower part being located between the substrate and the upper part. The third vertical structure is a second passive pillar extending through the stepped structure of the plurality of conductive layers. The second passive pillar is spaced apart from the first passive pillar in the horizontal direction and both have a dielectric structure. Each of the first passive column and the second passive column has an overall structure in which there is no interface, the uppermost end of the first passive column is higher than the uppermost end of the second passive column, and the height of the first passive column is greater than the height of the second passive column.

2. The integrated circuit device according to claim 1, wherein, The first channel layer is in direct contact with the substrate.

3. The integrated circuit device according to claim 1, wherein, The first passive column of the second vertical structure has an integral structure including insulating material.

4. The integrated circuit device according to claim 1, wherein, The plurality of vertical structures also includes a fourth vertical structure on the extended region. The fourth vertical structure overlaps with the second passive column of the third vertical structure and is spaced apart from the second passive column of the third vertical structure in the vertical direction.

5. The integrated circuit device according to claim 4, wherein, The first channel layer of the first vertical structure, the second channel layer of the second vertical structure, and the fourth vertical structure are arranged sequentially along the horizontal direction, and Wherein, the lowermost end of the second channel layer of the second vertical structure is at the first level, and the uppermost end of the second passive column of the third vertical structure is at the second level, which is lower than the first level.

6. The integrated circuit device according to claim 4, wherein, The fourth vertical structure includes a third channel layer, and The third channel layer is spaced apart from the stepped structure of the plurality of conductive layers in the vertical direction.

7. The integrated circuit device according to claim 4, wherein, The fourth vertical structure includes a third channel layer spaced apart from the substrate in the vertical direction, and The lowest point of the second channel layer is at a first level, and the lowest point of the third channel layer is at a second level, which is lower than the first level.

8. The integrated circuit device according to claim 7, wherein, The uppermost point of the second channel layer and the uppermost point of the third channel layer are at the same level.

9. The integrated circuit device according to claim 7, wherein, The third vertical structure has an integral structure including insulating material.

10. The integrated circuit device according to claim 1, wherein, The upper and lower parts of the second vertical structure are in direct contact with each other, and Wherein, the lowermost end of the upper part of the second vertical structure has a first width in the horizontal direction, and the uppermost end of the lower part of the second vertical structure has a second width in the horizontal direction, wherein the second width is wider than the first width, and The lowest end of the second channel layer directly contacts the highest end of the lower part of the second vertical structure.

11. An integrated circuit device, comprising: A substrate comprising a first region and a second region arranged in a horizontal direction; A stacked structure located on the substrate, wherein the stacked structure includes a plurality of conductive layers stacked on a first region of the substrate in a vertical direction perpendicular to the horizontal direction, and wherein the plurality of conductive layers extend to a second region of the substrate and have a stepped structure on the second region of the substrate; Multiple vertical structures are located on the substrate, wherein each of the multiple vertical structures extends in the vertical direction, and The plurality of vertical structures include: A first vertical structure is located on the first region of the substrate and extends through the plurality of conductive layers; A second vertical structure, located on the second region of the substrate, includes a first passive pillar of the stepped structure extending through the plurality of conductive layers; and A third vertical structure, located on the second region of the substrate, is a second passive pillar extending through the stepped structure of the plurality of conductive layers. The second passive pillar is spaced apart from the first passive pillar in the horizontal direction and both have a dielectric structure. Each of the first passive column and the second passive column has an overall structure in which there is no interface, the uppermost end of the first passive column is higher than the uppermost end of the second passive column, and the height of the first passive column is greater than the height of the second passive column.

12. The integrated circuit device according to claim 11, wherein, The first vertical structure includes a first channel layer that directly contacts the substrate, and The second vertical structure further includes a second channel layer spaced apart from the substrate in the vertical direction.

13. The integrated circuit device according to claim 12, wherein, The uppermost point of the first channel layer and the uppermost point of the second channel layer are at the same level.

14. The integrated circuit device according to claim 11, wherein, The plurality of vertical structures also includes a fourth vertical structure that overlaps with the third vertical structure in the vertical direction. The first vertical structure, the second vertical structure, and the fourth vertical structure are arranged sequentially along the horizontal direction, and The fourth vertical structure is spaced apart from the third vertical structure.

15. The integrated circuit device according to claim 11, wherein, The first passive column of the second vertical structure has an integral structure including a first insulating material.

16. The integrated circuit device according to claim 15, wherein, The second passive post has an integral structure including a second insulating material.

17. An integrated circuit device, comprising: The substrate includes a cell region and an extension region arranged in a horizontal direction; A stacked structure located on the substrate, wherein the stacked structure comprises a plurality of conductive layers stacked on the cell region in a vertical direction perpendicular to the horizontal direction, and wherein the plurality of conductive layers extend onto the extended region and have a stepped structure on the extended region; and A plurality of vertical structures are located on the substrate, wherein the plurality of vertical structures include: A first vertical structure extending through the plurality of conductive layers on the unit region, A second vertical structure extending through the stepped structure of the plurality of conductive layers, wherein the second vertical structure comprises a lower portion and an upper portion sequentially stacked on the substrate, the lower portion of the second vertical structure comprising a first passive pillar. A third vertical structure extending through the stepped structure of the plurality of conductive layers, the third vertical structure being a second passive pillar, the second passive pillar being spaced apart from the first passive pillar in the horizontal direction and both having a dielectric structure. Each of the first passive column and the second passive column has an overall structure in which there is no interface, the uppermost end of the first passive column is higher than the uppermost end of the second passive column, and the height of the first passive column is greater than the height of the second passive column.

18. The integrated circuit device according to claim 17, wherein, The first vertical structure includes a first channel layer, and The upper part of the second vertical structure includes a second channel layer spaced apart from the substrate.

19. The integrated circuit device according to claim 18, wherein, The first passive column of the second vertical structure has an integral structure including insulating material.

20. The integrated circuit device according to claim 17, wherein, The first vertical structure includes a first channel layer, and the lowermost end of the first channel layer is at a first horizontal level. The second vertical structure includes a second channel layer, and the lowest end of the second channel layer is at a second level higher than the first level.

21. The integrated circuit device according to claim 20, wherein, The first channel layer is in direct contact with the substrate.

22. The integrated circuit device according to claim 20, wherein, The uppermost point of the first channel layer and the uppermost point of the second channel layer are at the same level.

23. The integrated circuit device according to claim 17, wherein, The lowermost end of the upper part of the second vertical structure has a first width in the horizontal direction, and the uppermost end of the lower part of the second vertical structure has a second width in the horizontal direction, and the second width is greater than the first width.

24. The integrated circuit device according to claim 17, wherein, The upper part and the lower part of the second vertical structure are formed by different processes.

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