Semiconductor device and semiconductor device manufacturing method

Abstract

The present disclosure provides a semiconductor device and a method for manufacturing the semiconductor device, which belongs to the field of semiconductor technology. The device includes: a semiconductor substrate; at least one groove located in the semiconductor substrate; a lining layer covering the inner wall of the groove and having a porous structure; an isolation material deposited on the top of the lining layer, filling the groove, and diffusing into the pores of the lining layer. The trench isolation structure of the semiconductor device disclosed in the present disclosure has lower internal stress, improves the performance and reliability of the semiconductor device, is easy to implement in terms of process, and has strong applicability.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] The information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

[0003] In semiconductor manufacturing processes, it is often necessary to form a trench filling structure. For example, in a shallow trench isolation structure, an oxide is filled in the trench to form isolation between active regions of various devices.

[0004] With the reduction of semiconductor feature size, the increase of trench aspect ratio, and the improvement of requirements for trench profiles, the traditional chemical vapor deposition (CVD) process has been unable to perform the task of trench filling. Currently, spin-on dielectric layer (SOD) or fluid chemical vapor deposition (FCVD) processes are more commonly used to deposit flowable fillers in the trenches, and then solidify the fillers through heat treatment processes such as annealing to achieve complete filling of the trenches. Summary of the invention

[0005] The existing trench filling process requires heat treatment after filling. Due to the change of the structure or composition of the trench filler during heat treatment, it usually causes volume expansion and generates large internal stress, thereby reducing the reliability of the semiconductor device. In severe cases, it may cause Figure 1 As shown in the top view of FIG. 1 , the internal stress of the filler causes the surrounding active area 1 to shift, affecting the performance of the semiconductor device.

[0006] The purpose of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device, thereby overcoming the problem of high stress in the trenches of existing semiconductor devices at least to a certain extent.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0008] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; at least one groove located in the semiconductor substrate; a lining layer covering the inner wall of the groove and having a porous structure; and an isolation material deposited above the lining layer, filling the groove and diffusing into the pores of the lining layer.

[0009] In an exemplary embodiment of the present disclosure, the thickness of the lining layer is 2% to 10% of the width of the groove.

[0010] In an exemplary embodiment of the present disclosure, the porosity of the lining layer is 10% to 80%.

[0011] In an exemplary embodiment of the present disclosure, the material of the lining layer includes a dielectric material.

[0012] In an exemplary embodiment of the present disclosure, the dielectric material includes at least one of silicon, silicon monoxide, silicon nitride, boron nitride, silicon oxynitride, silicon carbon nitride ceramics, polynitrogen silane, fluorosilicate glass (FSG), borosilicate glass (BSG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), and hafnium dioxide.

[0013] In an exemplary embodiment of the present disclosure, the isolation material includes silicon oxide or silicon oxynitride.

[0014] In an exemplary embodiment of the present disclosure, the semiconductor device further includes: a pad oxide layer (Padoxide), located on the upper surface of the semiconductor substrate on both sides of the groove; a pad nitride layer (Pad nitride), located on the upper surface of the pad oxide layer; and the lining layer covers the upper surface of the pad nitride layer.

[0015] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: etching a groove on a semiconductor substrate; depositing a lining layer with a porous structure on an inner wall of the groove; depositing an isolation material above the lining layer to fill the groove; and heat treating the isolation material.

[0016] In an exemplary embodiment of the present disclosure, the depositing of the lining layer with a porous structure on the inner wall of the groove comprises: depositing the lining layer on the inner wall of the groove by chemical vapor deposition; treating the lining layer by freeze drying or supercritical drying to form the porous structure of the lining layer; wherein the precursor of the chemical vapor deposition comprises tetraethyl orthosilicate (TEOS), silane (SiH 4 ), tetramethylsilane (TMS), cage-type polysilsesquioxane (POSS), the chemical vapor deposition solvent includes deionized water (DI), hydrochloric acid (HCl), ammonia (NH 3 ·H 2 O), isopropyl alcohol (IPA), ethanol (ET) at least one; the freeze-drying conditions are -150 to -50°C, 20 to 100 Torr; the supercritical drying conditions are 40 to 200°C, 5 to 10 MPa.

[0017] In an exemplary embodiment of the present disclosure, depositing the isolation material on the liner layer includes: depositing the isolation material on the liner layer by spin coating a dielectric layer or fluid chemical vapor deposition.

[0018] The exemplary embodiments of the present disclosure have the following beneficial effects:

[0019] A lining layer with a porous structure is provided in the groove of the semiconductor device to separate the direct contact between the isolation material and the inner wall of the groove. When the isolation material expands in volume during heat treatment and other post-processes, it can diffuse into the pores of the lining layer. On the one hand, the volume expansion of the isolation material is released into the pores of the lining layer, which reduces the internal stress of the isolation material, improves the undesirable conditions such as groove cracking or active area displacement that may be caused by its large internal stress, and improves the performance and reliability of the semiconductor device. On the other hand, the structure of the lining layer added in this exemplary embodiment is relatively simple, easy to implement in terms of process, and has strong applicability.

[0020] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0022] Figure 1 A schematic diagram showing displacement of an active region in a conventional semiconductor device;

[0023] Figure 2 A schematic cross-sectional view of a semiconductor device in this exemplary embodiment is shown;

[0024] Figure 3 A schematic cross-sectional view showing another semiconductor device in this exemplary embodiment;

[0025] Figure 4 A flowchart showing a method for manufacturing a semiconductor device in this exemplary embodiment;

[0026] Figures 5 to 8 A schematic flow chart showing a method for manufacturing a semiconductor device in this exemplary embodiment is shown. DETAILED DESCRIPTION

[0027] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0028] An exemplary embodiment of the present disclosure first provides a semiconductor device, Figure 2 FIG. 4 shows a cross-sectional side view of the semiconductor device. Figure 2 As shown, the semiconductor device may include a semiconductor substrate 101, at least one trench 102 ( Figure 2 Two trenches 102 ), a lining layer 103 and an isolation material 104 are shown. The trench 102 is located in the semiconductor substrate 101 ; the lining layer 103 covers the inner wall of the trench 102 and is a porous structure with many pores; the isolation material 104 is deposited on the lining layer 103 , fills the trench 102 , and diffuses into the pores of the lining layer 103 .

[0029] The semiconductor substrate 101 may be a silicon substrate or a device structure with an active region formed therein. For example, the semiconductor substrate 101 may be a p-type silicon substrate or an n-type silicon substrate, or a substrate including a source electrode and a drain electrode. The cross section of the groove 102 may be an inverted trapezoid with a large opening and a small bottom, or a rectangle. When a plurality of grooves 102 are provided, the grooves 102 may be separated from each other. For example, the grooves 102 may be provided between the active regions, and the grooves 102 are used to isolate the active regions without contacting each other. The liner layer 103 may extend from the inner surface of the substrate 103 to the inner surface of the substrate 103. The isolating material 104 is filled in the groove 102, and the top of the isolating material 104 may be convex, flat or concave. The isolating material 104 may also extend to the upper surface of the semiconductor substrate 101 to form an isolating layer above the semiconductor substrate 101. The isolating material 104 is separated from the groove 102 by the lining layer 103. Since the lining layer 103 is a porous structure, the isolating material 104 may diffuse into the pores of the lining layer 103 during heat treatment or other subsequent processes if the volume expands, thereby reducing the internal stress.

[0030] Based on the above description, in this exemplary embodiment, a lining layer with a porous structure is provided in the groove of the semiconductor device to separate the direct contact between the isolation material and the inner wall of the groove. When the isolation material expands in volume during heat treatment and other post-processes, it can diffuse into the pores of the lining layer. On the one hand, the volume expansion of the isolation material is released into the pores of the lining layer, which reduces the internal stress of the isolation material, improves the undesirable conditions such as groove cracking or active area displacement that may be caused by its high internal stress, and improves the performance and reliability of the semiconductor device. On the other hand, the structure of the lining layer added in this exemplary embodiment is relatively simple, easy to implement in terms of process, and has strong applicability.

[0031] In an exemplary embodiment, the thickness of the lining layer 103 can be 2% to 10% of the width of the groove 102. The lining layer 103 at this width is easier to obtain, and the components of the lining layer 103 form a sidewall film on the inner wall of the groove 102. The thickness of the film is relatively low, which is conducive to the lining layer 103 forming a film with uniform thickness. On the other hand, at this width, the pores inside the lining layer 103 can better accommodate the diffused portion of the isolation material 104, and will not occupy too much of the filling space of the isolation material 104, affecting the normal filling structure of the isolation material 104.

[0032] In an exemplary embodiment, the porosity of the lining layer 103 may be 10% to 80%. Porosity refers to the percentage of the volume of all pores in the lining layer 103 to the total volume of the lining layer 103. The two parameters of the porosity and thickness of the lining layer 103 may determine the filling effect of the lining layer 103 after the isolation material 104 diffuses. Ideally, after the isolation material 104 is deposited and heat treated, the pores of the lining layer 103 can effectively accommodate the diffusion of the isolation material 104, forming a dense trench filling structure without generating additional internal stress. Therefore, the porosity of 10% to 80% and the thickness of the lining layer 103 of 2% to 10% of the width of the trench 102 may achieve a better coordination effect. When the thickness of the lining layer 103 is small, its porosity may be appropriately increased, and vice versa, its porosity may be appropriately reduced to obtain a dense trench filling structure.

[0033] Since the function of the isolation material 104 is usually to isolate the active areas of the devices on both sides, in an exemplary embodiment, the material of the liner layer 103 can be a dielectric material to cooperate with the isolation material 104 to play an isolation role, which can further improve the isolation effect of the trench filling structure of the semiconductor device and improve the performance of the semiconductor device.

[0034] Furthermore, the dielectric material may be one of silicon, silicon monoxide, silicon nitride, boron nitride, silicon oxynitride, silicon carbon nitride ceramics, polynitrogen silane, fluorosilicate glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, hafnium dioxide, or a dielectric material formed by a composite of multiple materials thereof. The above materials are all commonly used dielectric materials in semiconductor processes and can form a porous structure.

[0035] In an exemplary embodiment, the isolation material 104 may include silicon oxide or silicon oxynitride, such as SiO, SiO 2 、SiON、Si 2 N 2 O, etc., has a good isolation effect.

[0036] In an exemplary embodiment, reference Figure 3 As shown, the semiconductor device may also include a pad oxide layer 105 and a pad nitride layer 106, wherein the pad oxide layer 105 is deposited on the upper surface of the semiconductor substrate 101 on both sides of the groove 102, the pad nitride layer 106 is deposited on the upper surface of the pad oxide layer 105, the liner layer 103 may also cover the upper surface of the pad nitride layer 106, and the isolation material 104 may also be deposited on top of the entire liner layer 103 to form an isolation layer on the upper layer of the entire semiconductor device.

[0037] The pad oxide layer 105 and the pad nitride layer 106 protect the underlying structure, especially the corners on both sides of the top of the trench 102 from being damaged in subsequent etching processes, so that the isolation material 104 can normally isolate the active areas without generating leakage current.

[0038] based on Figure 3 In the structure, in an exemplary embodiment, the trench 102, the liner layer 103 and the isolation material 104 can form a shallow trench isolation (STI) to isolate the silicon substrate or active area on both sides of the trench 102. Since the structure combined with the liner layer 103 and the isolation material 104 can densely fill the trench 102 and has low internal stress, the shallow trench isolation of this embodiment has low leakage current and good isolation characteristics.

[0039] The exemplary embodiments of the present disclosure also provide a method for manufacturing a semiconductor device, referring to Figure 4 As shown, the method may include the following steps S110 to S140:

[0040] Step S110, reference Figure 5 , a trench 102 is etched on the semiconductor substrate 101.

[0041] Step S120, reference Figure 6 , a lining layer 103 with a porous structure is deposited on the inner wall of the groove 102 .

[0042] The deposition method for forming the porous structure may include chemical vapor deposition, sol-gel method, etc. In an exemplary embodiment, step S120 may be implemented by the following steps:

[0043] A liner layer 103 is deposited on the inner wall of the trench 102 by chemical vapor deposition.

[0044] The lining layer 103 is processed by freeze drying or supercritical drying to form a porous structure of the lining layer 103 .

[0045] Among them, the precursors for chemical vapor deposition may include TEOS, SiH 4 , TMS, POSS, the solvent of chemical vapor deposition may include DI, HCl, NH 3 ·H 2 At least one of O, IPA, and ET; the freeze-drying conditions may be: -150 to -50°C, 20 to 100 Torr; the supercritical drying conditions may be: 40 to 200°C, 5 to 10 MPa.

[0046] The above-mentioned solvent is an inorganic solvent or an organic small molecule solvent, and its molecular volume is significantly smaller than the molecular volume of the above-mentioned various precursors. In the process of chemical vapor deposition of precursors and solvents, the precursor molecules are coated by solvent molecules, so the lining layer 103 formed on the inner wall of the groove 102 can be an unstable state with a colloidal network structure, wherein the precursor molecules are connected to form a network skeleton, and the solvent molecules are in the network skeleton. In freeze drying or supercritical drying, after the solvent molecules in the colloidal network are converted into gas and removed, only the precursor molecules of the network skeleton remain in the lining layer 103, and the network structure is retained, so a large number of pores are left at the positions where the original solvent molecules are located, thereby forming a porous structure of the lining layer 103.

[0047] The principle of freeze drying is to solidify the solvent under low temperature conditions, and then reduce the pressure (or increase the temperature to a certain extent at the same time) to sublime the solid solvent molecules. 3 ·H 2Among O, IPA and ET, HCl and ET have the lowest melting points, which are -114°C. These two solvents can solidify quickly under -150°C. When other solvents or mixed solvents are used, the freeze-drying process temperature can be adjusted according to the melting point of the solvent used. In the sublimation stage, the lower the temperature, the lower the required pressure. If the temperature is not raised to a certain level, the solvent sublimates and absorbs heat, causing the local temperature of the lining layer 103 to drop, and the subsequent sublimation rate will slow down; when the temperature is raised, in order to prevent the solid solvent from melting, the maximum temperature can be no more than -50°C. For the above solvents, the conditions of 20 to 100 Torr are sufficient to sublime them. The most suitable process pressure can be selected according to the solid saturated vapor pressure curve of each solvent. In practical applications, the decompression rate can also be increased to reduce the heat absorbed from the inside of the lining layer 103 when the solvent molecules sublimate, which can increase the sublimation rate and improve the quality of the porous structure finally obtained.

[0048] The principle of supercritical drying is to control the pressure and temperature so that the solvent reaches its own critical point during the drying process and completes the supercritical transition from liquid to gas. During this process, the solvent does not produce obvious surface tension, and the transition from wet gel to aerogel can be completed while maintaining the network skeleton structure. In supercritical drying, it is necessary to select a suitable drying medium. The process temperature and pressure requirements of carbon dioxide as a drying medium are relatively low, and the solvent to be dried in this embodiment does not include carbon dioxide. Therefore, carbon dioxide can be used as a drying medium. The corresponding process conditions are 40-200°C and 5-10Mpa. The most suitable parameters can be selected within the process conditions according to the different types of solvents.

[0049] It should be noted that most of the above precursors are silicide molecules. After removing the sol molecules and performing subsequent heat treatment, most of the precursors can be converted into silicon oxide, silicon hydroxide, silicon carbide, silicon carbon hydride, etc., which are more suitable dielectric materials.

[0050] Step S130, reference Figure 7 , an isolation material 104 is deposited over the liner layer 103 to fill the trench 102 .

[0051] The isolation material 104 may extend to the upper surface of the semiconductor substrate 101 to form an isolation layer above the semiconductor substrate 101. In semiconductor manufacturing, chemical vapor deposition is a commonly used deposition process. In this embodiment, step S130 may be implemented by chemical vapor deposition, for example, using TEOS and O 2 The isolation material 104 mainly composed of silicon oxide is deposited as a raw material gas. Specifically, a mask layer can be formed first to reserve a deposition area for the isolation material 104, such as the location of the trench 102, and then the isolation material 104 is deposited using a chemical vapor deposition process, and then the mask layer is removed.

[0052] Furthermore, the deposition of the isolation material on the liner layer can be achieved by the following steps: the isolation material is deposited on the liner layer by spin coating the dielectric layer or fluid chemical vapor deposition. The deposits obtained by spin coating the dielectric layer or fluid chemical vapor deposition have fluidity and can better fill the trenches, especially the trenches with a large depth-to-width ratio, thereby improving the trench profile quality of the semiconductor device and reducing the leakage current that may be generated in the trench isolation part.

[0053] Step S140, reference Figure 8 , the isolation material 104 is heat treated.

[0054] The purpose of the heat treatment is to change the composition or structure of the deposited isolation material 104 so as to achieve an isolation effect. During the heat treatment, the isolation material 104 will diffuse into the pores of the lining layer 103 due to the change in volume.

[0055] In the above semiconductor device embodiment, the thickness of the liner layer 103 can be 2% to 10% of the width of the trench 102, and the porosity of the liner layer 103 can be 10% to 80%. Selecting appropriate size parameters of the liner layer 103 within this range can allow the pores of the liner layer 103 to effectively accommodate the diffusion of the isolation material 104. In practical applications, the thickness or porosity of the liner layer 103 can be slightly reduced under critical parameter conditions to preferentially ensure that the isolation material 104 fills the pores and prevents leakage current.

[0056] In an exemplary embodiment, in order to further improve the isolation property of the isolation material, the isolation material 104 may be made of the same material as the lining layer 103. For example, the lining layer 103 may be made of SiO 2 When SiO 2 The isolation material 104, after the isolation material 104 diffuses into the lining layer 103, the two-layer structure can be converted into a one-layer structure, thereby reducing defects on the interface between the isolation material 104 and the lining layer 103 and achieving a better isolation effect.

[0057] Based on the above method, a lining layer with a porous structure is first formed in the groove of the semiconductor device, and then an isolation material is deposited so that the isolation material can diffuse into the pores of the lining layer during heat treatment to reduce the internal stress caused by volume expansion and form a high-quality semiconductor trench isolation structure, thereby improving the performance and reliability of the semiconductor device. The manufacturing process is relatively simple, the process is easy to implement, and the applicability is strong.

[0058] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0059] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate is a silicon substrate; at least one trench located in the semiconductor substrate; A lining layer, covering the inner wall of the groove and having a porous structure; an isolation material deposited over the liner layer, filling the trenches, and diffusing into the pores of the liner layer; The thickness of the lining layer is 2% to 10% of the width of the groove.

2. The semiconductor device according to claim 1, wherein: The porosity of the lining layer is 10% to 80%.

3. The semiconductor device according to claim 1, wherein: The material of the lining layer includes a dielectric material.

4. The semiconductor device according to claim 3, characterized in that The dielectric material includes at least one of silicon, silicon monoxide, silicon nitride, boron nitride, silicon oxynitride, silicon carbon nitride ceramics, polynitrogen silane, fluorosilicate glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, and hafnium dioxide.

5. The semiconductor device according to claim 1, wherein: The isolation material includes silicon oxide or silicon oxynitride.

6. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A pad oxide layer is located on the upper surface of the semiconductor substrate at both sides of the trench; A pad nitride layer, located on the upper surface of the pad oxide layer; The liner layer covers an upper surface of the pad nitride layer.

7. A method for manufacturing a semiconductor device, characterized in that: include: etching a groove in a semiconductor substrate; Depositing a lining layer with a porous structure on the inner wall of the groove; depositing an isolation material over the liner layer to fill the trench; The insulating material diffuses into the pores of the lining layer; heat treating the insulating material; Depositing a lining layer with a porous structure on the inner wall of the groove comprises: Depositing the lining layer on the inner wall of the trench by chemical vapor deposition; The lining layer is treated by freeze drying or supercritical drying to form a porous structure of the lining layer; Among them, the precursor of the chemical vapor deposition includes at least one of tetraethyl orthosilicate, silane, tetramethylsilane, and cage-type polysilsesquioxane, and the solvent of the chemical vapor deposition includes at least one of deionized water, hydrochloric acid, ammonia water, isopropanol, and ethanol; the conditions of the freeze-drying are -150 to -50°C and 20 to 100 Torr; the conditions of the supercritical drying are 40 to 200°C and 5 to 10 MPa.

8. The method according to claim 7, characterized in that Depositing an isolation material above the liner layer comprises: An isolation material is deposited over the liner layer by spin-on dielectric layer or fluid chemical vapor deposition.

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