Dual battery selection circuit and electronic device

Abstract

The present invention discloses a dual battery selection circuit, which relates to the technical field of electronic circuits. The dual battery selection circuit includes a dual-way switch, a first fast-closing and slow-opening circuit, and a second fast-closing and slow-opening circuit. The dual-way switch has two input terminals and two output terminals. The two input terminals are connected to a main battery power supply, a backup battery power supply, and a battery switching signal through a logic circuit; the two output terminals output a first enable signal and a second enable signal respectively; the main battery power supply is connected to a common output terminal through a first fast-closing and slow-opening circuit, and a first enable signal is connected to the enable terminal of the first fast-closing and slow-opening circuit; the backup battery power supply is connected to a common output terminal through a second fast-closing and slow-opening circuit, and a second enable signal is connected to the enable terminal of the second fast-closing and slow-opening circuit. An embodiment of the present invention also discloses an electronic device including the dual battery selection circuit. The embodiment of the present invention realizes intelligent switching of dual batteries through the matching structure of the fast-closing and slow-opening circuit and the dual-way switch.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of electronic circuits, and in particular to a dual-battery selection circuit and an electronic device. Background Art

[0002] Existing smart devices all have built-in rechargeable batteries. As the functions of smart devices become more and more powerful, the power of their rechargeable batteries is gradually increased to improve battery life. In fact, the situation where a single battery affects normal work, study or games often occurs. Therefore, this situation can be avoided to a large extent in the case of dual batteries. However, the switching of the existing dual battery power supply mode is not smart enough, and it is easy to cause power outages during switching. Summary of the invention

[0003] In order to overcome the deficiencies of the prior art, the present invention aims to provide a dual-battery selection circuit and an electronic device, which realize intelligent switching of dual batteries through a fast-closing and slow-opening circuit and a coordinated structure of a dual-way switch.

[0004] In a first aspect, an embodiment of the present invention provides a dual battery selection circuit, which is used to select the output of a main battery power supply or a backup battery power supply, and comprises: a dual-way switch, a first fast-off-slow-opening circuit and a second fast-off-slow-opening circuit, wherein the dual-way switch has two input terminals and two output terminals corresponding to the two input terminals one by one, and the two input terminals are connected to the main battery power supply, the backup battery power supply and the battery switching signal through a logic circuit; the two output terminals respectively output a first enable signal and a second enable signal; the main battery power supply is connected to the common output terminal of the dual battery selection circuit through the first fast-off-slow-opening circuit, and the first enable signal is connected to the enable terminal of the first fast-off-slow-opening circuit to control the output of the main battery power supply; the backup battery power supply is connected to the common output terminal through the second fast-off-slow-opening circuit, and the second enable signal is connected to the enable terminal of the second fast-off-slow-opening circuit to control the output of the backup battery power supply.

[0005] In a preferred embodiment, the two input terminals are respectively a first input terminal and a second input terminal, and the two output terminals are respectively a first output terminal corresponding to the first input terminal and a second output terminal corresponding to the second input terminal; the first input terminal and the second input terminal are connected to the main battery power supply, the backup battery power supply and the battery switching signal through a logic circuit; the first output terminal outputs a first enable signal, and the second output terminal outputs a second enable signal.

[0006] In a preferred embodiment, the logic circuit includes an auxiliary power supply, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, an NMOS tube Q11, an NMOS tube Q12, an NMOS tube Q13, and an NMOS tube Q14. The output end of the auxiliary power supply is connected to the first input end through the resistor R15, and the output end of the auxiliary power supply is connected to the second input end through the resistor R16; the drain of the NMOS tube Q11, the gate of the NMOS tube Q12, and the drain of the NMOS tube Q13 are all connected to the first input end. The drain of the NMOS tube Q12 is connected to the second input terminal, and the gate of the NMOS tube Q11 is connected to the battery switching signal through the resistor R17; the gate of the NMOS tube Q13 is connected to the backup battery power supply through the resistor R18; the gate of the NMOS tube Q14 is connected to the main battery power supply through the resistor R19, and the drain of the NMOS tube Q14 is connected to the gate of the NMOS tube Q13; the source of the NMOS tube Q11, the source of the NMOS tube Q12, the source of the NMOS tube Q13 and the source of the NMOS tube Q14 are all grounded.

[0007] In a preferred embodiment, the first fast-off and slow-on circuit comprises an NMOS tube Q15, an NMOS tube Q5, a PMOS tube Q1, a PMOS tube Q2, an NPN transistor Q3, a PNP transistor Q4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, and a resistor R7; the gate of the NMOS tube Q15 and the gate of the NMOS tube Q5 are both connected to the first enable signal, and the source of the NMOS tube Q15 and the source of the NMOS tube Q5 are both grounded; the drain of the NMOS tube Q15 is connected to the main battery power supply through the resistor R1; the drain of the PMOS tube Q1 is connected to the main battery power supply, the source of the PMOS tube Q1 is connected to the source of the PMOS tube Q2, and the drain of the PMOS tube Q2 is connected to the common output terminal; the drain of the NMOS tube Q5 is connected to the between the source of the PMOS tube Q1 and the source of the PMOS tube Q2; the gate of the PMOS tube Q1 and the gate of the PMOS tube Q2 are both connected to between the resistor R6 and the resistor R7; the base of the NPN transistor Q3 is connected to between the resistor R1 and the drain of the NMOS tube Q15 through the resistor R2, the base of the NPN transistor Q3 is connected to the emitter of the NPN transistor Q3 through the resistor R3, and the emitter of the NPN transistor Q3 is grounded; the collector of the NPN transistor Q3 is connected to the base of the PNP transistor Q4 through the resistor R4, the base of the PNP transistor Q4 and the emitter of the PNP transistor Q4 are connected with a resistor R5, the emitter of the PNP transistor Q4 is also connected to between the source of the PMOS tube Q1 and the source of the PMOS tube Q2, and the collector of the PNP transistor Q4 is connected to between the resistor R6 and the resistor R7.

[0008] In a preferred embodiment, the second fast-off and slow-on circuit comprises an NMOS transistor Q16, an NMOS transistor Q10, a PMOS transistor Q6, a PMOS transistor Q7, an NPN transistor Q8, a PNP transistor Q9, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, and a resistor R14; the gate of the NMOS transistor Q16 and the gate of the NMOS transistor Q10 are both connected to the second enable signal, and the source of the NMOS transistor Q16 and the source of the NMOS transistor Q10 are both grounded; the drain of the NMOS transistor Q16 is connected to the backup battery power supply through the resistor R8; the drain of the PMOS transistor Q6 is connected to the backup battery power supply, the source of the PMOS transistor Q6 is connected to the source of the PMOS transistor Q7, and the drain of the PMOS transistor Q7 is connected to the common output terminal; the drain of the NMOS transistor Q10 is connected to the backup battery power supply through the resistor R14 and the resistor R13 in sequence. The gate of the PMOS tube Q6 and the gate of the PMOS tube Q7 are both connected between the resistor R13 and the resistor R14; the base of the NPN transistor Q8 is connected between the resistor R8 and the drain of the NMOS tube Q16 through the resistor R9, the base of the NPN transistor Q8 is connected to the emitter of the NPN transistor Q8 through the resistor R10, and the emitter of the NPN transistor Q8 is grounded; the collector of the NPN transistor Q8 is connected to the base of the PNP transistor Q9 through the resistor R11, the base of the PNP transistor Q9 and the emitter of the PNP transistor Q9 are connected with a resistor R12, the emitter of the PNP transistor Q9 is also connected between the source of the PMOS tube Q6 and the source of the PMOS tube Q7, and the collector of the PNP transistor Q9 is connected between the resistor R13 and the resistor R14.

[0009] In a preferred embodiment, the battery switching signal is generated by the EC or the AP;

[0010] When there is no charger to charge the main battery power supply and the backup battery power supply, if the power of the main battery power supply is greater than the first preset threshold, the battery switching signal is at a low level; if the power of the main battery power supply is less than the first preset threshold and the power of the backup battery power supply is greater than the second preset threshold, the battery switching signal is at a high level.

[0011] In a preferred embodiment, when a charger is present, then:

[0012] When the main battery power source is in place and the power level of the main battery power source is less than a third preset threshold, the battery switching signal controls the charger to charge the main battery power source;

[0013] When the backup battery power supply is in place and any of the following conditions are met, the battery switching signal controls the charger to charge the backup battery power supply:

[0014] Condition 1: The main battery power source is not in place, and the backup battery power source is less than a fourth preset threshold;

[0015] Condition 2: The power level of the main battery power source is greater than or equal to the third preset threshold, and the power level of the backup battery power source is less than the fourth preset threshold.

[0016] In a second aspect, an embodiment of the present invention provides an electronic device, which includes the dual battery selection circuit described in the first aspect of the present invention.

[0017] Compared with the prior art, the embodiment of the present invention realizes intelligent switching of dual batteries through the coordination structure of a fast-closing and slow-opening circuit and a dual-way switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a circuit schematic diagram of a dual-way switch of Example 1;

[0019] Figure 2 A schematic diagram of a circuit for supplying power to the main battery power supply of Example 1;

[0020] Figure 3 A schematic diagram of a circuit for supplying power to the backup battery power supply of Example 1.

[0021] Specific embodiment

[0022] Below, in conjunction with the accompanying drawings and specific embodiments, the embodiments of the present invention are further described. It should be noted that, under the premise of no conflict, the embodiments or technical features described below can be arbitrarily combined to form a new embodiment. Unless otherwise specified, the materials and equipment used in this embodiment can be purchased from the market.

[0023] Embodiment 1:

[0024] Please refer to Figure 1-3As shown, a dual battery selection circuit is used to select the output of a main battery power supply (VBATT_M) or a backup battery power supply (VBATT_SEC), which includes: a dual-way switch, a first fast-off slow-opening circuit and a second fast-off slow-opening circuit, the dual-way switch has two input terminals and two output terminals corresponding to the two input terminals one by one, the two input terminals are connected to the main battery power supply, the backup battery power supply and the battery switching signal (BATT_SW) through a logic circuit; the two output terminals output a first enable signal (VBATT_M) and a second enable signal (VBATT_SEC) respectively; the main battery power supply is connected to the common output terminal of the dual battery selection circuit through the first fast-off slow-opening circuit, the first enable signal is connected to the enable terminal of the first fast-off slow-opening circuit, and is used to control the output of the main battery power supply; the main battery power supply is connected to the common output terminal through the second fast-off slow-opening circuit, and the second enable signal is connected to the enable terminal of the second fast-off slow-opening circuit, and is used to control the output of the backup battery power supply.

[0025] The dual-way switch includes a dual-way selection chip U1, the two input terminals of which are respectively a first input terminal (1Z) and a second input terminal (2Z), and the two output terminals of which are respectively a first output terminal (1Y, whose level follows 1Z) corresponding to the first input terminal and a second output terminal (2Y, whose level follows 2Z) corresponding to the second input terminal. The first input terminal and the second input terminal are connected to the main battery power supply, the backup battery power supply and the battery switching signal through a logic circuit; the first output terminal outputs a first enable signal, and the second output terminal outputs a second enable signal.

[0026] The dual selection chip U1 also has enable pins (1E and 2E), which are active high and directly connected to the auxiliary power supply.

[0027] Please refer to Figure 1As shown, the logic circuit includes an auxiliary power supply (5V_VCC), a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, an NMOS tube Q11, an NMOS tube Q12, an NMOS tube Q13, and an NMOS tube Q14. The output end of the auxiliary power supply is connected to the first input end through the resistor R15, and the output end of the auxiliary power supply is connected to the second input end through the resistor R16; the drain of the NMOS tube Q11, the gate of the NMOS tube Q12, and the drain of the NMOS tube Q13 are all connected to the first input end. , the drain of the NMOS tube Q12 is connected to the second input terminal, the gate of the NMOS tube Q11 is connected to the battery switching signal through the resistor R17; the gate of the NMOS tube Q13 is connected to the backup battery power supply through the resistor R18; the gate of the NMOS tube Q14 is connected to the main battery power supply through the resistor R19, and the drain of the NMOS tube Q14 is connected to the gate of the NMOS tube Q13; the source of the NMOS tube Q11, the source of the NMOS tube Q12, the source of the NMOS tube Q13 and the source of the NMOS tube Q14 are all grounded.

[0028] The battery switching signal is generated by EC or AP. EC (Embed Controller) is widely used in laptops, tablets and various industrial computers. In laptops and tablets, it is also called KBC (Keyboard Controller). EC has a high status in the system. During the system startup process, EC controls the timing of most important signals. After booting up, EC controls the keyboard, indicator lights, fans, touchpads and other devices. In addition, EC also controls the system's standby, hibernation and other states; AP (Wireless Access Point) is a wireless access point that can receive battery power and generate a battery switching signal based on the battery power status.

[0029] When there is no charger to charge the main battery power supply and the backup battery power supply, if the power of the main battery power supply is greater than a first preset threshold value (for example, the first preset threshold value is set to 5% of the total power of the main battery power supply), the battery switching signal is a low level; if the power of the main battery power supply is less than the first preset threshold value and the power of the backup battery power supply is greater than the second preset threshold value (for example, the second preset threshold value is set to 5% of the total power of the backup battery power supply), the battery switching signal is a high level, that is, the battery switching signal defaults to a low level.

[0030] The working truth table of the first output terminal and the second output terminal is shown in Table 1:

[0031] Table 1. Truth table

[0032] VBATT_M VBATT_SEC BATT_SW 1Y 2Y 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 0 1 0 0 1 0 1

[0033] Taking the case where the main battery power is at a high level, the backup battery power is at a high level, and the battery switching signal is at a high level as an example, the main battery power is at a high level, so that the NMOS tube Q14 is turned on, thereby pulling down the voltage of the gate of the NMOS tube Q13, so that the NMOS tube Q13 is turned off, and the battery switching signal is at a high level, so that the NMOS tube Q11 is turned on, and the level of 1Z is pulled down to a low level, then 1Y is also at a low level. Since 1Z is at a low level, the NMOS tube Q12 is turned off, 2Z is ​​at a high level, and 2Y is also at a high level.

[0034] When a charger is available, the charger can charge the main battery power source and the backup battery power source, then:

[0035] When the main battery power source is in place and the power level of the main battery power source is less than a third preset threshold value (eg, the third preset threshold value is 90% of the total power level of the main battery power source), the battery switching signal controls the charger to charge the main battery power source.

[0036] When the backup battery power supply is in place and any of the following conditions are met, the battery switching signal controls the charger to charge the backup battery power supply:

[0037] Condition 1: The main battery power source is not in place, and the backup battery power source is less than a fourth preset threshold;

[0038] Condition 2: The power level of the main battery power source is greater than or equal to the third preset threshold, and the power level of the backup battery power source is less than the fourth preset threshold (for example, the fourth preset threshold is 90% of the total power level of the backup battery power source).

[0039] Electronic switches are respectively arranged between the charger and the main battery power supply and between the charger and the backup battery power supply, and the switching of the electronic switches is controlled by the battery switching signal. For example, a PMOS tube is arranged between the charger and the main battery power supply, and when the battery switching signal is at a low level, the charger charges the main battery power supply; an NMOS tube is arranged between the charger and the backup battery power supply, and when the battery switching signal is at a low level, the charger charges the backup battery power supply.

[0040] Please refer to Figure 2As shown, the first fast-off and slow-on circuit includes an NMOS tube Q15, an NMOS tube Q5, a PMOS tube Q1, a PMOS tube Q2, an NPN transistor Q3, a PNP transistor Q4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, and a resistor R7; the gate of the NMOS tube Q15 and the gate of the NMOS tube Q5 are both connected to the first enable signal, and the source of the NMOS tube Q15 and the source of the NMOS tube Q5 are both grounded; the drain of the NMOS tube Q15 is connected to the main battery power supply through the resistor R1; the drain of the PMOS tube Q1 is connected to the main battery power supply, the source of the PMOS tube Q1 is connected to the source of the PMOS tube Q2, and the drain of the PMOS tube Q2 is connected to the common output terminal; the drain of the NMOS tube Q5 is connected to the PMOS transistor Q1 through the resistor R7 and the resistor R6 in sequence. The gate of the PMOS transistor Q1 and the gate of the PMOS transistor Q2 are both connected between the resistor R6 and the resistor R7; the base of the NPN transistor Q3 is connected between the resistor R1 and the drain of the NMOS transistor Q15 through the resistor R2, the base of the NPN transistor Q3 is connected to the emitter of the NPN transistor Q3 through the resistor R3, and the emitter of the NPN transistor Q3 is grounded; the collector of the NPN transistor Q3 is connected to the base of the PNP transistor Q4 through the resistor R4, the base of the PNP transistor Q4 and the emitter of the PNP transistor Q4 are connected with the resistor R5, the emitter of the PNP transistor Q4 is also connected between the source of the PMOS transistor Q1 and the source of the PMOS transistor Q2, and the collector of the PNP transistor Q4 is connected between the resistor R6 and the resistor R7.

[0041] When the main battery power is in place (i.e., there can be voltage output) and V_MAIN is high: NMOS tubes Q5 and Q15 are turned on, resistors R6 and R7 divide the voltage so that the VGS of PMOS tubes Q1 and Q2 are both negative potentials, PMOS tubes Q1 and Q2 are turned on, and the common output terminal and the main battery power are directly connected, and the main battery power supplies power to the load through the common output terminal. When V_MAIN changes from high to low: NMOS tubes Q5 and Q15 are turned off, resistors R2, R1 and R3 divide the voltage, NPN transistor Q3 is turned on, and then resistors R5 and R4 will divide the voltage. At this time, PNP transistor Q4 is turned on, and the voltage difference between the two ends of resistor R6 is instantly discharged to 0V, so that PMOS tubes Q1 and Q2 are quickly turned off, thereby achieving the purpose of fast shutdown.

[0042] Please refer to Figure 3As shown, the second fast-off and slow-on circuit includes an NMOS tube Q16, an NMOS tube Q10, a PMOS tube Q6, a PMOS tube Q7, an NPN transistor Q8, a PNP transistor Q9, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, and a resistor R14; the gate of the NMOS tube Q16 and the gate of the NMOS tube Q10 are both connected to the second enable signal, and the source of the NMOS tube Q16 and the source of the NMOS tube Q10 are both grounded; the drain of the NMOS tube Q16 is connected to the backup battery power supply through the resistor R8; the drain of the PMOS tube Q6 is connected to the backup battery power supply, the source of the PMOS tube Q6 is connected to the source of the PMOS tube Q7, and the drain of the PMOS tube Q7 is connected to the common output terminal; the drain of the NMOS tube Q10 is connected to the PMOS transistor Q7 through the resistor R14 and the resistor R13 in sequence. between the source of the MOS transistor Q6 and the source of the PMOS transistor Q7; the gate of the PMOS transistor Q6 and the gate of the PMOS transistor Q7 are both connected between the resistor R13 and the resistor R14; the base of the NPN transistor Q8 is connected between the resistor R8 and the drain of the NMOS transistor Q16 through the resistor R9, the base of the NPN transistor Q8 is connected to the emitter of the NPN transistor Q8 through the resistor R10, and the emitter of the NPN transistor Q8 is grounded; the collector of the NPN transistor Q8 is connected to the base of the PNP transistor Q9 through the resistor R11, the resistor R12 is connected between the base of the PNP transistor Q9 and the emitter of the PNP transistor Q9, the emitter of the PNP transistor Q9 is also connected between the source of the PMOS transistor Q6 and the source of the PMOS transistor Q7, and the collector of the PNP transistor Q9 is connected between the resistor R13 and the resistor R14.

[0043] When the backup battery power is in place (i.e., voltage output is available) and V_SEC is high: NMOS tube Q10 and NMOS tube Q16 are turned on, resistor R13 and resistor R14 divide the voltage so that the VGS of PMOS tube Q6 and PMOS tube Q7 are both negative potential, PMOS tube Q6 and PMOS tube Q7 are turned on, and the common output terminal and the backup battery power are directly connected, and the backup battery power supplies power to the load through the common output terminal. When V_SEC changes from high to low: NMOS tube Q10 and NMOS tube Q16 are turned off, resistor R9, resistor R8 and resistor R10 divide the voltage, NPN transistor Q8 is turned on, and then resistor R12 and resistor R11 will divide the voltage. At this time, PNP transistor Q9 is turned on, and the voltage difference between the two ends of resistor R13 is instantly discharged to 0V, so that PMOS tube Q6 and PMOS tube Q7 are quickly turned off and cut off, thereby achieving the purpose of fast shutdown.

[0044] Embodiment 2:

[0045] Embodiment 2 discloses an electronic device, which may be a laptop, a tablet computer, a mobile phone, or a mobile power supply. In addition to the dual-battery selection circuit in the above embodiment, the electronic device also includes necessary components, such as a PCB board for mounting various components of the dual-battery selection circuit and a housing for mounting the PCB board, an output interface, an indicator light, a display screen, etc. Of course, other components may also be included as needed, such as a radiator, etc.

[0046] The above implementation modes are only preferred implementation modes of the embodiments of the present invention and cannot be used to limit the protection scope of the embodiments of the present invention. Any non-substantial changes and replacements made by technicians in this field on the basis of the embodiments of the present invention shall fall within the scope of protection required by the embodiments of the present invention.

Claims

1. A dual battery selection circuit, characterized in that: It is used to select the output of the main battery power supply or the backup battery power supply, and includes: a dual-way switch, a first fast-off-slow-opening circuit and a second fast-off-slow-opening circuit, the dual-way switch has two input terminals and two output terminals corresponding to the two input terminals one by one, the two input terminals are connected to the main battery power supply, the backup battery power supply and the battery switching signal through a logic circuit; the two output terminals output a first enable signal and a second enable signal respectively; the main battery power supply is connected to the common output terminal of the dual battery selection circuit through the first fast-off-slow-opening circuit, the first enable signal is connected to the enable terminal of the first fast-off-slow-opening circuit, and is used to control the output of the main battery power supply; the backup battery power supply is connected to the common output terminal through the second fast-off-slow-opening circuit, and the second enable signal is connected to the enable terminal of the second fast-off-slow-opening circuit, and is used to control the output of the backup battery power supply; The first fast-off and slow-on circuit comprises an NMOS transistor Q15, an NMOS transistor Q5, a PMOS transistor Q1, a PMOS transistor Q2, an NPN transistor Q3, a PNP transistor Q4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, and a resistor R7; the gate of the NMOS transistor Q15 and the gate of the NMOS transistor Q5 are both connected to the first enable signal, and the source of the NMOS transistor Q15 and the source of the NMOS transistor Q5 are both grounded; the drain of the NMOS transistor Q15 is connected to the main battery power supply through the resistor R1; the drain of the PMOS transistor Q1 is connected to the main battery power supply, the source of the PMOS transistor Q1 is connected to the source of the PMOS transistor Q2, and the drain of the PMOS transistor Q2 is connected to the common output terminal; the drain of the NMOS transistor Q5 is connected to the PMOS transistor Q15 through the resistor R7 and the resistor R6 in sequence. 1 and the source of the PMOS tube Q2; the gate of the PMOS tube Q1 and the gate of the PMOS tube Q2 are both connected to between the resistor R6 and the resistor R7; the base of the NPN transistor Q3 is connected to between the resistor R1 and the drain of the NMOS tube Q15 through the resistor R2, the base of the NPN transistor Q3 is connected to the emitter of the NPN transistor Q3 through the resistor R3, and the emitter of the NPN transistor Q3 is grounded; the collector of the NPN transistor Q3 is connected to the base of the PNP transistor Q4 through the resistor R4, the base of the PNP transistor Q4 and the emitter of the PNP transistor Q4 are connected to the resistor R5, the emitter of the PNP transistor Q4 is also connected to between the source of the PMOS tube Q1 and the source of the PMOS tube Q2, and the collector of the PNP transistor Q4 is connected to between the resistor R6 and the resistor R7; The second fast-off and slow-on circuit comprises an NMOS transistor Q16, an NMOS transistor Q10, a PMOS transistor Q6, a PMOS transistor Q7, an NPN transistor Q8, a PNP transistor Q9, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, and a resistor R14; the gate of the NMOS transistor Q16 and the gate of the NMOS transistor Q10 are both connected to the second enable signal, and the source of the NMOS transistor Q16 and the source of the NMOS transistor Q10 are both grounded; the drain of the NMOS transistor Q16 is connected to the backup battery power supply through the resistor R8; the drain of the PMOS transistor Q6 is connected to the backup battery power supply, the source of the PMOS transistor Q6 is connected to the source of the PMOS transistor Q7, and the drain of the PMOS transistor Q7 is connected to the common output terminal; the drain of the NMOS transistor Q10 is connected to the PMOS transistor Q10 through the resistor R14 and the resistor R13 in sequence. between the source of the S transistor Q6 and the source of the PMOS transistor Q7; the gate of the PMOS transistor Q6 and the gate of the PMOS transistor Q7 are both connected to between the resistor R13 and the resistor R14; the base of the NPN transistor Q8 is connected to between the resistor R8 and the drain of the NMOS transistor Q16 through the resistor R9, the base of the NPN transistor Q8 is connected to the emitter of the NPN transistor Q8 through the resistor R10, and the emitter of the NPN transistor Q8 is grounded; the collector of the NPN transistor Q8 is connected to the base of the PNP transistor Q9 through the resistor R11, the base of the PNP transistor Q9 and the emitter of the PNP transistor Q9 are connected with a resistor R12, the emitter of the PNP transistor Q9 is also connected to between the source of the PMOS transistor Q6 and the source of the PMOS transistor Q7, and the collector of the PNP transistor Q9 is connected to between the resistor R13 and the resistor R14.

2. The dual battery selection circuit as claimed in claim 1, characterized in that: The two input ends are respectively a first input end and a second input end, and the two output ends are respectively a first output end corresponding to the first input end and a second output end corresponding to the second input end; the first input end and the second input end are connected to the main battery power supply, the backup battery power supply and the battery switching signal through a logic circuit; the first output end outputs a first enable signal, and the second output end outputs a second enable signal.

3. The dual battery selection circuit as claimed in claim 2, characterized in that: The logic circuit includes an auxiliary power supply, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, an NMOS tube Q11, an NMOS tube Q12, an NMOS tube Q13, and an NMOS tube Q14. The output end of the auxiliary power supply is connected to the first input end through the resistor R15, and the output end of the auxiliary power supply is connected to the second input end through the resistor R16; the drain of the NMOS tube Q11, the gate of the NMOS tube Q12, and the drain of the NMOS tube Q13 are all connected to the first input end, and the NMOS tube Q14 is connected to the gate of the NMOS tube Q12. The drain of Q12 is connected to the second input terminal, the gate of the NMOS tube Q11 is connected to the battery switching signal through the resistor R17; the gate of the NMOS tube Q13 is connected to the backup battery power supply through the resistor R18; the gate of the NMOS tube Q14 is connected to the main battery power supply through the resistor R19, and the drain of the NMOS tube Q14 is connected to the gate of the NMOS tube Q13; the source of the NMOS tube Q11, the source of the NMOS tube Q12, the source of the NMOS tube Q13 and the source of the NMOS tube Q14 are all grounded.

4. The dual battery selection circuit according to any one of claims 1 to 3, characterized in that: The battery switching signal is generated by the EC or AP; When there is no charger to charge the main battery power supply and the backup battery power supply, if the power of the main battery power supply is greater than the first preset threshold, the battery switching signal is at a low level; if the power of the main battery power supply is less than the first preset threshold and the power of the backup battery power supply is greater than the second preset threshold, the battery switching signal is at a high level.

5. The dual battery selection circuit as claimed in claim 4, characterized in that: When there is a charger, then: When the main battery power source is in place and the power level of the main battery power source is less than a third preset threshold, the battery switching signal controls the charger to charge the main battery power source; When the backup battery power supply is in place and any of the following conditions are met, the battery switching signal controls the charger to charge the backup battery power supply: Condition 1: The main battery power source is not in place, and the backup battery power source is less than a fourth preset threshold; Condition 2: The power level of the main battery power source is greater than or equal to the third preset threshold, and the power level of the backup battery power source is less than the fourth preset threshold.

6. An electronic device, characterized in that: It comprises the dual battery selection circuit as described in any one of claims 1-5.

Images