Semiconductor memory device and manufacturing method thereof

Abstract

Disclosed are a semiconductor memory device and a method for manufacturing the same. The device may include: a first substrate including a cell array region; a first interlayer insulating layer covering the first substrate; a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region; a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate; and a contact plug penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer to electrically connect the cell array region to the core region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application Nos. 10-2018-0107365 and 10-2019-0013052, filed on September 7, 2018, and January 31, 2019, respectively, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor memory device and a method for manufacturing the same. Background Art

[0004] A semiconductor memory device includes a plurality of circuit regions disposed therein. For example, a semiconductor memory device includes: a cell array region in which memory elements are disposed; and a peripheral region in which circuits for driving the memory elements and performing data input / output operations are disposed. There are differences between the cell array region and the peripheral region in terms of technical requirements for electrical characteristics. At the same time, in order to meet the growing demand for highly integrated semiconductor memory devices, it is necessary to form more circuits in a limited chip area. To this end, it is desirable to form a semiconductor memory device having a reduced form factor and being configured to allow the device to have electrical characteristics optimized for each region and improved reliability. Summary of the Invention

[0005] Embodiments of the inventive concept provide a semiconductor memory device having improved reliability and increased integration density.

[0006] Embodiments of the inventive concept provide a method of optimizing electrical characteristics of a device for respective regions in a process of manufacturing a semiconductor memory device.

[0007] According to some embodiments, the present disclosure relates to a semiconductor memory device, comprising: a first substrate including a cell array region; a first interlayer insulating layer covering the first substrate; a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region; a first adhesive insulating layer inserted between the first interlayer insulating layer and the second substrate; and a contact plug penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region to the core region.

[0008] According to some embodiments, the present disclosure relates to a semiconductor device including: a first substrate including a cell array area; a second substrate disposed on the first substrate, the second substrate including a core area electrically connected to the cell array area; and a third substrate disposed on the second substrate, the third substrate including a peripheral circuit area electrically connected to the core area.

[0009] According to some embodiments, the present disclosure relates to a semiconductor memory device, including: a first substrate including a cell array region; a first interlayer insulating layer covering the first substrate; a second substrate disposed on the first interlayer insulating layer, the second substrate including a logic region electrically connected to the cell array region; a first adhesive insulating layer inserted between the first interlayer insulating layer and the second substrate; and a contact plug penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region to the logic region.

[0010] According to some embodiments, the present disclosure relates to a method for manufacturing a semiconductor memory device, including: manufacturing a first wafer having a chip area and a scribe area; preparing a second wafer; forming a first preliminary bonding insulating layer on the first wafer; forming a second preliminary bonding insulating layer on the second wafer; placing the second wafer on the first wafer so that the first preliminary bonding insulating layer contacts the second preliminary bonding insulating layer; converting the first preliminary bonding insulating layer and the second preliminary bonding insulating layer into a bonding insulating layer; and forming a first transistor and a first interconnection line on the second wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0012] Figure 1 is a block diagram of a semiconductor memory device according to an example embodiment of the inventive concept.

[0013] Figure 2 is a conceptual diagram of a semiconductor memory device according to example embodiments of the inventive concepts.

[0014] Figure 3 is a plan view of a semiconductor memory device according to an example embodiment of the inventive concept.

[0015] Figure 4 is shown along Figure 3 1 and 2 are diagrams of vertical cross-sections of a semiconductor memory device according to example embodiments of the inventive concept taken along lines AA′, BB′, CC′, and DD′.

[0016] Figure 5 is a plan view illustrating a first wafer according to example embodiments of the inventive concepts.

[0017] Figures 6A to 6M is a diagram illustrating the manufacture of an example embodiment of the present invention (e.g., having Figure 4 A cross-sectional view of a process of a semiconductor memory device (vertical cross-section).

[0018] Figure 7 is shown along Figure 3 1 and 2 are diagrams of vertical cross-sections of a semiconductor memory device according to example embodiments of the inventive concept taken along lines AA′, BB′, CC′, and DD′.

[0019] Figure 8 is shown along Figure 3 1 and 2 are diagrams of vertical cross-sections of a semiconductor memory device according to example embodiments of the inventive concept taken along lines AA′, BB′, CC′, and DD′.

[0020] Figure 9 is shown along Figure 3 1 and 2 are diagrams of vertical cross-sections of a semiconductor memory device according to example embodiments of the inventive concept taken along lines AA′, BB′, CC′, and DD′.

[0021] Figure 10 is shown along Figure 3 1 and 2 are diagrams of vertical cross-sections of a semiconductor memory device according to example embodiments of the inventive concept taken along lines AA′, BB′, CC′, and DD′.

[0022] Figure 11 is a conceptual diagram illustrating a semiconductor memory device according to example embodiments of the inventive concept.

[0023] Figure 12 is a cross-sectional view illustrating a semiconductor memory device according to example embodiments of the inventive concepts.

[0024] Figure 13 is a conceptual diagram illustrating a semiconductor memory device according to example embodiments of the inventive concept.

[0025] Figure 14 is a cross-sectional view illustrating a semiconductor memory device according to example embodiments of the inventive concepts.

[0026] It should be noted that these figures are intended to illustrate the general characteristics of methods, structures and / or materials utilized in certain example embodiments and to supplement the written description provided below. However, these figures are not to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment and should not be interpreted as defining or limiting the range of values ​​or properties encompassed by the example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0027] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0028] Figure 1 is a block diagram of a semiconductor memory device according to an example embodiment of the inventive concept.

[0029] Reference Figure 1 For example, the semiconductor memory device according to example embodiments may be a dynamic random access memory (DRAM) device. The semiconductor memory device may include a cell array region 10. Word lines WL and bit lines BL that cross each other may be provided on the cell array region 10. A core region 20 may be provided around or near the cell array region 10. Sub-word line drivers 22 (also referred to as word line drivers 22) and sense amplifiers 24 may be placed in the core region 20. A peripheral circuit region 30 may be provided around or near the core region 20. A row decoder 32 and a column decoder 34 may be placed in the peripheral circuit region 30. A region including the core region 20 and the peripheral circuit region 30 may be referred to as a logic region.

[0030] The row decoder 32 may decode a row address signal or a refresh address signal. The column decoder 34 may decode a column address signal and select a bit line BL. The sub-word line driver 22 may select a specific word line from the word lines WL in response to the row address signal or the refresh address signal. If the cell capacitor of the selected memory cell is configured to store a minute amount of charge, it may be difficult to directly generate a digital signal to be output externally from the charge stored in the cell capacitor. The sense amplifier 24 may amplify a signal corresponding to the stored charge.

[0031] Figure 2 is a conceptual diagram of a semiconductor memory device according to example embodiments of the inventive concepts.

[0032] Reference Figure 2 The semiconductor memory device according to the present embodiment may include a first substrate 100, a second substrate 200, and a third substrate 300 sequentially stacked. Cell array regions 10 spaced apart from each other may be provided on the first substrate 100. Each cell array region 10 may include a plurality of word lines and a plurality of bit lines intersecting the word lines.

[0033] The core region 20 may be placed on the second substrate 200. Each core region 20 may include a first sub-word line driver 22a and a second sub-word line driver 22b (also referred to as word line drivers 22a and 22b) and a first sense amplifier 24a and a second sense amplifier 24b. In each core region 20, the first sub-word line driver 22a and the second sub-word line driver 22b may be placed symmetrically relative to each other. In each core region 20, the first sense amplifier 24a and the second sense amplifier 24b may be placed symmetrically relative to each other. The first sub-word line driver 22a and the second sub-word line driver 22b may be disposed adjacent to the ends of the word lines disposed on the cell array region 10. The first sense amplifier 24a and the second sense amplifier 24b may be disposed adjacent to the ends of the bit lines disposed on the cell array region 10. In some embodiments, the core region 20 may vertically overlap the cell array region 10. For example, when viewed from the top, each core region 20 may overlap the cell array region 10 to which the first and second sub word line drivers 22 a and 22 b and the first and second sense amplifiers 24 a and 24 b are connected.

[0034] One of the cell array regions 10 may be electrically connected to the core region 20 disposed directly thereon. The ends of the bit lines on the cell array region 10 may be electrically connected to the first sense amplifier 24a and the second sense amplifier 24b of the core region 20 via the first contact plug MC1. The ends of the word lines on the cell array region 10 may be electrically connected to the first sub-word line driver 22a and the second sub-word line driver 22b of the core region 20 via the second contact plug MC2. The bottom surface of the first contact plug MC1 may have a height different from the height of the bottom surface of the second contact plug MC2. The bottom surface of the first contact plug MC1 may have a height higher than the height of the bottom surface of the second contact plug MC2. In some embodiments, the first contact plug MC1 and the second contact plug MC2 may be disposed between the core region 20 and the corresponding cell array region 10. For example, when viewed from the top, the first contact plug MC1 and the second contact plug MC2 may be located within the boundary between the corresponding core region 20 and the cell array region 10.

[0035] A row decoder 32, a column decoder 34, and an input / output terminal region 36 may be provided on the third substrate 300. The first sub word line driver 22a and the second sub word line driver 22b included in each of the core regions 20 may be electrically connected to the row decoder 32. The first sense amplifier 24a and the second sense amplifier 24b included in each of the core regions 20 may be electrically connected to the column decoder 34. Input / output terminals connected to external devices may be provided in the input / output terminal region 36.

[0036] For the sake of illustration, Figure 2An example of the first substrate 100 including four cell array regions 10 is shown, but the number of the cell array regions 10 is not limited thereto. The number of the core regions 20 may be equal to or less than the number of the cell array regions 10.

[0037] Will refer to Figure 3 and Figure 4 Describe in more detail Figure 2 semiconductor memory device. Figure 3 is a plan view of a semiconductor memory device according to an example embodiment of the inventive concept. Figure 4 is shown along Figure 3 1 and 2 are diagrams of vertical cross-sections of a semiconductor memory device according to example embodiments of the inventive concept taken along lines AA′, BB′, CC′, and DD′.

[0038] Reference Figures 2 to 4 According to the present embodiment, the semiconductor memory device 1000 may include a first substrate 100. The semiconductor memory device 1000 may be a semiconductor package. The first substrate 100 may include a single crystal semiconductor substrate or a semiconductor epitaxial layer. A plurality of cell array regions 10 may be placed on the first substrate 100, such as Figure 2 However, for the sake of illustration, Figure 3 Schematic diagram showing the layout of memory cells arranged on one cell array region.

[0039] like Figure 3 and Figure 4 As shown, a device isolation layer 102 may be provided in the first substrate 100 to define an active area AR. Each active area AR may be a strip-shaped structure elongated in a first direction D1. The first direction D1 may be a direction coplanar with the second direction D2 and the third direction D3, but may be angled relative to the second direction D2 and the third direction D3. Word lines WL may be provided in the first substrate 100. Each of the word lines WL may be a linear pattern extending in a second direction D2 intersecting the first direction D1. The word lines WL may be buried in the first substrate 100. For example, the top surface of the word lines WL may be lower than the top surface of the first substrate 100. The word lines WL may be covered by a word line capping pattern 103.

[0040] First source / drain regions 101a and second source / drain regions 101b spaced apart from each other may be provided in a first substrate 100. The first source / drain region 101a may be provided on one side of each word line WL, and the second source / drain region 101b may be provided on the opposite side of each word line WL. The first substrate 100 may be covered by a pad insulating layer 104. Bit lines BL may be provided on the pad insulating layer 104. Each bit line BL may be a linear pattern extending in a third direction D3 intersecting both the first direction D1 and the second direction D2. The bit lines BL may be covered by a bit line capping pattern 105. Side surfaces of the bit lines BL may be covered by insulating spacers SP, and side surfaces of the bit line capping pattern 105 may be covered by insulating spacers SP. The insulating spacers SP may contact side surfaces of the bit lines BL and the bit line capping pattern 105.

[0041] Each of the bit lines BL can be electrically connected to the first source / drain region 101a via a bit line contact plug DC. Storage node contact plugs BC can be provided between adjacent bit lines BL. Storage node contact plugs BC can be electrically connected to the second source / drain region 101b. Bottom electrodes BE can be provided on each of the storage node contact plugs BC. The bottom electrodes BE can be covered by a dielectric layer DL. A top electrode TE can be placed on the dielectric layer DL. The bottom electrode BE, the dielectric layer DL, and the top electrode TE can form a capacitor. The top electrode TE can be covered by a first interlayer insulating layer 106. The first interlayer insulating layer 106 can also be referred to as a first interlayered insulating layer 106. The first interlayer insulating layer 106 can include a silicon oxide layer.

[0042] An adhesive insulating layer 150 may be placed on the first interlayer insulating layer 106. The adhesive insulating layer 150 may include a silicon oxide layer. The adhesive insulating layer 150 may also include at least one of nitrogen or carbon. The second substrate 200 may be placed on the adhesive insulating layer 150. The adhesive insulating layer 150 may be used to attach the first interlayer insulating layer 106 to the second substrate 200.

[0043] For example, the second substrate 200 may be a silicon epitaxial layer. The first transistors TR1 may be disposed on the second substrate 200. Each of the first transistors TR1 may include a first gate insulating layer GL1. The first transistors TR1 may be covered by a second interlayer insulating layer 210. The second interlayer insulating layer 210 may also be referred to as a second interlayer insulating layer 210. Although not shown, the second interlayer insulating layer 210 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a porous insulating layer, and may have a single-layer or multi-layer structure. A first interconnect line 212 electrically connected to the first transistors TR1 may be disposed in the second interlayer insulating layer 210. A first conductive pad 214 may be disposed on top of the second interlayer insulating layer 210. The first conductive pad 214 may include copper.

[0044] With reference Figure 2 The circuit corresponding to the core region 20 described above may be provided on the second substrate 200. For example, the first transistor TR1 and the first interconnection line 212 may constitute a circuit included in the reference circuit. Figure 2 Sub-word line drivers 22a and 22b and sense amplifiers 24a and 24b in the core region 20 are depicted.

[0045] Some of the first interconnect lines 212 may be electrically connected to the bit lines BL and word lines WL via first and second contact plugs MC1 and MC2. Specifically, the first contact plugs MC1 may be disposed to penetrate the second substrate 200, the adhesive insulating layer 150, the first interlayer insulating layer 106, and the bit line capping pattern 105, and contact the ends of the bit lines BL. The second contact plugs MC2 may be disposed to penetrate the second substrate 200, the adhesive insulating layer 150, the first interlayer insulating layer 106, the pad insulating layer 104, and the word line capping pattern 103, and contact the ends of the word lines WL. A first contact insulating layer 120 may be interposed between the first contact plugs MC1 and the second substrate 200. For example, the first contact insulating layer 120 may surround the first contact plugs MC1 and contact the side surfaces of the first contact plugs MC1. In some embodiments, the first contact insulating layer 120 may have the same height as the first contact plugs MC1 and may extend the entire length of the first contact plugs MC1. The second contact insulating layer 122 may be interposed between the second contact plugs MC2 and the second substrate 200. For example, the second contact insulating layer 122 may surround the second contact plug MC2, contacting a side surface of the second contact plug MC2. In some embodiments, the second contact insulating layer 122 may have the same height as the second contact plug MC2 and may extend the entire length of the second contact plug MC2.

[0046] For example, Figure 3 As shown, the ends of the odd-numbered bit lines BL may be directed toward Figure 3 The top side (eg, in the third direction D3) of the bit lines BL may protrude, and the ends of the even-numbered bit lines BL may be directed toward Figure 3 The bottom side of the odd-numbered word line WL may protrude (eg, in a direction opposite to the third direction D3). Figure 3 The left side of the word line WL (eg, in a direction opposite to the second direction D2) protrudes, and the end of the even-numbered word line WL may be toward Figure 3 The first contact plugs MC1 and the second contact plugs MC2 may protrude to the right (e.g., in the second direction D2). Therefore, the misalignment margin in the process of forming the first contact plugs MC1 and the second contact plugs MC2 may be increased. For example, the first contact plugs MC1 contacting the bit lines BL may be offset relative to each other in the second direction D2. The second contact plugs MC2 contacting the word lines WL may be offset relative to each other in the third direction D3.

[0047] A third interlayer insulating layer 310 may be disposed on the second interlayer insulating layer 210. The third interlayer insulating layer 310 may also be referred to as the third interlayer insulating layer 310. A third substrate 300 may be disposed on the third interlayer insulating layer 310. The third substrate 300 may be a semiconductor single crystal wafer or a semiconductor epitaxial layer. The second transistors TR2 may be disposed on a surface of the third substrate 300 facing toward the second substrate 200 and covered by the third interlayer insulating layer 310. Each of the second transistors TR2 may include a second gate insulating layer GL2. A second interconnect line 312 electrically connected to the second transistors TR2 may be disposed in the third interlayer insulating layer 310. A second conductive pad 314 may be disposed in the bottom of the third interlayer insulating layer 310. The second conductive pad 314 may be aligned with the first conductive pad 214. The second conductive pad 314 may include copper. Although not shown, the third interlayer insulating layer 310 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a porous insulating layer, and may have a single-layer or multi-layer structure. Through-holes TSV may be provided to penetrate the third substrate 300. External conductive pads 316 may be provided on the through-holes TSV. The external conductive pads 316 may be input / output pads connected to an external device.

[0048] The third interlayer insulating layer 310 and the second interlayer insulating layer 210 may contact each other. The second conductive pad 314 and the first conductive pad 214 may contact each other and may be electrically connected to each other. Figure 2 The circuit corresponding to the peripheral circuit region 30 may be provided on the third substrate 300. In detail, the second transistor TR2 and the second interconnection line 312 may constitute a reference Figure 2 The row decoder 32 and column decoder 34 are depicted.

[0049] In an example embodiment of the present inventive concept, the density of the first transistors TR1 disposed on the second substrate 200 may be greater than the density of the second transistors TR2 disposed on the third substrate 300. For example, the number of first transistors TR1 disposed on the second substrate 200 may be greater than the number of second transistors TR2 disposed on the third substrate 300. In an example embodiment, the second gate insulating layer GL2 may be thicker than the first gate insulating layer GL1. The second transistors TR2 may be high-voltage transistors. The first transistors TR1 may be low-voltage transistors.

[0050] For the peripheral circuit region 30 provided with input / output pads, it may be important to increase the data transfer speed during data input / output operations. In an exemplary embodiment of the present inventive concept, since the second transistor TR2 is a high-voltage transistor and the second gate insulating layer GL2 has a relatively large thickness, a high voltage can be applied to the second transistor TR2, and this can increase the data transfer speed during data input / output operations. Therefore, the data exchange speed or performance of the semiconductor memory device can be increased.

[0051] At the same time, due to the large density or number of the first transistors TR1 on the core region 20, even when the amount of leakage current generated in each of the first transistors TR1 is small, the operation of the semiconductor memory device may be greatly affected by the total leakage current of the first transistors TR1. Therefore, it may be important to reduce the total amount of leakage current for the core region 20. In an example embodiment of the present inventive concept, since the first transistors TR1 are low-voltage transistors and the first gate insulating layer GL1 has a relatively thin thickness, a low voltage can be applied to the first transistors TR1, which can reduce the leakage current in each of the first transistors TR1.

[0052] In a semiconductor memory device according to an exemplary embodiment of the present invention, devices in various circuit regions can be implemented on different substrates. Therefore, it is easy to implement devices optimized for each circuit region and realize a semiconductor memory device with improved reliability. Furthermore, the core regions 20 corresponding to the cell array region 10 can be vertically connected to the cell array region 10 via the first and second contact plugs MC1 and MC2, respectively, which can reduce the planar size. Therefore, the form factor of the semiconductor memory device can be reduced. Furthermore, the degree of freedom in designing the semiconductor memory device can be increased.

[0053] Figure 5 is a plan view illustrating a first wafer according to example embodiments of the inventive concepts. Figures 6A to 6M is a diagram illustrating the manufacture of an example embodiment of the present invention (e.g., having Figure 4 A cross-sectional view of a process of a semiconductor memory device (vertical cross-section).

[0054] Reference Figure 5 and Figure 6A , the first wafer 100w can be manufactured. Figure 5 As shown, the first wafer 100w may include a plurality of chip regions CHR spaced apart from each other. The chip regions CHR may be separated from each other by scribe lane regions SCL. In some embodiments, the scribe lane regions SCL may include the following regions in the first wafer 100w: regions in which no circuits (e.g., transistors) are formed and / or regions in which no circuits (e.g., transistors) as part of an integrated circuit of an uncut chip are formed. Each chip region CHR may include a reference Figures 2 to 4 The cell array region 10 is described. In detail, the first wafer 100w may include a first substrate 100 and a first interlayer insulating layer 106. In the first wafer 100w, referring to Figure 3 and Figure 4 The described word lines WL, bit lines BL, and capacitors may be provided on the chip region CHR. The first alignment key AK1 may be provided on the scribe lane region SCL of the first wafer 100w. The first alignment key AK1 may be covered by the first interlayer insulating layer 106. The process of manufacturing the first wafer 100w may include a process of manufacturing memory cells in the cell array region of the DRAM device.

[0055] like Figure 6B As shown, a second wafer 200w may be manufactured. The manufacture of the second wafer 200w may include forming a semiconductor epitaxial layer 200e on a single crystal semiconductor substrate 200s. The single crystal semiconductor substrate 200s and the semiconductor epitaxial layer 200e may be doped with, for example, a first impurity of a first conductivity type. The first impurity of the first conductivity type may be a P-type dopant (e.g., boron). The concentration of the first impurity doped in the single crystal semiconductor substrate 200s may be different from the concentration of the first impurity in the semiconductor epitaxial layer 200e. For example, the concentration of the first impurity doped in the single crystal semiconductor substrate 200s may be greater than the concentration of the first impurity in the semiconductor epitaxial layer 200e. The difference in the concentration of the first impurity between the single crystal semiconductor substrate 200s and the semiconductor epitaxial layer 200e may result in a difference in etching / polishing rates in a subsequent polishing / etching process.

[0056] Reference Figure 6C , the edge portion of the second wafer 200w may be partially removed. Specifically, the edge portion of the semiconductor epitaxial layer 200e may be removed to expose the top surface of the single crystal semiconductor substrate 200s. This process may be performed to prevent process failures in subsequent polishing / grinding processes.

[0057] Reference Figure 6D, a first preliminary bonding insulating layer 150a may be deposited to cover the entire top surface of the first wafer 100w. The first preliminary bonding insulating layer 150a may be deposited on the first interlayer insulating layer 106. A second preliminary bonding insulating layer 150b may be deposited to cover the entire top surface of the second wafer 200w. For example, the second preliminary bonding insulating layer 150b may be formed on the semiconductor epitaxial layer 200e. In addition, the second preliminary bonding insulating layer 150b may be formed on the side surfaces of the semiconductor epitaxial layer 200e and on the top surface of the single crystal semiconductor substrate 200s exposed by removing the edge portion of the semiconductor epitaxial layer 200e. The first preliminary bonding insulating layer 150a and the second preliminary bonding insulating layer 150b may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, metal oxide, or metal nitride, or may include these materials.

[0058] Reference Figure 6E and Figure 6F , the second wafer 200w may be disposed on the first wafer 100w so that the first preliminary adhesive insulating layer 150a and the second preliminary adhesive insulating layer 150b contact each other. Thereafter, an annealing process may be performed. As a result of the annealing process, the first preliminary adhesive insulating layer 150a and the second preliminary adhesive insulating layer 150b may be bonded to each other to form the adhesive insulating layer 150.

[0059] Reference Figure 6G , the single crystal semiconductor substrate 200s can be removed from the second wafer 200w. This removal process can be performed using at least one of a back grinding process, a chemical mechanical polishing (CMP) process, or a wet etching process. This removal process can be performed using an etchant containing at least one of hydrofluoric acid, nitric acid, phosphoric acid, or acetic acid. Due to the difference in concentration of the first impurity described previously, there may be a difference in polishing / etching rate between the single crystal semiconductor substrate 200s and the semiconductor epitaxial layer 200e. Therefore, the single crystal semiconductor substrate 200s can be selectively removed.

[0060] If in Figure 6C If the edge portion of the semiconductor epitaxial layer 200e is not removed in the step of removing the single crystal semiconductor substrate 200s, the remaining edge portion of the semiconductor epitaxial layer 200e after removing the single crystal semiconductor substrate 200s may be relatively thin compared to its main portion and may be mechanically weak. In this case, during the grinding / polishing process, the edge portion of the semiconductor epitaxial layer 200e may be cracked, resulting in process failure. In contrast, according to example embodiments of the present inventive concept, since the edge portion of the semiconductor epitaxial layer 200e is not removed in the step of removing the single crystal semiconductor substrate 200s, the edge portion of the semiconductor epitaxial layer 200e may be relatively thin compared to its main portion and may be mechanically weak. In this case, during the grinding / polishing process, the edge portion of the semiconductor epitaxial layer 200e may be cracked, resulting in process failure. Figure 6C In the step of removing the edge portion of the semiconductor epitaxial layer 200e in advance, the edge portion of the semiconductor epitaxial layer 200e can be prevented from being broken. For example, process failure can be prevented.

[0061] Reference Figure 6G and Figure 6H , after the single crystal semiconductor substrate 200 s is removed, the semiconductor epitaxial layer 200 e may remain on the adhesive insulating layer 150 . Figure 6H Show Figure 6G In the final structure, the semiconductor epitaxial layer 200e may correspond to Figure 4 In some embodiments, when the second wafer 200w is disposed on the first wafer 100w, the semiconductor epitaxial layer 200e may not include any circuits.

[0062] Reference Figure 6I The semiconductor epitaxial layer 200e overlapping the scribe street region SCL of the first wafer 100w may be removed to form a groove GR exposing the adhesive insulating layer 150. The groove GR may overlap the scribe street region SCL of the first wafer 100w. An insulating gap-filling layer 202 may be formed to fill the groove GR. The insulating gap-filling layer 202 may include a silicon oxide layer. Since the insulating gap-filling layer 202, the adhesive insulating layer 150, and the first interlayer insulating layer 106 include silicon oxide layers, they may be transparent. Therefore, the first alignment key AK1 can be identified through the groove GR or the insulating gap-filling layer 202.

[0063] The first alignment key AK1 can be used to accurately identify the positions of the ends of the bit lines BL and word lines WL in the first wafer 100w. Therefore, the first contact hole MH1 and the second contact hole MH2 can be accurately formed without misalignment. Specifically, the semiconductor epitaxial layer 200e, the adhesive insulating layer 150, the first interlayer insulating layer 106, and the bit line capping pattern 105 can be sequentially etched to form the first contact hole MH1 that exposes the end of the bit line BL. Similarly, the semiconductor epitaxial layer 200e, the adhesive insulating layer 150, the first interlayer insulating layer 106, the pad insulating layer 104, and the word line capping pattern 103 can be sequentially etched to form the second contact hole MH2 that exposes the end of the word line WL. In example embodiments, the first contact hole MH1 and the second contact hole MH2 can be formed simultaneously.

[0064] Reference Figure 6J , an insulating layer may be conformally deposited and anisotropically etched to form first and second contact insulating layers 120 and 122 covering side surfaces of the first and second contact holes MH1 and MH2, respectively. Thereafter, a conductive layer may be deposited to fill the first and second contact holes MH1 and MH2, and a polishing process and / or an etching process may be performed on the conductive layer to form first and second contact plugs MC1 and MC2 in the first and second contact holes MH1 and MH2, respectively.

[0065] Reference Figure 6K, a first transistor TR1, a first interconnection line 212, a first conductive pad 214, and a second interlayer insulating layer 210 may be formed on the semiconductor epitaxial layer 200e. The first transistor TR1, the first interconnection line 212, and the first conductive pad 214 may not be formed on the scribe line region SCL. A second alignment key AK2 may be formed on the scribe line region SCL of the semiconductor epitaxial layer 200e. The first transistor TR1 may be formed to have a low-voltage transistor structure.

[0066] Reference Figure 6L and Figure 4 , a third wafer 300w can be prepared. In the final structure, the third wafer 300w may correspond to Figure 4 A third substrate 300 may be formed on the third wafer 300w. A third interlayer insulating layer 310 may be formed on the third wafer 300w. A reference Figure 4 The second transistor TR2, the second interconnect line 312, and the second conductive pad 314 are described. The second transistor TR2 may be formed into a structure having a high-voltage transistor. The third wafer 300w may be placed on the semiconductor epitaxial layer 200e so that the third interlayer insulating layer 310 and the second conductive pad 314 are in contact with the second interlayer insulating layer 210 and the first conductive pad 214, respectively. Then, a thermal compression process may be performed to bond the third interlayer insulating layer 310 to the second interlayer insulating layer 210. In example embodiments, the second conductive pad 314 may be bonded to the first conductive pad 214.

[0067] Reference Figure 6M , a cutting process for removing the scribe lane region SCL may be performed to form a plurality of semiconductor memory devices 1000. Figure 6M , the scribe line region SCL is shown by a dotted line frame.

[0068] The method for manufacturing a semiconductor memory device according to an example embodiment of the present invention may include forming devices with different required characteristics on different substrates, stacking the substrates, and connecting the substrates to each other. If the cell array area, the core area, and the peripheral circuit area are all provided in a single substrate, the devices on each area may be affected by the process of forming the devices on other areas. This may lead to an increase in process complexity or process failure. For example, when manufacturing memory cells on the cell array area, it may be necessary to form or remove a mask layer covering the core area and the peripheral circuit area. In contrast, the manufacturing method according to the present embodiment may include forming devices with different required characteristics on different substrates, stacking the substrates, and connecting the substrates to each other, and this may prevent the various areas from being interfered with by other areas. Therefore, the overall process of manufacturing a semiconductor memory device can be simplified and process failures can be reduced. In addition, the device can be easily optimized to have the electrical characteristics required by each circuit area.

[0069] Figure 7is shown along Figure 3 1 and 2 are diagrams of vertical cross-sections of a semiconductor memory device according to example embodiments of the inventive concept taken along lines AA′, BB′, CC′, and DD′.

[0070] Reference Figure 7 In the semiconductor memory device 1000a according to the present embodiment, the first adhesive insulating layer 150 may be provided on the first interlayer insulating layer 106. The second substrate 200 and the second interlayer insulating layer 210 may be sequentially stacked on the first adhesive insulating layer 150. The second adhesive insulating layer 250 may be provided on the second interlayer insulating layer 210. The third substrate 300 and the third interlayer insulating layer 310 may be sequentially stacked on the second adhesive insulating layer 250. The first adhesive insulating layer 150 may be used to bond the first interlayer insulating layer 106 to the second substrate 200. The second adhesive insulating layer 250 may be used to attach the second interlayer insulating layer 210 to the third substrate 300. The second transistor TR2 and the second interconnection line 312 may be provided on the third substrate 300. The third contact plug MC3 may be provided to penetrate a portion of the third substrate 300, the second adhesive insulating layer 250, and the second interlayer insulating layer 210 and electrically connect some of the second interconnection lines 312 to some of the first interconnection lines 212. In addition to the above-mentioned structural features, Figure 7 The semiconductor memory device 1000a may have the same Figures 2 to 4 The semiconductor memory device 1000 has substantially the same features as described above.

[0071] Figure 7 The second adhesive insulating layer 250 of the semiconductor memory device 1000a may be used in the same manner as in the reference Figures 6B to 6F The first adhesive insulating layer 150 is formed by the same or similar method as described above. The third contact plug MC3 may be formed by the same or similar method as described above. Figure 6I and Figure 6J The first contact plug MC1 and the second contact plug MC2 are formed by the same or similar method as described above.

[0072] Figure 8 is shown along Figure 3 1 and 2 are diagrams of vertical cross-sections of a semiconductor memory device according to example embodiments of the inventive concept taken along lines AA′, BB′, CC′, and DD′.

[0073] Reference Figure 8In the semiconductor memory device 1000b according to example embodiments, a connection member 350 may be inserted between the first conductive pad 214 and the second conductive pad 314. For example, the connection member 350 may include at least one of a copper bump, a solder ball, or a solder layer. The top surface of the second interlayer insulating layer 210 may be covered by the layer 211, and the top surface of the third interlayer insulating layer 310 may be covered by the layer 311. The layers 211 and 311 may surround the respective lower and upper portions of the connection member 350. Each of the layers 211 and 311 may be an insulating layer. In addition to the above features, Figure 8 The semiconductor memory device 1000b may have a reference Figures 2 to 4 Essentially the same features as described.

[0074] Figure 8 The semiconductor memory device 1000 b may be manufactured by connecting the third substrate 300 to the second substrate 200 in a flip-chip bonding manner.

[0075] Figure 9 is shown along Figure 3 1 and 2 are diagrams of vertical cross-sections of a semiconductor memory device according to example embodiments of the inventive concept taken along lines AA′, BB′, CC′, and DD′.

[0076] Reference Figure 9 In the semiconductor memory device 1000c according to this embodiment, a conductive structure 330 may be provided instead of Figure 4 The through-hole TSV and the first conductive pad 214 and the second conductive pad 314. The conductive structure 330 may be referred to as a back-via stack (BVS). The conductive structure 330 may be provided to penetrate a portion of the third substrate 300, the third interlayer insulating layer 310, and the second interlayer insulating layer 210, and may be used to electrically connect some first interconnect lines 212 to some second interconnect lines 312. Although not shown, an insulating layer may be inserted between the conductive structure 330 and the third substrate 300. A passivation layer 332 may be provided on the third substrate 300. The passivation layer 332 may cover the inner surface of the conductive structure 330. The conductive structure 330 may be placed in the recessed region R1. The passivation layer 332 may fill the recessed region R1 in which the conductive structure 330 is provided. In addition to the above features, Figure 9 The semiconductor memory device 1000c may have the same Figures 2 to 4 Essentially the same features as described.

[0077] Figure 9 The semiconductor memory device can be manufactured by the following process. The third wafer 300w can be placed on the semiconductor epitaxial layer 200e, such as Figure 6LAs shown, a recessed region R1 can then be formed by removing a portion of the third wafer 300w, the third interlayer insulating layer 310, and the second interlayer insulating layer 210 in the region where the conductive structure 330 is to be formed. Thereafter, a conductive layer can be conformally deposited and patterned to form the conductive structure 330. Next, a passivation layer 332 can be formed. Subsequent processes can be performed using the same or similar methods as described above.

[0078] Figure 10 is shown along Figure 3 1 and 2 are diagrams of vertical cross-sections of a semiconductor memory device according to example embodiments of the inventive concept taken along lines AA′, BB′, CC′, and DD′.

[0079] Reference Figure 10 , the semiconductor memory device 1000d according to this embodiment may have a vertically inverted Figure 8 The third substrate 300 and the third interlayer insulating layer 310 may be provided adjacent to the second interlayer insulating layer 210. A through-hole TSV may be provided in the third substrate 300. The through-hole TSV may be electrically connected to the first conductive pad 214 through the connecting member 350. In addition to the above features, Figure 10 The semiconductor memory device 1000d may have a reference Figure 8 Essentially the same features as described.

[0080] Figure 11 is a conceptual diagram illustrating a semiconductor memory device according to example embodiments of the inventive concept. Figure 12 is a cross-sectional view illustrating a semiconductor memory device according to example embodiments of the inventive concepts.

[0081] Reference Figure 11 and Figure 12 In the semiconductor memory device 1000e according to the present embodiment, the first substrate 100 may include a cell array region 10 and a core region 20. The core region 20 may be positioned adjacent to the corresponding cell array region 10. The first transistor TR1 may be provided on the core region 20. Although not shown, a first interconnection line may be provided on the core region 20. On the core region 20, the first transistor TR1 and the first interconnection line may constitute a sub-word line driver and a sense amplifier.

[0082] The second substrate 200 may be provided on the first substrate 100. An adhesive insulating layer 150 may be interposed between the first interlayer insulating layer 106 and the second substrate 200. The adhesive insulating layer 150 may contact the top surface of the first interlayer insulating layer 106 and the bottom surface of the second substrate 200. The second substrate 200 may include a peripheral circuit region 30. A second transistor TR2, a second interconnection line 312, a second conductive pad 314, and a second interlayer insulating layer 210 may be provided on the second substrate 200. In the peripheral circuit region 30, the second transistor TR2 and the second interconnection line 312 may constitute a row decoder 32 and a column decoder 34. The second conductive pad 314 may correspond to an input / output pad.

[0083] The fourth contact plug MC4 may be provided on the core region 20 of the first substrate 100. The fourth contact plug MC4 may be used to electrically connect the first transistor TR1 on the core region 20 to the second interconnection line 312 on the peripheral circuit region 30. In addition to the above features, Figure 12 The semiconductor memory device 1000e may have the same Figures 2 to 4 Essentially the same features as described.

[0084] Figure 13 is a conceptual diagram illustrating a semiconductor memory device according to example embodiments of the inventive concept. Figure 14 is a cross-sectional view illustrating a semiconductor memory device according to example embodiments of the inventive concepts.

[0085] Reference Figure 13 and Figure 14 In the semiconductor memory device 1000f according to the present embodiment, the second substrate 200 may include a core region 20 and a peripheral circuit region 30. Only the cell array region 10 may be provided on the first substrate 100. The first transistor TR1 and the first interconnection line 212 may be provided on the core region 20 of the second substrate 200. The second transistor TR2, the second interconnection line 312 and the second conductive pad 314 may be provided on the peripheral circuit region 30 of the second substrate 200. The second substrate 200 may be covered by a second interlayer insulating layer 210. The end of the bit line BL provided on the first substrate 100 may be electrically connected to some first interconnections 212 provided on the core region 20 through the first contact plug MC1. The end of the word line WL provided in the first substrate 100 may be electrically connected to other first interconnections 212 provided on the core region 20 through the second contact plug MC2. In addition to the above features, Figure 13 The semiconductor memory device 1000f may have the same Figures 2 to 4 Essentially the same features as described.

[0086] Various arrangements of the cell array region, the core region, and the peripheral circuit region of the semiconductor memory device are described above, but the present invention is not limited to these examples. Figure 2 、 Figure 11 and Figure 13 In the embodiment of the present invention, the vertical positions of the substrates 100, 200 and 300 may be changed or reversed.

[0087] In a semiconductor memory device according to an exemplary embodiment of the present invention, devices in various circuit regions can be implemented on different substrates. Consequently, devices with optimized structure and performance for each circuit region can be easily implemented, resulting in a semiconductor memory device with improved reliability. Furthermore, core regions corresponding to cell array regions can be provided on the cell array regions, thereby reducing the planar size. Consequently, the form factor of the semiconductor memory device can be reduced. Furthermore, the degree of freedom in designing the semiconductor memory device can be increased.

[0088] A method for manufacturing a semiconductor memory device according to an exemplary embodiment of the present inventive concept may include forming devices having different required characteristics on different substrates, stacking the substrates, and connecting the substrates. This can prevent interference between different regions. Furthermore, this can simplify the overall process for manufacturing the semiconductor memory device and reduce process failures. Furthermore, the device can be easily optimized to have the electrical characteristics required by each circuit region.

[0089] While example embodiments of the present inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device comprising: a first substrate including a cell array region; a first interlayer insulating layer covering a top surface of the first substrate; a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region; a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate; as well as first contact plugs and second contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region, The bottom surface of the first contact plug is located above the top surface of the first substrate, and the bottom surface of the second contact plug is located below the top surface of the first substrate.

2. The semiconductor memory device according to claim 1 , further comprising: word lines disposed on the cell array region to be parallel to each other; bit lines disposed on the cell array region to cross the word lines and be parallel to each other; a word line driver disposed on the core region to apply an electrical signal to the word line; as well as a sense amplifier provided on the core region to apply an electrical signal to the bit line, The first contact plug connects the sense amplifier to an end of the bit line; and the second contact plug connects the word line driver to an end of the word line.

3. The semiconductor memory device according to claim 2, in, The word lines are buried in the first substrate, and Wherein, the bit line is arranged on the first substrate.

4. The semiconductor memory device according to claim 1, wherein The second substrate contacts the first adhesive insulating layer.

5. The semiconductor memory device according to claim 1, wherein The second substrate further includes a peripheral circuit region electrically connected to the core region.

6. The semiconductor memory device according to claim 1, further comprising: A third substrate is provided on the second substrate, wherein the third substrate includes a peripheral circuit region electrically connected to the core region.

7. The semiconductor memory device according to claim 6, further comprising: a first transistor disposed on the second substrate; as well as a second transistor provided on the third substrate, wherein the first transistor is a low voltage transistor, and Wherein, the second transistor is a high-voltage transistor.

8. The semiconductor memory device according to claim 7, wherein The density of the first transistors on the second substrate is greater than the density of the second transistors on the third substrate.

9. The semiconductor memory device according to claim 6, further comprising: a first transistor disposed on the second substrate; as well as a second transistor provided on the third substrate, Wherein, the first transistor includes a first gate insulating layer, Wherein, the second transistor includes a second gate insulating layer, and The first gate insulating layer is thinner than the second gate insulating layer.

10. The semiconductor memory device according to claim 6, further comprising: a second interlayer insulating layer covering the second substrate; as well as a third interlayer insulating layer covering the third substrate, Wherein, the second interlayer insulating layer contacts the third interlayer insulating layer.

11. The semiconductor memory device according to claim 10, further comprising: a first interconnection line disposed in the second interlayer insulating layer; a second interconnection line disposed in the third interlayer insulating layer; as well as A conductive structure penetrates the third substrate, the third interlayer insulating layer, and a portion of the second interlayer insulating layer and contacts both the first interconnection line and the second interconnection line.

12. The semiconductor memory device according to claim 6, further comprising: a second interlayer insulating layer covering the second substrate; a second adhesive insulating layer interposed between the second interlayer insulating layer and the third substrate; as well as An upper contact plug penetrates the third substrate, the second adhesive insulating layer, and a portion of the second interlayer insulating layer to electrically connect the peripheral circuit region to the core region.

13. A semiconductor device comprising: a first substrate including a cell array region; a second substrate disposed on a top surface of the first substrate, the second substrate including a core region electrically connected to the cell array region; a third substrate provided on the second substrate, the third substrate including a peripheral circuit region electrically connected to the core region; an adhesive insulating layer interposed between the first substrate and the second substrate; first and second contact plugs penetrating the second substrate and the adhesive insulating layer and electrically connecting the cell array region to the core region, The bottom surface of the first contact plug is located above the top surface of the first substrate, and the bottom surface of the second contact plug is located below the top surface of the first substrate.

14. The semiconductor device according to claim 13, further comprising: a first transistor disposed on the second substrate; as well as a second transistor provided on the third substrate, wherein the first transistor is a low voltage transistor, and Wherein, the second transistor is a high-voltage transistor.

15. The semiconductor device according to claim 13, further comprising: a first transistor disposed on the second substrate; as well as a second transistor provided on the third substrate, Wherein, the first transistor includes a first gate insulating layer, Wherein, the second transistor includes a second gate insulating layer, and The first gate insulating layer is thinner than the second gate insulating layer.

16. The semiconductor device according to claim 13, further comprising: A connection member is interposed between the second substrate and the third substrate to electrically connect the core region to the peripheral circuit region.

17. A semiconductor memory device comprising: a first substrate including a cell array region; a first interlayer insulating layer covering a top surface of the first substrate; a second substrate disposed on the first interlayer insulating layer, the second substrate including a logic region electrically connected to the cell array region; a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate; as well as first contact plugs and second contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region to the logic region, The bottom surface of the first contact plug is located above the top surface of the first substrate, and the bottom surface of the second contact plug is located below the top surface of the first substrate.

18. The semiconductor memory device according to claim 17, in, The logic area includes a core area and a peripheral circuit area, and Wherein, the semiconductor memory device comprises: word lines disposed on the cell array region and parallel to each other; bit lines disposed on the cell array region to cross the word lines and be parallel to each other; a word line driver provided on the core region to apply an electrical signal to the word line; and a sense amplifier provided on the core region to apply an electrical signal to the bit line, and The first contact plug connects the sense amplifier to an end of the bit line; and the second contact plug connects the word line driver to an end of the word line.

19. The semiconductor memory device according to claim 17, further comprising: a third substrate disposed on the second substrate, wherein the logic region includes a core region, and The third substrate includes a peripheral circuit region electrically connected to the core region.

20. A method of manufacturing a semiconductor memory device, comprising: Manufacturing a first wafer having a chip region and a scribe lane region, wherein the first wafer includes a first substrate and a first interlayer insulating layer covering a top surface of the first substrate; preparing a second wafer, wherein the second wafer includes a second substrate; forming a first preliminary adhesive insulating layer on the first wafer; forming a second preliminary adhesive insulating layer on the second wafer; placing the second wafer on the first wafer so that the first preliminary adhesive insulating layer contacts the second preliminary adhesive insulating layer; converting the first preliminary adhesive insulating layer and the second preliminary adhesive insulating layer into adhesive insulating layers; forming a first contact plug and a second contact plug, wherein the first contact plug and the second contact plug penetrate the second substrate and the adhesive insulating layer, wherein a bottom surface of the first contact plug is located above a top surface of the first substrate, and a bottom surface of the second contact plug is located below the top surface of the first substrate; as well as A first transistor and a first interconnection line are formed on the second wafer.

21. The method according to claim 20, wherein Fabricating the first wafer includes forming word lines and bit lines on the chip region and forming alignment keys on the scribe street region.

22. The method according to claim 20, in, The step of preparing the second wafer includes forming a semiconductor epitaxial layer on a single crystal semiconductor substrate. The single crystal semiconductor substrate and the semiconductor epitaxial layer are doped with first impurities, and The concentration of the first impurity doped in the single crystal semiconductor substrate is different from the concentration of the first impurity doped in the semiconductor epitaxial layer.

23. The method according to claim 22, further comprising: Before forming the second preliminary bonding insulating layer on the second wafer, an edge portion of the semiconductor epitaxial layer is removed to expose the single crystal semiconductor substrate.

24. The method according to claim 23, further comprising: Before forming the first transistor and the first interconnection line on the second wafer, the single crystal semiconductor substrate is removed.

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