Defect inspection apparatus and defect inspection method

Abstract

An embodiment provides a defect inspection apparatus and a defect inspection method capable of shortening inspection time in defect inspection of semiconductor manufacturing. The defect inspection apparatus according to the embodiment includes an acquisition unit, a clipping unit, a first number assignment unit, a matching unit, and a verification unit. The acquisition unit acquires electronic information representing a pattern developed on a wafer. The clipping unit clips a portion corresponding to the electronic information in the figure shown in the design data to obtain design information. The first number assignment unit assigns a first number to each pattern shown in the electronic information and assigns a second number to each pattern shown in the design information. The matching unit creates relationship information indicating the correspondence between the first number and the second number. The verification unit verifies whether the pattern shown in the electronic information includes a defect on the circuit of the wafer based on the relationship information and node information corresponding to each pattern shown in the design information.

Description

[0001] [Related Application]

[0002] This application claims priority based on Japanese Patent Application No. 2018-171609 (filing date: September 13, 2018). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a defect inspection apparatus and a defect inspection method. Background Art

[0004] As a method for defect inspection in semiconductor manufacturing processes, conventionally, SEM (Scanning Electron Microscope) images etc. are acquired during the process, and visual inspection is performed on them by an operator.

[0005] On the other hand, in order to inspect the electrical influence of defects, it is necessary to determine the generation location and type of defects, and check which part of the semiconductor circuit becomes defective, which requires a lot of time.

[0006] In addition, there is also known a method called Die To Database, which discovers defects by obtaining the difference between image data based on a design pattern (design) obtained using CAD (Computer-Aided Design) and the acquired SEM image.

[0007] However, since the pattern of the SEM image developed on the wafer is, for example, greatly affected by the exposure conditions during pattern formation, it is difficult to be exactly the same as the design pattern. Therefore, it is also difficult to accurately extract only the truly problematic defect part as the difference.

[0008] Furthermore, a method of creating CAD data based on the acquired SEM image and checking the CAD data against circuit data is also considered. Generally, the range of the area that can be acquired using the SEM image is limited, so depending on the wiring connection status of the area not included in the SEM image, the criticality of the defect is different. Therefore, it is necessary to check the entire chip, which requires a lot of time. Summary of the Invention

[0009] Embodiments provide a defect inspection apparatus and a defect inspection method capable of shortening the inspection time in defect inspection in semiconductor manufacturing.

[0010] The defect inspection device of the embodiment includes an acquisition unit, a clipping unit, a first numbering unit, a matching unit, and a verification unit. The acquisition unit acquires electronic information representing patterns developed on a wafer. The clipping unit clips the part corresponding to the electronic information in the figure shown in the design data to obtain design information. The first numbering unit assigns a first number to each pattern shown in the electronic information and assigns a second number to each pattern shown in the design information. The matching unit creates relationship information indicating the correspondence between the first number and the second number. The verification unit verifies whether the patterns shown in the electronic information contain defects on the circuit of the wafer based on the relationship information and the node information corresponding to each pattern shown in the design information.

[0011] In addition, it may further include a conversion unit that obtains conversion information obtained by converting the electronic information acquired by the acquisition unit into CAD (Computer Aided Design) data, and the first numbering unit assigns a first number to each pattern shown in the conversion information, and the verification unit verifies whether the patterns shown in the conversion information contain defects on the circuit of the wafer based on the relationship information and the node information.

[0012] In addition, it may further include a classification unit that classifies the defect types of the conversion information based on the content of the relationship information created by the matching unit, and the verification unit verifies whether the patterns shown in the conversion information contain defects on the circuit of the wafer according to the defect types classified by the classification unit.

[0013] In addition, it may further include a second numbering unit that assigns a node number as node information to each pattern shown in the design information, and the verification unit verifies whether the patterns shown in the conversion information contain defects on the circuit of the wafer based on the relationship information and the node number.

[0014] In addition, when the classification unit shows that the defect type of the conversion information is a short - circuit state, the verification unit specifies the pattern in the design information corresponding to the pattern in the conversion information in the short - circuit state according to the relationship information, and verifies whether the patterns shown in the conversion information contain defects on the circuit of the wafer according to the correspondence between the specified pattern in the design information and the node number.

[0015] In addition, it may further include: a replacement unit that extracts, as replacement information, a specific range including the conversion information from data obtained by replacing a part corresponding to the conversion information in the pattern shown in the design data with the conversion information; and an execution unit that performs LVS (Layout Versus Schematic) on a part or all of the schematic data of the wafer and the design data, and when the defect type indicated by the classification unit for the conversion information is an open state, the verification unit verifies whether the pattern indicated by the conversion information includes a defect on the circuit of the wafer based on the result of the LVS performed by the execution unit using the replacement information extracted by the replacement unit and the schematic data.

[0016] In addition, the execution unit may also generate node numbers corresponding to each pattern shown in the design data by pre-performing LVS on the schematic data and all the design data, and the second assignment unit assigns the node numbers generated by the execution unit to each pattern shown in the design information.

[0017] In addition, a defect inspection device according to another embodiment includes an acquisition unit, an assignment unit, a matching unit, and a classification unit. The acquisition unit acquires electronic information representing a pattern developed on a wafer. The assignment unit assigns a first number to each pattern shown in the electronic information, and assigns a second number to each pattern shown in the design information, which is a part corresponding to the electronic information in the pattern shown in the design data. The matching unit creates relationship information indicating the correspondence between the first number and the second number. The classification unit classifies the defect types of the electronic information based on the content of the relationship information created by the matching unit.

[0018] In addition, a defect inspection device according to another embodiment includes an acquisition unit, an assignment unit, a matching unit, and a verification unit. The acquisition unit acquires electronic information representing a pattern developed on a wafer. The assignment unit assigns a first number to each pattern shown in the electronic information, and assigns a second number to each pattern shown in the design information, which is a part corresponding to the electronic information in the pattern shown in the design data. The matching unit creates relationship information indicating the correspondence between the first number and the second number. The verification unit verifies whether the pattern shown in the electronic information includes a defect on the circuit of the wafer based on the node numbers corresponding to each pattern shown in the relationship information and the design information. Description of the Drawings

[0019] Figure 1 (a), 1(b), and 1(c) are diagrams for explaining the difference between the SEM image and the image based on the CAD design data.

[0020] Figure 2 is a diagram for explaining the LVS (verification operation) performed on the entire chip.

[0021] Figure 3 is a diagram showing an example of the overall configuration of the SEM device according to the embodiment.

[0022] Figure 4 This is a diagram showing the hardware configuration example of the controller of the embodiment.

[0023] Figure 5 This is a diagram showing the functional block configuration example of the controller of the embodiment.

[0024] Figure 6 (a), 6(b), 6(c) are diagrams showing examples of converting the SEM image of the embodiment into CAD.

[0025] Figure 7 (a), 7(b) are diagrams showing examples of replacing the SEM image in the design CAD of the embodiment.

[0026] Figure 8 This is a diagram for explaining the normal operation of the LVS of the SEM device of the embodiment.

[0027] Figure 9 This is a diagram for explaining the node numbers of the SEM device of the embodiment.

[0028] Figure 10 This is a flowchart of the overall process including the defect inspection process of the embodiment.

[0029] Figure 11 This is a flowchart of the defect inspection process of the SEM device of the embodiment.

[0030] Figure 12 (a), 12(b), 12(c), 12(d) are diagrams showing the operation of assigning graphic numbers to the SEM device of the embodiment.

[0031] Figure 13 (a), 13(b), 13(c), 13(d) are diagrams for explaining the types of defects of the SEM device of the embodiment.

[0032] Figure 14 (a), 14(b), 14(c), 14(d) are diagrams for explaining the matching of the SEM device of the embodiment.

[0033] Figure 15 (a), 15(b), 15(c), 15(d), 15(e) are diagrams for explaining the matching of the SEM device of the embodiment.

[0034] Figure 16 (a), 16(b), 16(c), 16(d), 16(e) are diagrams for explaining the matching of the SEM device of the embodiment.

[0035] Figure 17It is a flowchart for classifying defect types of the SEM device according to the embodiment.

[0036] Figure 18 It is a flowchart for circuit verification of the SEM device according to the embodiment.

[0037] Figure 19 (a), 19(b), 19(c), 19(d), 19(e) are diagrams for explaining the circuit verification of the SEM device according to the embodiment.

[0038] Figure 20 (a), 20(b), 20(c) are diagrams for explaining the circuit verification of the SEM device according to the embodiment.

[0039] Figure 21 (a), 21(b), 21(c) are diagrams for explaining the circuit verification of the SEM device according to the embodiment.

[0040] Figure 22 (a), 22(b), 22(c) are diagrams for explaining the circuit verification of the SEM device according to the embodiment.

[0041] Figure 23 (a), 23(b), 23(c), 23(d), 23(e) are diagrams for explaining the defect types of the SEM device according to the variation example of the embodiment.

[0042] Figure 24 (a), 24(b), 24(c), 24(d), 24(e), 24(f) are diagrams for explaining the circuit verification of the SEM device according to the variation example of the embodiment. Specific Embodiments

[0043] Hereinafter, with reference to the accompanying drawings, the SEM device according to the embodiment will be described in detail. In addition, these embodiments are examples, and the present invention is not limited to these embodiments.

[0044] Figure 1 It is a diagram for explaining the difference between the SEM image and the image based on the CAD design data. While referring to Figure 1 , the error included in the difference between the SEM image and the designed CAD will be explained.

[0045] Figure 1 (a) shows the SEM image 500, which is obtained by irradiating an electron beam from an electron source toward the wafer in the SEM device and detecting secondary electrons emitted from the wafer in order to inspect circuit defects in the chips on the wafer on which various semiconductor parts are mounted. In addition, Figure 1 (a) The image shown schematically shows the actual SEM image, and here, for convenience, it is called the SEM image. AsFigure 1 As shown by the dashed line in (a), the SEM image 500 contains defects on the circuit.

[0046] In addition, an image corresponding to the SEM image 500 based on the data obtained from CAD design (referred to as design CAD 510) is shown in Figure 1 (b). In theory, by extracting the difference between the SEM image 500 shown in Figure 1 (a) and the design CAD 510 shown in Figure 1 (b), an image representing only the defective part can be extracted. However, as described above, the pattern of the wafer shown in the SEM image is greatly affected by the exposure conditions during pattern formation. Therefore, in practice, as shown in the difference image 550 in Figure 1 (c), parts unrelated to the defective part are also extracted as differences (errors). In this way, it is difficult to make the design pattern (design CAD) and the pattern of the wafer shown in the SEM image exactly match outside the defective part. Therefore, it is difficult to accurately extract only the defective part as a difference with good precision.

[0047] Figure 2 This is a diagram for explaining a method of defect inspection for the entire chip, namely LVS (Layout Versus Schematic). While referring to the example in Figure 2 , the case where there are defects in the local pattern of the SEM image and LVS is performed on the entire chip will be described.

[0048] LVS refers to an operation or tool for checking whether there are no circuit inconsistencies between the schematic data obtained by designing the circuit of the wafer chip and the design pattern (design CAD) created for creating the pattern. In the description of this embodiment, the term LVS is used to represent the checking operation.

[0049] In the Figure 2 wiring pattern, the obtained SEM image 501 shows the state of the wiring (white background pattern) with a local short circuit. In this SEM image 501, it seems that the upper wiring 601 and the lower wiring 602 are short-circuited in the central part of the SEM image 501. However, it is possible that, as shown on the left side of Figure 2 , the two wirings outside the field of view of the SEM image 501 are continuously formed via the wiring 603. Or, alternatively, it is also possible that, as shown on the right side of Figure 2 , the wiring 611 on the same layer as the upper wiring of the SEM image 501 and the wiring 612 on the same layer as the lower wiring of the SEM image 501 are not formed continuously with each other as in the example described on the left side of Figure 2 , but for example, each wiring is connected via the vias 611a and 612a and via the wiring 621.

[0050] In this way, LVS is performed using the replacement image obtained by replacing the portion corresponding to the SEM image 501 in the design pattern (design CAD) of the entire chip with the SEM image 501 and the schematic data defining the circuit connection state of the entire chip, whereby it is possible to determine whether the defect (short circuit) on the SEM image 501 is an actually fatal defect. In Figure 2 cases where the upper and lower wirings on the SEM image 501 are formed continuously with each other or are connected via other wirings such as lower-layer wirings. These cases are all equivalent to short circuits, and even if it is determined to be in a short-circuit state when judged from the SEM image 501, it is still determined that there is no problem in operation and it is not a fatal defect for the entire chip.

[0051] However, since performing LVS on the entire chip as described above requires a large amount of time, it is not practical to perform LVS for each SEM image as a defect inspection. Hereinafter, in the present embodiment, the configuration and operation of the SEM apparatus capable of shortening the inspection time in semiconductor manufacturing defect inspection will be described.

[0052] Figure 3 is a diagram showing an example of the overall configuration of the SEM apparatus according to the embodiment. While referring to Figure 3 , the overall configuration of the SEM apparatus 1 of the present embodiment will be described.

[0053] As Figure 3 shown, the SEM apparatus 1 of the present embodiment includes an electron gun column 11, a stage 21, a detector 23, a controller 31, a signal processing circuit 32, a monitor 33, an image storage unit 34, a column control circuit 35, a stage drive control circuit 36, a coordinate storage unit 37, and a recipe file storage unit 38.

[0054] The electron gun column 11 is a device that irradiates an electron beam EB onto a specimen (e.g., a wafer 22 on the stage 21). The electron gun column 11 includes an electron source 12, a magnetic field lens 13, and a scanning coil 14 inside thereof.

[0055] The electron source 12 is a device that irradiates an electron beam EB by heating a filament made of tungsten or the like.

[0056] The magnetic field lens 13 is a lens that includes a wire wound in a coil shape and a magnetic yoke surrounding the periphery of the wire, and generates magnetic force lines for rotating an object by the current flowing in the wire, and adjusts the thickness of the electron beam EB irradiated from the electron source 12.

[0057] The scanning coil 14 is a coil that scans the electron beam EB irradiated from the electron source 12 and adjusted in thickness by the magnetic field lens 13 on the specimen.

[0058] The stage 21 is a platform for placing specimens such as a wafer 22 that is the irradiation target of the electron beam EB. In addition to performing in-plane movement (X-axis, Y-axis) and vertical movement (Z-axis), the stage 21 performs actions such as tilting of the placement surface and rotation of the placement surface, for example.

[0059] The detector 23 is a device that detects secondary electrons SE emitted from the wafer 22 by irradiating the wafer 22 with the electron beam EB from the electron source 12.

[0060] The controller 31 is a controller responsible for the overall control of the SEM apparatus 1. Specifically, the controller 31 controls the signal processing circuit 32, the monitor 33, and the image storage unit 34, and performs a defect inspection process using the SEM image (an example of an electron image) generated by the signal processing circuit 32.

[0061] The signal processing circuit 32 is a circuit that, according to the control of the controller 31, detects the amount of secondary electrons detected by the detector 23, thereby generating one image (SEM image). The SEM image generated by the signal processing circuit 32 is stored in the image storage unit 34. Such an SEM image can be generated, for example, in a manner that covers the entire wafer chip with all images, or a pattern abnormal part can be specified in advance using an optical inspection apparatus, and an image can be generated for the area including its coordinates. Alternatively, a main detection part can be preset (for example, a part that is likely to have circuit defects or a part with a high pattern density based on past experience or previous processes), and an image can be generated for the detection part.

[0062] The monitor 33 is a display device such as a CRT (Cathode Ray Tube) monitor, a liquid crystal display, or an organic EL (Electro Luminescence) display that displays the SEM image generated by the signal processing circuit 32 and the like.

[0063] The image storage unit 34 is a storage device that stores the SEM image generated by the signal processing circuit 32. The image storage unit 34 is, for example, a device such as an HDD (Hard Disk Drive), an SSD (Solid State Drive), a flash memory, or an optical disc that can perform storage electrically, magnetically, or optically. In addition, the image storage unit 34 may store not only SEM images, but also, for example, design pattern (design CAD) data and schematic data of the chip. Additionally, at least any one of the SEM image, the design pattern (design CAD), and the schematic data may be stored in an external device outside the SEM apparatus 1.

[0064] The column control circuit 35 is a circuit that controls the operation of the electron gun column 11 according to the control of the controller 31. For example, the column control circuit 35 controls the verification operation of the electron beam using the electron source 12, the adjustment operation of the electron beam using the magnetic lens 13, and the scanning operation of the electron beam using the scanning coil 14, etc.

[0065] The stage drive control circuit 36 is a circuit that controls the operation of the stage 21 on which the wafer 22 is placed according to the control of the controller 31. For example, the stage drive control circuit 36 controls operations such as the movement in the plane of the stage 21 (X-axis, Y-axis), the vertical movement (Z-axis), the inclination of the placement surface, and the rotation of the placement surface.

[0066] The coordinate storage unit 37 is a storage device that stores coordinate data, which specifies the coordinates on the stage 21 (wafer 22) where the electron beam EB is irradiated, or the coordinates for driving the stage 21, etc. The coordinate storage unit 37 is, for example, a device such as an HDD, SSD, flash memory, or optical disc that stores data electrically, magnetically, or optically.

[0067] The recipe file storage unit 38 is a storage device that stores a recipe file, which specifies measurement points and measurement conditions, etc., for irradiating the electron beam EB on the stage 21 to obtain an SEM image. The recipe file storage unit 38 is, for example, a device such as an HDD, SSD, flash memory, or optical disc that stores data electrically, magnetically, or optically.

[0068] In addition, in Figure 3 the example shown, for convenience, the image storage unit 34, the coordinate storage unit 37, and the recipe file storage unit 38 are illustrated as different storage devices, but it is not limited to this, and it may also be composed of one storage device. In addition, at least any one of the image storage unit 34, the coordinate storage unit 37, and the recipe file storage unit 38 may be provided in an external device outside the SEM apparatus 1.

[0069] In addition, Figure 3 the configuration of the SEM apparatus 1 shown represents an example, and for example, it may also include constituent elements other than Figure 3 the constituent elements shown.

[0070] Figure 4 is a diagram showing an example of the hardware configuration of the controller according to the embodiment. While referring to Figure 4 , the hardware configuration of the controller 31 according to this embodiment will be described.

[0071] As Figure 4As shown, the controller 31 includes a CPU (Central Processing Unit) 101, a ROM (Read Only Memory) 102, a RAM (Random Access Memory) 103, an input / output I / F (Interface) 104, and a control circuit I / F 105. Each device is connected in such a way that they can communicate with each other via a bus.

[0072] The CPU 101 is an arithmetic device that controls the operations of the entire controller 31 and, further, the entire SEM device 1. The ROM 102 is a non-volatile storage device that stores programs such as firmware executed by the CPU 101 to control various functions. The RAM 103 is a volatile storage device used as the working area of the CPU 101.

[0073] The input / output I / F 104 is an interface for data input / output between the controller 31 and external storage devices (image storage unit 34, coordinate storage unit 37, and recipe file storage unit 38).

[0074] The control circuit I / F 105 is an interface for exchanging control data including operation instructions between the signal processing circuit 32, the column control circuit 35, and the stage drive control circuit 36.

[0075] In addition, Figure 4 The hardware configuration of the controller 31 shown represents an example and may also include components other than Figure 4 the components shown. For example, when data communication is performed between the SEM device 1 and an external device, a network I / F corresponding to communication protocols such as TCP (Transmission Control Protocol) / IP (Internet Protocol) or UDP (User Datagram Protocol) / IP may also be provided.

[0076] Figure 5 is a diagram showing an example of the functional block configuration of the controller according to the embodiment. Figure 6 is a diagram showing an example of converting the SEM image according to the embodiment into CAD. Figure 7 is a diagram showing an example of replacing with the SEM image in the design CAD according to the embodiment. Figure 8 is a diagram for explaining the normal operation of the LVS of the SEM device according to the embodiment. Figure 9 is a diagram for explaining the node numbers of the SEM device according to the embodiment. While referring to Figures 5 - 9, while explaining the configuration of the functional blocks of the controller 31 of the SEM apparatus 1 of the present embodiment.

[0077] As Figure 5 shown, the controller 31 of the present embodiment includes a first acquisition unit 201 (acquisition unit), a second acquisition unit 202, a clipping unit 203, a conversion unit 204, a replacement unit 205, an LVS execution unit 206 (execution unit), a first assignment unit 207 (assignment unit), a matching unit 208, a classification unit 209, a second assignment unit 210, and a circuit verification unit 211.

[0078] The first acquisition unit 201 is a functional unit that acquires an SEM image representing a local pattern on a wafer generated by the signal processing circuit 32 and stored in an external storage unit 220. The first acquisition unit 201 is implemented by executing a program of the CPU 101 as Figure 4 shown, and the input / output I / F 104. In addition, the storage unit 220 is implemented by, for example, the image storage unit 34 as Figure 3 shown. Further, the storage unit 220 can be provided by an external device outside the SEM apparatus 1. In this case, the first acquisition unit 201 only needs to acquire the SEM image from the external device via the network I / F.

[0079] The second acquisition unit 202 is a functional unit that acquires design CAD data (an example of design data) stored in an external storage unit 220. The second acquisition unit 202 is implemented by executing a program of the CPU 101 as Figure 4 shown, and the input / output I / F 104.

[0080] The clipping unit 203 is a functional unit that clips a portion of the pattern shown in the design CAD data of the entire chip acquired by the second acquisition unit 202 that corresponds to the SEM image acquired by the first acquisition unit 201. Hereinafter, the graphical portion of the design CAD data corresponding to the SEM image clipped by the clipping unit 203 may sometimes be simply referred to as "design CAD" (an example of design information).

[0081] The conversion unit 204 is a functional unit that converts the SEM image acquired by the first acquisition unit 201 into CAD data. For example, the conversion unit 204 binarizes the SEM image 502 shown in Figure 6 (a) with a specific luminance value as a boundary to generate the binarized image 552 shown in Figure 6 (b). Then, the conversion unit 204 converts from the binarized image 552 into the CAD data (defect CAD 522) shown in Figure 6 (c). In addition, hereinafter, the CAD data converted from the SEM image by the conversion unit 204 may sometimes be referred to as "conversion CAD" (an example of conversion information).

[0082] The replacement unit 205 is a functional unit that replaces, in the figure shown in the design CAD data of the entire chip acquired by the second acquisition unit 202, the part corresponding to the converted CAD obtained by the conversion performed by the conversion unit 204 with the converted CAD. Hereinafter, the CAD data obtained by the following method may sometimes be referred to as "replacement CAD", and the method refers to replacing, with the converted CAD, the part corresponding to the converted CAD in the figure shown in the design CAD data of the entire chip. For example, the replacement unit 205 obtains by replacing, in the figure shown in the design CAD data, the part corresponding to the defective CAD 522 (converted CAD) shown in Figure 7 (a) with the defective CAD 522 to obtain Figure 7 (b) the replacement CAD 532 shown.

[0083] The LVS execution unit 206 is a functional unit that executes LVS, which checks whether the schematic data obtained by designing the circuit of the wafer chip is consistent with the CAD data (such as design CAD data) in terms of the circuit. As Figure 8 shown, the LVS execution unit 206 inputs the replacement CAD 532, which is the CAD data to be the object of LVS, the lower-layer CAD data of the replacement CAD 532, i.e., the lower-layer CAD 512a, and the upper-layer CAD data of the replacement CAD 532, i.e., the upper-layer CAD 512b, and executes LVS using these CAD data and the schematic data.

[0084] In this way, by using the LVS execution unit 206 to execute LVS between the schematic data and the design CAD data corresponding to the entire chip, an AGF (Added Node GDS File, an added node GDS (General Data Stream) file) that is given information indicating whether the respective wiring patterns shown in the design CAD data are electrically connected to each other can be obtained. In the AGF, when multiple wiring patterns on the design CAD data are electrically connected (shorted) at any position on the chip, they are associated with the same number (node number) (an example of node information). By grasping the conduction (short circuit) state of the respective wiring patterns of the design CAD data through the AGF, for example, as Figure 9 shown, it is possible to assign node numbers ([[]] Figure 9 A1 to A6 in the figure) indicating the wiring patterns that are electrically connected (shorted) to the respective wiring patterns shown in the design CAD 513 cut out from the design CAD data.

[0085] The first number-assigning unit 207 is a functional unit that assigns numbers (graphic numbers) (first number, second number) to each wiring pattern of the converted CAD obtained by the conversion unit 204 and each wiring pattern of the design CAD obtained by the clipping unit 203 in any order to determine the defect type of the following converted CAD.

[0086] The matching unit 208 is a functional unit that correlates (matches) the wiring patterns of the converted CAD and the wiring patterns of the design CAD using the assigned graphic numbers.

[0087] The classification unit 209 is a functional unit that classifies (determines) the defect category (defect type) of the wiring pattern of the converted CAD based on the result of the matching performed by the matching unit 208. Details of what defect type it is classified into will be described below.

[0088] The second number-assigning unit 210 is a functional unit that assigns node numbers to each wiring pattern of the design CAD based on the AGF obtained by the LVS execution unit 206. Here, "assigning node numbers to each wiring pattern of the design CAD" means making each wiring pattern of the design CAD in a state associated with any node number. For example, the result of LVS is a concept that also includes the operation in the following case, which is to clip the part corresponding to the converted CAD from the design CAD data of the entire chip where node numbers are associated with each wiring pattern, thereby obtaining the design CAD associated with node numbers.

[0089] The circuit verification unit 211 is a functional unit that determines whether there is a fatal defect in the wiring pattern shown in the converted CAD using the matching result of the converted CAD and the design CAD obtained by the matching unit 208 and the node numbers assigned to the design CAD by the second number-assigning unit 210. The specific operation of the circuit verification unit 211 will be described below.

[0090] The clipping unit 203, conversion unit 204, replacement unit 205, LVS execution unit 206, first number-assigning unit 207, matching unit 208, classification unit 209, second number-assigning unit 210, and circuit verification unit 211 are implemented by the CPU 101 shown in Figure 4 executing software, that is, a program. In addition, part or all of the above functional units can also be implemented by a hardware circuit such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit) instead of executing a program.

[0091] In addition, Figure 5Each functional part of the controller 31 shown conceptually represents a function and is not limited to this configuration. For example, it is also possible to configure multiple functional parts shown as independent functional parts in the Figure 5 shown controller 31 in the form of one functional part. On the other hand, it is also possible to use the Figure 5 shown controller 31 to divide the functions of one functional part into multiple ones and configure them as multiple functional parts.

[0092] Figure 10 is a flowchart of the overall process including the defect inspection process of the embodiment. While referring to Figure 10 , an overview of the overall process of the semiconductor manufacturing process including the defect inspection process using the SEM device 1 of the present embodiment will be described.

[0093] (Step S11)

[0094] Perform the pre-process (Process A) before the inspection process in the semiconductor manufacturing process. In Process A, for example, after performing wafer cleaning, oxidation, diffusion, and film formation, a circuit pattern or the like is formed by photolithography. Then, move to Step S12.

[0095] (Step S12)

[0096] Perform an inspection process for inspecting and measuring the wafer on which the circuit pattern (wiring pattern) is formed. In the inspection process, for example, perform the following operations on the circuit pattern formed on the wafer: defect inspection, detecting abnormal patterns based on the differential image of the optical image or SEM image obtained from adjacent identical patterns; and detecting process abnormalities based on the measurement of the line width and aperture of the circuit pattern and the measurement of the wafer film thickness. In addition, in the inspection process, the electron gun column 11, the detector 23, and the signal processing circuit 32 can also be used to generate an SEM image of the target part on the wafer and store it in the storage unit 220. In addition, in this step, the LVS execution unit 206 can also perform LVS of the schematic data and the design CAD data corresponding to the entire chip in advance to obtain the AGF. Then, move to Step S13.

[0097] (Step S13)

[0098] Perform a defect re-inspection process, which is to check whether the circuit pattern formed on the wafer is defective in the circuit according to the designed connection relationship. The defect re-inspection process corresponds to the defect inspection process using the SEM device 1 of the present embodiment. The detailed situation of the defect inspection process will be described below. Then, move to Step S14.

[0099] (Step S14)

[0100] The subsequent process (Process B) after the defect reinspection process. In Process B, for example, cutting and encapsulation are performed. The cutting chips the integrated circuits formed on the wafer, etc., and the encapsulation includes processes that facilitate the protection of the chips carrying the integrated circuits cut by the cutting and the connection with the peripheral circuits. After this subsequent process is completed, the semiconductor manufacturing process is completed.

[0101] In addition, the processes in each of the above steps are examples. Of course, there may be other processes or steps included, and there may be cases where the processes are repeated multiple times.

[0102] Figure 11 It is a flowchart of the defect inspection process of the SEM device according to the embodiment. Figure 12 It is a diagram showing the operation of assigning graphic numbers to the SEM device according to the embodiment. Figure 13 It is a diagram for explaining the types of defects of the SEM device according to the embodiment. Figure 14 It is a diagram for explaining the matching of the SEM device according to the embodiment. Figure 15 It is a diagram for explaining the matching of the SEM device according to the embodiment. Figure 16 It is a diagram for explaining the matching of the SEM device according to the embodiment. While referring to Figures 11 - 16 , the flow of the defect inspection process in the SEM device 1 of the present embodiment will be described. In addition, the LVS of the schematic data and the design CAD data corresponding to the entire chip is pre-executed by the LVS execution unit 206 to obtain the AGF.

[0103] (Step S131)

[0104] The first acquisition unit 201 of the SEM device 1 acquires an SEM image representing a local pattern on the wafer generated by the signal processing circuit 32 stored in the external storage unit 220. The second acquisition unit 202 of the SEM device 1 acquires the design CAD data of the wafer that is the object of the defect inspection process from the external storage unit 220. The clipping unit 203 of the SEM device 1 clips the part of the graphic shown in the design CAD data of the entire chip acquired by the second acquisition unit 202 corresponding to the SEM image acquired by the first acquisition unit 201 to obtain the design CAD. Then, after confirming that step S132 is completed, it proceeds to step S133.

[0105] (Step S132)

[0106] Simultaneously with the process of step S131, the conversion unit 204 of the SEM device 1 converts the SEM image acquired by the first acquisition unit 201 into CAD data to obtain the converted CAD. Then, after confirming that step S131 is completed, it proceeds to step S133.

[0107] (Step S133)

[0108] In order to determine the defect type of the converted CAD described below, the first assigning unit 207 of the SEM device 1 assigns numbers (pattern numbers) in an arbitrary order to each wiring pattern of the converted CAD obtained by the converting unit 204 and each wiring pattern of the design CAD obtained by the editing unit 203 .

[0109] For example, the first granting unit 207 Figure 12 (a) is converted from the SEM image 504 shown in Figure 12 (b) shows the wiring pattern of the conversion CAD 524. Figure 12 (c) Assign graphic numbers (D1 to D7). Similarly, the first assigning unit 207 assigns graphic numbers (G1 to G8) to each wiring pattern of the design CAD corresponding to the conversion CAD 524, that is, the design CAD 514. When assigning numbers to the wiring patterns of the conversion CAD and the design CAD, different wiring patterns are assigned different graphic numbers, but the order of the assigned graphic numbers can be arbitrary. For example, Figure 12 The wiring pattern shown by the pattern number "D3" in the conversion CAD 524 shown in (c) is judged to be the same as Figure 12 The wiring pattern shown in (d) corresponds to the pattern number "G4" in the design CAD 514, but the pattern numbers may be different.

[0110] Here, first refer to Figure 13 , while explaining the defect types classified in the defect type classification in the following step S135. Figure 13 The design CAD 514 shown in (a) and the drawing numbers (G1 to G8) are the same as those in the Figure 12 The design shown in (c) is the same as CAD514. Figure 13 The conversion CAD 524a shown in (b) is assigned pattern numbers D1 to D9. Compared with the design CAD 514, the wiring pattern shown by pattern number D9 is redundantly present, so it is classified as the defect type of "island". Figure 13 The conversion CAD 524b shown in (c) is assigned pattern numbers D1 to D7 and has a wiring pattern of pattern number D2, as if the wiring pattern of pattern number G2 in the design CAD 514 is short-circuited with the wiring pattern of pattern number G3, so it is classified as a defect type of "short circuit". Figure 13 The conversion CAD 524c shown in (d) is assigned pattern numbers D1 to D7, and since the wiring pattern of pattern number G7 in the design CAD 514 does not exist, it is classified as a defect type of "missing". Figure 13(e) The converted CAD524d shown is assigned graphic numbers D1 to D9. The wiring pattern with graphic number G2 in the design CAD514 is in a state where it is separated into the wiring pattern with graphic number D2 and the wiring pattern with graphic number D8, so it is classified as a defect type of "open circuit". In addition, among the defect types classified in the defect type classification in step S135, in this classification level, it is not limited to indicating that each defect type is a fatal defect on the actual circuit. The final determination of whether there is a fatal defect in the chip circuit is carried out through the circuit check in step S136.

[0111] Return to Figure 11 , and continue the explanation. After the graphic numbers are assigned by the first assignment unit 207 in step S133, it moves to step S134.

[0112] (Step S134)

[0113] The matching unit 208 of the SEM device 1 correlates (matches) the wiring pattern of the converted CAD with the wiring pattern of the design CAD using the assigned graphic numbers.

[0114] For example, when performing Figure 14 the matching of the design CAD514 assigned graphic numbers G1 to G8 shown in (a) and Figure 14 the converted CAD524e assigned graphic numbers D1 to D8 shown in (b), the matching unit 208 overlaps the design CAD514 and the converted CAD524e, and creates matrix information (an example of relationship information) as shown in Figure 14 (c) in a way that can grasp the association of the graphic numbers of the overlapping wiring patterns. In the matrix shown in Figure 14 (c), it indicates that the graphic numbers of the design CAD correspond to the same graphic numbers through the converted CAD. In addition, in this matrix, the "Σ" (the "Σ" in "Design (G)") existing in the row indicates whether there are several wiring patterns corresponding to the wiring pattern of a specific graphic number of the converted CAD (from SEM) on the design CAD (from design). On the other hand, in this matrix, the "Σ" (the "Σ" in "SEM (D)") existing in the column indicates whether there are several wiring patterns corresponding to the wiring pattern of a specific graphic number of the design CAD (from design) on the converted CAD (from SEM). In the matrix shown in Figure 14 (c), the "Σ" values of the rows are all 1, and the "Σ" values of the columns are also all 1, so the wiring pattern of the design CAD and the wiring pattern of the converted CAD correspond to each other one by one. In this case, the converted CAD is classified as a defect type of "no defect".

[0115] However, as described above, the graphic numbers assigned by the first assignment unit 207 are assigned in an arbitrary order. Therefore, it is not limited to assigning the same graphic numbers to the same wiring pattern using the design CAD and the conversion CAD. In Figure 14 In the example shown, among the wiring patterns specified by the graphic numbers of the design CAD 514 and the wiring patterns specified by the graphic numbers of the conversion CAD 524e, the graphic numbers do not match each other. However, the matrix representing the association of the graphic numbers created by the matching unit 208 for the design CAD 514 and the conversion CAD 524e becomes Figure 14 the matrix shown in (d). The "Σ" values of all rows are 1, and the "Σ" values of all columns are also 1. The wiring patterns of the design CAD and the wiring patterns of the conversion CAD are associated with each other one by one. Therefore, as the defect type, it becomes the category of "no defect".

[0116] In addition, for the sake of convenience, the information on the association of the graphic numbers created by the matching unit 208 is set to be shown in the matrix form as Figure 14 shown, but it is not limited thereto. As long as it is information specifying the association of the graphic numbers, it can be information in any form.

[0117] In addition, as shown in Figure 15 (b), the conversion CAD 524a assigned the graphic numbers (D1 to D9) includes Figure 15 the wiring pattern specified by the graphic number D9 that the design CAD 514 shown in (a) does not have as a wiring pattern. In this case, the matrix representing the association of the graphic numbers created by the matching unit 208 for the design CAD 514 and the conversion CAD 524a becomes as Figure 15 shown in (d). Figure 15 The matrix shown in (d) indicates that there is no wiring pattern in the design CAD 514 corresponding to the wiring pattern of the graphic number D9 in the conversion CAD 524a, and the "Σ" value of the row corresponding to the graphic number D9 of the conversion CAD 524a becomes 0. In this case, in the next step S135, the conversion CAD 524a is classified as the defect type of "island".

[0118] In addition, as shown in Figure 15 (c), the conversion CAD 524c assigned the graphic numbers (D1 to D7) does not have a wiring pattern corresponding to the wiring pattern of the graphic number G7 in the Figure 15 design CAD 514 shown in (a). In this case, the matrix representing the association of the graphic numbers created by the matching unit 208 for the design CAD 514 and the conversion CAD 524c becomes as Figure 15 shown in (e). Figure 15In the matrix representation shown in (e), there is no wiring pattern in the converted CAD524c corresponding to the wiring pattern of the graphic number G7 in the design CAD514, and the "Σ" value of the column corresponding to the graphic number G7 of the design CAD514 becomes 0. In this case, in the next step S135, the converted CAD524c is classified as a defect type of "omission".

[0119] In addition, as Figure 16 shown in (b), the converted CAD524b assigned with graphic numbers (D1 to D7) contains a wiring pattern of graphic number D2 such that Figure 16 the wiring pattern of graphic number G2 in the design CAD514 shown in (a) is short-circuited with the wiring pattern of graphic number G3. In this case, the matrix representing the association of the graphic numbers created by the matching unit 208 for the design CAD514 and the converted CAD524b becomes as Figure 16 shown in (d). Figure 16 The matrix shown in (d) represents that there are two wiring patterns shown by graphic numbers G2 and G3 in the design CAD514 as the wiring patterns corresponding to the wiring pattern of graphic number D2 in the converted CAD524b, and the "Σ" value of the row corresponding to the graphic number D2 of the converted CAD524b becomes 2. In this case, in the next step S135, the converted CAD524b is classified as a defect type of "short circuit".

[0120] In addition, as Figure 16 shown in (c), the converted CAD524d assigned with graphic numbers (D1 to D9) presents Figure 16 a state where the wiring pattern of graphic number G2 in the design CAD514 shown in (a) is separated into the wiring pattern of graphic number D2 and the wiring pattern of graphic number D8. In this case, the matrix representing the association of the graphic numbers created by the matching unit 208 for the design CAD514 and the converted CAD524d becomes as Figure 16 shown in (e). Figure 16 The matrix shown in (e) represents that there are two wiring patterns shown by graphic numbers D2 and D8 in the converted CAD524d as the wiring patterns corresponding to the wiring pattern of graphic number G2 in the design CAD514, and the "Σ" value of the column corresponding to the graphic number G2 of the design CAD514 becomes 2. In this case, in the next step S135, the converted CAD524b is classified as a defect type of "open circuit".

[0121] Return to Figure 11 , and continue the description. After the matching is performed by the matching unit 208 in step S134, it proceeds to step S135.

[0122] (Step S135)

[0123] The classification unit 209 of the SEM apparatus 1 classifies (determines) the defect category (defect type) of the wiring pattern of the converted CAD based on the result of the matching performed by the matching unit 208. Details of the classification operation of the defect type using this classification unit 209 will be described below.

[0124] (Step S136)

[0125] The second assignment unit 210 of the SEM apparatus 1 assigns node numbers to each wiring pattern of the design CAD based on the AGF obtained by the LVS execution unit 206. In addition, the circuit verification unit 211 of the SEM apparatus 1 determines whether there is a fatal defect in the circuit of the wiring pattern shown in the converted CAD using the matching result of the converted CAD and the design CAD obtained by the matching unit 208 and the node numbers assigned to the designed CAD by the second assignment unit 210. Details of the circuit verification operation using this second assignment unit 210 and the circuit verification unit 211 will be described below.

[0126] In the process of steps S131 to S136 as described above, the defect inspection process of the SEM apparatus 1 is executed.

[0127] Figure 17 It is a flowchart of the defect type classification of the SEM apparatus of the embodiment. While referring to Figure 17 , the process of the classification operation of the defect type ( Figure 11 step S135) in the defect inspection process of the SEM apparatus 1 of the present embodiment will be described.

[0128] (Step S1351)

[0129] The classification unit 209 of the SEM apparatus 1 statistically processes the "Σ" of the rows and the "Σ" of the columns in the matrix of the association of the graphic numbers of the specified design CAD and the converted CAD created by the matching unit 208. Then, it proceeds to step S1352.

[0130] (Step S1352)

[0131] The classification unit 209 determines whether all the "Σ" values of the rows and the "Σ" values of the columns are 1. When all the "Σ" values are 1 (step S1352: Yes), it proceeds to step 1353, and when any of the "Σ" values is other than 1 (step S1352: No), it proceeds to step S1354.

[0132] (Step S1353)

[0133] When the classification unit 209 determines that all the "Σ" values of the rows and the "Σ" values of the columns in the matrix associated with the specified graphic number are 1, it classifies the defect type of the converted CAD as "no defect". Then, it ends the classification operation of the defect type.

[0134] (Step S1354)

[0135] When the classification unit 209 determines that any of the "Σ" values in the matrix associated with the specified graphic number is other than 1, it further determines whether any of the "Σ" values contains 0. When any of the "Σ" values contains 0 (Step S1354: Yes), it proceeds to Step S1355. When it does not contain 0 (Step S1354: No), it proceeds to Step S1358.

[0136] (Step S1355)

[0137] The classification unit 209 further determines whether the "Σ" with 0 as its value is the "Σ" of the row ("Σ" in "Design (G)") or the "Σ" of the column ("Σ" in "SEM (D)"). When the "Σ" with 0 as its value is the "Σ" of the row ("Σ" in "Design (G)") (Step S1355: Design), it proceeds to Step S1356. When it is the "Σ" of the column ("Σ" in "SEM (D)") (Step S1355: SEM), it proceeds to Step S1357.

[0138] (Step S1356)

[0139] The classification unit 209 classifies the defect type of the converted CAD as "island". For example, in the case of the converted CAD 524a shown in Figure 15 (b), when the matching unit 208 creates a matrix as shown in Figure 15 (d), the classification unit 209 classifies the defect type of the converted CAD 524a as "island". Then, it ends the classification operation of the defect type.

[0140] (Step S1357)

[0141] The classification unit 209 classifies the defect type of the converted CAD as "missing". For example, in the case of the converted CAD 524c shown in Figure 15 (c), when the matching unit 208 creates a matrix as shown in Figure 15 (e), the classification unit 209 classifies the defect type of the converted CAD 524c as "missing". Then, it ends the classification operation of the defect type.

[0142] (Step S1358)

[0143] The classification unit 209 further determines whether the value is non-zero and a value other than 1, that is, whether the "Σ" with a value of 2 or more is the "Σ" of the row ("Σ" in "Design (G)") or the "Σ" of the column ("Σ" in "SEM (D)"). In the case where the "Σ" with a value of 2 or more is the "Σ" of the row ("Σ" in "Design (G)") (step S1358: Design), it proceeds to step S1359. In the case where it is the "Σ" of the column ("Σ" in "SEM (D)") (step S1358: SEM), it proceeds to step S1360.

[0144] (Step S1359)

[0145] The classification unit 209 classifies the defect type of the converted CAD as "short circuit". For example, in the case of the converted CAD 524b shown in Figure 16 (b), when the matching unit 208 creates a matrix as shown in Figure 16 (d), the classification unit 209 classifies the defect type of the converted CAD 524b as "short circuit". Then, the classification operation of the defect type ends.

[0146] (Step S1360)

[0147] The classification unit 209 classifies the defect type of the converted CAD as "open circuit". For example, in the case of the converted CAD 524d shown in Figure 16 (c), when the matching unit 208 creates a matrix as shown in Figure 16 (e), the classification unit 209 classifies the defect type of the converted CAD 524d as "open circuit". Then, the classification operation of the defect type ends.

[0148] Using the process of steps S1351 to S1360 described above, the classification operation of the defect type in the defect inspection process of the SEM device 1 is executed.

[0149] Figure 18 It is a flowchart of the circuit check of the SEM device of the embodiment. Figure 19 It is a diagram for explaining the circuit check of the SEM device of the embodiment. Figure 20 It is a diagram for explaining the circuit check of the SEM device of the embodiment. Figure 21 It is a diagram for explaining the circuit check of the SEM device of the embodiment. Figure 22 It is a diagram for explaining the circuit check of the SEM device of the embodiment. While referring to Figures 18 - 22 , the process of the circuit check operation ( Figure 11 step S136) in the defect inspection process of the SEM device 1 of the present embodiment will be described.

[0150] (Step S1361)

[0151] The circuit verification unit 211 of the SEM apparatus 1 confirms which defect type the converted CAD that is the object of the defect inspection process is classified into by the classification unit 209. When the converted CAD is classified into the defect type of "no defect" (step S1361: no defect), it proceeds to step S1362. When it is classified into the defect types of "island" or "short circuit" (step S1361: island or short circuit), it proceeds to step S1363. When it is classified into the defect types of "missing" or "open circuit" (step S1361: missing or open circuit), it proceeds to step S1365.

[0152] (Step S1362)

[0153] The circuit verification unit 211 determines that there is no critical defect in the circuit on the chip corresponding to the converted CAD. Then, the circuit verification operation ends.

[0154] (Step S1363)

[0155] The second assignment unit 210 and the circuit verification unit 211 of the SEM apparatus 1 perform circuit verification in the short - circuit mode. For example, here, in step S1361, it is assumed that the converted CAD is classified into the defect type of "short circuit" for explanation.

[0156] Figure 19 (a) The design CAD 514 shown represents the state in which the graphic numbers G1 to G8 are assigned in the step S133 shown above. Figure 11 shown in the step S133. Figure 19 (b) The converted CAD 524b shown represents the state in which the graphic numbers D1 to D7 are assigned in the same step S133. Figure 19 (c) The matrix shown represents the matrix of the association of the graphic numbers created by the matching unit 208 for the design CAD 514 and the converted CAD 524b in the step S134 shown above. Figure 11 shown in the step S134.

[0157] In addition, as described above, when performing the defect inspection process, the LVS between the schematic data and the design CAD data corresponding to the entire chip is performed by the LVS execution unit 206 in advance to obtain the AGF. Therefore, node numbers are associated with each wiring pattern of the design CAD 514. Accordingly, the second assignment unit 210 assigns node numbers to each wiring pattern of the design CAD 514 based on the AGF obtained by the LVS execution unit 206. The state in which the node numbers A1 to A6 are assigned to the design CAD 514 is set as Figure 19 (d) The design CAD 514a shown.

[0158] The circuit verification unit 211 creates a matrix as shown in Figure 19 (e) that represents the association between the graphic numbers (G1 to G8) of the design CAD 514 and the node numbers (A1 to A6) of the design CAD 514a. Then, the circuit verification unit 211 refers to the Figure 19 matrix shown in (c) created by the matching unit 208, and identifies that the wiring pattern of the graphic number D2 that becomes in the "short circuit" state in the conversion CAD 524b corresponds to the wiring patterns of the graphic numbers G2 and G3 of the design CAD 514. Then, the circuit verification unit 211 refers to the Figure 19 matrix shown in (e) that has been created, and confirms the node numbers of the wiring patterns of the design CAD 514a corresponding to the wiring patterns of the graphic numbers G2 and G3 of the design CAD 514 that have been identified.

[0159] In the case of the Figure 19 matrix shown in (e), the circuit verification unit 211 can confirm that the node numbers of the wiring patterns of the design CAD 514a corresponding to the wiring patterns of the graphic numbers G2 and G3 of the design CAD 514 are A1 and A2, respectively. Therefore, the circuit verification unit 211 finds that in the conversion CAD 524b representing the actual circuit state, the wiring pattern of the graphic number D2 in a short circuit state shorts the wiring patterns of different node numbers to each other, and determines that there is a defect in the circuit (determines NG).

[0160] On the other hand, when the circuit verification unit 211 confirms that in the conversion CAD 524b, the wiring pattern of the graphic number D2 in a short circuit state shorts the wiring patterns of the same node numbers to each other, it determines that there is no defect in the circuit (determines OK).

[0161] In addition, regarding the case where the conversion CAD is classified as a defect type of "island" in step S1361, the circuit verification unit 211, for example, in the conversion CAD (such as the conversion CAD 524a) representing the actual circuit state, there is no wiring pattern in the design CAD 514a that is assigned a node number and corresponds to the redundant wiring pattern (such as the wiring pattern of the graphic number D9 in the conversion CAD 524a). Therefore, it can also be determined that there is no defect in the circuit (determines OK).

[0162] In addition, when the conversion CAD is classified as a defect type of "island" in step S1361, it can also be as follows. That is, first, among the graphics shown in the design CAD data of the entire chip acquired by the second acquisition unit 202, the conversion CAD (such as Figure 20(a) The converted CAD 524a as shown. Here, graphic numbers D1 to D9 are assigned to each wiring pattern in the converted CAD 524a. Next, using the replacement unit 205, in the graphic shown in the CAD data, the part corresponding to the converted CAD 524a is replaced with the converted CAD 524a (replacement CAD). Based on this replacement CAD, as Figure 20 (b) shown, the design CAD 518 representing the via patterns G1 to G3 (wiring for connecting upper-layer wiring and lower-layer wiring) existing in the same part as the converted CAD 524a is extracted. Furthermore, as Figure 20 (c) shown, the design CAD 518 is combined with the converted CAD 524a to create the converted CAD 524m in which the wiring pattern and the via pattern are combined. Next, again in the same manner as in step S133, the first assignment unit 207 re-assigns graphic numbers D1 to D8 to each pattern of the converted CAD 524m. After that, the circuit verification unit 211 performs circuit verification in the same manner as in the case of the defect type classified as "short circuit". Based on the result, the circuit verification unit 211 can also determine whether there is no circuit defect (determination OK) or there is a circuit defect (determination NG).

[0163] Then, it proceeds to step S1364.

[0164] (Step S1364)

[0165] In the case where it is determined to be OK by the circuit verification unit 211 (step S1364: OK), it proceeds to step S1362, and in the case where it is determined to be NG (step S1364: NG), it proceeds to step S1367.

[0166] (Step S1365)

[0167] The second assignment unit 210 and the circuit verification unit 211 of the SEM device 1 perform circuit verification in the open-circuit mode. For example, here, it is assumed that in step S1361, the converted CAD is classified as the defect type of "open circuit" for explanation.

[0168] Figure 21 (a) The design CAD 514 shown represents the state in which graphic numbers G1 to G8 are assigned in the Figure 11 step S133 shown. Figure 21 (b) The converted CAD 524d shown represents the state in which graphic numbers D1 to D9 are assigned in the same step S133. Figure 21 (c) The matrix shown represents the one in the Figure 11In step S134 shown above, a matrix of associations of graphic numbers created by the matching unit 208 for the design CAD 514 and the converted CAD 524d. Also, as described above, for each wiring pattern in the design CAD 514, a node number is associated. Therefore, the second number-assigning unit 210 assigns node numbers to the respective wiring patterns of the design CAD 514 based on the AGF obtained by the LVS execution unit 206. As described above, the state in which node numbers A1 to A6 are assigned to the design CAD 514 is set as Figure 19 the design CAD 514a shown in (d).

[0169] The circuit verification unit 211 creates a matrix as described above showing the association between the graphic numbers (G1 to G8) of the design CAD 514 and the node numbers (A1 to A6) of the design CAD 514a. The circuit verification unit 211 refers to the matrix created by the matching unit 208 Figure 19 shown in (c), and identifies that the wiring patterns of the graphic numbers D2 and D8 that are in the "open circuit" state in the converted CAD 524d correspond to the wiring pattern of the graphic number G2 of the design CAD 514. Then, the circuit verification unit 211 refers to the created Figure 21 matrix shown in (e), and confirms the node number of the wiring pattern in the design CAD 514a corresponding to the wiring pattern of the graphic number G2 of the design CAD 514 that has been identified. In Figure 19 the example shown in Figure 21 , the circuit verification unit 211 can confirm that the node number of the wiring pattern in the design CAD 514a corresponding to the wiring pattern of the graphic number G2 of the design CAD 514 is A2. However, in this case, the circuit verification unit 211 cannot determine whether the wiring patterns of the graphic numbers D2 and D8 that are in the open circuit state in the converted CAD 524d representing the actual circuit state are conducting (short-circuited) or not conducting in other parts of the entire chip.

[0170] Therefore, in this case, as Figure 22As shown in (a), in the patterns shown in the design CAD data of the entire chip acquired by the second acquisition unit 202, the replacement unit 205 of the SEM device 1 replaces the part corresponding to the converted CAD 524d obtained by the conversion performed by the conversion unit 204 with the converted CAD 524d. Then, the replacement unit 205 extracts, from the CAD data obtained by replacing with the converted CAD 524d, the part of a specific range including the converted CAD 524d as the replacement CAD 534 (an example of replacement information). As described below, node numbers are associated with the respective wiring patterns of the replacement CAD 534 (including the converted CAD 524d). Since the wiring patterns of the graphic numbers D2 and D8 determined to have defects (open circuits) are specified in the converted CAD 524d, even if LVS is not performed using the CAD data of the entire chip, as long as LVS is performed on the part of the specific range including the converted CAD 524d as described above, it is possible to determine whether it is actually a fatal defect in the circuit. Then, the LVS execution unit 206 executes LVS of the schematic data and the replacement CAD 534, which is the part of the specific range including the replaced converted CAD 524d, in the CAD data of the entire chip. Regarding the specific range, specifically, it is the range including the wiring patterns of the graphic numbers D2 and D8 determined to have defects (open circuits) in the converted CAD 524d and the patterns belonging to the node number A2 specified by the matching unit 208 and the circuit verification unit 211. Since the number of patterns for which LVS is executed can be reduced in advance based on the node numbers, the inspection time can be shortened.

[0171] Consider the following situation: The trace result obtained by the LVS of the LVS execution unit 206 is, for example, as Figure 22 As shown in (b), in the circuit part other than the converted CAD 524d in the patterns included in the design CAD constituting the node number A2 corresponding to the graphic numbers D2 and D8 as open circuit defects, it is detected that the wiring pattern of the graphic number D2 and the wiring pattern of the graphic number D8 are conducting. In this case, the circuit verification unit 211 can determine that, in the converted CAD 524d representing the actual circuit state, the wiring patterns of the graphic numbers D2 and D8 determined to be in an open circuit state are wiring patterns of the same node number, and in this case, it is determined that there is no defect in the circuit (determined OK).

[0172] On the other hand, consider the following situation: The trace result obtained by the LVS of the LVS execution unit 206 is, for example, as Figure 22As shown in (c), in the circuit part that constitutes the figure included in the design CAD corresponding to the node number A2 corresponding to the figure numbers D2 and D8 which are open circuit defects and excluding the conversion CAD524d, it is detected that the wiring pattern of the figure number D2 and the wiring pattern of the figure number D8 are not conducting. In this case, the circuit verification unit 211 can determine that in the conversion CAD524d representing the actual circuit state, the wiring patterns of the figure numbers D2 and D8 determined to be in the open circuit state are wiring patterns of different node numbers. In this case, it is determined that there is a circuit defect (determination NG).

[0173] In addition, regarding the case where the conversion CAD is classified as a "missing" defect type in step S1361, the circuit verification unit 211, for example, confirms that in the conversion CAD (such as Figure 13 the conversion CAD524c shown in (d)) representing the actual circuit state, there is no wiring pattern corresponding to the wiring pattern of the node number A6 of the design CAD514a. However, in this case, the circuit verification unit 211 cannot determine what kind of influence the wiring pattern that does not exist on the conversion CAD524c that has become missing has on the entire chip's circuit.

[0174] Therefore, similarly, the replacement unit 205 replaces the part corresponding to the conversion CAD524c obtained by the conversion of the conversion unit 204 with the conversion CAD524c in the figures shown in the design CAD data of the entire chip obtained by the second acquisition unit 202, and extracts the replacement CAD equivalent to Figure 22 the replacement CAD534 shown in (a). Then, the LVS execution unit 206 executes LVS on the schematic data and the specific range part of the CAD data of the entire chip that includes the replaced conversion CAD524c. Regarding the specific range, specifically, it is the range that includes the figure belonging to the node number A6 specified by the figure number G7 in the design CAD corresponding to the conversion CAD524c.

[0175] Consider the following situation: The tracing result obtained by the LVS of the LVS execution unit 206 is, for example, that in the circuit part within the replacement CAD and excluding the conversion CAD524c, no non-conducting part is detected in the circuit including the wiring pattern of the node number A6. In this case, the circuit verification unit 211 can determine that in the conversion CAD524c representing the actual circuit state, the non-existence of the wiring pattern corresponding to the node number A6 will not cause adverse effects on the circuit. In this case, it is determined that there is no circuit defect (determination OK).

[0176] On the other hand, consider the following situation for the tracking result obtained by LVS in the LVS execution unit 206: in the circuit part within the replacement CAD and excluding the conversion CAD 524c, a part where there is no conduction or the like is detected in the circuit including the wiring pattern with the node number A6. In this case, the circuit verification unit 211 can determine that in the conversion CAD 524c representing the actual circuit state, the wiring pattern corresponding to the node number A6 does not cause an adverse effect on the circuit. In this case, it is determined that there is a defect in the circuit (determined as NG).

[0177] Then, it proceeds to step S1366.

[0178] (Step S1366)

[0179] When it is determined as OK by the circuit verification unit 211 (step S1366: OK), it proceeds to step S1362. When it is determined as NG (step S1366: NG), it proceeds to step S1367.

[0180] (Step S1367)

[0181] The circuit verification unit 211 determines that there is a fatal defect in the circuit on the chip corresponding to the conversion CAD. Then, the circuit verification operation ends.

[0182] As described above, in the SEM device 1 of the present embodiment, graphic numbers are assigned to each wiring pattern of the conversion CAD and the design CAD, and association (matching) is performed using each graphic number. Based on the result of this association, the defect types of the conversion CAD are classified. Then, node numbers are assigned to the wiring patterns of the design CAD. Based on the result of the association between the graphic number and the node number of the design CAD, the conversion CAD representing the actual circuit state is used to determine whether there is a defect in the circuit. In this defect inspection process, for example, it is not necessary to perform LVS between the schematic data and the design CAD data of the entire chip, so the inspection time for defect inspection in semiconductor manufacturing can be shortened.

[0183] In addition, in the SEM device 1 of the present embodiment, as the defect types of the conversion CAD, for example, when classified as "short circuit" or "island", based on the association between the graphic numbers of the design CAD and the conversion CAD, and the result of the association between the graphic number and the node number in the design CAD, the conversion CAD representing the actual circuit state is used to determine whether there is a defect in the circuit. In this case, it is possible to determine whether there is a defect in the circuit without performing LVS, so the inspection time can be further shortened.

[0184] In addition, in the SEM apparatus 1 of the present embodiment, as the types of defects to be converted in the CAD, for example, in the case of being classified as "open circuit" or "missing", in the patterns shown in the design CAD data of the entire chip, the portion corresponding to the converted CAD obtained by the conversion by the conversion unit 204 is replaced with the converted CAD, and from the replaced CAD data, a portion including a specific range of the converted CAD is extracted as the replaced CAD. Then, LVS is performed on the schematic data and the replaced CAD, which is a portion of the specific range including the converted CAD in the CAD data of the entire chip, using the converted CAD representing the actual circuit state to determine whether there are defects in the circuit. In this case, even when performing LVS, the CAD data to be the object of performing LVS can be set to a limited range, so the inspection time can be shortened.

[0185] In addition, the processing of the execution object performed by the LVS execution unit 206 is not limited to LVS. In addition to the processing for obtaining AGF, for example, it may be processing for performing equipotential tracing. Further, the defect inspection process is performed using the converted CAD converted from the SEM image and the design CAD obtained by clipping the portion corresponding to the SEM image from the design CAD data, but the defect inspection process may be performed using image data instead of CAD data. For example, instead of the converted CAD, the SEM image itself or an image obtained by performing image processing suitable for the defect inspection process on the SEM image may be used.

[0186] (Modification example)

[0187] A description will be given centering on actions different from those of the SEM apparatus 1 of the above-described embodiment. In the above-described embodiment, the defect inspection process using the SEM image of the circuit pattern (wiring pattern) has been described. In this modification example, a description will be given of the defect inspection process using the SEM image of the via holes connecting the circuit patterns of different layers. In addition, since the configuration of the SEM apparatus of this modification example is the same as that of the SEM apparatus 1 of the above-described embodiment, the same reference numerals are attached to each device, circuit, functional unit, etc. for description.

[0188] Figure 23 This is a diagram for explaining the types of defects of the SEM apparatus according to the modification example of the embodiment. While referring to Figure 23 , a description will be given of the types of defects classified according to the types of defects of the SEM apparatus 1 according to this modification example.

[0189] Figure 23 (a) The shown design CAD 515 is a graphic portion shown in the design CAD data corresponding to the SEM image of the via holes, which is obtained by clipping by the clipping unit 203, and graphic numbers (G1 to G3) are assigned by the first assignment unit 207. In addition, Figure 23(b) to Figure 23 The figure shown in (d) represents the converted CAD obtained by the conversion unit 204 converting the SEM image of the through-hole into CAD data. Figure 23 The converted CAD 525a shown in (b) is assigned graphic numbers D1 to D4. Compared with the design CAD 515, there is an extra through-hole shown by the graphic number D4, so it is classified as a defect type of "island". Figure 23 The converted CAD 525b shown in (c) is assigned graphic numbers D1 and D2, and has a through-hole of graphic number D1 like the through-hole of graphic number G1 and the through-hole of graphic number G3 in the design CAD 515 being short-circuited, so it is classified as a defect type of "short circuit".

[0190] Figure 23 The converted CAD 525c shown in (d) is assigned graphic numbers D1 and D2, and there is no through-hole of graphic number G3 in the design CAD 515, so it is classified as a defect type of "missing". Figure 23 The converted CAD 525d shown in (e) is assigned graphic numbers D1 and D2, and there is no through-hole of graphic number G3 in the design CAD 515. Therefore, it is assumed that the upper wiring pattern and the lower wiring pattern that should have been connected by the existing through-hole are in an open state, so it is classified as a defect type of "open circuit". In addition, in the acquisition of the SEM image of the through-hole, due to electrification during imaging, the generation of secondary electrons from through-holes that cannot conduct to the lower layer, such as open through-holes, is extremely reduced. So as Figure 23 shown in (d) and Figure 23 (e), they are the same as the converted CAD.

[0191] Figure 24 It is a diagram for explaining the circuit verification of the SEM device for a variation example of the embodiment. While referring to Figure 24 , the circuit verification operation of the defect inspection process in the SEM device 1 of this variation example will be described.

[0192] Here, it is assumed that in the step S1361 of the Figure 18 , the converted CAD is classified as a defect type of "island" for explanation. However, when there is a through-hole in the converted CAD of the through-hole that does not exist in the design CAD, it is a defect type with the property that the upper wiring pattern and the lower wiring pattern may be misconnected (short-circuited). Therefore, it is necessary to perform the circuit verification in the case where the converted CAD shown in Figure 19 is classified as a defect type of "short circuit".

[0193] Figure 24 The lower layer CAD 516a shown in (a) represents in the Figure 11In step S13 shown, the lower-layer design CAD is in a state where graphic numbers G1 to G8 are assigned. Figure 24 The lower-layer CAD 516b shown in (c) represents a state where graphic numbers G1 and G2 are assigned to the upper-layer design CAD in the same step S133. Figure 24 The conversion CAD 526 shown in (b) represents a state where graphic numbers D1 to D4 are assigned in the same step S133. In addition, as described above, when performing the defect inspection process, the LVS of the schematic data and the design CAD data corresponding to the entire chip is pre-executed by the LVS execution unit 206 to obtain the AGF. Therefore, node numbers are associated with each wiring pattern in each of the lower-layer and upper-layer design CADs. Accordingly, the second assignment unit 210 assigns node numbers to each wiring pattern of the lower-layer and upper-layer design CADs based on the AGF obtained by the LVS execution unit 206. The state where node numbers A1 to A6 are assigned to the lower-layer design CAD is set as Figure 24 the lower-layer CAD 517a shown in (d). The state where node numbers A1 and A6 are assigned to the upper-layer design CAD is set as Figure 24 the upper-layer CAD 517b shown in (e).

[0194] The circuit verification unit 211 creates a matrix as shown in Figure 24 (f) that represents the association between the graphic numbers of the lower-layer CAD 516a and the upper-layer CAD 516b and the node numbers of the lower-layer CAD 517a and the upper-layer CAD 517b. Then, the circuit verification unit 211 identifies the via hole of the graphic number D4 that becomes an "island" state in the conversion CAD 526 and connects (shorts) the via hole of the graphic number G2 of the lower-layer CAD 516a to the via hole of the graphic number G2 of the upper-layer CAD 516b. Then, the circuit verification unit 211 refers to the created Figure 24 (f) matrix and confirms the node numbers of the via holes in the lower-layer CAD 517a and the upper-layer CAD 517b corresponding to the identified via hole of the graphic number G2 of the lower-layer CAD 516a and the via hole of the graphic number G2 of the upper-layer CAD 516b. In the case of the matrix shown in Figure 24 (f), the circuit verification unit 211 can confirm that the node numbers of the via holes in the lower-layer CAD 517a and the upper-layer CAD 517b corresponding to the via hole of the graphic number G2 of the lower-layer CAD 516a and the via hole of the graphic number G2 of the upper-layer CAD 516b are A2 and A6, respectively. Therefore, the circuit verification unit 211 finds that in the conversion CAD 526 representing the actual via hole state, the shorted (short) via hole of the graphic number D4 shorts the via holes with different node numbers, and determines that there is a defect in the circuit (determines NG).

[0195] On the other hand, when the circuit verification unit 211 confirms that in the converted CAD 526, the vias with the graphic number D4 of a short circuit short-circuit the vias with the same node number, it determines that there is no circuit defect (determination OK).

[0196] In addition, even when the converted CAD is classified as a defect type of "short circuit" in the step S1361 described above, it is possible to determine whether there is a circuit defect in the same manner as described above. Figure 18

[0197] In addition, in the step S1361 described above, when the converted CAD is classified as a defect type of "open circuit" or "missing", it is only necessary to perform the same process as the process of step S1365 described above (execute the LVS of the replacement CAD using a specific range). Figure 18 Figure 18

[0198] As described above, in the SEM device 1 of this modification example, graphic numbers are assigned to the vias of the converted CAD and the design CAD, and the association (matching) is performed using each graphic number. Based on the result of this association, the defect type of the converted CAD is classified. Then, node numbers are assigned to the vias of the design CAD, and based on the association result of the graphic number and the node number of the design CAD, the converted CAD representing the actual circuit state is used to determine whether there is a circuit defect. In this defect inspection process, for example, it is not necessary to execute the LVS of the schematic data and the design CAD data of the entire chip, so the inspection time for defect inspection in semiconductor manufacturing can be shortened.

[0199] In addition, in the SEM device 1 of this modification example, as the defect type of the converted CAD, for example, when it is classified as "short circuit" or "island", based on the association of the graphic numbers of the design CAD and the converted CAD, and the result of the association between the graphic number and the node number in the design CAD, the converted CAD representing the actual circuit state is used to determine whether there is a circuit defect. In this case, it is possible to determine whether there is a circuit defect without performing the LVS, so the inspection time can be further shortened.

[0200] In addition, in the SEM apparatus 1 of this modification example, as the defect types for converting CAD, for example, in the case of being classified as "open circuit" or "missing", in the patterns shown in the design CAD data of the entire chip, the portion corresponding to the converted CAD obtained by the conversion performed by the conversion unit 204 is replaced with the converted CAD, and a portion of the specific range including the converted CAD is extracted from the replaced CAD data as the replacement CAD. Then, LVS is performed on the schematic data and the replacement CAD, which is the portion of the specific range including the replaced converted CAD in the CAD data of the entire chip, and it is determined whether there is a defect in the circuit using the converted CAD representing the actual circuit state. In this case, even when performing LVS, the CAD data to be the object of performing LVS can be set to a limited range, so the inspection time can be shortened.

[0201] In addition, the program executed by the SEM apparatus 1 of the above-described embodiment and modification example can also be pre-loaded and provided to a ROM or the like in advance.

[0202] In addition, the program executed by the SEM apparatus 1 of the above-described embodiment and modification example can also be configured to be recorded as a file in a form that can be installed or executed in a computer-readable recording medium such as a CD-ROM (Compact Disc - Read Only Memory), a floppy disk (FD), a CD-R (Compact Disc - Recordable), or a DVD (Digital Versatile Disc), and provided as a computer program product.

[0203] In addition, it can also be configured to store the program executed by the SEM apparatus 1 of the above-described embodiment and modification example in a computer connected to a network such as the Internet and provide it by downloading via the network. In addition, it can also be configured to provide or distribute the program executed by the SEM apparatus 1 of the above-described embodiment and modification example via a network such as the Internet.

[0204] In addition, the program executed by the SEM apparatus 1 of the above-described embodiment and modification example can cause a computer to function as each of the above-described functional units. The CPU of this computer can read the program from a computer-readable storage medium into the main storage device and execute it.

[0205] The embodiments and modification examples of the present invention have been described, but these embodiments and modification examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments and modification examples can be implemented in various other ways, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modification examples are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalents.

[0206] [Description of Symbols]

[0207] 1 SEM apparatus

[0208] 11 Electron gun barrel

[0209] 12 Electron source

[0210] 13 Magnetic field lens

[0211] 14 Scanning coil

[0212] 21 Stage

[0213] 22 Wafer

[0214] 23 Detector

[0215] 31 Controller

[0216] 32 Signal processing circuit

[0217] 33 Monitor

[0218] 34 Image storage unit

[0219] 35 Column control circuit

[0220] 36 Stage drive control circuit

[0221] 37 Coordinate storage unit

[0222] 38 Recipe file storage unit

[0223] 101 CPU

[0224] 102 ROM

[0225] 103 RAM

[0226] 104 Input / output I / F

[0227] 105 Control circuit I / F

[0228] 201 First acquisition unit

[0229] 202 Second acquisition unit

[0230] 203 Editing unit

[0231] 204 Conversion unit

[0232] 205 Replacement unit

[0233] 206 LVS execution unit

[0234] 207 First assignment unit

[0235] 208 Matching unit

[0236] Classification Section 209

[0237] Second Application Section 210

[0238] Circuit Verification Section 211

[0239] Storage Section 220

[0240] SEM Images 500 - 502, 504

[0241] Design CAD 510

[0242] Lower - layer CAD 512a

[0243] Upper - layer CAD 512b

[0244] Design CAD 513, 514, 514a, 515

[0245] Lower - layer CAD 516a

[0246] Upper - layer CAD 516b

[0247] Lower - layer CAD 517a

[0248] Upper - layer CAD 517b

[0249] Design CAD 518

[0250] Defect CAD 522

[0251] Conversion CAD 524

[0252] Conversion CAD 524a - 524e

[0253] Conversion CAD 524m

[0254] Conversion CAD 525a - 525d

[0255] Conversion CAD 526

[0256] Replacement CAD 532

[0257] Replacement CAD 534

[0258] Differential Image 550

[0259] Binary Image 552

[0260] Wiring 601 - 603

[0261] Wiring 611, 612

[0262] Through - holes 611a, 612a

[0263] 621 Wiring

[0264] EB Electron Beam

[0265] SE Secondary Electron

Claims

1. A defect inspection device, comprising: An acquisition unit that acquires electronic information representing a pattern developed on a wafer; An extraction unit that extracts a portion corresponding to the electronic information from the pattern shown in the design data to obtain design information; A first number assignment unit that assigns a first number to each pattern shown in the electronic information and assigns a second number to each pattern shown in the design information; A matching unit that creates relationship information representing the correspondence between the first number and the second number; A verification unit that verifies whether the patterns shown in the electronic information include defects on the circuit of the wafer based on the relationship information and the node information corresponding to each pattern shown in the design information; A conversion unit that obtains conversion information obtained by converting the electronic information acquired by the acquisition unit into CAD (Computer Aided Design) data; A classification unit that classifies the types of defects in the conversion information based on the content of the relationship information created by the matching unit; And A second number assignment unit that assigns node numbers to each pattern shown in the design information as the node information; and The first number assignment unit assigns the first number to each pattern shown in the conversion information; The verification unit verifies whether the patterns shown in the conversion information include defects on the circuit of the wafer based on the relationship information and the node information; The verification unit verifies whether the patterns shown in the conversion information include defects on the circuit of the wafer according to the types of defects classified by the classification unit; The verification unit verifies whether the patterns shown in the conversion information include defects on the circuit of the wafer based on the relationship information and the node numbers; When the type of defect in the conversion information shown by the classification unit is a short - circuit state, the verification unit determines the pattern in the design information corresponding to the pattern in the conversion information in the short - circuit state according to the relationship information, and verifies whether the patterns shown in the conversion information include defects on the circuit of the wafer according to the correspondence between the determined pattern in the design information and the node numbers.

2. A defect inspection device, comprising: An acquisition unit that acquires electronic information representing a pattern developed on a wafer; An extraction unit that extracts a portion corresponding to the electronic information from the pattern shown in the design data to obtain design information; A first number assignment unit that assigns a first number to each pattern shown in the electronic information and assigns a second number to each pattern shown in the design information; A matching unit that creates relationship information representing the correspondence between the first number and the second number; A verification unit that verifies whether the patterns shown in the electronic information include defects on the circuit of the wafer based on the relationship information and the node information corresponding to each pattern shown in the design information; A conversion unit that obtains conversion information obtained by converting the electronic information acquired by the acquisition unit into CAD (Computer Aided Design) data; A classification unit that classifies the types of defects in the conversion information based on the content of the relationship information created by the matching unit; A second number assignment unit that assigns node numbers to each pattern shown in the design information as the node information; A replacement unit that extracts a specific range part including the conversion information as replacement information from the data obtained by replacing the part corresponding to the conversion information in the graphics shown in the design data with the conversion information; And An execution unit that executes LVS (Layout Versus Schematic) of a part or all of the schematic data of the wafer and the design data; and The first number assignment unit assigns the first number to each pattern shown in the conversion information; The verification unit verifies whether the patterns shown in the conversion information include defects on the circuit of the wafer based on the relationship information and the node information; The checking unit checks whether the pattern shown in the conversion information includes a defect on the circuit of the wafer according to the type of the defect classified by the classification unit; The checking unit checks whether the pattern shown in the conversion information includes a defect on the circuit of the wafer based on the relationship information and the node number; When the type of the defect of the conversion information shown by the classification unit is an open circuit state, the checking unit checks whether the pattern shown in the conversion information includes a defect on the circuit of the wafer according to the result of the LVS executed by the execution unit using the replacement information extracted by the replacement unit and the schematic data; 3. The defect inspection device according to claim 2, wherein the execution unit pre-executes the LVS of the schematic data and all the design data, thereby generating the node numbers corresponding to the respective patterns shown in the design data. The second number assigning unit assigns the node numbers generated by the execution unit to the respective patterns shown in the design information.

4. A defect inspection device, comprising: An acquisition unit that acquires electronic information representing a pattern developed on a wafer; A first number assigning unit that assigns a first number to each pattern shown in the electronic information, and assigns a second number to each pattern shown in the design information, which is a part of the pattern shown in the design data corresponding to the electronic information. A matching unit creates relationship information representing the correspondence between the first number and the second number; A checking unit checks whether the pattern shown in the electronic information includes a defect on the circuit of the wafer based on the relationship information and the node information corresponding to each pattern shown in the design information; A conversion unit obtains conversion information obtained by converting the electronic information acquired by the acquisition unit into CAD (Computer Aided Design) data; A classification unit classifies the type of the defect of the conversion information based on the content of the relationship information created by the matching unit; And A second number assigning unit assigns a node number as the node information to each pattern shown in the design information; and The first number assigning unit assigns the first number to each pattern shown in the conversion information; The checking unit checks whether the pattern shown in the conversion information includes a defect on the circuit of the wafer based on the relationship information and the node information; The checking unit checks whether the pattern shown in the conversion information includes a defect on the circuit of the wafer according to the type of the defect classified by the classification unit; The checking unit checks whether the pattern shown in the conversion information includes a defect on the circuit of the wafer based on the relationship information and the node number; When the type of the defect of the conversion information shown by the classification unit is a short circuit state, the checking unit determines the pattern in the design information corresponding to the pattern in the conversion information in the short circuit state according to the relationship information, and checks whether the pattern shown in the conversion information includes a defect on the circuit of the wafer according to the correspondence between the determined pattern in the design information and the node number; 5. A defect inspection method, comprising: An acquisition step of acquiring electronic information representing a pattern developed on a wafer; An editing step of editing a part corresponding to the electronic information in the graph shown in the design data to obtain design information; A first number assigning step of assigning a first number to each pattern shown in the electronic information and assigning a second number to each pattern shown in the design information; A matching step of creating relationship information representing the correspondence between the first number and the second number; A checking step of checking whether the pattern shown in the electronic information includes a defect on the circuit of the wafer based on the relationship information and the node information corresponding to each pattern shown in the design information; A conversion step of obtaining conversion information obtained by converting the electronic information obtained in the obtaining step into CAD (Computer Aided Design) data; A classification step of classifying the defect types of the conversion information based on the content of the relationship information created in the matching step; And A second assigning step of assigning a node number to each pattern shown in the design information as the node information; and The first assigning step assigns the first number to each pattern shown in the conversion information; The checking step checks whether the pattern shown in the conversion information includes a defect on the circuit of the wafer based on the relationship information and the node information; The checking step checks whether the pattern shown in the conversion information includes a defect on the circuit of the wafer according to the defect type classified by the classification step; The checking step checks whether the pattern shown in the conversion information includes a defect on the circuit of the wafer based on the relationship information and the node number; When the defect type of the conversion information shown by the classification step is a short-circuit state, the checking step determines the pattern in the design information corresponding to the pattern in the conversion information in the short-circuit state according to the relationship information, and checks whether the pattern shown in the conversion information includes a defect on the circuit of the wafer according to the correspondence between the determined pattern in the design information and the node number.

Images