Semiconductor device and control method thereof

Abstract

The present application relates to a semiconductor device and a control method thereof. A semiconductor device capable of self-diagnosing a clock monitoring circuit without increasing the size of the circuit is provided. According to one embodiment, the semiconductor device includes a first oscillator circuit, a clock monitoring circuit, and a timing signal generating circuit, which is used to periodically switch the operation mode of the clock monitoring circuit to one of a first mode to a third mode, and the clock monitoring circuit includes: a clock counter, which is configured to count the number of oscillations of the clock signal in the first mode, and is configured to shift the pulse of the input signal to the output signal in normal times in the third mode; a comparison circuit, which is used to compare whether the count value of the clock counter per predetermined period is within the expected value in the second mode; and an edge detection circuit, which is used to detect whether the pulse of the input signal is shifted to the output signal of the clock counter in the third mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2018-172617 filed on September 14, 2018 including specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method of controlling the semiconductor device, and to a semiconductor device and a method of controlling the semiconductor device suitable for, for example, performing self-diagnosis of a clock monitoring circuit without increasing the circuit scale. Background Art

[0004] For example, a semiconductor device mounted on a vehicle needs to operate normally to ensure safety, and a related technology is disclosed in Patent Document 1.

[0005] The semiconductor device disclosed in Patent Document 1 includes an oscillator and an oscillation abnormality detector. The oscillation abnormality detector specifies the frequency of the clock based on a count value obtained by measuring the frequency of the clock output from the oscillator. When the frequency exceeds a predetermined frequency range, the oscillation abnormality detector outputs an abnormal oscillation signal. This allows the semiconductor device to determine whether the oscillator is operating normally.

[0006] However, the configuration disclosed in Patent Document 1 does not have a function of determining whether the oscillation abnormality detector is abnormal. Therefore, if the oscillation abnormality detector is abnormal, it cannot be determined whether the oscillator is operating normally.

[0007] A solution to this problem is disclosed in Patent Document 2. The pulse period measurement device disclosed in Patent Document 2 includes at least an internal clock generation circuit, a free-running counter, a substitute clock generation circuit, a memory, a verification free-running counter, and an operation unit.

[0008] First, before measurement starts, the pulse period measurement device supplies a substitute clock generated by a substitute clock generation circuit to the free-running counter instead of the internal clock. The pulse period measurement device detects a malfunction of the free-running counter by comparing the count value of the substitute clock of the free-running counter with the integrated value of the substitute clock sequentially stored in a memory.

[0009] During the measurement period, the pulse period measurement device supplies an internal clock generated by the internal clock generation circuit to each of the free running counter and the verification free running counter. The pulse period measurement device detects a malfunction of the free running counter by comparing a count value of the internal clock by the free running counter with a count value of the internal clock by the verification free running counter. Summary of the invention

[0010] However, in the configuration of Patent Document 2, in addition to the free-running counter for measuring the internal clock generated by the internal clock generating circuit (oscillator) during the measurement period, it is necessary to further provide a verification free-running counter for measuring the internal clock in parallel with the free-running counter, and therefore, the circuit size increases. Other objects and novel features will become apparent from the description and drawings of this specification.

[0011] According to one embodiment, a semiconductor device includes: a first oscillation circuit for generating an internal clock signal; a first clock monitoring circuit; and a mode switching circuit for periodically switching the operation mode of the first clock monitoring circuit to any one of a first mode to a third mode, wherein the first clock monitoring circuit includes: a first clock counter configured to count the number of oscillations of the internal clock signal in the first mode, and configured to shift the pulse of an input signal to a normal output signal in the third mode; a first comparison circuit for comparing whether the count value of the first clock counter per predetermined time period is within an expected value range in the second mode; and a first detection circuit for detecting whether the pulse of the input signal is shifted to the output signal of the first clock counter in the third mode.

[0012] According to another embodiment, a control method of a semiconductor device is a control method of a semiconductor device as follows, wherein the semiconductor device includes a first oscillator circuit for generating an internal clock signal, a first clock monitoring circuit, and a mode switching circuit for periodically switching an operation mode of the first clock monitoring circuit to any one of a first mode to a third mode, wherein in the first mode, a counter is configured by a logic circuit provided in the first clock monitoring circuit, the counter is used to count the number of oscillations of the internal clock signal, in the second mode, it is determined whether the count value of the counter per predetermined time period is within an expected value, and in the third mode, a shift register is configured by a logic circuit provided in the first clock monitoring circuit to detect whether a pulse of an input signal is shifted to an output signal of the shift register.

[0013] According to the above-described embodiments, it is possible to provide a semiconductor device capable of performing self-diagnosis of a clock monitoring circuit without increasing the circuit scale and a control method thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram showing an exemplary configuration of a semiconductor device according to the first embodiment.

[0015] Figure 2 It is shown Figure 1 FIG. 1 is a block diagram of a specific configuration example of an oscillation abnormality detector provided in a semiconductor device shown in FIG.

[0016] Figure 3 It is shown Figure 2 1 is a block diagram of a specific configuration example of a timing signal generating circuit provided in an oscillation abnormality detector shown in FIG.

[0017] Figure 4 It is shown in Figure 2 A diagram showing a specific configuration of a clock monitoring circuit provided in an oscillation abnormality detector is shown.

[0018] Figure 5 It is shown Figure 2 A diagram showing an exemplary configuration of an abnormality detection circuit provided in an oscillation abnormality detector.

[0019] Figure 6 It is shown Figure 1 0 is a timing diagram of the operation of the semiconductor device shown in FIG.

[0020] Figure 7 is a block diagram showing a configuration example of a semiconductor device according to a second embodiment.

[0021] Figure 8 It is shown Figure 7 A block diagram of a configuration example of an oscillation abnormality detector provided in a semiconductor device shown in FIG.

[0022] Fig. 9 It is shown Figure 8 A diagram showing an exemplary configuration of an abnormality detection circuit provided in an oscillation abnormality detector.

[0023] Fig.10 It is shown Figure 7 0 is a timing diagram of the operation of the semiconductor device shown in FIG.

[0024] Fig.11 is a diagram showing a configuration example of an abnormality detection circuit provided in a semiconductor device according to a third embodiment. DETAILED DESCRIPTION

[0025] For clear explanation, the following description and drawings are appropriately omitted and simplified. In addition, the various elements of the functional blocks for performing various processes described in the drawings can be configured by a CPU (central processing unit), a memory and other circuits in hardware, and implemented by a program loaded in the memory in software. Therefore, it will be appreciated by those skilled in the art that these functional blocks can be implemented in various forms by separate hardware, separate software or a combination of software and hardware, and the present invention is not limited to any of them. In the drawings, the same elements are represented by the same reference numerals, and their repeated descriptions are omitted as required.

[0026] Moreover, various types of non-transitory computer-readable media can be used to store the above-mentioned program and provide it to the computer. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (e.g., floppy disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (read-only memory, CD-R, CD-R / W, solid-state memory (e.g., mask ROM, PROM (programmable ROM), EPROM (erasable PROM, flash ROM, RAM (random access memory)). The program can also be provided to the computer via various types of temporary computer-readable media. Examples of temporary computer-readable media include electrical signals, optical signals, and electromagnetic waves. Temporary computer-readable media can provide the program to the computer via wired or wireless communication paths (e.g., wires and optical fibers).

[0027] First embodiment

[0028] Figure 1 is a block diagram showing an exemplary configuration of a semiconductor device 1 according to a first embodiment. In the semiconductor device 1 according to the present embodiment, the corresponding clock monitoring circuits 131 to 133 are configured with a counter for counting the number of oscillations of the clock signal generated by the oscillation circuit according to the operation mode, and are configured with a shift register for detecting whether the pulse of the input signal is shifted to the output signal. In other words, in the semiconductor device 1 according to the present embodiment, the clock monitoring circuits 131 to 133 not only monitor the clock signal, but also self-diagnose the clock signal by using the period in which the clock signal is not monitored. Therefore, unlike the prior art, the semiconductor device 1 according to the present embodiment does not need to provide a verification clock monitoring circuit separately, and therefore, the self-diagnosis of the clock monitoring circuits 131 to 133 can be performed without increasing the circuit size. Hereinafter, a specific description will be given.

[0029] like Figure 1 As shown, the semiconductor device 1 includes a first oscillator circuit 11, a second oscillator circuit 12, an oscillation abnormality detector 13, a reset control circuit 14, and peripheral circuits 15_1 to 15_n, where n is an arbitrary integer of 1 or more.

[0030] The first oscillator circuit 11 generates a clock signal CLK1. The peripheral circuits 15_1 to 15_n operate in synchronization with the clock signal CLK1. The second oscillator circuit 12 generates a clock signal CLK2.

[0031] The oscillation abnormality detector 13 detects abnormality in the clock signal CLK1 generated by the first oscillator circuit 11. For example, when an abnormal state of the clock signal CLK1 is detected, the oscillation abnormality detector 13 activates the detection signal D1.

[0032] The reset control circuit 14 outputs an internal reset signal iRST corresponding to the reset signal RST supplied from the outside of the semiconductor device 1 and the detection signal D1 supplied from the oscillation abnormality detector 13. The internal reset signal iRST is input to the internal reset signal peripheral circuits 15_1 to 15_n.

[0033] For example, the reset control circuit 14 sets the internal reset signal iRST to be valid (L level) in response to the reset signal RST becoming valid (L level). In addition, when the detection signal D1 becomes valid (that is, when the oscillation abnormality detector 13 detects the abnormal state of the clock signal CLK1), the reset control circuit 14 makes the internal reset signal iRST valid (L level) regardless of the reset signal RST. As a result, the peripheral circuits 15_1 to 15_n are initialized.

[0034] Figure 2 1 is a block diagram showing a specific configuration example of the oscillation abnormality detector 13. Figure 2 As shown, the oscillation abnormality detector 13 includes clock monitoring circuits 131 to 133 , a timing signal generating circuit 134 , and an abnormality detecting circuit 135 .

[0035] Each of the clock monitoring circuits 131 to 133 monitors the clock signal CLK1 generated by the first oscillator circuit 11 .

[0036] The timing signal generating circuit 134 periodically switches the operation modes of the clock monitoring circuits 131 to 133 .

[0037] For example, the timing signal generating circuit 134 periodically switches the operation mode of the clock monitoring circuit 131 to one of the following modes: a counting mode (first mode) for counting the number of oscillations of the clock signal CLK1, a comparison mode (second mode) for comparing the count signal with an expected value, and a self-diagnosis mode (third mode) for self-diagnosis of the clock monitoring circuit 131. The timing signal generating circuit 134 periodically switches the operation mode of the clock monitoring circuit 132 to one of the following modes: a counting mode for counting the number of oscillations of the clock signal CLK1, a comparison mode for comparing the count signal with an expected value, and a self-diagnosis mode for self-diagnosis of the clock monitoring circuit 132. In addition, the timing signal generating circuit 134 periodically switches the operation mode of the clock monitoring circuit 133 to one of the following modes: a counting mode for counting the clock signal CLK1, a comparison mode for comparing the count signal with an expected signal, and a self-diagnosis mode for performing self-diagnosis of the clock monitoring circuit 133.

[0038] In the present embodiment, the timing signal generating circuit 134 periodically switches the operation modes of the clock monitoring circuits 131 to 133 so that the operation modes of the clock monitoring circuits 131 to 133 are different from each other. Therefore, the clock monitoring circuits 131-133 can always use any one of them to monitor the clock signal CLK1. On the other hand, in another clock monitoring circuit that does not monitor the clock signal CLK1, the clock signal self-diagnosis is compared with the count value and the expected value, and the self-diagnosis is performed.

[0039] Specifically, the timing signal generating circuit 134 outputs the sampling signals S1 to S3 and the comparator signals C1 to C3 in synchronization with the rising edge of the clock signal CLK2 .

[0040] Figure 3 1 is a diagram showing a specific configuration example of the timing signal generating circuit 134. Figure 3 As shown, the timing signal generating circuit 134 includes a down counter DC1, a logic circuit CT1, selectors SL11, SL12, and flip-flops FF11, FF12.

[0041] The down counter DC1 is, for example, a 6-bit counter, and counts down the count value in synchronization with the rising edge of the clock signal CLK2. In the present embodiment, the down counter DC1 counts down the count value one by one from the maximum value "2Fh" (hexadecimal notation; 47 in decimal notation) to the minimum value "00h". When the count value reaches the minimum value "00h", the count value returns to the maximum value "2Fh".

[0042] The down counter DC1 outputs the value of the most significant bit among the 6-bit values ​​constituting the count value as the sampling signal S1.

[0043] The logic circuit CT1 outputs selection signals A1 to A3 and comparison signals C1 to C3 based on the count value of the down counter DC1. Specifically, when the count value of the down counter DC1 is "00h", the logic circuit CT1 temporarily sets the selection signal A1 to the H level, when the count value is "10h", the selection signal A2 is temporarily set to the H level, and when the count value is "20h", the selection signal A3 is temporarily set to the H level. When the count value of the down counter DC1 is "08h", the logic circuit CT1 temporarily sets the comparison signal C2 to the H level, when the count value is "18h", the comparison signal C1 is temporarily set to the H level, and when the count value is "28h", the comparison signal C3 is temporarily set to the H level.

[0044] The selector SL11 selects and outputs one of the H level signal, L level signal and output signal of the selector SL11 based on the selection signals A2 and A3. Specifically, when both the selection signals A2 and A3 indicate the L level, the selector SL11 selects and outputs the output signal of the selector SL11, that is, maintains the output signal. When the selection signal A2 is at the L level and the selection signal A3 is at the H level, the selector SL11 selects and outputs the H level signal. In addition, when the selection signal A2 indicates the H level, the selector SL11 selects and outputs the L level signal regardless of the selection signal A3.

[0045] The flip-flop FF11 acquires the output signal of the selector SL11 in synchronization with the rising edge of the clock signal CLK2 , and outputs the acquired output signal as the sampling signal S2 .

[0046] The selector SL12 selects and outputs one of the H level signal, L level signal and output signal of the selector SL12 based on the selection signals A1 and A2. Specifically, when both the selection signals A1 and A2 indicate the L level, the selector SL12 selects and outputs the output signal of the selector SL11, that is, maintains the output signal. When the selection signal A1 indicates the L level and the selection signal A2 indicates the H level, the selector SL11 selects and outputs the H level signal. In addition, when the selection signal A1 indicates the H level, the selector SL11 selects and outputs the L level signal regardless of the selection signal A2.

[0047] The flip-flop FF12 acquires the output signal of the selector SL12 in synchronization with the rising edge of the clock signal CLK2 , and outputs the acquired output signal as the sampling signal S3 .

[0048] With such a configuration, the timing signal generating circuit 134 sequentially sets the sampling signals S1 to S3 to the H level within a predetermined period, and temporarily sets the comparator signals C1 to C3 to the H level after a period in which the sampling signals S1 to S3 respectively indicate the H level has passed.

[0049] Note that the timing signal generating circuit 134 may be appropriately changed to another configuration having a function equivalent to the above-described configuration.

[0050] Figure 4 1 is a diagram showing a specific configuration example of the clock monitoring circuit 131. Figure 4 As shown, the clock monitoring circuit 131 includes an edge detection circuit ED11, a logic circuit (clock counter) LC1, an edge detection circuit ED12, an expected value storage register RG11, a measured value storage register RG12, and a comparison circuit CP1.

[0051] The edge detection circuit ED11 detects the rising edge of the sampling signal S3 and outputs a pulse signal.

[0052] The logic circuit LC1 includes m flip-flops (m is an integer equal to or greater than 2) connected in cascade, m selectors, and a combinational circuit. Each of the m selectors is set at a previous stage of the m flip-flops, and selectively outputs a signal input to the m flip-flops according to an operation mode (specifically, a logical product of the sampling signal S1 and the self-diagnosis success signal K1).

[0053] For example, when the sampling signal S1 indicates an L level or when the self-diagnosis success signal K1 indicates an L level, the first-stage selector selects and outputs a pulse signal output from the edge detection circuit ED11 to the first-stage trigger. The selector of the k-th stage in the second and subsequent stages (k is an arbitrary integer from 2 to m) selects and outputs the output signal of the trigger in the previous stage (k-1 stage) with respect to the trigger of the k-th stage. That is, when the sampling signal S1 indicates an L level or when the self-diagnosis success signal K1 indicates an L level, the logic circuit LC1 configures the shift register. When the pulse signal is normally output, the shift register shifts (propagates) the pulse signal output from the edge detection circuit ED11 to the output signal.

[0054] For example, when the sampling signal S1 indicates an H level and the self-diagnosis success signal K1 indicates an H level, the first-stage selector selects and outputs a signal obtained by inverting the output signal of the first-stage trigger to the first-stage trigger. The selector of the k-th stage after the second stage selects and outputs the exclusive OR of the output signal of the k-th stage trigger and the output signal of the first to k-1-th stage triggers to the k-th stage trigger. That is, when the sampling signal S1 indicates an H level and the self-diagnosis success signal K1 indicates an H level, the logic circuit LC1 configures a binary counter. The binary counter outputs the corresponding output signals of the plurality of triggers as the count value (measurement value) of the binary counter.

[0055] The edge detection circuit ED12 detects whether or not a pulse of an input signal (a pulse signal output from the edge detection circuit ED11 ) is normally shifted to an output signal of a shift register formed by the logic circuit LC1 .

[0056] For example, when the edge detection circuit ED12 detects that the pulse of the input signal is shifting to the output signal of the shift register, the self-diagnosis success signal K1 is set to the H level. This means that the logic circuit LC1 has not failed. In addition, when the pulse of the input signal is not shifting to the output signal of the shift register, the edge detection circuit ED12 sets the self-diagnosis success signal K1 to the L level. This means that the logic circuit LC1 has failed.

[0057] The measured value storage register RG12 stores a count value (measured value) F1 of a binary counter constituted by the logic circuit LC1 for each predetermined period. The expected value storage register RG11 stores a maximum expected value and a minimum expected value in advance.

[0058] The comparison circuit CP1 compares whether the count value stored in the measurement value storage register RG12 is within the expected value stored in the expected value storage register RG11, for example, in synchronization with the rise of the comparison signal C1, and outputs the comparison result as the monitoring result M1 of the clock signal CLK1. For example, when the count value is within the range of the expected value, the comparison circuit CP1 outputs the monitoring result M1 of the L level, and when the count value is outside the range of the expected value, the monitoring result M1 of the H level is output.

[0059] Note that the configuration of the clock monitoring circuit 131 can be appropriately changed to another configuration having a function equivalent to the above-described configuration.

[0060] Since the specific configuration of the clock monitoring circuit 132 is the same as that of the clock monitoring circuit 131, its description is omitted. However, in the clock monitoring circuit 132, the sampling signal S1 is input instead of the sampling signal S3, the sampling signal S2 is input instead of the sampling signal S1, the monitoring result M2 is output in synchronization with the comparison signal C2 instead of the monitoring result M1 being output in synchronization with the comparison signal C1, the count value F2 is output instead of the count value F1, and the self-diagnosis success signal K2 is generated instead of the self-diagnosis success signal K1. The clock monitoring circuit 132 is provided with a logic circuit LC2 corresponding to the logic circuit LC1.

[0061] Since the specific configuration of the clock monitoring circuit 133 is the same as that of the clock monitoring circuit 131, its description is omitted. However, in the clock monitoring circuit 132, the sampling signal S2 is input instead of the sampling signal S3, the sampling signal S3 is input instead of the sampling signal S1, the monitoring result M3 is output in synchronization with the comparison signal C3 instead of the monitoring result M1 being output in synchronization with the comparison signal C1, the count value F3 is output instead of the count value F1, and the self-diagnosis success signal K3 is generated instead of the self-diagnosis success signal K1. The clock monitoring circuit 133 is provided with a logic circuit LC3 corresponding to the logic circuit LC1.

[0062] The abnormality detection circuit 135 detects an abnormality in the clock signal CLK1 generated by the first oscillator circuit 11 based on the measurement value signals F1 to F3 and the monitoring results M1 to M3 output from the clock monitoring circuits 131 to 133. For example, when the abnormality of the clock signal CLK1 generated by the first oscillator circuit 11 is not detected, the detection signal D1 of the L level is output, and when the abnormality is detected, the detection signal D1 of the H level is output. In addition, the abnormality detection circuit 135 detects a malfunction of the clock monitoring circuits 131 to 133 based on the monitoring results M1 to M3 and the measurement values ​​F1 to F3.

[0063] Figure 5 1 is a diagram showing a specific configuration example of the abnormality detection circuit 135. Figure 5 As shown, the abnormality detection circuit 235 includes comparison circuits CMP1 to CMP3 , OR circuits OR1 - OR3 , a selector SL13 , and a flip-flop FF13 .

[0064] The comparison circuit CMP1 compares a count value (measurement value) F1 counted per predetermined period by the clock counter of the clock monitoring circuit 131 with a count value (measurement value) F3 counted per predetermined period by the clock counter of the clock monitoring circuit 133 in synchronization with the rise of the comparison signal C1.

[0065] The comparison circuit CMP2 compares the count value (measurement value) F1 counted per predetermined period by the clock counter of the clock monitoring circuit 131 with the count value (measurement value) F2 counted per predetermined period by the clock counter of the clock monitoring circuit 132 in synchronization with the rise of the comparison signal C2.

[0066] The comparison circuit CMP3 compares the count value (measurement value) F2 counted per predetermined period by the clock counter of the clock monitoring circuit 132 with the count value (measurement value) F3 counted per predetermined period by the clock counter of the clock monitoring circuit 133 in synchronization with the rise of the comparison signal C3.

[0067] The OR circuit OR1 outputs the logical OR of the monitoring results M1 to M3 through the clock monitoring circuits 131 to 133, respectively. The OR circuit OR2 outputs the logical sum of the comparison results through the comparison circuits CMP1 to CMP3, respectively. The OR circuit OR3 outputs the OR of the outputs of the OR circuits OR1 and OR2. The selector SL13 selects and outputs the output signal of the flip-flop FF13 or the H level signal according to the output signal of the OR circuit OR3. The flip-flop FF13 acquires the output signal of the selector SL13 in synchronization with the rising edge of the clock signal CLK2, and outputs the acquired output signal as the detection signal D1.

[0068] Note that the configuration of the abnormality detection circuit 135 can be appropriately changed to another configuration having a function equivalent to the above-described configuration.

[0069] Next, we will refer to Figure 6 The operation of the semiconductor device 1 is described. Figure 6 is a timing chart showing the operation of the semiconductor device 1 .

[0070] like Figure 6 As shown, the clock monitoring circuits 131 to 133 are controlled so that their operation modes are different from each other.

[0071] Specifically, in the time period from time t11 to time t12, the clock monitoring circuit 131 counts the number of oscillations (sampling) of the clock signal CLK1, the clock monitoring circuit 132 performs self-diagnosis, and the clock monitoring circuit 133 compares the count value of each predetermined time period of the clock signal CLK1 counted in the immediately previous time period with the expected value.

[0072] Thereafter, in the period from time t12 to time t13, the clock monitoring circuit 131 compares the count value of each predetermined period of the clock signal CLK1 counted in the immediately preceding period with the expected value, the clock monitoring circuit 132 counts the number of oscillations (sampling) of the clock signal CLK1, and the clock monitoring circuit 133 performs self-diagnosis.

[0073] Thereafter, in the period from time t13 to time t14, the clock monitoring circuit 131 performs self-diagnosis, the clock monitoring circuit 132 compares the count value of each predetermined period of the clock signal CLK1 counted in the immediately preceding period with the expected value, and the clock monitoring circuit 133 counts the number of oscillations (sampling) of the clock signal CLK1.

[0074] Here, the clock monitoring circuits 131-133 continuously monitor the clock signal CLK1 using any one of them. On the other hand, in another clock monitoring circuit that does not monitor the clock signal CLK1, the clock signal self-diagnosis is compared with the count value and the expected value, and the self-diagnosis is performed.

[0075] Hereinafter, the operation of the semiconductor device 1 will be described in more detail. Although the operation of the clock monitoring circuit 131 among the clock monitoring circuits 131 to 133 will be mainly described below, the operations of the clock monitoring circuits 132 and 133 are basically the same as the operation of the clock monitoring circuit 131 except that the operation timing is different.

[0076] First, when the count value of the down counter DC1 is initialized from "00h" to "2Fh" (that is, when the value of the most significant bit of the count value changes from "0" to "1"), the sampling signal S1 switches from the L level to the H level (time t11). As a result, the clock monitoring circuit 131 starts counting the number of oscillations of the clock signal CLK1 at time t11.

[0077] At this time, in the clock monitoring circuit 131 , since the sampling signal S1 indicates the H level and the self-diagnosis success signal K1 indicates the H level, a binary counter is configured by the logic circuit LC1 .

[0078] Thereafter, when the count value of the down counter DC1 becomes "1Fh" (i.e., when the value of the most significant bit of the count value changes from "1" to "0"), the sampling signal S1 switches from the H level to the L level (time t12). Thus, the measurement of the clock signal CLK1 by the binary counter configured by the logic circuit LC1 ends, and the measured value of the clock signal is stored in the measured value storage register RG12.

[0079] Thereafter, when the count value of the down counter DC1 counts down to "18h", the comparator signal C1 temporarily changes to the H level (time t12a).

[0080] As a result, the comparison circuit CP1 provided in the clock monitoring circuit 131 compares the measured value F1 stored in the measured value storage register RG12 with the expected value stored in the expected value storage register RG11, for example, in synchronization with the rising edge (time t12a) of the comparison signal C1. Figure 6 In this case, the comparison circuit CP1 outputs an L-level monitoring result M1 indicating that the measurement value F1 is within the expected range.

[0081] At this time, the comparison circuit CMP1 provided in the abnormality detection circuit 135 compares the measurement value F1 output from the clock monitoring circuit 131 with the measurement value F3 output from the clock monitoring circuit 133 in synchronization with the rise of the comparison signal C1. For example, when the measurement value F1 and the measurement value F3 coincide with each other, the comparison circuit CMP1 outputs an L level comparison result. Figure 6 In this case, not only the monitoring result M1 but also the monitoring results M2 and M3 indicate an L level, and the respective comparison results of the comparison circuits CMP1 to CMP3 indicate an L level, so that the abnormality detection circuit 135 outputs an L level detection signal D1, indicating that there is no abnormality in the clock signal CLK1 (and there is no fault in the clock monitoring circuits 131 to 133).

[0082] Thereafter, in synchronization with the falling edge of the comparison signal C1, the count value of the binary counter constituted by the logic circuit LC1 is initialized to "0", and the self-diagnosis success signal K1 is switched from the H level to the L level (time t12b).

[0083] When the measurement value F1 exceeds the expected range in the clock monitoring circuit 131, the comparison circuit CP1 outputs the monitoring result M1 of the H level in synchronization with the rise of the comparison signal C1. At this time, the abnormality detection circuit 135 outputs the H level detection signal D1 indicating that the clock signal CLK1 is abnormal.

[0084] When the measurement values ​​F1 and F3 do not coincide with each other in the abnormality detection circuit 135, the comparison circuit CMP1 outputs an H level comparison result in synchronization with the rise of the comparison signal C1. At this time, the abnormality detection circuit 135 outputs an H level detection signal D1 indicating that the clock signal CLK1 is abnormal.

[0085] Thereafter, when the count value of the down counter DC1 counts down to "10h", the selection signal A2 is temporarily set to H level, so that the sampling signal S3 switches from L level to H level (time t13). As a result, the clock monitoring circuit 131 starts the self-diagnosis operation at time t13.

[0086] At this time, in the clock monitoring circuit 131, since the sampling signal S1 indicates the L level, the shift register is configured by the logic circuit signal LC1. By detecting the rising edge of the sampling signal S3, the shift register shifts the pulse signal output from the edge detection circuit ED11 to the output signal from time t13 to t13a.

[0087] exist Figure 6 In the process, since the pulse of the input signal is normally shifted to the output signal of the shift register formed by the logic circuit LC1, the edge detection circuit ED12 switches the self-diagnosis success signal K1 from the L level to the H level (time t13a).

[0088] Thereafter, when the count value of the down counter DC1 counts down to "08h", the comparator signal C2 is temporarily set to the H level. For example, the self-diagnosis success signal K1 is output to the outside in synchronization with the rising edge of the comparison signal C2 (time t13b). Thereafter, in synchronization with the falling edge of the comparison signal C2, the value of the output signal of the shift register constituted by the logic circuit LC1 is initialized to "0" (time t13c).

[0089] Thereafter, when the count value of the down counter DC1 reaches "00h", the count value is initialized to "2Fh" (time t14). Thereafter, the operation from time t11 to t14 is repeated.

[0090] When the pulse of the input signal is not normally shifted to the output signal of the shift register formed by the logic circuit LC1 in the clock monitoring circuit 131, the edge detection circuit ED12 maintains the self-diagnosis success signal K1 at the L level. In the subsequent counting mode, even if the sampling signal S1 switches from the L level to the H level, the logic circuit signal LC1 maintains the configuration of the shift register without switching to the configuration of the binary counter. That is, the clock monitoring circuit 131 does not count the number of oscillations of the clock signal CLK1 in the counting mode. As a result, in the subsequent comparison mode, since the measured value F1 exceeds the expected range, the clock monitoring circuit 131 outputs the monitoring result M1 of the H level from the comparison circuit CP1. At this time, the abnormality detection circuit 135 outputs the H level detection signal D1 indicating that the clock monitoring circuit 131 has failed.

[0091] As described above, in the semiconductor device 1 according to the present embodiment, the clock monitoring circuits 131 to 133 are configured with a counter for counting the number of oscillations of the clock signal CLK1 generated by the first oscillator circuit 11 according to the operation mode, and are configured with a shift register for detecting whether a pulse of an input signal is shifted to an output signal. In other words, in the semiconductor device 1 according to the present embodiment, the clock monitoring circuits 131 to 133 not only monitor the clock signal CLK1, but also self-diagnose the clock signal CLK1 by using a period in which the clock signal CLK1 is not monitored. As a result, unlike the prior art, the semiconductor device 1 according to the present embodiment does not need to additionally provide a verification clock monitoring circuit, and therefore, self-diagnosis of the clock monitoring circuits 131 to 133 can be performed without increasing the circuit size.

[0092] In this embodiment, the timing signal generating circuit 134 periodically switches the operation modes of the clock monitoring circuits 131 to 133 so that the operation modes of the clock monitoring circuits 131 to 133 are different from each other. Therefore, the clock monitoring circuits 131-133 can always use any one of them to monitor the clock signal CLK1.

[0093] In addition, the semiconductor device 1 according to the present embodiment can monitor the clock signal CLK1 by comparing the monitoring results of the clock monitoring circuits 131 to 133 with each other. However, the comparison of the monitoring results of the clock monitoring circuits 131 to 133 can be omitted. In this case, the abnormality detection circuit 135 outputs the detection signal D1 only based on the monitoring results M1 to M3 of the clock monitoring circuits 131 to 133.

[0094] In the present embodiment, three clock monitoring circuits 131 to 133 are provided, but the present invention is not limited thereto. Only one clock monitoring circuit 131 may be provided as long as the clock signal CLK1 does not need to be constantly monitored and can be monitored periodically.

[0095] Figure 7 2 is a block diagram showing an exemplary configuration of a semiconductor device 2 according to the second embodiment. Compared with the semiconductor device 1 , the semiconductor device 2 includes an oscillation abnormality detector 23 instead of the oscillation abnormality detector 13 .

[0096] Figure 8 2 is a block diagram showing a specific configuration example of the oscillation abnormality detector 23. Figure 8 As shown, compared with the oscillation abnormality detector 13, the oscillation abnormality detector 23 includes a timing signal generating circuit 234 instead of the timing signal generating circuit 134, an abnormality detecting circuit 235 instead of the abnormality detecting circuit 135, and only two clock monitoring circuits 131 and 132 of the three clock monitoring circuits 131 to 133.

[0097] The timing signal generating circuit 234 periodically switches the operation modes of the clock monitoring circuits 131 and 132. Specifically, the timing signal generating circuit 234 outputs the sampling signals S1 and S2 and the comparison signals C1 and C2 in synchronization with the rising edge of the clock signal CLK2.

[0098] The down counter DC1 provided in the timing signal generating circuit 234 is, for example, a 5-bit counter, and counts down the count value in synchronization with the rising edge of the clock signal CLK2. In the present embodiment, the down counter DC1 counts down the count value one by one from the maximum value "1Fh" (hexadecimal notation; decimal notation 31) to the minimum value "00h". When the count value reaches the minimum value "00h", the count value returns to the maximum value "1Fh".

[0099] The timing signal generating circuit 234 is configured to output the value of the most significant bit of the 5-bit value constituting the count value of the down counter DC1 as the sampling signal S1. The timing signal generating circuit 234 is configured to raise the sampling signal S2 when the count value of the down counter signal DC1 becomes "0Fh". In addition, the timing signal generating circuit 234 is configured to temporarily set the comparison signals C1 and C2 to the H level at the timing when the count value of the down counter DC1 becomes "08h" and "18h" respectively.

[0100] The clock monitoring circuit 131 receives the reset signal RST instead of the sampling signal S3. Therefore, the edge detection circuit ED11 provided in the clock monitoring circuit 131 detects the rising edge of the reset signal RST instead of the sampling signal S3, and outputs the pulse signal P1.

[0101] The clock monitoring circuit 132 receives the reset signal RST instead of the sampling signal S1. Therefore, the edge detection circuit (circuit corresponding to the edge detection circuit ED11) provided in the clock monitoring circuit 132 detects the rising edge of the reset signal RST instead of the sampling signal S1, and outputs a pulse signal (P1).

[0102] Therefore, the operation mode of the clock monitoring circuits 131 and 132 is set to the self-diagnosis mode while performing initialization by the reset signal RST. Thereafter, the operation mode of the clock monitoring circuits 131 and 132 is periodically switched to become mutually different modes between the count mode and the comparison mode.

[0103] The abnormality detection circuit 235 detects an error in the clock signal CLK1 generated by the first oscillator circuit 11 based on the monitoring results M1, M2 and the measurement values ​​F1, F2 respectively by the clock monitoring circuits 131, 132. For example, when the clock signal CLK1 generated by the first oscillator circuit 11 is normal, the detection signal D1 of the L level is output, and when the abnormality of the clock signal CLK1 is detected, the detection signal D1 of the H level is output. In addition, the abnormality detection circuit 235 detects a malfunction of the clock monitoring circuit 131 or 132 based on the monitoring result M1 or M2 and the measurement value F1 or F2.

[0104] Fig. 9 2 is a diagram showing a specific configuration example of the abnormality detection circuit 235. Fig. 9 As shown, the abnormality detection circuit 235 includes a comparison circuit CMP1, OR circuits OR1, OR3, a selector SL13 and a flip-flop circuit FF13.

[0105] The comparison circuit CMP1 compares the count value (measurement value) F1 counted by the clock counter of the clock monitoring circuit 131 and the count value (measurement value) F2 counted by the clock counter of the clock monitoring circuit 132 every predetermined period in synchronization with the rising edges of the comparison signal C1 and the comparison signal C2.

[0106] The logical sum circuit OR1 outputs the logical sum of the monitoring results M1 and M2 respectively passed through the clock monitoring circuits 131 and 132. The OR circuit OR3 outputs the logical sum of the output of the OR circuit OR1 and the comparison result of the comparison circuit CMP1. The selector SL13 selects and outputs the H level signal or the output signal of the flip-flop FF13 according to the output signal of the OR circuit OR3. The flip-flop FF13 acquires the output signal of the selector SL13 in synchronization with the rising edge of the clock signal CLK2, and outputs the acquired output signal as the detection signal D1.

[0107] Note that the configuration of the abnormality detection circuit 235 can be appropriately changed to another configuration having a function equivalent to the above-described configuration.

[0108] Since the remaining configuration of the oscillation abnormality detector 23 is the same as that of the oscillation abnormality detector 13 , the description thereof is omitted.

[0109] Next, we will refer to Fig.10 The operation of the semiconductor device 2 is described. Fig.10 is a timing chart showing the operation of the semiconductor device 2 .

[0110] like Fig.10 As shown, first, during the period from time t21 to time t22, the clock monitoring circuits 131 and 132 are both self-diagnosed. Thereafter, after time t22, the clock monitoring circuits 131 and 132 count the number of oscillations (sampling) of the clock signal CLK1 alternately. When one of the clock monitoring circuits 131 and 132 counts the number of oscillations of the clock signal CLK1, the other compares the count value of the clock signal CLK1 just counted per predetermined period with the expected value.

[0111] Hereinafter, the operation of the semiconductor device 2 will be described in more detail. Although the operation of the clock monitoring circuit 131 of the clock monitoring circuits 131 and 132 will be mainly described below, the operation of the clock monitoring circuit 132 is basically the same as that of the clock monitoring circuit 131 except that the operation timing is different.

[0112] First, at time t21, both sampling signals S1 and S2 are at L level. Therefore, each of the clock monitoring circuits 131 and 132 performs a self-diagnostic operation from time t21 to time t22.

[0113] At this time, in the clock monitoring circuit 131, since the sampling signal S1 indicates the L level, the shift register is configured by the logic circuit signal LC1. The shift register detects the rising edge of the reset signal RST to shift the pulse signal (P1) output from the edge detection circuit ED11 to the output signal (time t21a-t21b).

[0114] exist Fig.10 In the process, since the pulse of the input signal is normally shifted to the output signal of the shift register formed by the logic circuit LC1, the edge detection circuit ED12 switches the self-diagnosis success signal K1 from the L level to the H level (time t21b).

[0115] At this time, in the clock monitoring circuit 132, since the sampling signal S2 indicates the L level, the shift register is configured by the logic circuit signal LC2. The shift register shifts the pulse signal (P1) output from the edge detection circuit (corresponding to the edge detection circuit ED11) to the output signal by detecting the rising edge (time t21a-t21b) of the reset signal RST.

[0116] exist Fig.10 In the process, since the pulse of the input signal is normally shifted to the output signal of the shift register formed by the logic circuit LC2, the circuit corresponding to the edge detection circuit ED12 switches the self-diagnosis success signal K2 from the L level to the H level (time t21b).

[0117] When the pulse of the input signal is not normally shifted to the output signal of the shift register formed by the logic circuit LC1 in the clock monitoring circuit 131, the edge detection circuit ED12 maintains the self-diagnosis success signal K1 at the L level. In the subsequent counting mode, even if the sampling signal S1 switches from the L level to the H level, the logic circuit signal LC1 maintains the configuration of the shift register without switching to the configuration of the binary counter. That is, the clock monitoring circuit 131 does not count the number of oscillations of the clock signal CLK1 in the counting mode. As a result, since the measured value F1 exceeds the expected range in the subsequent comparison mode, the clock monitoring circuit 131 outputs the H level monitoring result M1. At this time, the abnormality detection circuit 235 outputs the H level detection signal D1 indicating that the clock monitoring circuit 131 has failed.

[0118] Similarly, in the clock monitoring circuit 132, if the pulse of the input signal is not normally shifted to the output signal of the shift register configured by the logic circuit LC2, the circuit corresponding to the edge detection circuit ED12 keeps the self-diagnosis success signal K2 at the L level. In the subsequent counting mode, even if the sampling signal S2 is switched from the L level to the H level, the logic circuit signal LC2 maintains the configuration of the shift register without switching to the configuration of the binary counter. That is, the clock monitoring circuit 132 does not count the number of oscillations of the clock signal CLK1 in the counting mode. As a result, since the measured value F2 exceeds the expected range in the subsequent comparison mode, the clock monitoring circuit 132 outputs the H level monitoring result M2. At this time, the abnormality detection circuit 235 outputs the H level detection signal D1 indicating that the clock monitoring circuit 132 has failed.

[0119] Thereafter, when the count value of the down counter DC1 is set to the maximum value "1Fh" (i.e., when the value of the most significant bit of the count value is set to "1"), the sampling signal S1 switches from the L level to the H level (time t22). As a result, the clock monitoring circuit 131 starts counting the number of oscillations of the clock signal CLK1 at time t22.

[0120] At this time, in the clock monitoring circuit 131 , since the sampling signal S1 indicates the H level and the self-diagnosis success signal K1 indicates the H level, a binary counter is configured by the logic circuit LC1 .

[0121] Thereafter, when the count value of the down counter DC1 counts down to "0Fh" (i.e., when the value of the most significant bit of the count value changes from "1" to "0"), the sampling signal S1 switches from the H level to the L level (time t23). Thus, the measurement of the clock signal CLK1 by the binary counter configured by the logic circuit LC1 ends, and the measured value of the clock signal is stored in the measured value storage register RG12.

[0122] Thereafter, when the count value of the down counter DC1 counts down to "08h", the comparator signal C1 temporarily changes to the H level (time t23a).

[0123] Therefore, the comparison circuit CP1 provided in the clock monitoring circuit 131 compares the measured value F1 stored in the measured value storage register RG12 with the expected value stored in the expected value storage register RG11, for example, in synchronization with the rising edge (time t23a) of the comparison signal C1. Fig.10 , the comparison circuit CP1 outputs an L-level monitoring result M1 indicating that the measurement value F1 is within the expected range.

[0124] Thereafter, in synchronization with the falling edge of the comparator C1, the count value of the binary counter formed by the logic circuit LC1 is initialized to "0" (time t23b).

[0125] When the measured value F1 exceeds the expected range in the clock monitoring circuit 131, the comparison circuit CP1 outputs the monitoring result M1 of the H level in synchronization with the rise of the comparison signal C1. At this time, the abnormality detection circuit 235 outputs the H level detection signal D1 indicating that the clock signal CLK1 is abnormal.

[0126] During a period in which the clock monitoring circuit 131 compares the measured value F1 with the expected value, the clock monitoring circuit 132 counts the number of oscillations of the clock signal CLK1 from time t23 to time t24.

[0127] Thereafter, when the count value of the down counter DC1 reaches "00h", the count value is initialized to "2Fh" (time t24). Thereafter, the operation from time t22 to t24 is repeated.

[0128] The comparison circuit CMP1 provided in the abnormality detection circuit 235 compares the measurement value F1 output from the clock monitoring circuit 131 with the measurement value F2 output from the clock monitoring circuit 132 in synchronization with the rising edges of the comparison signal C1 and the comparison signal C2. For example, when the measurement value F1 and the measurement value F2 coincide with each other, an L level comparison result is output. Fig.10In the example, since the monitoring results M1 and M2 show L level and the comparison result of the comparison circuit CMP1 shows L level, the abnormality detection circuit 235 outputs an L level detection signal D1 indicating that the clock signal CLK1 has no error and the clock monitoring circuits 131 and 132 have no failure.

[0129] When the measurement values ​​F1 and F3 do not coincide with each other in the abnormality detection circuit 235, the comparison circuit CMP1 outputs an H level comparison result in synchronization with the rise of the comparison signal C1. At this time, the abnormality detection circuit 235 outputs an H level detection signal D1 indicating that the clock signal CLK1 is abnormal.

[0130] As described above, in the semiconductor device 2 according to the present embodiment, the respective clock monitoring circuits 131 and 132 are configured with a counter for counting the number of oscillations of the clock signal CLK1 generated by the first oscillator circuit 11 according to the operation mode, and a shift register for detecting whether a pulse of an input signal is shifted to an output signal. That is, in the semiconductor device 2 according to the present embodiment, the clock monitoring circuits 131, 132 perform self-diagnosis not only by monitoring the clock signal CLK1 but also by utilizing a period in which the clock signal CLK1 is not monitored. As a result, the semiconductor device 2 according to the present embodiment can perform self-diagnosis of the clock monitoring circuits 131, 132 with a circuit size smaller than that of the semiconductor device 1.

[0131] Furthermore, in the present embodiment, in a predetermined period after initialization by the reset signal RST, the operation mode of each of the clock monitoring circuits 131 and 132 is set to the self-diagnosis mode, and thereafter, the operation mode of each of the clock monitoring circuits 131 and 132 is periodically switched so that the operation mode of each of the count mode and the comparison mode is different from each other between the count mode and the comparison mode. As a result, the clock monitoring circuit 131 or 132 can always monitor the clock signal CLK1 by using one of the clock signals after performing self-diagnosis.

[0132] In addition, the semiconductor device 2 according to the present embodiment can monitor the clock signal CLK1 by comparing the monitoring results of the clock monitoring circuits 131 and 132 with each other. However, the comparison of the monitoring results of the clock monitoring circuits 131 and 132 can be omitted. Then, the abnormality detection circuit 235 is configured to output a detection signal based only on the monitoring results M1, M2 by the clock monitoring circuits 131, 132.

[0133] Fig.113 is a diagram showing a specific configuration of an abnormality detection circuit 335 provided in the semiconductor device 3 according to the third embodiment. Compared with the abnormality detection circuit 135, the abnormality detection circuit 335 further includes a selector SL31, a difference storage register RG31, a comparison circuit CP31, and a flip-flop FF31.

[0134] In response to the comparison signals C1 to C3, the selector SL31 selects and outputs one of the following items: the difference between the measurement value F1 and the measurement value F3 compared by the comparison circuit CMP1, the difference between the measurement value F1 and the measurement value F2 compared by the comparison circuit CMP2, and the difference between the measurement value F2 and the measurement value F3 compared by the comparison circuit CMP3. For example, when the comparison signal C1 is at an H level, the selector SL31 selects and outputs the difference output from the comparison result CMP1, when the comparison signal C2 is at an H level, the difference output from the comparison result CMP2 is selected and output, and when the comparison signal C3 is at an H level, the difference output from the comparison result CMP3 is selected and output.

[0135] The difference values ​​output from the selector SL31 are sequentially stored in the difference value storage register RG31.

[0136] The comparison circuit CP31 compares the latest difference value stored in the difference storage register RG31 with the difference value stored immediately before the latest difference value. Here, when the difference between the latest difference value and the immediately preceding difference value is greater than a predetermined value, the comparison circuit CP31 outputs a comparison result indicating that the oscillation frequency of the clock signal CLK1 generated by the first oscillator circuit 11 may exceed the allowable range. The flip-flop FF31 acquires the comparison result by the comparison circuit CP31 in synchronization with the rising edge of the clock signal CLK2, and outputs the acquired result as a warning signal. The warning signal is used, for example, as an interrupt signal indicating a precursor of a failure of the first oscillator circuit 11.

[0137] Since the remaining configuration of the semiconductor device 3 is the same as that of the semiconductor device 1 , the description thereof is omitted.

[0138] As described above, the semiconductor device 3 according to the present embodiment can exhibit the same effects as the semiconductor device 1 and can detect the presence of a malfunction sign in the first oscillator circuit 11 by monitoring changes in the measured value of the number of oscillations of the clock signal CLK1 .

[0139] As described above, in the semiconductor devices according to the first to third embodiments, the corresponding clock monitoring circuit is configured with a counter for counting the number of oscillations of the clock signal generated by the oscillation circuit according to the operation mode, and is configured with a shift register for detecting whether the pulse of the input signal is shifted to the output signal. That is, in the semiconductor devices according to the first to third embodiments, the clock monitoring circuit performs self-diagnosis not only by monitoring the clock signal but also by using a period in which the clock signal is not monitored. As a result, unlike the prior art, the semiconductor devices according to the first to third embodiments do not require an additional verification clock monitoring circuit, and therefore, self-diagnosis of the clock monitoring circuit can be performed without increasing the circuit size.

[0140] Although the invention made by the inventors has been specifically described based on the embodiments, the present invention is not limited to the embodiments that have been described, and it goes without saying that various modifications can be made without departing from the gist thereof.

Claims

1. A semiconductor device, comprising: A first oscillator circuit generates an internal clock signal; a first clock monitoring circuit; and a mode switching circuit, which periodically switches the operation mode of the first clock monitoring circuit to any one of the first mode, the second mode and the third mode, Wherein, the first clock monitoring circuit comprises: a first clock counter; a first comparison circuit; and The first detection circuit, Among them, the first clock monitoring circuit performs counting processing in the first mode, and the counting processing counts the number of oscillations by using the first clock counter; performs comparison processing in the second mode, and the comparison processing determines whether the number of oscillations is within a predetermined range by using the first comparison circuit; and performs detection processing in the third mode, and the detection processing detects whether the pulse of the input signal is shifted to the output signal by using the first detection circuit.

2. The semiconductor device according to claim 1, in, The first clock counter comprises: Multiple cascading triggers; and a plurality of selectors that switch a signal input to each of the plurality of cascade flip-flops according to the operation mode; and The first clock counter configures a binary counter by using the plurality of cascade flip-flops in the first mode, and configures a shift register by using the plurality of cascade flip-flops in the third mode.

3. The semiconductor device according to claim 1, further comprising: The second clock monitoring circuit, wherein the mode switching circuit is configured to periodically switch the operation mode of the second clock monitoring circuit to any one of the first mode, the second mode and the third mode, and Wherein, the second clock monitoring circuit comprises: a second clock counter configured to count oscillations in the first mode and to shift the pulses of the input signal to the output signal in a normal state in the third mode; a second comparison circuit to determine whether a count value of the second clock counter during a predetermined period is within an expected value, and A second detector detects whether the pulse of the input signal is shifted to the output signal of the second clock counter in the third mode.

4. The semiconductor device according to claim 3, in, Each of the first clock counter and the second clock counter comprises: Multiple cascading triggers; a plurality of selectors that switch a signal input to each of the plurality of cascade flip-flops according to a provided operation mode, and The first clock counter configures a binary counter by using the plurality of cascade flip-flops in the first mode, and configures a shift register by using the plurality of cascade flip-flops in the third mode.

5. The semiconductor device according to claim 3, in, The mode switching circuit is configured to switch the operation modes of the first clock monitoring circuit and the second clock monitoring circuit, so that in a first time period, the operation modes of the first clock monitoring circuit and the second clock monitoring circuit are switched to the third mode, and in a second time period after the first time period, the operation modes of the first clock monitoring circuit and the second clock monitoring circuit are periodically switched to mutually different operation modes in the first mode and the second mode.

6. The semiconductor device according to claim 5, in, In the third mode, the pulses of the input signals of the first and second clock counters are generated by initializing a peripheral circuit operating in synchronization with the internal clock signal using a reset signal.

7. The semiconductor device according to claim 3, further comprising: The third clock monitoring circuit, wherein the mode switching circuit is configured to periodically switch the operation mode of the third clock monitoring circuit to any one of the first mode, the second mode and the third mode, and Wherein, the third clock monitoring circuit comprises: a third clock counter configured to count oscillations of the internal clock signal in the first mode and to shift the pulses of the input signal to the output signal in a normal state in the third mode; a third comparison circuit to determine whether a count value of the third clock counter during a predetermined period is within an expected value, and A third detector detects whether the pulse of the input signal is shifted to the output signal of the third clock counter in the third mode.

8. The semiconductor device according to claim 7, in, Each of the first clock counter, the second clock counter and the third clock counter comprises: Multiple cascaded triggers; and a plurality of selectors for switching a signal input to each of the plurality of cascade flip-flops according to a provided operation mode, The first clock counter configures a binary counter by using the plurality of cascade flip-flops in the first mode, and configures a shift register by using the plurality of cascade flip-flops in the third mode.

9. The semiconductor device according to claim 7, in, The mode switching circuit is a mode switching circuit for operating each of the first clock monitoring circuit, the second clock monitoring circuit and the third clock monitoring circuit, and the mode switching circuit is a mode switching circuit for operating each of the first mode, the second mode and the third mode.

10. The semiconductor device according to claim 7, further comprising: Count value comparison circuit, wherein, during a period in which the first clock counter counts the number of oscillations of the internal clock signal, the count value comparison circuit compares the count value of the second clock counter per predetermined period with the count value of the third clock counter per predetermined period, wherein, during a period in which the second clock counter counts the number of oscillations of the internal clock signal, the count value comparison circuit compares the count value of the third clock counter per predetermined period with the count value of the first clock counter per predetermined period, During a period in which the third clock counter counts the number of oscillations of the internal clock signal, the count value comparison circuit compares the count value of the first clock counter per predetermined period with the count value of the second clock counter per predetermined period.

11. The semiconductor device according to claim 7, in, When the difference between any of the first difference value, the second difference value, and the third difference value and the difference value output immediately before any of the first difference value, the second difference value, and the third difference value is greater than a predetermined value, a warning signal is output, wherein the first difference value is the difference between the count values ​​of each of the second clock counter and the third clock counter per predetermined period, the second difference value is the difference between the count values ​​of each of the third clock counter and the first clock counter per predetermined period, and the third difference value is the difference between the count values ​​of each of the first clock counter and the second clock counter per predetermined period.

12. A method of controlling a semiconductor device, in, The semiconductor device comprises: A first oscillator circuit generates an internal clock signal; a first clock monitoring circuit; and a mode switching circuit for periodically switching the operation mode of the first clock monitoring circuit to any one of a first mode, a second mode and a third mode, and Wherein, the method comprises: A counting step of counting the number of oscillations of the internal clock signal by using a first clock counter in the first clock monitoring circuit in the first mode; A comparing step of determining whether the number of oscillations of the internal clock signal is within an expected range by using a first comparing circuit in the first clock monitoring circuit in the second mode; and A detecting step of detecting whether a pulse of an input signal is shifted to an output signal by using a first detecting circuit in the first clock monitoring circuit in the third mode.

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