Memory device and method for reading data

Abstract

A nonvolatile memory and a vertical NAND flash memory are provided. The nonvolatile memory includes: a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region; a first bit line and a second bit line; an outer memory cell string including memory cells connected to outer pillars extending through the outer region; an inner memory cell string including memory cells connected to inner pillars extending through the inner region; and a data input / output circuit. The data input / output circuit includes: a page buffer circuit connected to the first bit line during a first read operation and connected to the second bit line during a second read operation; and a read voltage determination unit that selects a first optimal read voltage for use during the first read operation and a second optimal read voltage for use during the second read operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2018-0113034 filed on September 20, 2018, in the Korean Intellectual Property Office, the subject matter of which is incorporated herein by reference. Technical Field

[0003] The present inventive concept generally relates to memory devices. More particularly, certain embodiments of the present inventive concept relate to a nonvolatile memory device that performs a read operation using one of a plurality of candidate read voltages. Background Art

[0004] Semiconductor memory devices can be roughly divided into two categories based on whether they retain stored data when power is removed. These categories include volatile memory devices that lose stored data when power is removed, and non-volatile memory devices that retain stored data when power is removed. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM), and examples of non-volatile memory devices include flash memory devices and read-only memory (ROM).

[0005] Among nonvolatile memories, flash memory devices have become increasingly popular in recent years due to attractive features such as relatively low cost, high storage capacity, low power consumption, fast access speed, and resistance to physical shock.

[0006] Depending on the design of the memory, the memory cell of the flash memory can store one bit of data or multiple bits of data. In the case of a memory cell storing one bit of data, it may have a threshold voltage corresponding to one of two threshold voltage states representing data "1" and data "0". In the case of a memory cell storing two bits of data, it may have a threshold voltage corresponding to one of four threshold voltage states representing data "11", "10", etc. In the case of a memory cell storing three bits of data, it may have a threshold voltage corresponding to one of eight threshold voltage states representing data "111", "110", etc.

[0007] During a read operation, one or more memory cells storing a specific data value can be interrogated or "read." A read operation can be defined differently depending on the performance characteristics of the components comprising the memory device. However, a read operation is typically performed by selectively applying one or more control voltages to various components of a memory cell array, including the memory cells to be read. Accurately defining and applying the appropriate read voltages is an important consideration in defining a read operation. Summary of the Invention

[0008] Embodiments of the inventive concept provide a memory device that offers improved performance during a read operation.

[0009] In one embodiment, the present invention provides a nonvolatile memory device comprising: a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region; a first bit line and a second bit line; an outer memory cell string including memory cells connected to outer pillars extending vertically upward through the outer region; an inner memory cell string including memory cells connected to inner pillars extending vertically upward through the inner region; and a data input / output (I / O) circuit. The data I / O circuit comprises: a page buffer circuit connected to the first bit line during a first read operation for memory cells of the outer memory cell string and connected to the second bit line during a second read operation for memory cells of the inner memory cell string; and a read voltage determination unit that selects a first optimal read voltage for use during the first read operation and a second optimal read voltage for use during the second read operation.

[0010] In another embodiment, the present invention contemplates providing a nonvolatile memory comprising: a memory cell region including a first end, an external region proximate the first end, and an internal region separated from the first end by the external region; a first bit line and a second bit line; an external memory cell string including memory cells connected to external pillars extending vertically upward through the external region; an internal memory cell string including memory cells connected to internal pillars extending vertically upward through the internal region; and a data input / output (I / O) circuit. The data I / O circuit includes: a page buffer circuit, which includes a first page buffer and a second page buffer, the first page buffer being connected to a first bit line during a first read operation for memory cells of an external memory cell string, and the second page buffer being connected to a second bit line during a second read operation for memory cells of an internal memory cell string; and a read voltage determination unit, which selects a first optimal read voltage used during the first read operation and a second optimal read voltage different from the first optimal read voltage used during the second read operation, wherein the first page buffer includes a first storage register storing a first candidate read voltage and a second storage register storing a second candidate read voltage, and the read voltage determination unit selects one of the first candidate read voltage and the second candidate read voltage as the first optimal read voltage.

[0011] In another embodiment, the present invention contemplates a vertical NAND flash memory comprising: a NAND memory cell region defined at a first end by a first word line cut and at a second end opposite the first end by a second word line cut, wherein the NAND memory cell region comprises a first outer region proximate the first end, a second outer region proximate the second end, and an inner region between the first outer region and the second outer region; bit lines extending above the memory cell region and comprising a first bit line and a second bit line; a first outer NAND string comprising a NAND cell connected to a first outer pillar, the first outer pillar extending vertically upward through the first outer region; a second outer NAND string comprising a NAND cell connected to a second outer pillar, the second outer pillar extending vertically upward through the second outer region; a first inner NAND string comprising a NAND cell connected to the first inner pillar, the first inner pillar extending vertically upward through the inner region; a second inner NAND string comprising a NAND cell connected to the second inner pillar, the second inner pillar extending vertically upward through the inner region; and a data input / output (I / O) circuit. The data I / O circuit includes: a page buffer circuit including a first page buffer and a second page buffer, the first page buffer being connected to a first bit line during a first read operation for memory cells of at least one of the first external NAND string and the second external NAND string, the second page buffer being connected to a second bit line during a second read operation for memory cells of at least one of the first internal NAND string and the second internal NAND string; and a read voltage determination unit that selects a first optimal read voltage for use during the first read operation and a second optimal read voltage for use during the second read operation.

[0012] In another embodiment, the present invention provides a method for reading data in a nonvolatile memory, the nonvolatile memory comprising: a memory cell region having a first end, an outer region proximate the first end, and an inner region separated from the first end by the outer region; a first bit line and a second bit line; an outer memory cell string comprising a first memory cell connected to an outer pillar extending vertically upward through the outer region; an inner memory cell string comprising a second memory cell connected to an inner pillar extending vertically upward through the inner region; and a data input / output (I / O) circuit. The method comprises: sensing a data set stored in at least one of the first memory cell and the second memory cell; sampling the data set to determine a plurality of candidate read voltages; and selecting one of the plurality of candidate read voltages as a first optimal read voltage for reading the first memory cell, and selecting one of the candidate read voltages as a second optimal read voltage for reading the second memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features of the inventive concept will become more apparent in view of certain exemplary embodiments shown in the accompanying drawings, in which:

[0014] Figure 1 is a block diagram illustrating a memory system 100 according to an embodiment of the inventive concept;

[0015] Figure 2 This is to further illustrate an embodiment of Figure 1 A block diagram of a memory device 500;

[0016] Figure 3 This is further illustrated in an example Figure 2 A perspective view of a memory cell array 510;

[0017] Figure 4 yes Figure 2 and Figure 3 An equivalent circuit diagram of a memory cell array 510;

[0018] Figure 5 This is further illustrated in an example Figure 2 and Figure 3 A plan view of a memory cell array 510;

[0019] Figure 6 It further shows Figure 5 A conceptual circuit diagram of a specific connection relationship of NAND strings in a memory cell array;

[0020] Figure 7 This is further illustrated in an example Figure 2 A block diagram of the data I / O circuit;

[0021] Figure 8 This is further illustrated in an example Figure 7 A block diagram of a page buffer circuit 531;

[0022] Figure 9 and Figure 10 They are shown respectively Figure 8 A conceptual circuit diagram of a first page buffer and a second page buffer;

[0023] Figure 11 、 Figure 14 and Figure 15 They are shown as follows: Figure 7 A conceptual diagram of various physical configurations of the page buffer circuit 531;

[0024] Figure 12 It shows Figure 5 a scatter plot of memory cell read results showing a characteristic difference between a first pillar memory cell and a second pillar memory cell;

[0025] Figure 13 is a set of scatter plots further illustrating the foregoing; and

[0026] Figure 16 is a flowchart summarizing a method of reading a memory device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0027] Various memory devices and methods for reading data from such memory devices will be described with reference to the accompanying drawings. The illustrated embodiments are provided as teaching examples. The scope of the inventive concept is defined by the appended claims and their equivalents. Those skilled in the art will recognize that modifications may be made to the illustrated embodiments without departing from the scope of the inventive concept.

[0028] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the inventive concept.

[0029] refer to Figure 1 , the memory system 100 may generally include a memory controller 300 and at least one memory device 500 .

[0030] The memory device 500 may perform (or implement) various data access operations, including read operations, write operations, and erase operations, under the control of the memory controller 300. For example, during a read operation, the memory controller 300 may provide one or more control signals CTRL, one or more commands CMD, and one or more addresses ADDR to the memory device 500 in order to retrieve data DATA stored in the memory device 500. During a write (or program) operation, the memory controller 300 may provide one or more control signals CTRL, one or more commands CMD, one or more addresses ADDR, and write data DATA to be stored in the memory device 500 to the memory device 500.

[0031] Figure 2 This is to further illustrate a specific embodiment Figure 1 1 is a block diagram of a memory device 500.

[0032] refer to Figure 2 , the memory device 500 includes a memory cell array 510 , an address decoder 520 , a data input / output (I / O) circuit 530 , a voltage generating circuit 550 , and a control logic 560 .

[0033] The memory cell array 510 may be connected to the address decoder 520 via word lines WL and selection lines such as string selection lines SSL and ground selection lines GSL. The memory cell array 510 may also be connected to the data I / O circuit 530 via bit lines BL.

[0034] As will be appreciated by those skilled in the art, the memory cell array 510 may include a large number of memory cells arranged in rows and columns. Each memory cell may be configured to store one bit of data or multiple bits of data. In certain embodiments of the present inventive concept, the memory cell array 510 may be a plurality of memory cells as described below. Figure 3 、 Figure 4 and Figure 5 Describes the vertical NAND flash memory type.

[0035] The address decoder 520 may be configured to operate in response to one or more control signals provided by the control logic 560 and / or an externally provided address ADDR (e.g., a row address). Assuming that the address decoder 520 is configured to decode the externally provided row address ADDR, the address decoder 520 may select a word line identified by the decoded row address from a plurality of word lines WL. The address decoder 520 may also be configured to select various select lines (e.g., a string select line SSL and / or a ground select line GSL) in response to the decoded row address.

[0036] In this regard, the address decoder 520 may also be configured to provide various voltages received from the voltage generation circuit 550 in order to select / deselect one or more word lines and / or select lines.

[0037] The address decoder 520 (or alternatively, another separately provided address decoder) may be used to decode a column address received as part of an externally provided address ADDR. Here, the address decoder 520 may provide the decoded column address DCA to the data I / O circuit 530. Therefore, in certain embodiments of the present inventive concept, the address decoder 520 may include a row decoder for decoding a row address, a column decoder for decoding a column address, and an address buffer for storing the received address ADDR.

[0038] The data I / O circuit 530 may alternatively be used to output read data retrieved from the memory cell array 510 to an external device during a read operation, or to receive write (or programming) data to be written to the memory cell array 510 from an external device during a write operation. In either operating mode, the data I / O circuit 530 may operate in response to one or more control signals provided by the control logic 560 and a decoded column address DCA provided by the address decoder 520. In this regard, the data I / O circuit 530 may select one or more bit lines BL in response to the decoded column address DCA and the control signals provided by the control logic 560.

[0039] The data I / O circuit 530 may be variously configured and may include elements such as a page buffer (or page register), a sense amplifier, a write driver, a column selection circuit, etc., in order to exchange data with one or more external devices.

[0040] The voltage generation circuit 550 may be connected to the memory cell array 510, the address decoder 520, and the control logic 560. The voltage generation circuit 550 receives an externally provided power signal (e.g., a power supply voltage Vcc and a ground voltage Vss) and generates various control voltages from the power signal in response to a control signal received from the control logic 560. Those skilled in the art will recognize that control voltages commonly used during read / write operations include a high voltage Vpp, a program voltage Vpgm, a pass voltage Vpass, a read voltage Vread, and an erase voltage Vers.

[0041] Under the control of the control logic 560, the control voltages generated by the voltage generation circuit 550 are variously and selectively provided to the address decoder 520 and the memory cell array 510. For example, during a program operation, the program voltage Vpgm and the pass voltage Vpass may be provided to the memory cell array 510 through the address decoder 520; during a read operation, the read voltage Vread may be provided to the memory cell array 510 through the address decoder 520; and during an erase operation, the erase voltage Vers may be provided to the memory cell array 510. However, these are merely convenient examples of the many different control voltages that may be generated by the voltage generation circuit 550 during one or more data access operations.

[0042] As described above, the control logic 560 may be connected to the address decoder 520, the data I / O circuit 530, and the voltage generation circuit 550 to control the operation and interoperation of these and other components within the memory device 500. The control logic 560 may control the overall operation of the memory device 500 in response to one or more externally provided control signals CTRL.

[0043] Figure 3 An example of a vertical NAND memory structure is shown. Figure 2 1 is a perspective view of a memory cell array 510.

[0044] refer to Figure 3 , assuming that the first direction D1 is a vertical direction, the second direction D2 is a first horizontal direction intersecting the vertical direction D1, and the third direction D3 is a second horizontal direction intersecting the vertical direction D1 and the first horizontal direction D2. Here, the vertical direction D1, the first horizontal direction D2, and the second horizontal direction D3 are substantially orthogonal to each other.

[0045] The memory cell array 510 may include a plurality of word lines WL vertically stacked on a substrate 501 between at least one ground select line GSL and at least one string select line SSL. The different vertical word line WL stacks may be separated by a word line cut region WDCT. Various doped regions DOP may be formed in the word line cut region WDCT on the substrate, and the doped regions DOP may be used as a common source node or common source line CSL, through which a common source voltage is supplied.

[0046] A plurality of vertical channels or channel holes pass through at least one ground selection line GSL, a plurality of word lines WL, and at least one string selection line SSL. A bit line BL may be connected to upper surfaces of the plurality of vertical channels and may extend in a second horizontal direction D3.

[0047] The memory cell array 510 can be effectively divided into a plurality of memory cell array regions Rm by the word line cutting region WDCT. In this regard, the respective memory cell array regions (or memory groups) Rm can be physically separated and electrically isolated from each other by the word line cutting region division.

[0048] Figure 4 yes Figure 2 and Figure 3 FIG. 5 is an equivalent circuit diagram of a relevant portion of a memory cell array 510 of a memory device 500 .

[0049] refer to Figure 4 , the memory cell array 510 may include a plurality of NAND memory cell strings NS, each NAND memory cell string NS extending in a vertical direction D1. (Hereinafter, the term "memory cell string" is used to refer to an element of a vertical memory cell array that connects a plurality of memory cells and extends substantially in a vertical direction, regardless of the memory cell type, such as flash memory, resistive memory, magnetic memory, etc.) The plurality of NAND memory cell strings NS may be arranged in a first horizontal direction D2 to form a string column, and the plurality of string columns may be arranged in a second horizontal direction D3 to form a string array.

[0050] Figure 4 Each NAND memory cell string NS includes at least one ground selection transistor GSTV, a memory cell MC, and at least one string selection transistor SSTV arranged in series in a vertical direction D1 between a common source line CSL and bit lines BL(1), ..., BL(m). The ground selection transistor GSTV can be connected to ground selection lines GSL11, GSL12, ..., GSLi1, GSLi2, and the string selection transistor SSTV can be connected to string selection lines SSL11, SSL12, ..., SSLi1, SSLi2.

[0051] Memory cells MC arranged in the same layer can be commonly connected to one of the word lines WL(1), WL(2), ..., WL(n-1), WL(n). Multiple ground selection lines GSL11, ..., GSLi2 and multiple string selection lines SSL11, ..., SSLi2 can extend in the first horizontal direction D2 and can be arranged in the second horizontal direction D3. Multiple word lines WL(1), ..., WL(n) can extend in the first horizontal direction D2 and can be arranged in the vertical direction D1 and the second horizontal direction D3. Multiple bit lines BL(1), ..., BL(m) can extend in the second horizontal direction D3 and can be arranged in the first horizontal direction D2. The memory cells MC can be controlled according to the level of the voltage applied to the word lines WL(1), ..., WL(n).

[0052] A vertical or three-dimensional (3D) NAND flash memory device including the memory cell array 510 includes NAND flash memory cells and thus performs write / read operations according to a page size unit while performing erase operations according to a block size unit.

[0053] In some embodiments, two string selection transistors SSTV included in one NAND memory cell string NS may be connected to one string selection line, and two ground selection transistors GSTV included in one NAND memory cell string NS may be connected to one ground selection line. In some embodiments, one NAND memory cell string NS may include one string selection transistor SSTV and one ground selection transistor GSTV.

[0054] Figure 5 is a plan view further illustrating some embodiments of the present inventive concept, wherein a memory cell array 510 includes a plurality of vertically (ie, vertical direction D1) arranged pillars P, which are variously connected to bit lines BL extending in a second horizontal direction D3. Figure 5 The memory cell array 510 described in the context of Figure 2 and Figure 3 The embodiment is described (for example, as the memory cell array region Rm).

[0055] refer to Figure 3 、 Figure 4 and Figure 5, the common source line CSL corresponding to the doping region DOP can be arranged in the corresponding word line cutting region WDCT. Therefore, each memory cell array region Rm may include an inner region Ri surrounded by relative outer regions Ro1 and Ro2. Here, each outer region Ro1 and Ro2 can be defined as a region extending from the corresponding ends E1, E2 of the memory cell array region Rm toward the inner region Ri by a spacing distance "d1". Therefore, the inner region Ri can be understood as a region of the memory cell array region Rm arranged between the relative outer regions Ro1 and Ro2, and in certain embodiments of the present invention, the inner region Ri can be further understood as a region spaced at least a first distance d1 from either end of the first end E1 and the second end E2.

[0056] exist Figure 5 In the example shown, the memory cell array region Rm has a first end E1 and an opposite second end E2, wherein the first end E1 is adjacent to the first word line cutting region WDCT1 and the opposite second end E2 is adjacent to the second word line cutting region WDCT2. Each word line cutting region WDCT extends in a first horizontal direction D2, and each arrangement of the first outer region / inner region / second outer region extends in the first horizontal direction D2.

[0057] The pillars P extending vertically downward (in the vertical direction D1) through the inner region Ri and the outer regions Ro1 and Ro2 can be formed in various patterns or geometries consistent with the performance expectations of the memory device. Figure 5 As shown, the pillars P can be formed in a row-by-row zigzag pattern, wherein alternate rows in the second horizontal direction D3 are offset in the first horizontal direction D2. This zigzag pattern allows the overall size of the memory cell array region Rm to be reduced in at least one of the first horizontal direction D2 and the second horizontal direction D3, and is hereinafter referred to as a "staggered row arrangement."

[0058] In the context of the respective arrangements of these columns P relative to the inner region Ri and the outer regions Ro1 and Ro2, each column P can be identified as an outer column P1 (or first column P1) or an inner column P2 (or second column P2). That is, the outer column P1 is arranged in the outer region Ro, and the inner column P2 is arranged in the inner region Ri. Here, the expression "arranged in (or alternately formed in)" refers to the position of the center of the column P. Therefore, the column whose center is arranged in the inner region Ri will be the inner column P2, and the column whose center is arranged in the outer region will be the outer column P1. However, in addition to their respective centers, parts of some columns may be arranged in both the outer region Ro and the inner region Ri.

[0059] Each row of columns in the above description extends in the first horizontal direction D2. Figure 5In the illustrated example, two rows of inner pillars P2 are arranged in the inner region Ri, one row of outer pillars P1 is arranged in the first outer region Ro1, and another row of outer pillars P1 is arranged in the second outer region Ro2, for a total of four rows of pillars P arranged in the first horizontal direction D2. In some embodiments of the present inventive concept, each pillar P in the memory device 500 may be formed identically regardless of being arranged in the inner or outer regions.

[0060] Reference again Figure 5 Each outer pillar P1 in the first outer region Ro1 may be separated from the first end E1 by a first distance Do, and each outer pillar P1 in the second outer region Ro2 may be separated from the second end E2 by the first distance Do. Conversely, each inner pillar P2 may be separated from both the first outer region Ro1 and the second outer region Ro2 by at least a second distance Di that is greater than the first distance Do.

[0061] It should be noted here that Figure 5 The number of pillars P, the number of inner and outer pillar rows, and the arrangement of the pillar rows shown in FIG are merely exemplary. In other embodiments of the present inventive concept, other pillar configurations are possible. For example, each outer region Ro may be arranged with two rows of outer pillars P1, an inner region Ri may be provided with only one outer region Ro, four rows of inner pillars P2 may be arranged in an inner region Ri, a symmetrical arrangement of the pillar rows may be provided, and so on.

[0062] Reference again Figure 5 , the bit lines BL of the memory device 500 may include a first bit line BLo and a second bit line BLi. The first bit line BLo and the second bit line BLi may be adjacently disposed to form a pair of bit lines extending in the second horizontal direction D3. The first bit line BLo and the second bit line BLi are spaced apart in the first horizontal direction D2. For clarity, Figure 5 Only one pair of bit lines (ie, a first bit line BLo and a second bit line BLi) is shown in FIG.

[0063] With this configuration, each outer (or first) pillar P1 can be electrically connected to a corresponding first bit line BLo, and each inner (or second) pillar P2 can be electrically connected to a corresponding second bit line BLi. However, these bit line-to-pillar connections can be reversed if appropriate.

[0064] Embodiments of the present inventive concept similar to the memory devices described with respect to the aforementioned figures provide significant performance advantages over conventional memory devices. For example, a conventional nonvolatile memory device including a vertical memory cell array processes data reads from a memory cell string having internal pillars in the same manner as data reads from a memory cell string having external pillars, despite the fact that internal pillar-memory cell strings and external pillar-memory cell strings in the same memory cell array may exhibit different performance characteristics. Therefore, embodiments of the present inventive concept are better able to compensate for process variations that may occur associated with internal pillar memory cell strings and external pillar memory cell strings.

[0065] In this regard, embodiments of the inventive concept may further improve the performance of read operations by determining more appropriate (and thus potentially different) read voltages that may be applied to outer and inner pillar memory cell strings, respectively.

[0066] For example, in early NAND flash memory devices, the read reference voltage value (hereinafter referred to as the read voltage) was fixed during design. However, several types of read data errors are caused by shifts in one or more memory cell threshold voltage distributions. To compensate for shifts in memory cell voltage distributions, a class of mechanisms, often referred to as read retry, has been implemented in more modern flash memory devices. Read retry methods allow the read voltage to be dynamically adjusted in response to shifts in one or more memory cell voltage distributions. During a read retry, a memory controller may initially read data from a target memory cell in a memory cell array using a default read voltage. If the resulting read data is acceptable (e.g., if the resulting read data can be successfully corrected by a component error detection and correction mechanism), the default read voltage is deemed appropriate. However, if the resulting read data is unacceptable, the memory controller may reread the target memory cell using a read voltage different from the default read voltage. The memory controller may repeat these steps until it successfully reads data using one or more read voltages. The possible read voltages that may be selected and used by the memory controller during a read retry are referred to as candidate read voltages.

[0067] However, it should be noted that repeated read retry attempts may significantly increase the overall read operation latency. Therefore, a mechanism to reduce the number of read retries while utilizing the effective capabilities of read retries is highly desirable.

[0068] Figure 6 It further shows Figure 4 and Figure 5 A conceptual circuit diagram of multiple NAND memory cell strings in a memory cell array 510 is shown.

[0069] refer to Figure 4 、 Figure 5 and Figure 6 , the plurality of NAND memory cell strings include both internal NAND strings NSi and external NAND strings NSo, wherein each internal NAND string NSi includes an internal (or second) second pillar P2 and each external NAND string NSo includes an external (or first) pillar P1.

[0070] Each internal NAND string NSi can be conceptually understood as having one end connected to the internal (or second) bit line BLi and the other end connected to the common source line CSL through an internal resistor R1 having a first resistance value. Each external NAND string NSo can be conceptually understood as having one end connected to the external (or first) bit line BLo and the other end connected to the common source line CSL through an external resistor R2 having a second resistance value.

[0071] As above reference Figure 5 As described above, since the second distance Di between each inner NAND string NSi (including the inner pillar or second pillar P2) and the common source line CSL (i.e., the word line cutting region WDCT) is greater than the first distance Do between each outer NAND string NSo (including the outer pillar or first pillar P1) and the common source line CSL, the first resistance value of the inner resistor R1 can be greater than the second resistance value of the outer resistor R2. That is, the overall performance characteristics of each inner NAND string NSi can be different from the overall performance characteristics of each outer NAND string NSo, and therefore, the resulting asymmetric connection structure (such as between the inner NAND string NSi and the outer NAND string NSo) can produce different data results in response to using a single read voltage during a read operation.

[0072] Figure 7 This is further illustrated in an example Figure 2 1. A block diagram of the data I / O circuit 530 is shown.

[0073] refer to Figure 4 、 Figure 5 、 Figure 6 and Figure 7, and as will be described below in some additional detail, the data I / O circuit 530 may include a page buffer circuit 531, which may be used to selectively connect a first bit line BLo during a first read operation for memory cells of an external memory cell string, and selectively connect a second bit line BLi during a second read operation for memory cells of an internal memory cell string. In this context, an "external memory cell string" is a memory cell string including memory cells connected to an external pillar P1, and an "internal memory cell string" is a memory cell string including memory cells connected to an internal pillar P2. The data I / O circuit 530 may also include a read voltage determination unit 532, which may be used to identify (or "select") a first optimal read voltage to be used during the first read operation, and to select a second optimal read voltage to be used during the second read operation. Here, the first read operation and the second read operation may be understood as being independently controlled by dynamically selecting a relatively optimal read voltage as a reference read voltage, at least during the respective read operations. Nevertheless, the first read operation and the second read operation in this regard may be performed together (or simultaneously), sequentially, or at different times.

[0074] Therefore, the data I / O circuit 530 may generally include a page buffer circuit 531 and a read voltage determination unit 532 .

[0075] The page buffer circuit 531 may include a plurality of page buffers, such as Figure 8 As further illustrated in one example in . For clarity, an example is given herein where each page buffer is connected to a single bit line BL, but this is not always the case. The page buffer circuit 531 can receive data from the first bit line BLo and / or the second bit line BLi and can output data DATA, where the data DATA can include first data DATA1 and / or second data DATA2.

[0076] The first data DATA1 may be data read from an external NAND string NSo including memory cells connected to an external (or first) pillar P1 (e.g., during a first read operation), and the second data DATA2 may be data read from an internal NAND string NSi including memory cells connected to an internal (or second) pillar P2 (e.g., during a second read operation). That is, the first data DATA1 and the second data DATA2 may be data associated with data accessed via the first bit line BLo and the second bit line BLi, respectively.

[0077] The read voltage determination unit 532 may be used to determine an optimal read voltage (Vread) in order to most accurately obtain the first data DATA1 and / or the second data DATA2 .

[0078] Figure 8 This is to further illustrate an embodiment of Figure 7 1 is a block diagram of a page buffer circuit 531.

[0079] refer to Figure 8 , the page buffer circuit 531 may include a first page buffer 531a and a second page buffer 531b, wherein the first page buffer 531a may be a combination of one or more page buffers, each of which is respectively connected to the first bit line BLo. Therefore, in some embodiments of the present inventive concept, the first page buffer 531a may include a first group of page buffers, each of which is respectively connected to receive the first data DATA1 from the external NAND string NSo including the memory cells connected to the external (or first) pillar P1. Similarly, in some embodiments of the present inventive concept, the second page buffer 531b may include a second group of page buffers, each of which is respectively connected to receive the second data DATA2 from the internal NAND string NSi including the memory cells connected to the internal (or second) pillar P2.

[0080] The first page buffer 531 a may thus be used to output first data DATA1 through one or more first bit lines BLo, and the second page buffer 531 b may be used to output second data DATA2 through one or more second bit lines BLi.

[0081] Figure 9 This is to further illustrate an embodiment of Figure 8 Conceptual circuit diagram of the first page buffer. Figure 9 , for clarity, the first bit line BLo is represented by an equivalent resistor BLo.

[0082] refer to Figure 9Each of the one or more page buffers included in the first page buffer 531a can be connected to the first bit line BLo and can include a bit line turn-off transistor BLSHFT, a sense node SO, a first register Rg1 (S), a second register Rg2 (L), a third register Rg3 (M), a fourth register Rg4 (F), and a fifth register Rg5 (C). Here, the first register Rg1 (S) can be used as a sense register; the second register Rg2 (L) can be used as, for example, a first storage register associated with the least significant data bit; the third register Rg3 (M) can be used as, for example, a second storage register associated with the most significant data bit; the fourth register Rg4 (F) can be used as, for example, a third storage register associated with a force bit; and the fifth register Rg5 (C) can be used as a data latch (or cache) register. Therefore, with this configuration, the fifth register Rg5 can be used to store data to be output, which is provided as the first data DATA1. Here, each storage register Rg2, Rg3, and Rg4 can be used to store a specific candidate read voltage. In this context, those skilled in the art will appreciate that each of the storage registers can be used to store a data value indicating a corresponding read voltage (hereinafter referred to as a "stored candidate read voltage"). During a read operation, the read voltage determination unit 532 and / or the control logic 560 can be used to select one of the stored candidate read voltages as the optimal read voltage for reading a particular data set.

[0083] The first bit line BLo may be connected to the sensing node SO through a bit line turn-off transistor BLSHFT, the operation of which is controlled by applying, for example, a bit line turn-off signal BLSHF as a gate signal.

[0084] Generally speaking, reading a target memory cell (e.g., a memory cell identified by an externally provided address) can be referred to as sensing the memory cell. Again assuming the operating context of a NAND flash memory device, sensing the memory cell involves an initialization step (Initialize), a precharge step (Precharge), a bit line deployment step (BL Deploy), an offset deployment step (SO Deploy), and a sensing step (Sensing). In some embodiments of the present inventive concept, the bit line deployment step and the offset deployment step can be performed simultaneously.

[0085] During an initialization step (Initialization), the first register Rg1 (ie, the sense latch) may be initialized.

[0086] During the precharge step (precharge), the sensing node SO may be charged to a predetermined voltage level. Here, the voltage level of the bit line shutoff signal BLSHF may be converted to a precharge voltage, and the first bit line BLo connected to the sensing node SO may be charged to a predetermined voltage level.

[0087] During the deployment steps (BL deployment and SO deployment), the precharge of the first bit line BLo is completed. Here, the bit line shutdown signal BLSHF can be transitioned to a deployment voltage that is lower than the precharge voltage but still higher than the ground voltage. Depending on the on / off state of the target memory cell, the charge from the first bit line BLo can be retained or released to the common source line CSL. Therefore, when the memory cell MC is turned on, the voltage of the first bit line BLo can be further reduced relative to the voltage maintained by the first bit line BL0 when the memory cell MC is turned off.

[0088] In the case where a single transistor is used to implement the bit line turn-off transistor BLSHFT, the precharge step and the deployment step are controlled by the single transistor. Therefore, the mismatch between the transistors can be minimized compared to the case where multiple transistors are used to control the precharge step and the deployment step respectively. However, it will be understood by those skilled in the art that the NAND flash memory device assumed in this example invention may include multiple transistors to implement the bit line turn-off transistor for precise control.

[0089] During the sensing step (sensing), the ON / OFF state of the target memory cell MC can be determined based on whether the first register Rg1 is flipped. In this case, when the precharge step has switched to the deployment step, the bit line shutoff signal BLSHF can be reduced from the precharge voltage to the deployment voltage for a specific time period. In this case, when the specific time period is defined as the deployment time, the result of determining the state of the memory cell MC can change according to the deployment time. The change in deployment time can be regarded as a change in the effective read level, just as the read level changes. That is, the effective read level can increase when the deployment time is shortened, and the effective read level can decrease when the deployment time is extended.

[0090] Therefore, some memory devices according to embodiments of the present inventive concept can define multiple valid read levels as multiple candidate read voltages according to corresponding deployment times.Memory cell sensing can then be performed multiple times during a single extended deployment time.

[0091] therefore, Figure 7The read voltage determination unit 532 can be used to determine multiple candidate read voltages and further to determine an optimal read voltage from the multiple candidate read voltages. Therefore, data associated with the multiple candidate read voltages can be stored in respective registers of the first page buffer 531a. The read voltage determination unit 532 can receive the data and find the optimal read voltage from the multiple candidate read voltages.

[0092] For example, each of the second register Rg2, the third register Rg3, and the fourth register Rg4 may be a register for storing data according to a corresponding candidate read voltage. Figure 9 In the context of the example shown, three data values ​​may be obtained from three sensing operations performed at different points during deployment time. These three data values ​​may be stored in a second register Rg2, a third register Rg3, and a fourth register Rg4, respectively.

[0093] The read voltage determination unit 532 can be implemented differently and can include, for example, a large number of bit counter circuits or current comparators. In this regard, the subject matter of U.S. Patents 8,773,908 and 9,007,839 is incorporated herein by reference. However, in a specific configuration, the read voltage determination unit 532 can be used to determine (or calculate) data stored in the second register Rg2, the third register Rg3, and the fourth register Rg4 included in the plurality of first page buffers 531a to select the optimal read voltage from the candidate read voltages.

[0094] Figure 10 This is to further illustrate an embodiment of Figure 8 Another conceptual circuit diagram of the second page buffer. Figure 10 , for clarity, the second bit line BLi is represented by an equivalent resistor BLi.

[0095] refer to Figure 10 Any one of the second page buffers 531b may have a structure similar to that of the first page buffer 531a. That is, the second page buffer 531b may be connected to the second bit line BLi and may include a bit line turn-off transistor BLSHFT, a sensing node SO, a first register Rg1, a second register Rg2, a third register Rg3, a fourth register Rg4, and a fifth register Rg5.

[0096] Here, the second bit line BLi can correspond to the first bit line BLo, and the remaining components can perform the same functions as the first page buffer 531a. That is, the second page buffer 531b can store data corresponding to multiple candidate read voltages stored when the deployment time is changed, and can even store data relative to the second bit line BLi. The read voltage determination unit 532 can be used to determine data corresponding to multiple candidate read voltages in the multiple second page buffers 531b, and can also be used to find the optimal read voltage from the multiple candidate read voltages. The data corresponding to the identified optimal read voltage can then be stored in the fifth register Rg5 and output as the second data DATA2.

[0097] In some embodiments of the present inventive concept, the plurality of candidate read voltages stored in the second page buffer 531b (i.e., the second plurality of candidate read voltages) may be the same as the plurality of candidate read voltages stored in the first page buffer 531a (i.e., the first plurality of candidate read voltages). However, in other embodiments of the present inventive concept, the first plurality of candidate read voltages may be different from the second plurality of candidate read voltages. In this manner, the first data DATA1 provided by the first page buffer 531a may be independently determined relative to the second data DATA2 provided by the second page buffer 531b.

[0098] Figure 11 It shows Figure 7 A conceptual diagram of one possible physical configuration of the page buffer circuit 531 is shown.

[0099] refer to Figure 11 , it is assumed that the page buffer circuit 531 includes a first stage S1 to a sixth stage S6 , wherein the first stage S1 to the sixth stage S6 have the same first size (eg, size 1 ).

[0100] The first size (Size 1) may be a value predetermined according to a number of constraints, such as physical space limitations in which the page buffer circuit 531 may be formed, ease of wiring structure, etc. For example, the first size (Size 1) may be 16 KB or 32 KB, but the present invention is not limited thereto.

[0101] The first to sixth levels S1 to S6 can be independently sensed in the sensing step. In other words, for example, when the first level S1 is sensed, the second level S2 does not necessarily have to be sensed.

[0102] exist Figure 11 , the first to sixth stages S1 to S6 are shown, but this is only an example and the scope of the inventive concept is not limited thereto. That is, the number of stages may be 12 or 18. The number of stages may be a standard number predetermined according to various constraints such as stage size.

[0103] In one level, a unit having a third size (Size 3) may be the minimum unit for determining the type of a page buffer, the third size (Size 3) being one-quarter the first size (Size 1). Here, the type of the page buffer refers to whether the page buffer is a first page buffer 531a or a second page buffer 531b. That is, the type of the page buffer refers to whether the page buffer processes the first data DATA1 stored in the outer NAND string NSo including the outer (or first) pillar P1, or processes the second data DATA2 stored in the inner NAND string NSi including the inner (or second) pillar P2.

[0104] Here, a unit having the third size (Size 3) may include a plurality of page buffers. For example, when one bit line contains one bit of information and the third size (Size 3) is 4 KB, 32,768 (=4×1024×8) page buffers may be included in the unit having the third size (Size 3). In this regard, the expression "type of page buffer" refers to whether all 32,768 page buffers are first page buffers 531a or second page buffers 531b.

[0105] In one stage, a half column having a second size (Size 2) can be independently sensed, where the second size is half of the first size (Size 1). That is, in the first stage S1, the front portion having the second size (Size 2) and the rear portion having the second size (Size 2) can be independently and in parallel sensed.

[0106] according to Figure 11 In the illustrated embodiment, in the first to sixth stages S1 to S6 , the first page buffer 531 a may be disposed at the front portion having the second size (Size 2 ), and the second page buffer 531 b may be disposed at the rear portion having the second size (Size 2 ).

[0107] All of the first to sixth stages S1 to S6 of the page buffer circuit 531 may not be used for sensing. That is, only some of the first to sixth stages S1 to S6 of the page buffer circuit 531 may be sampled and used for sensing.

[0108] This can improve the speed and efficiency of calculation. That is, when a sufficient amount of data is ensured even through some sampling, relatively accurate data values ​​can be obtained, and thus sampling can be performed at higher speed and efficiency.

[0109] Therefore, as an example, only the first stage S1, the second stage S2, and the fourth stage S4 may be sampled to derive data. In this case, all the front portions of the first stage S1, the second stage S2, and the fourth stage S4 having the second size (Size 2) may be the first page buffer 531a, and the rear portions having the second size (Size 2) may be the second page buffer 531b.

[0110] Therefore, according to this embodiment, data associated with the first page buffer 531 a and data associated with the second page buffer 531 b may be divided into two groups to derive first data DATA1 and second data DATA2 .

[0111] Figure 12 is a memory cell threshold voltage distribution graph (or scatter plot) for certain memory cells, illustrating the characteristic differences between memory cells connected by external pillar P1 and memory cells connected by internal pillar P2, wherein scatter plot Co shows data read from external pillar P1 and scatter plot Ci shows data read from internal pillar P2. The significant difference between the external pillar P1 data and the internal pillar P2 data may be caused by varying process conditions and the different relative connection distances between external pillar P1 and internal pillar P2 and the common source line CSL. The scatter plot illustrates the relationship between a plurality of memory cells (along the vertical axis) and the threshold voltage of a particular memory cell (along the horizontal axis).

[0112] In view of the aforementioned scatter plot shift, which is a function of the specific pillar type (i.e., internal pillars versus external pillars) and the corresponding differences in the connection structure, read operations performed on memory devices according to embodiments of the present invention provide data that is significantly more accurate than read operations performed on conventional memory devices because embodiments of the present invention are able to select and use more optimal read voltages during read operations.

[0113] Figure 13 (include Figure 13 (a) Figure 13 (b) and Figure 13 (c)) shows a scatter plot of two data values ​​read from a memory device according to an embodiment of the inventive concept. Figure 13 (a) shows a scatter plot of all memory cells in the memory cell array; Figure 13 (b) shows a scatter diagram of a memory cell connected to an external pillar P1 via a first bit line BLo; Figure 13 (c) shows a scatter diagram of a memory cell connected to the internal pillar P2 via the second bit line BLi. Figure 13 The corresponding scatter plot is similar to the previous one about Figure 12 Describe the scatter plot.

[0114] refer to Figure 13 , Figure 13 (a) The "ON" cells on the left indicate multiple memory cells storing data values ​​of "1", Figure 13 (a) The "OFF" cells on the right indicate a plurality of memory cells storing a data value of "0". As discussed above, the ON / OFF determination of individual memory cells can be made with reference to a particular read voltage (Vread). Recognizing the difficulty of dynamically selecting a relatively optimal read voltage, embodiments of the present inventive concept provide a plurality of candidate read voltages from which an optimal read voltage can be selected. Figure 7 、 Figure 8 、 Figure 9 and Figure 10 The described working examples assume three candidate read voltages RL1, RL2, and RL3, although any reasonable number of candidate read voltages may be provided by other embodiments of the present inventive concept. And as previously described, various methods may be used to define the candidate read voltages (e.g., a method using a large number of bit counters (MSBs) circuit, a method using a current comparator, etc.). For example, the three candidate read voltages RL1, RL2, and RL3 assumed in the previous working examples may be three read voltages derived at different times during an extended deployment period, wherein the first candidate read voltage RL1 has the lowest level, the third candidate read voltage RL3 has the highest level, and the second candidate read voltage RL2 has a level intermediate between the lowest and highest levels.

[0115] exist Figure 13 (a) in the scatter plot (which is actually Figure 13 (b) and Figure 13 (c) The second candidate read voltage RL2 can be identified as the optimal read voltage. Figure 13 In the scatter plot of (b), the second candidate read voltage RL2 can be identified as the optimal read voltage, and Figure 13 In the distribution diagram of (c), the third candidate read voltage RL3 can be identified as the optimal read voltage.

[0116] Those skilled in the art will appreciate that various computational methods can be used to identify a particular data set (e.g., Figure 13 ) an optimal read voltage for a data set (those data sets conceptually illustrated in the scatter plot of FIG). For example, by adaptively "learning" through data sampling, an optimal read voltage can be identified from multiple candidate read voltages. Here, difference information (e.g., the ratio of ones and zeros in the data set) can be used to identify the candidate read voltage that produces the lowest bit error rate, as indicated by the error detection and correction (ECC) capability associated with the memory device storing the data set. Alternatively or additionally, data sampling can be used to identify the candidate read voltage that produces the shortest read operation latency.

[0117] Regardless of the method used to identify the optimal read voltage from a plurality of candidate read voltages, the present inventive concept recognizes that the performance characteristics of the memory cells connected to the outer pillar P1 and the performance characteristics of the memory cells connected to the inner pillar P2 may produce the following results: Figure 13 Thus, embodiments of the inventive concept can dynamically select different optimal read voltages for reading (1) memory cells connected to the outer pillar P1 and (2) memory cells connected to the inner pillar P2 as needed.

[0118] The following will refer to Figure 14 Another memory device according to some embodiments of the present invention is described. The contents described in the above embodiments will be omitted or simplified.

[0119] Figure 14 and Figure 15 It shows Figure 7 The corresponding conceptual diagram of the possible physical configuration of the page buffer circuit and can be compared with Figure 11 ’s concept map for comparison.

[0120] refer to Figure 14 The page buffer circuit 531 may have the same type of page buffer for each half column in the first to sixth stages S1 to S6. For example, for the first, third, fourth, and sixth stages S1, S3, S4, and S6, the front half columns of the second size (size 2) may be configured as the first page buffer 531a, and the rear half columns may be configured as the second page buffer 531b.

[0121] On the other hand, for the second stage S2 and the fifth stage S5 , the front half columns having the second size (Size 2 ) may be configured as the second page buffer 531 b , and the rear half columns may be configured as the first page buffer 531 a .

[0122] In this case, the front half columns of the first, third, fourth, and sixth stages S1, S3, S4, and S6 may be connected to the rear half columns of the second and fifth stages S2 and S5 to derive the first data DATA1 of the first page buffer 531a.

[0123] Additionally, on the other hand, the front half columns of the second and fifth stages S2 and S5 may be connected to the rear half columns of the first, third, fourth, and sixth stages S1, S3, S4, and S6 to derive the second data DATA2 of the second page buffer 531b.

[0124] Alternatively, the first page buffer 531 a and the second page buffer 531 b may be processed independently and in parallel only at the sampling stage in the first to sixth stages S1 to S6 .

[0125] That is, although not arranged inside the page buffer circuit 531, the page buffer type can be determined in units of the second size (size 2), and a connection relationship can be formed so that page buffers of the same type are counted together. In this case, accurate data can be read from the memory cell connected to the outer pillar P1 and from the memory cell connected to the inner pillar P2.

[0126] Therefore, using the memory device according to the embodiment of the inventive concept, the reliability of the data read operation can be further improved.

[0127] refer to Figure 15 , in the page buffer circuit 531, sensing can be independently performed on each cell having the third size (Size 3) in the first to sixth stages S1 to S6. That is, the half column having the front portion of the second size (Size 2) and the half column having the rear portion of the second size (Size 2) do not need to be of the same type.

[0128] Each stage may include four cells having a third size (Size 3). For example, for the sixth stage S6, the first and fourth cells having the third size (Size 3) may be configured as a first page buffer 531a, and the second and third cells may be configured as a second page buffer 531b.

[0129] Each of the other stages may include a unit consisting of two first page buffers 531 a and a unit consisting of two second page buffers 531 b .

[0130] In this case, cells constituting the first page buffer 531 a in each stage may be connected to each other to derive the first data DATA1 of the first page buffer 531 a .

[0131] Additionally, on the other hand, cells constituting the second page buffer 531 b in each stage may be connected to each other to derive the second data DATA2 of the second page buffer 531 b.

[0132] Alternatively, the first page buffer 531 a and the second page buffer 531 b may be processed independently and in parallel only at the sampling stage in the first to sixth stages S1 to S6 .

[0133] That is, although not arranged inside the page buffer circuit 531, the page buffer type can be determined in units of the third size (size 3), and a connection relationship can be formed so that page buffers of the same type are counted together. In this case, accurate data can be read from the memory cells connected to the external pillar P1 and from the memory cells connected to the internal pillar P2.

[0134] According to this embodiment, calculations irrelevant to the arrangement of the page buffer circuit 531 can be performed while the first and second page buffers 531a and 531b are separated from each other. Therefore, in certain embodiments of the present inventive concept, it can be helpful to improve the connection design between bit lines and page buffers.

[0135] In addition, accurate data of the first pillar P1 and the second pillar P2 can be derived. Therefore, with the memory device according to some embodiments of the inventive concept, the reliability of the data read operation can be further improved.

[0136] Will refer to Figure 1 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 and Figure 16 A method of reading data from a memory device according to an embodiment of the inventive concept is described, wherein: Figure 16 is a flowchart illustrating a read operation.

[0137] refer to Figure 16 , the exemplary read method starts in response to receiving a read request (S100). That is, referring to Figure 1 , the memory controller 300 may request a read operation by transmitting at least one of a control signal CTRL, a command CMD, and an address ADDR to the memory device 500 .

[0138] Next, a data sensing step is performed. For example, the selected data page may be sensed in response to a read request (S200). That is, referring to Figure 9 and Figure 10 , the page sensing step may include initialization, precharging, bit line deployment, offset deployment and sensing.

[0139] Here, consistent with the previous description and Figure 16During the page sensing step (S200) of the method shown, the sense latch Rg1 can be initialized; the sense node SO can be precharged to a predetermined voltage level, and the bit line shutdown signal BLSHF can be transitioned to a precharge voltage, so that the first bit line BLo and the second bit line BLi connected to the sense node SO are charged to the predetermined voltage level. Then, the precharging of the first bit line BLo ends, and the bit line shutdown signal BLSHF transitions to a deployment voltage that is lower than the precharge voltage but higher than the ground voltage. Under these conditions, depending on the ON / OFF state of the target memory cell, the charge in the first bit line BLo will be retained or released to the common source line CSL. Then, when the memory cell MC is turned on, the voltage level of the first bit line BLo and the second bit line BLi can be further reduced compared to when the memory cell MC is turned off. Then, whether the memory cell MC is turned on or off can be determined based on whether the first register Rg1 (e.g., the sense latch) is flipped.

[0140] Once you're done Figure 16 The page sensing step (S200) of the reading method shown in FIG. 1 can sample the read page data (eg, the read data temporarily stored in the read buffer) (S300). Figure 11 , not all page buffers constituting the page buffer circuit 531 need to be used to sample the page data. Rather, only some of the page buffers in the page buffer circuit 531 may be used to sample the sensed read data. It should be noted here that the sensing step and the sampling step may be performed simultaneously in certain embodiments of the present inventive concept. Thus, as an example, only the first stage S1, the second stage S2, and the fourth stage S4 of the first to sixth stages S1 to S6 may be used to sample the page data.

[0141] Once the page data has been sampled ( S300 ), a first optimal read voltage may be selected ( S410 ) and / or a second optimal read voltage may be selected ( S420 ).

[0142] That is, reference Figure 7 、 Figure 8 、 Figure 9 and Figure 10 , the read voltage determination unit 532 may be configured to determine (or select) an optimal read voltage from a plurality of stored candidate read voltages according to the sample data set. Figure 13 (b), wherein a data set is sampled from a memory cell connected to the external pillar P1, a first read voltage RL1 may be selected, or a reference voltage RL2 may be selected. Figure 13 (c), where another data set obtained from memory cells connected to the internal pillar P2 is sampled, a third read voltage RL3 may be selected.

[0143] Therefore, in some embodiments of the present invention, the data values ​​corresponding to the respective candidate read voltages may be stored in the first page buffer 531a. The read voltage determination unit 532 may then receive the sampled data results and identify the best read voltage from the plurality of candidate read voltages. As previously described, for example, Figure 9 and Figure 10 As shown in FIG, each of the second register Rg2, the third register Rg3, and the fourth register Rg4 can be used as a register to store a data value corresponding to the candidate read voltage in the illustrated embodiment.

[0144] After one or both of the first optimal read voltage (S410) and the second optimal read voltage (S420) have been selected, the first data DATA1 and the second data DATA2 may be output (S500). That is, referring to Figure 8 , the first data DATA1 may be output by the first page buffer 531 a , and the second data DATA2 may be output by the second page buffer 531 b .

[0145] While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the inventive concept as set forth in the appended claims. It is therefore intended that the present embodiments be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than the foregoing description as indicating the scope of the inventive concept.

Claims

1. A nonvolatile memory comprising: a memory cell region comprising an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region; a first bit line and a second bit line; an outer memory cell string comprising memory cells connected to outer pillars extending vertically upward through the outer region; an interior memory cell string comprising memory cells connected to interior pillars extending vertically upward through the interior region; as well as A data input / output circuit comprising: a page buffer circuit that connects the first bit line during a first read operation for memory cells of the outer memory cell string and connects the second bit line during a second read operation for memory cells of the inner memory cell string; as well as a read voltage determination unit that selects a first optimal read voltage for use during the first read operation from a first plurality of candidate read voltages stored in the page buffer circuit and selects a second optimal read voltage for use during the second read operation from a second plurality of candidate read voltages stored in the page buffer circuit.

2. The nonvolatile memory according to claim 1, wherein: The first bit line and the second bit line are paired bit lines extending above an upper surface of the memory cell region.

3. The nonvolatile memory according to claim 2, wherein: The page buffer circuit includes: a first page buffer connected to the first bit line during the first read operation; and A second page buffer is connected to the second bit line during the second read operation.

4. The nonvolatile memory according to claim 1, wherein: The memory cell region further includes a plurality of vertically stacked word lines extending in a first horizontal direction, and The first bit line and the second bit line extend in a second horizontal direction.

5. The nonvolatile memory according to claim 1 , further comprising: Control logic that controls the data input / output circuit to perform the first read operation independently of the second read operation. The nonvolatile memory according to claim 5 , wherein: The control logic controls the data input / output circuit to simultaneously perform the first read operation and the second read operation.

7. The nonvolatile memory according to claim 1, wherein: The outer memory cell string is one of a plurality of outer memory cell strings, each outer memory cell string including memory cells connected to corresponding outer pillars extending upward through the outer region, and the inner memory cell string is one of a plurality of inner memory cell strings, each inner memory cell string including memory cells connected to corresponding inner pillars extending upward through the inner region, The center of each outer post is disposed at least a first distance from the first end, and the center of each inner post is disposed at least a second distance from the first end, and The second distance is greater than the first distance.

8. The nonvolatile memory according to claim 7, wherein: The respective outer columns are arranged together in a first column row extending in a first horizontal direction, said respective inner columns being arranged together in a second column row extending in said first horizontal direction, The first column row and the second column row are arranged in a staggered row arrangement, and The first bit line and the second bit line extend in a second horizontal direction.

9. The nonvolatile memory according to claim 1, wherein: The nonvolatile memory is a vertical NAND flash memory, the outer memory cell string is a first NAND string connected between the first bit line and a common source line, and the inner memory cell string is a second NAND string connected between the second bit line and the common source line.

10. The nonvolatile memory according to claim 9, wherein: The first NAND string has a first connection resistance between the first bit line and the common source line, and the second NAND string has a second connection resistance between the second bit line and the common source line that is different from the first connection resistance.

11. A non-volatile memory comprising: a memory cell region comprising a first end, an outer region proximate the first end, and an inner region separated from the first end by the outer region; a first bit line and a second bit line; an outer memory cell string comprising memory cells connected to outer pillars extending vertically upward through the outer region; an interior memory cell string comprising memory cells connected to interior pillars extending vertically upward through the interior region; as well as Data input / output circuit, including: a page buffer circuit comprising a first page buffer connected to the first bit line during a first read operation for memory cells of the external memory cell string and a second page buffer connected to the second bit line during a second read operation for memory cells of the internal memory cell string; a read voltage determination unit that selects a first optimal read voltage used during the first read operation and a second optimal read voltage different from the first optimal read voltage used during the second read operation, The first page buffer includes a first storage register storing a first candidate read voltage and a second storage register storing a second candidate read voltage, and The read voltage determination unit selects one of the first candidate read voltage and the second candidate read voltage as the first optimal read voltage.

12. The nonvolatile memory according to claim 11, wherein: The first page buffer further includes: a bit line turn-off transistor connecting the first bit line and a sensing node; a sense register that senses a voltage on the first bit line during the first read operation; an output register storing first output data generated by the first read operation, The sensing register, the first storage register, the second storage register and the output register are respectively connected to the sensing node.

13. The nonvolatile memory according to claim 11, wherein: The second page buffer includes a third storage register storing a third candidate read voltage and a fourth storage register storing a fourth candidate read voltage, and The read voltage determination unit selects one of the third candidate read voltage and the fourth candidate read voltage as the second optimal read voltage.

14. The nonvolatile memory according to claim 13, wherein: The second page buffer further includes: a bit line turn-off transistor connecting the second bit line and a sensing node; a sense register that senses a voltage on the second bit line during the second read operation; an output register storing second output data generated by the second read operation, The sensing register, the third storage register, the fourth storage register and the output register are respectively connected to the sensing node.

15. The nonvolatile memory according to claim 13, wherein: At least one of the first candidate read voltage stored in the first storage register of the first page buffer and the second candidate read voltage stored in the second storage register of the first page buffer is the same as at least one of the third candidate read voltage stored in the third storage register of the second page buffer and the fourth candidate read voltage stored in the fourth storage register of the second page buffer.

16. The nonvolatile memory according to claim 11, wherein: The outer memory cell string is one of a plurality of outer memory cell strings, each outer memory cell string including memory cells connected to corresponding outer pillars extending upward through the outer region, and the inner memory cell string is one of a plurality of inner memory cell strings, each inner memory cell string including memory cells connected to corresponding inner pillars extending upward through the inner region, and The center of each outer post is disposed at least a first distance from the first end, and the center of each inner post is disposed at least a second distance from the first end, the second distance being greater than the first distance.

17. The nonvolatile memory according to claim 16, wherein: The respective outer columns are collectively arranged in a first column row, and the respective inner columns are collectively arranged in a second column row, and The first column row and the second column row are arranged in a staggered row arrangement.

18. The nonvolatile memory according to claim 11, wherein: The nonvolatile memory is a vertical NAND flash memory, the outer memory cell string is a first NAND string connected between the first bit line and a common source line, and the inner memory cell string is a second NAND string connected between the second bit line and the common source line.

19. The nonvolatile memory according to claim 18, wherein: The first NAND string has a first connection resistance between the first bit line and the common source line, and the second NAND string has a second connection resistance between the second bit line and the common source line that is different from the first connection resistance.

20. A vertical NAND flash memory comprising: a NAND memory cell region defined at a first end by a first wordline cut and at a second end opposite the first end by a second wordline cut, wherein the NAND memory cell region includes a first outer region proximate the first end, a second outer region proximate the second end, and an inner region between the first outer region and the second outer region; bit lines extending over the memory cell region and including a first bit line and a second bit line; a first outer NAND string comprising NAND cells connected to a first outer pillar extending vertically upward through the first outer region; a second outer NAND string comprising NAND cells connected to a second outer pillar extending vertically upward through the second outer region; a first interior NAND string comprising a NAND cell connected to a first interior pillar extending vertically upward through the interior region; a second inner NAND string comprising a NAND cell connected to a second inner pillar extending vertically upward through the inner region; and A data input / output circuit comprising: a page buffer circuit comprising a first page buffer connected to the first bit line during a first read operation for memory cells of at least one of the first outer NAND string and the second outer NAND string, and a second page buffer connected to the second bit line during a second read operation for memory cells of at least one of the first inner NAND string and the second inner NAND string, and a read voltage determination unit that selects a first optimal read voltage for use during the first read operation and a second optimal read voltage for use during the second read operation, wherein the read voltage determination unit selects one of a first candidate read voltage and a second candidate read voltage as the first optimal read voltage, the first candidate read voltage and the second candidate read voltage being stored in the first page buffer.

21. The vertical NAND flash memory according to claim 20, wherein: The first bit line and the second bit line are paired bit lines disposed adjacent to each other.

22. The vertical NAND flash memory according to claim 20, wherein: The NAND memory cell region further includes a plurality of vertically stacked word lines extending in a first horizontal direction, and the bit lines extend in a second horizontal direction.

23. The vertical NAND flash memory according to claim 20, further comprising: Control logic that controls the data input / output circuit to perform the first read operation independently of the second read operation.

24. The vertical NAND flash memory according to claim 23, wherein: The control logic controls the data input / output circuit to simultaneously perform the first read operation and the second read operation.

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