Memory device and operating method thereof

Abstract

The invention relates to a memory device and an operating method thereof. According to an embodiment of the present disclosure, an operating method of a memory device including a memory bank including a plurality of edge memory cell arrays and a plurality of internal memory cell arrays arranged between the plurality of edge memory cell arrays may be provided. The operating method may include: receiving a fine-grained refresh command; identifying a refresh target pointer value for a refresh target determination list, the refresh target determination list including a plurality of row addresses of the memory bank; identifying a pointing row address corresponding to a refresh target pointer value among the plurality of row addresses; determining a first memory cell array type corresponding to the pointing row address; and performing a first refresh operation for a refresh target number of fine-grained refresh target row addresses, wherein the refresh target number is determined based on the first memory cell array type.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a semiconductor memory device. More particularly, the disclosure relates to a volatile memory device and an operating method thereof. BACKGROUND

[0002] A volatile memory device, such as a dynamic random access memory (DRAM), can store data in the form of a charge charged in a memory cell. The charge charged in the memory cell of the volatile memory device can leak due to various reasons. Accordingly, the volatile memory device can perform a refresh operation to recharge the charge charged in the memory cell.

[0003] Due to recent trends of the volatile memory device toward higher integration, higher capacity, and higher input / output speed, the ratio of time spent on the refresh operation to the entire operating time of the volatile memory device gradually increases. That is, there occurs a problem in which the input / output performance of the volatile memory device is limited by the refresh operation. SUMMARY

[0004] The disclosure aims to solve the above-described technical problem. More particularly, the disclosure serves to provide a memory device and an operating method thereof, which performs a plurality of fine-grained refresh operations instead of a conventional refresh operation.

[0005] According to an embodiment of the disclosure, an operating method of a memory device including a memory bank including a plurality of edge memory cell arrays and a plurality of internal memory cell arrays arranged between the plurality of edge memory cell arrays can be provided. The operating method can include receiving a fine-grained refresh command, identifying a refresh target pointer value for a refresh target determination list including a plurality of row addresses of the memory bank, identifying a pointing row address corresponding to the refresh target pointer value among the plurality of row addresses, determining a first memory cell array type corresponding to the pointing row address, and performing a first refresh operation for a refresh target number of fine-grained refresh target row addresses, wherein the refresh target number is determined based on the first memory cell array type.

[0006] According to embodiments of the present disclosure, a memory device that communicates with an external device can be provided. The memory device can include a memory bank, a row decoder connected to the memory bank, and a control logic circuit configured to manage a refresh target pointer value and a refresh target determination list including a plurality of row addresses, wherein the control logic circuit is configured to determine a plurality of regular refresh target row addresses corresponding to a regular refresh command provided from the external device based on the refresh target pointer value and the refresh target determination list, and determine one or more fine-grained refresh target row addresses corresponding to a fine-grained refresh command provided from the external device based on the refresh target pointer value and the refresh target determination list, wherein a number of the plurality of regular refresh target row addresses is greater than a number of the one or more fine-grained refresh target row addresses.

[0007] According to embodiments of the present disclosure, a memory device can be provided. The memory device can include a first memory bank, a row decoder connected to the first memory bank, and a control logic circuit configured to perform a regular refresh operation on the first memory bank for a first time period by controlling the row decoder in response to a first regular refresh command for the first memory bank, and perform a fine-grained refresh operation on the first memory bank for a second time period shorter than the first time period by controlling the row decoder in response to a first fine-grained refresh command for the first memory bank.

[0008] According to embodiments of the present disclosure, a memory controller can be provided. The memory controller can include a command issuing circuit, a refresh undercount counter configured to manage a refresh undercount for a first memory bank, and a refresh scheduling circuit configured to determine a command to be issued by the command issuing circuit based on the refresh undercount, wherein the refresh undercount counter is configured to decrease the refresh undercount by a first value each time the command issuing circuit issues a regular refresh command for the first memory bank, and decrease the refresh undercount by a second value smaller than the first value each time the command issuing circuit issues a fine-grained refresh command for the first memory bank.

[0009] According to embodiments, a method of manufacturing a memory device can include providing a memory bank, providing a row decoder connected to the memory bank, and providing a control logic circuit configured to manage a refresh target pointer value and a refresh target determination list including a plurality of row addresses, wherein the control logic circuit is configured to determine a plurality of regular refresh target row addresses corresponding to a regular refresh command provided from an external device based on the refresh target pointer value and the refresh target determination list, and determine one or more fine-grained refresh target row addresses corresponding to a fine-grained refresh command provided from the external device based on the refresh target pointer value and the refresh target determination list, wherein a number of the plurality of regular refresh target row addresses is greater than a number of the one or more fine-grained refresh target row addresses. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram illustrating how a regular refresh operation is performed on one memory bank.

[0012] Figure 3 is a diagram illustrating Figure 1 the operation of the refresh scheduling circuit of

[0013] Figure 4 is a diagram illustrating Figure 1 the operation of the refresh scheduling circuit of

[0014] Figure 5 is a block diagram illustrating a memory device of Figure 1 in more detail.

[0015] Figure 6 is a diagram illustrating some configurations of Figure 5 in more detail.

[0016] Figure 7 is a diagram illustrating how a refresh operation is performed in more detail.

[0017] Figure 8 is a timing diagram illustrating the operation of a memory device according to an embodiment of the present disclosure in response to a regular refresh command.

[0018] Figure 9 is a timing diagram illustrating the operation of a memory device according to an embodiment of the present disclosure in response to a fine-grained refresh command.

[0019] Figure 10 and Figure 11 is a diagram illustrating the operation of a memory system according to an embodiment.

[0020] Figure 12 and Figure 13 is a diagram illustrating an operation of a memory system according to an embodiment.

[0021] Figure 14 is a flowchart illustrating an operation method of a memory device in response to a regular refresh command.

[0022] Figure 15 is a flowchart illustrating an operation method of a memory device in response to a fine-grained refresh command.

[0023] Figure 16 and Figure 17 is a timing diagram illustrating an operation of a memory system according to an embodiment.

[0024] Figure 18 is a timing diagram illustrating an operation of a memory system according to an embodiment.

[0025] Figure 19 is a graph illustrating an effect of fine-grained refresh according to an embodiment of the disclosure.

[0026] Figure 20 is a flowchart illustrating a regular refresh scheduling of a host device according to an embodiment.

[0027] Figure 21 is a diagram illustrating a fine-grained refresh scheduling of a host device according to an embodiment.

[0028] Figure 22 is a diagram illustrating an operation of a memory system according to an embodiment.

[0029] Figure 23 is a timing diagram illustrating how a memory device manages refresh credit count when a refresh target determination list is implemented to refer to Figure 22 described in a manner.

[0030] Figure 24 is a block diagram illustrating a memory system according to an embodiment.

[0031] Figure 25 is a timing diagram illustrating how Figure 24 a memory device manages refresh credit count.

[0032] Figure 26 is a block diagram illustrating a memory system according to an embodiment.

[0033] Figure 27 is a timing diagram illustrating an operation of a memory system according to Figure 26 an embodiment. DETAILED DESCRIPTION

[0034] Hereinafter, the embodiments of the disclosure will be described in detail to the extent that those skilled in the art of the disclosure can readily practice the disclosure.

[0035] The components described below can be implemented as various types of software, such as firmware, applications, or the like, or can be implemented as various types of hardware, such as circuitry, electronic circuitry, processors, or the like. However, the scope of the disclosure is not limited thereto, and the components described below can also be implemented as a combination of software and hardware.

[0036] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the disclosure. Referring to Figure 1 , the memory system MS can include a host device 10 and a memory device 100.

[0037] The host device 10 can control the memory device 100 by issuing various types of commands CMD and addresses ADDR. For example, the host device 10 can issue a read command to read data DATA from the memory device 100, or issue a write command to store data DATA in the memory device 100.

[0038] In an embodiment, the host device 10 can issue various types of commands CMD and addresses ADDR (hereinafter, which can be referred to as "CA") in the form of command / address signals.

[0039] In an embodiment, the host device 10 can be included in one of various types of processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), or the like.

[0040] In an embodiment, the host device 10 can be referred to as a memory controller. However, the scope of the disclosure is not limited to these terms.

[0041] The memory device 100 can include a memory bank 140. The memory bank 140 can store data DATA. For example, the memory bank 140 can include a plurality of memory cell rows MCR. Each of the plurality of memory cell rows MCR can include a plurality of memory cells.

[0042] Each of the plurality of memory cells included in the memory bank 140 can store data in the form of a charge charged to a capacitor. However, the amount of charge charged to each of the plurality of memory cells can change over time, and the data stored in the memory bank 140 can be corrupted. Accordingly, the memory device 100 can perform a refresh operation on the plurality of memory cells in response to the control of the host device 10, so that the amount of charge stored in each of the plurality of memory cells can be maintained. Hereinafter, how the memory device 100 performs a refresh operation in response to the control from the host device 10 will be described.

[0043] The memory device 100 can include a control logic circuit 120. The control logic circuit 120 can control the overall operation of the memory device 100. For example, the control logic circuit 120 can perform a regular refresh operation on the memory bank 140 in response to a regular refresh command REF R provided from the host device 10, or can perform a fine-grained refresh operation on the memory bank 140 in response to a fine-grained refresh command REF F provided from the host device 10.

[0044] The control logic circuit 120 can include a refresh manager 121. The refresh manager 121 can manage the details of how to perform a refresh operation on the memory device 100. For example, the refresh manager 121 can determine a refresh order of a plurality of memory cells included in the memory bank 140.

[0045] In an embodiment, the refresh manager 121 can be referred to as a refresh management circuit. However, the scope of the present disclosure is not limited to these terms.

[0046] In an embodiment, the number of memory cell rows MCR refreshed when the fine-grained refresh operation is performed can be smaller than the number of memory cell rows MCR refreshed when the regular refresh operation is performed.

[0047] In an embodiment, the number of memory cell rows MCR refreshed when the fine-grained refresh operation is performed can be smaller than or equal to the number of word lines (hereinafter, referred to as "WLs") connected to the memory bank 140 that the control logic circuit 120 can activate simultaneously in response to an activation command (hereinafter, referred to as "ACT") provided from the host device 10 (hereinafter, such a number can be referred to as "the maximum number of word lines activated simultaneously for an activation command"). For example, the maximum number of word lines activated simultaneously for an activation command can be 2. In this case, the number of memory cell rows MCR refreshed when the fine-grained refresh operation is performed can be 1 or 2. However, the scope of the present disclosure is not limited thereto. For example, the control logic circuit 120 can be implemented to refresh the number of memory cell rows MCR equal to the maximum number of word lines activated simultaneously for an activation command every time the fine-grained refresh command REF F is received. Below, the embodiment in which the control logic circuit 120 is implemented to refresh the number of memory cell rows MCR equal to the maximum number of word lines activated simultaneously for an activation command every time the fine-grained refresh command REF F is received is described in more detail. Figure 22 and Figure 23 In an embodiment, the number of memory cell rows MCR refreshed when the fine-grained refresh operation is performed can be smaller than or equal to the number of word lines (hereinafter, referred to as "WLs") connected to the memory bank 140 that the control logic circuit 120 can activate simultaneously in response to an activation command (hereinafter, referred to as "ACT") provided from the host device 10 (hereinafter, such a number can be referred to as "the maximum number of word lines activated simultaneously for an activation command"). For example, the maximum number of word lines activated simultaneously for an activation command can be 2. In this case, the number of memory cell rows MCR refreshed when the fine-grained refresh operation is performed can be 1 or 2. However, the scope of the present disclosure is not limited thereto. For example, the control logic circuit 120 can be implemented to refresh the number of memory cell rows MCR equal to the maximum number of word lines activated simultaneously for an activation command every time the fine-grained refresh command REF F is received. Below, the embodiment in which the control logic circuit 120 is implemented to refresh the number of memory cell rows MCR equal to the maximum number of word lines activated simultaneously for an activation command every time the fine-grained refresh command REF F is received is described in more detail.

[0048] In an embodiment, the number of memory cell rows MCR being refreshed when a regular refresh operation is performed can be eight or more. However, the scope of the present disclosure is not limited to the particular number of memory cell rows MCR being refreshed when a regular refresh operation is performed. For example, the number of memory cell rows being refreshed when a regular refresh operation is performed can be 4 or more, or 16 or more.

[0049] The host device 10 can include a command issuing circuit 11, a refresh deficit counter 12, a timer circuit 13, and a refresh scheduling circuit 14.

[0050] The command issuing circuit 11 can issue various types of commands CMD for controlling the memory device 100. For example, the command issuing circuit 11 can issue various types of commands CMD to the memory device 100, such as an activate command ACT, a precharge command (hereinafter referred to as "PREC"), a read command, a write command, a regular refresh command REF R, a fine-grained refresh command REF F, and the like.

[0051] The command issuing circuit 11 can issue the regular refresh command REF R in each regular refresh period. The memory device 100 can refresh some memory cell rows MCR included in the memory bank 140 in response to the regular refresh command REF R. In this way, the host device 10 can maintain the integrity of data stored in the memory device 100 by repeatedly issuing the regular refresh command REF R.

[0052] However, the command issuing circuit 11 can not issue the regular refresh command REF R in a particular regular refresh period under the control of the refresh scheduling circuit 14. That is, in the particular regular refresh period, the command issuing circuit 11 can skip issuing the regular refresh command REF R in response to the control of the refresh scheduling circuit 14. In this case, the host device 10 can issue another command instead of issuing the regular refresh command REF R, which can improve the operational efficiency of the memory system MS. For example, if the memory device 100 does not perform a regular refresh operation, the host device 10 can be able to perform an input / output operation on the memory device 100.

[0053] The manner in which the command issuing circuit 11 skips issuing the regular refresh command REF R in response to the control of the refresh scheduling circuit 14 will be described in detail below.

[0054] The refresh deficit counter 12 can manage a refresh deficit count DCNT. The refresh deficit count DCNT can indicate the degree to which a refresh operation is needed for the memory bank 140.

[0055] The refresh deficit counter 12 can decrease the refresh deficit count DCNT each time the command issue circuit 11 issues a command instructing a refresh operation on the memory bank 140. For example, the refresh deficit counter 12 can decrease the refresh deficit count DCNT each time the command issue circuit 11 issues a regular refresh command REF R to the memory bank 140 or issues a fine-grained refresh command REF F to the memory bank 140.

[0056] The refresh deficit counter 12 can increase the refresh deficit count DCNT at each regular refresh period.

[0057] The timer circuit 13 can detect a regular refresh period. For example, the timer circuit 13 can generate a "regular refresh period notification" each time a length of time corresponding to a regular refresh period elapses. The timer circuit 13 can provide the "regular refresh period notification" to other components of the host device 10. Thus, each component of the host device 10 can recognize a regular refresh period based on the timer circuit 13.

[0058] The refresh scheduling circuit 14 can control the operation of the command issue circuit 11 based on the refresh deficit count DCNT. For example, the refresh scheduling circuit 14 can determine whether the command issue circuit 11 skips issuing a regular refresh command REF R during each regular refresh period based on the refresh deficit count DCNT. More specifically, the refresh scheduling circuit 14 can determine a degree of need for a refresh operation on the memory bank 140 based on the refresh deficit count DCNT. When the degree of need for a refresh operation on the memory bank 140 is low (e.g., when the refresh deficit count DCNT is a sufficiently low value), the refresh scheduling circuit 14 can control the command issue circuit 11 to skip issuing a regular refresh command REF R.

[0059] That is, according to the example embodiment of the present disclosure, the refresh scheduling circuit 14 can control the command issue circuit 11 to skip issuing a regular refresh command REF R when the command issue circuit 11 has issued a sufficient number of fine-grained refresh commands REF F to the memory bank 140. In this case, the integrity of data stored in the memory device 100 is ensured while the time taken for the memory device 100 to perform a regular refresh operation can be reduced. In this case, the time during which the host device 10 is allowed to access the memory bank 140 can be increased, and thus the operational efficiency of the memory system MS can be improved.

[0060] In an embodiment, the command structure of the regular refresh command REF R and the fine-grained refresh command REF F can be different. For example, the combination of the command / address signals CA representing the regular refresh command REF R can be different from the combination of the command / address signals CA representing the fine-grained refresh command REF F. That is, the host device 10 can flexibly issue the regular refresh command REF R and the fine-grained refresh command REF F without changing the operating mode of the memory device 100. For example, the host device 10 can issue both the regular refresh command REF R and the fine-grained refresh command REF F while the mode register value stored in the mode register array included in the memory device 100 is constantly maintained. However, the scope of the present disclosure is not limited thereto.

[0061] Figure 2 is a diagram illustrating how to perform a regular refresh operation on one memory bank. Hereinafter, for a more concise explanation, reference is made to Figure 1 and Figure 2 a representative description is given of how to perform a regular refresh operation on the memory bank 140. Figure 2 The horizontal axis of can represent time, and the vertical axis can represent the number of memory cell rows MCR refreshed per unit time by the memory device 100.

[0062] The memory device 100 can perform a regular refresh operation during a regular refresh consumption time tRFC R in response to the regular refresh command REF R. For example, the memory device 100 can refresh some of the plurality of memory cells included in the memory bank 140 in response to the regular refresh command REF R. Accordingly, in order to refresh all of the memory cells included in the memory bank 140, the memory device 100 can have to perform the regular refresh operation multiple times.

[0063] In an embodiment, the host device 10 can not be able to access the memory bank 140 during the regular refresh consumption time tRFC R for the memory bank 140. For example, the host device 10 can be prohibited from issuing other commands to the memory bank 140 during the regular refresh consumption time tRFC R for the memory bank 140. In other words, the input / output performance of the memory device 100 can be degraded due to the regular refresh consumption time tRFC R for the memory bank 140, in which the input / output operation of the memory bank 140 is restricted (e.g., constrained).

[0064] The time during which the integrity of the data stored in the memory cell is guaranteed without a refresh operation can be referred to as a retention time tRT. In order to ensure the integrity of the data stored in all of the memory cells of the memory bank 140, each memory cell must be refreshed at least once within the retention time tRT.

[0065] In an embodiment, each time the memory device 100 performs a regular refresh operation within one retention time tRT, it can refresh different combinations of memory cell rows MCR. For example, the command issue circuit 11 can issue a first regular refresh command and a second regular refresh command to the memory bank 140 within one retention time tRT. In this case, the memory device 100 can refresh a first plurality of memory cell rows in response to the first regular refresh command, and can refresh a second plurality of memory cell rows different from the first plurality of memory cell rows in response to the second regular refresh command.

[0066] To ensure the integrity of data stored in all memory cells of the memory bank 140, the command issue circuit 11 should issue a predetermined number of regular refresh commands REF R during the retention time tRT. For example, the command issue circuit 11 should issue the regular refresh command REF R 8192 times during a single retention time tRT. However, the scope of the present disclosure is not limited to the number of regular refresh commands REF R that should be issued by the command issue circuit 11 during a single retention time tRT.

[0067] To issue the predetermined number of regular refresh commands REF R during a single retention time tRT, the command issue circuit 11 can issue a regular refresh command REF R at each regular refresh period. That is, each time a length of time corresponding to the regular refresh interval tREFI elapses, the command issue circuit 11 can issue a regular refresh command REF R.

[0068] Figure 3 is a graph showing the operation of the refresh scheduling circuit of Figure 1 In the following, for a more concise explanation, reference is made to Figures 1 to 3 Embodiments of adjusting the timing at which the refresh scheduling circuit 14 controls the command issue circuit 11 to issue regular refresh commands REF R to the memory bank 140 are typically described. Figure 3 The horizontal axis of the graph of

[0069] With reference to Figures 1 to 3 , a regular refresh period can start at each of a first time point ta, a second time point tb, a third time point tc, a fourth time point td, and a fifth time point te. In this case, as described above with reference to Figure 2 , the command issue circuit 11 can in principle have to issue a regular refresh command REF R at each of the first time point ta, the second time point tb, the third time point tc, the fourth time point td, and the fifth time point te.

[0070] The refresh scheduling circuit 14 can pull (e.g., advance) or delay the issuance of the regular refresh command REF_R of the command issuance circuit 11 by a predetermined number of times. For example, instead of issuing the regular refresh command REF_R at the second time point tb, the command issuance circuit 11 can issue the regular refresh command REF_R at a sixth time point tf between the third time point tc and the fourth time point td. That is, the host device 10 can delay the issuance of the regular refresh command REF_R for the second time point tb to the sixth time point tf. Conversely, instead of issuing the regular refresh command REF_R at the fourth time point td, the host device 10 can issue the regular refresh command REF_R at a seventh time point tg between the third time point tc and the fourth time point td. That is, the host device 10 can advance the issuance of the regular refresh command REF_R for the fourth time point td to the seventh time point tg. In this case, since the timing at which the command issuance circuit 11 issues the regular refresh command REF_R to the memory bank 140 can be flexibly adjusted, the operation efficiency of the memory system MS can be improved.

[0071] In an embodiment, the number of times the command issuance circuit 11 can advance or delay the issuance of the regular refresh command REF_R to the memory bank 140 can be referred to as a “refresh fluctuation threshold”.

[0072] Figure 4 is a graph illustrating the operation of the refresh scheduling circuit of Figure 1 . Hereinafter, for a more concise explanation, the operation of the refresh scheduling circuit 14 when performing the fine-grained refresh operation on the memory bank 140 is representatively described. Figures 1 to 4 The horizontal axis of Figure 4 may represent time, and the vertical axis can represent the number of memory cell rows MCR refreshed per unit time by the memory device 100.

[0073] The command issuance circuit 11 can issue a plurality of fine-grained refresh commands REF_F to the memory bank 140 within one regular refresh interval tREFI. The memory device 100 can perform a fine-grained refresh operation in response to each of the plurality of fine-grained refresh commands REF_F.

[0074] In an embodiment, each time the memory device 100 performs a fine-grained refresh operation within one regular refresh interval tREFI, it can refresh a different combination of memory cell rows MCR. For example, the command issuance circuit 11 can issue a first fine-grained refresh command and a second fine-grained refresh command within one regular refresh interval tREFI. In this case, the memory device 100 can refresh a first set of memory cell rows in response to the first fine-grained refresh command, and can refresh a second set of memory cell rows that does not overlap with the first set in response to the second fine-grained refresh command.

[0075] The number of memory cell rows MCR refreshed when the memory device 100 performs a fine-grained refresh operation can be smaller than the number of memory cell rows refreshed when the memory device 100 performs a regular refresh operation. Accordingly, the memory device 100 can perform a fine-grained refresh operation multiple times to refresh memory cell rows MCR corresponding to one regular refresh operation. In this way, the memory device 100 can replace a regular refresh operation with multiple fine-grained refresh operations. For example, the memory device 100 can perform a fine-grained refresh operation multiple times to pre-refresh memory cell rows that are to be refreshed by a regular refresh operation. However, the scope of the present disclosure is not limited thereto, and the memory device 100 can perform a fine-grained refresh operation multiple times to refresh memory cell rows that should have been refreshed by a regular refresh operation but were not refreshed due to skipping issuance of a regular refresh command REF R. In other words, the refresh scheduling circuit 14 can replace issuance of a regular refresh command REF R with issuance of multiple fine-grained refresh commands REF F.

[0076] That is, according to the embodiment of the present disclosure, a regular refresh operation can be replaced with multiple fine-grained refresh operations performed in shorter time units. In this case, deterioration of input / output performance of the memory device 100 due to a regular refresh consuming time tRFC R can be prevented. Accordingly, according to the embodiment of the present disclosure, operation efficiency and operation performance of the memory system MS can be improved.

[0077] Figure 5 is a block diagram of a memory device illustrating in more detail Figure 1 . Referring to Figures 1 to 5 , the memory device 100 can include a command / address decoder 110, a control logic circuit 120, a row decoder 130, a memory bank 140, a sense amplifier & write driver (S / A & W / D) 150, an input / output (I / O) circuit 160, and a voltage supply circuit VSC.

[0078] The command / address decoder 110 can receive a command / address signal CA provided from the host device 10. The command / address decoder 110 can decode the command / address signal CA into a command CMD and an address ADDR. That is, the command / address decoder 110 can receive the command CMD and the address ADDR from the host device 10 in the form of the command / address signal CA.

[0079] The control logic circuit 120 can receive a command CMD and an address ADDR. The control logic circuit 120 can control overall operations of the memory device 100 based on the command CMD and the address ADDR. For example, the control logic circuit 120 can control operations of the row decoder 130, the sense amplifier & write driver 150, the input / output circuit 160, and the voltage supply circuit VSC based on the command CMD and the address ADDR.

[0080] The row decoder 130 can be connected to the memory bank 140 through a plurality of word lines WL. The row decoder 130 can control the plurality of word lines WL in response to a control of the control logic circuit 120. For example, the row decoder 130 can receive a driving voltage VDRV from the voltage supply circuit VSC in response to a control of the control logic circuit 120, and can activate some of the plurality of word lines WL based on the driving voltage VDRV.

[0081] The memory bank 140 can be connected to the row decoder 130 via the plurality of word lines WL, and can be connected to the sense amplifier & write driver 150 via a plurality of global input / output lines GIO.

[0082] The memory bank 140 can include a plurality of memory cells arranged in a matrix form. Among the plurality of memory cells, a memory cell connected to one word line WL can be referred to as one memory cell row MCR. That is, memory cells connected to different word lines WL can be referred to as different memory cell rows MCR.

[0083] In an embodiment, each of the plurality of memory cells included in the memory bank 140 can be a dynamic random access memory (DRAM) cell, but the scope of the present disclosure is not limited thereto.

[0084] The sense amplifier & write driver 150 can be connected to the memory bank 140 with the plurality of global input / output lines GIO. The sense amplifier & write driver 150 can receive data from the memory bank 140 through the plurality of global input / output lines GIO or store data DATA in the memory bank 140 through the plurality of global input / output lines GIO in response to a control of the control logic circuit 120.

[0085] The input / output circuit 160 can communicate with the host device 10. For example, the input / output circuit 160 can provide data DATA received from the host device 10 to the sense amplifier & write driver 150, or can transmit data DATA provided from the sense amplifier & write driver 150 to the host device 10.

[0086] The control logic circuit 120 can include a refresh manager 121. The refresh manager 121 can manage the refresh target determination list LST and the refresh target pointer value PT_TG.

[0087] The refresh manager 121 can determine the memory cell rows MCR to be refreshed in response to the regular refresh command REF_R and the fine-grained refresh command REF_F based on the refresh target determination list LST and the refresh target pointer value PT_TG. The detailed method how the refresh manager 121 determines the memory cell rows MCR to be refreshed will be described below with reference to Figures 10 to 13 The detailed method how the refresh manager 121 determines the memory cell rows MCR to be refreshed will be described below with reference to

[0088] Figure 6 is a diagram illustrating some configurations of Figure 5 in more detail. Referring to Figures 1 to 6 , the memory bank 140 can include first to nth memory cell arrays 141_1 to 141_n and first to (n-1)th bit line sense amplifiers 142_1 to 142_n-1. Each of the first to nth memory cell arrays 141_1 to 141_n can include a plurality of memory cell rows MCR.

[0089] Each of the first to nth memory cell arrays 141_1 to 141_n can be connected to a different word line group WLG. For example, the first to nth memory cell arrays 141_1 to 141_n can be connected to first to nth word line groups WLG1 to WLGn, respectively. Each of the first to nth word line groups WLG1 to WLGn can exclusively include a plurality of word lines WL. That is, the word lines WL included in each of the first to nth word line groups WLG1 to WLGn can not overlap with each other. For example, the first word line group WLG1 can include word lines WL11 to WL1m, and the second word line group WLG2 can include word lines WL21 to WL2m.

[0090] Each of the first to nth memory cell arrays 141_1 to 141_n can include a first sub-array SUBa and a second sub-array SUBb. For example, the first to nth memory cell arrays 141_1 to 141_n can include first to nth sub-arrays SUBa_1 to SUBa_n and first to nth sub-arrays SUBb_1 to SUBb_n, respectively.

[0091] The first sub-array SUBa and the second sub-array SUBb included in the same memory cell array 141 can be connected to the same word line group WLG. For example, the first sub-array SUBa_1 and the second sub-array SUBb_1 can both be connected to the word lines WL11 to WL1m.

[0092] Each memory cell row MCR included in the memory bank 140 can include a plurality of memory cells connected to different bit lines. In this case, with respect to the plurality of memory cells of one memory cell row MCR, some of them can be included in the first sub-array SUBa, and the rest can be included in the second sub-array SUBb.

[0093] The first sub-array SUBa and the second sub-array SUBb included in the same memory cell array 141 can be connected to different bit line groups. For example, the first sub-array SUBa can be connected to odd-numbered bit lines, and the second sub-array SUBb can be connected to even-numbered bit lines. However, the scope of the present disclosure is not limited thereto.

[0094] Each of the first through nth memory cell arrays 141_1 through 141_n can be connected to one or more bit line sense amplifiers 142. For example, the first through (n-1)th sub-arrays SUBa_1 through SUBa_n-1 can be connected to the first through (n-1)th bit line sense amplifiers 142_1 through 142_n-1, respectively, through a plurality of bit lines BL, and the second through nth sub-arrays SUBb_2 through SUBb_n can be connected to the first through (n-1)th bit line sense amplifiers 142_1 through 142_n-1, respectively, through a plurality of bit lines BL.

[0095] Each of the first memory cell array 141_1 and the nth memory cell array 141_n can be referred to as an "edge memory cell array." That is, each of the first memory cell array 141_1 and the nth memory cell array 141_n can be referred to as having an "edge memory cell array type." Each of the edge memory cell arrays can be connected to one bit line sense amplifier 142.

[0096] In an embodiment, the edge memory cell arrays can be referred to by various terms, such as outer memory cell array, outer storage cell array, etc. However, the scope of the present disclosure is not limited to these terms.

[0097] In an embodiment, the first sub-array SUBa_n and the second sub-array SUBb_1 can not be connected to any bit line sense amplifier.

[0098] The second through (n-1)th memory cell arrays 141_2 through 141_n-1 can be placed between the first memory cell array 141_1 and the nth memory cell array 141_n. Each of the second through (n-1)th memory cell arrays 141_2 through 141_n-1 can be referred to as an "internal memory cell array." That is, each of the second through (n-1)th memory cell arrays 141_2 through 141_n-1 can be referred to as having an "internal memory cell array type." Each of the internal memory cell arrays can be connected to two bit line sense amplifiers 142.

[0099] In an embodiment, the internal memory cell array can be referred to by various terms, such as a normal memory cell array, an inner memory cell array, a non-edge memory cell array, etc. However, the scope of the present disclosure is not limited to these terms.

[0100] When a word line WL connected to the internal memory cell array is activated, the first sub-array SUBa and the second sub-array SUBb included in the internal memory cell array can provide data to different bit line sense amplifiers 142 from each other. For example, when a word line WL21 is activated, data stored in memory cells included in the first sub-array SUBa_2 and connected to the word line WL21 can be provided to the second bit line sense amplifier 142_2, and data stored in memory cells included in the second sub-array SUBb_2 and connected to the word line WL21 can be provided to the first bit line sense amplifier 142_1. That is, when a word line WL connected to the internal memory cell array is activated, data stored in a memory cell row MCR connected to the word line WL can be distributed to two bit line sense amplifiers 142.

[0101] When a word line WL connected to the edge memory cell array is activated, only one of the first sub-array SUBa and the second sub-array SUBb included in the edge memory cell array can provide data to the bit line sense amplifier 142. For example, when a word line WL11 is activated, data stored in memory cells included in the first sub-array SUBa_1 and connected to the word line WL11 can be provided to the first bit line sense amplifier 142_1. On the other hand, when a word line WLn1 is activated, data stored in memory cells included in the second sub-array SUBb_n and connected to the word line WLn1 can be provided to the (n-1)-th bit line sense amplifier 142_n-1. That is, when a word line WL connected to the edge memory cell array is activated, only some (e.g., half) of data stored in a memory cell row MCR connected to the word line WL can be provided to the bit line sense amplifier 142.

[0102] In an embodiment, data stored in memory cells included in the second sub-array SUBb_1 and the first sub-array SUBa_n can be dummy data. For example, the second sub-array SUBb_1 and the first sub-array SUBa_n can store invalid data. From this perspective, a sub-array storing invalid data can also be referred to as an invalid sub-array. However, the scope of the present disclosure is not limited thereto.

[0103] Each of the first to (n-1)th bit line sense amplifiers 142_1 to 142_n-1 can temporarily store data received through the plurality of bit lines BL. Each of the first to (n-1)th bit line sense amplifiers 142_1 to 142_n-1 can restore the temporarily stored data to the memory cells connected to the activated word line WL. For example, when the word line WL21 is activated, the second bit line sense amplifier 142_2 can temporarily store data stored in the first subarray SUBa_2, and then restore the temporarily stored data to the first subarray SUBa_2; and the first bit line sense amplifier 142_1 can temporarily store data stored in the second subarray SUBb_2, and then restore the temporarily stored data to the second subarray SUBb_2. In this way, when a certain word line WL is activated, a row of memory cells connected to the activated word line WL can be refreshed.

[0104] The first memory cell array 141_1 and the n-th memory cell array 141_n can be logically combined (e.g., paired). For example, the first memory cell array 141_1 and the n-th memory cell array 141_n can share a row address (hereinafter, referred to as "RA"). For example, when an activation command ACT corresponding to one row address RA for the edge memory cell array is issued from the host device 10, the control logic circuit 120 can simultaneously activate one word line WL connected to the first memory cell array 141_1 and one word line WL connected to the n-th memory cell array 141_n. In this case, data of the first subarray SUBa_1 can be provided to the first bit line sense amplifier 142_1, and data of the second subarray SUBb_n can be provided to the (n-1)th bit line sense amplifier 142_n-1.

[0105] In an embodiment, a group of row addresses RA corresponding to the first word line group WLG1 can be the same as a group of row addresses RA corresponding to the n-th word line group WLGn. For example, the row addresses RA corresponding to the word lines WL11 to WL1m can be respectively the same as the row addresses RA corresponding to the word lines WLn1 to WLnm. However, the scope of the present disclosure is not limited thereto.

[0106] That is, when an activation command corresponding to a row address RA for the edge memory cell array is issued from the host device 10, two word lines can be simultaneously activated. In other words, even in a typical case in which the host device 10 accesses the memory bank 140 (e.g., when the memory device 100 performs a normal operation), two word lines WL can be simultaneously activated. The maximum number of word lines WL that can be simultaneously activated in the typical case in which the host device 10 accesses the memory bank 140 can be referred to as the "maximum number of word lines simultaneously activated for an activation command" or the "maximum number of word lines simultaneously activated."

[0107] In an embodiment, the maximum number of word lines simultaneously activated with respect to the memory bank 140 can be "2". However, the scope of the present disclosure is not limited thereto.

[0108] Accordingly, even in a typical case in which the host device 10 accesses the memory bank 140, the voltage supply circuit VSC can secure power for simultaneously activating as many word lines as the "maximum number of simultaneously activated word lines". According to the embodiment of the present disclosure, in response to the fine-grained refresh command REF_F, a fine-grained refresh operation for a number of memory cell rows MCR smaller than or equal to the "maximum number of simultaneously activated word lines" can be simultaneously performed. In this case, the overhead of the voltage supply circuit VSC for providing a driving voltage VDRV to one or more word lines WL while performing the fine-grained refresh operation can be minimized. In this case, the time taken for the voltage supply circuit VSC to generate the driving voltage VDRV can be minimized, and the memory device 100 can perform the fine-grained refresh operation in a time shorter than the conventional refresh consumed time tRFC_R.

[0109] Each of the first to (n-1)th bit line sense amplifiers 142_1 to 142_n-1 can be connected to the plurality of local input / output lines LIO by the plurality of global input / output lines GIO. Each of the first to (n-1)th bit line sense amplifiers 142_1 to 142_n-1 can control the voltage level of the plurality of local input / output lines LIO based on the voltage level of the bit line BL connected thereto. Further, each of the first to (n-1)th bit line sense amplifiers 142_1 to 142_n-1 can control the voltage level of the bit line BL based on the voltage level of the local input / output line LIO.

[0110] The sense amplifier & write driver 150 can be connected to the plurality of global input / output lines GIO. The sense amplifier & write driver 150 can provide data represented by the voltage level of the plurality of global input / output lines GIO to the input / output circuit 160, or control the voltage level of the plurality of global input / output lines GIO based on data provided from the input / output circuit 160.

[0111] For a brief description, Figure 6 The plurality of local input / output lines LIO and the plurality of global input / output lines GIO are shown as being directly connected, but the scope of the present disclosure is not limited thereto. For example, various types of components such as local sense amplifiers can be further connected between the plurality of local input / output lines LIO and the plurality of global input / output lines GIO.

[0112] Figure 7 is a diagram illustrating in more detail how to perform a refresh operation. Referring to Figures 1 to 7In response to the regular refresh command REF_R or the fine-grained refresh command REF_F, the control logic circuit 120 can perform a refresh operation on one or more memory cell rows MCR. For example, the control logic circuit 120 can perform a refresh operation on about eight (e.g., eight to ten) memory cell rows MCR in response to the regular refresh command REF_R, and can perform a refresh operation on one or two memory cell rows MCR in response to the fine-grained refresh command REF_F. However, the scope of the present disclosure is not limited to the specific number of memory cell rows MCR that the control logic circuit 120 refreshes in response to the regular refresh command REF_R or the fine-grained refresh command REF_F.

[0113] The control logic circuit 120 can perform a refresh operation on two or more memory cell rows MCR at the same time. For example, the control logic circuit 120 can refresh eight memory cell rows MCR at the same time in response to a single regular refresh command REF_R, and can refresh two memory cell rows MCR at the same time in response to a single fine-grained refresh command REF_F. However, the scope of the present disclosure is not limited thereto, and the control logic circuit 120 can be implemented to refresh a total of eight memory cell rows MCR by refreshing four memory cell rows MCR per cycle for two cycles, or can be implemented to refresh a total of eight memory cell rows MCR by refreshing two memory cell rows MCR per cycle for four cycles.

[0114] More specifically, the control logic circuit 120 can refresh one memory cell row MCR of each of a plurality of memory cell arrays 141 that are not adjacent to each other. For example, the control logic circuit 120 can activate a word line connected to a first memory cell row MCRa included in the third memory cell array 141_3. In this case, data stored in the first memory cell row MCRa can be temporarily stored in the second bit line sense amplifier 142_2 and the third bit line sense amplifier 142_3, and then restored. At the same time, the control logic circuit 120 can activate a word line connected to a second memory cell row MCRb included in the fifth memory cell array 141_5. In this case, data stored in the second memory cell row MCRb can be temporarily stored in the fourth bit line sense amplifier 142_4 and the fifth bit line sense amplifier 142_5, and then restored. In this way, the control logic circuit 120 can refresh two or more memory cell rows MCR at the same time. For a more concise explanation, Figure 7 Only the third to fifth memory cell arrays 141_3 to 141_5 are illustrated in FIG. 1, but the scope of the present disclosure is not limited thereto. For example, the control logic circuit 120 can refresh two or more memory cell rows MCR at the same time in response to the regular refresh command REF_R; or can refresh two memory cell rows MCR included in two edge memory cell arrays, respectively, at the same time in response to the fine-grained refresh command REF_F.

[0115] In an embodiment, the plurality of memory cell arrays 141 that are not adjacent to each other can not share the bit line sense amplifier with each other. For example, one or more memory cell arrays can be included between the plurality of memory cell arrays 141 that are not adjacent to each other.

[0116] In an embodiment, as the number of memory cell rows MCR that the control logic circuit 120 refreshes at the same time increases, the amount of power required to supply the drive voltage VDRV to the word lines WL connected to the corresponding memory cell rows MCR can increase. In this case, the time taken by the voltage supply circuit VSC to prepare and supply the drive voltage VDRV to the word lines WL connected to the corresponding memory cell rows MCR can increase. Therefore, depending on how many memory cell rows MCR the control logic circuit 120 refreshes at the same time, the time taken by the control logic circuit 120 to complete the operations for the regular refresh command REF R and the fine-grained refresh command REF F can vary.

[0117] Figure 8 is a timing chart illustrating an operation of a memory device in response to a regular refresh command according to an embodiment of the disclosure. Figure 8 The horizontal axis of can represent time.

[0118] Referring to Figures 1 to 8 , the host device 10 can issue a regular refresh command REF R to the memory bank 140 at a first time point t1. In this case, the control logic circuit 120 can perform a regular refresh operation on the memory bank 140 between the first time point t1 and a second time point t2. For example, the control logic circuit 120 can perform a refresh operation on about eight memory cell rows MCR included in the memory bank 140 between the first time point t1 and the second time point t2.

[0119] The time required for the control logic circuit 120 to complete the regular refresh operation on the memory bank 140 can be referred to as a regular refresh consumption time tRFC R. For example, the time interval between the first time point t1 and the second time point t2 can be referred to as the regular refresh consumption time tRFC R.

[0120] The host device 10 can issue a subsequent command to the memory bank 140 after the regular refresh consumption time tRFC R elapses from the first time point t1. For example, the host device 10 can issue an activate command ACT, a regular refresh command REF R, or a fine-grained refresh command REF F to the memory bank 140 at a third time point t3 after the second time point t2.

[0121] In an embodiment, the "activation command ACT to the memory bank 140" can refer to an activation command corresponding to a bank address of the memory bank 140.

[0122] In an embodiment, the "fine-grained refresh command REF F to the memory bank 140" can refer to a fine-grained refresh command corresponding to a bank address of the memory bank 140.

[0123] In an embodiment, the "regular refresh command REF R to the memory bank 140" can refer to a full-bank refresh command or a per-bank refresh command to the memory bank 140. However, the scope of the present disclosure is not limited to these examples.

[0124] In an embodiment, the access to the memory bank 140 by the host device 10 can be prohibited during the regular refresh consumption time tRFC R. For example, the host device 10 can not issue an activation command ACT to the memory bank 140 between the first time point tl and the second time point t2.

[0125] Figure 9 is a timing chart illustrating an operation of a memory device in response to a fine-grained refresh command according to an embodiment of the present disclosure. Figure 9 The horizontal axis of can represent time.

[0126] Referring to Figures 1 to 9 At the fourth time point t4, the host device 10 can issue a fine-grained refresh command REF F to the memory bank 140. In this case, the control logic circuit 120 can perform a fine-grained refresh operation on the memory bank 140 between the fourth time point t4 and the fifth time point t5. For example, the control logic circuit 120 can perform a refresh operation on one or two memory cell rows MCR included in the memory bank 140 between the fourth time point t4 and the fifth time point t5.

[0127] The time required for the control logic circuit 120 to complete the fine-grained refresh operation on the memory bank 140 can be referred to as a fine-grained refresh consumption time tRFC F. For example, the time interval between the fourth time point t4 and the fifth time point t5 can be referred to as the fine-grained refresh consumption time tRFC F.

[0128] The host device 10 can issue a subsequent command to the memory bank 140 after the fine-grained refresh consumption time tRFC F elapses from the fourth time point t4. For example, the host device 10 can issue an activation command ACT, a regular refresh command REF R, or a fine-grained refresh command REF F to the memory bank 140 at a sixth time point t6 after the fifth time point t5.

[0129] The fine-grained refresh consumption time tRFC_F can be shorter than the regular refresh consumption time tRFC_R. For example, the fine-grained refresh consumption time tRFC_F can be a time length corresponding to the same bank activation minimum interval (hereinafter referred to as "tRC") of the memory bank 140, and the regular refresh consumption time tRFC_R can be a time length longer than the same bank activation minimum interval tRC of the memory bank 140.

[0130] In an embodiment, the fine-grained refresh consumption time tRFC_F can have the same length as the same bank activation minimum interval tRC. However, the scope of the present disclosure is not limited thereto, and the fine-grained refresh consumption time tRFC_F can have a length similar to the same bank activation minimum interval tRC.

[0131] In an embodiment, the regular refresh consumption time tRFC_R can be at least twice the same bank activation minimum interval tRC of the memory bank 140. However, the scope of the present disclosure is not limited thereto.

[0132] In an embodiment, the fine-grained refresh consumption time tRFC_F can be about 60 ns. However, the scope of the present disclosure is not limited thereto.

[0133] In an embodiment, the regular refresh consumption time tRFC_R can be 120 ns to 400 ns. However, the scope of the present disclosure is not limited thereto.

[0134] In an embodiment, the access of the memory bank 140 by the host device 10 can be prohibited during the fine-grained refresh consumption time tRFC_F. For example, the host device 10 can not issue an activate command ACT to the memory bank 140 between the fourth time point t4 and the fifth time point t5.

[0135] That is, the time length during which the access of the memory bank 140 is prohibited when the host device 10 issues the fine-grained refresh command REF_F can be shorter than the time length during which the access of the memory bank 140 is prohibited when the host device 10 issues the regular refresh command REF_R.

[0136] In an embodiment, the fourth time point t4 can be a time point after the third time point t3. Alternatively, the sixth time point t6 can be a time point before the first time point t1. In other words, the host device 10 can flexibly issue the regular refresh command REF_R and the fine-grained refresh command REF_F to one memory bank 140. In this case, the command issuance schedule of the host device 10 can be more flexibly determined, and thus the operation efficiency of the memory system MS can be improved.

[0137] Figure 10 and Figure 11is a diagram illustrating an operation of a memory system according to an embodiment. Hereinafter, the operation of the memory system according to the embodiment will be described with reference to Figure 10 The operation of the memory device 100 according to the embodiment is described, and reference will be made to Figure 11 The operation of the host device 10 according to the embodiment is described.

[0138] First, reference is made to Figures 1 to 10 The refresh target determination list LST can be implemented as the following refresh target determination list LSTa.

[0139] The refresh target determination list LSTa can include a plurality of row addresses RA arranged in order. For example, the refresh target determination list LSTa can include the 0th to 18th row addresses RA0 to RA18. The 0th to 18th row addresses RA0 to RA18 can have different orders (e.g., have different ranks or order indexes).

[0140] The refresh manager 121 can perform a refresh operation on the plurality of row addresses RA in response to the regular refresh command REF_R provided from the host device 10. For example, the refresh manager 121 can perform a refresh operation on eight row addresses RA in response to the regular refresh command REF_R. However, the scope of the present disclosure is not limited to a specific number of row addresses RA corresponding to the memory cell rows MCR refreshed by the refresh manager 121 in response to the regular refresh command REF_R. For example, the refresh manager 121 can perform a refresh operation on any number of row addresses RA such as 4, 16, or 32 in response to the regular refresh command REF_R. However, hereinafter, it is assumed that the refresh manager 121 performs a refresh operation on eight row addresses RA in response to the regular refresh command REF_R.

[0141] The refresh manager 121 can perform a refresh operation on one or more row addresses RA in response to the fine-grained refresh command REF_F provided from the host device 10. For example, the refresh manager 121 can perform a refresh operation on one or two row addresses RA in response to the fine-grained refresh command REF_F.

[0142] The refresh manager 121 can sequentially perform a refresh operation on the plurality of row addresses RA included in the refresh target determination list LSTa in response to the regular refresh command REF_R and the fine-grained refresh command REF_F. For example, based on the refresh target determination list LSTa and the refresh target pointer value PT_TG, the refresh manager 121 can determine on which row addresses RA to perform a refresh operation (hereinafter, the row addresses can be referred to as refresh target row addresses RA_TG) in response to the regular refresh command REF_R or the fine-grained refresh command REF_F.

[0143] In an embodiment, the refresh target row address RA_TG corresponding to the regular refresh command REF_R can be referred to as a "regular refresh target row address".

[0144] In an embodiment, the refresh target row address RA_TG corresponding to the fine-grained refresh command REF_F can be referred to as a "fine-grained refresh target row address".

[0145] Hereinafter, the operation of the refresh manager 121 when the first regular refresh command REF_R1, the first to third fine-grained refresh commands REF_F1 to REF_F3, and the second regular refresh command REF_R2 are sequentially received from the host device 10 in a state where the refresh target pointer value PT_TG indicates the 0th row address RA0 (e.g., a state where the refresh target pointer value PT_TG is "0") is exemplarily described. However, the scope of the present disclosure is not limited thereto.

[0146] The refresh manager 121 can determine the refresh target row address RA_TG for the first regular refresh command REF_R1 based on the refresh target pointer value PT_TG. For example, the refresh manager 121 can determine a total of eight row addresses RA having a continuous order (e.g., an order sequence in the refresh target determination list LSTa) from the row address indicated by the refresh target pointer value PT_TG (hereinafter, the row address indicated by the refresh target pointer value PT_TG can be referred to as a pointed row address RA_PTD) as the refresh target row address RA_TG. For a more detailed example, the refresh manager 121 can determine the 0th to 7th row addresses RA0 to RA7 as the refresh target row address RA_TG for the first regular refresh command REF_R1. The refresh manager 121 can perform a refresh operation for the refresh target row address RA_TG.

[0147] The number of memory cell rows MCR refreshed by the refresh manager 121 in response to the regular refresh command REF_R can vary depending on the type of the memory cell array corresponding to each of the refresh target row addresses RA_TG. For example, if each of the 0th to 7th row addresses RA0 to RA7 corresponds to the internal memory cell array described above with reference to FIG. 1, the refresh manager 121 can perform a refresh operation for a total of eight memory cell rows MCR. On the other hand, if some of the 0th to 7th row addresses RA0 to RA7 correspond to the external memory cell array described above with reference to FIG. 1, the refresh manager 121 can perform a refresh operation for a total of eight memory cell rows MCR. Figure 6 Figure 6 ​The described edge storage cell array, the refresh manager 121 can perform a refresh operation on as many storage cell rows MCR as the sum of eight and the number of row addresses corresponding to the edge storage cell array. For a more detailed example, if two of the first through seventh row addresses RA0 through RA7 correspond to the edge storage cell array, the refresh manager 121 can perform a refresh operation on a total of ten storage cell rows MCR.

[0148] In an embodiment, the number of refresh target row addresses RA_TG corresponding to one regular refresh command REF_R can be referred to as the "number of regular refresh targets." However, the scope of the present disclosure is not limited to these terms.

[0149] After completing the refresh operation corresponding to the refresh target row addresses RA_TG for the first regular refresh command REF_R1, the refresh manager 121 can increase the refresh target pointer value PT_TG by the number of row addresses RA for which the refresh operation has been completed. For example, the refresh manager 121 can increase the refresh target pointer value PT_TG by "8" (e.g., update it to point to the eighth row address RA8) after completing the regular refresh operation in response to the first regular refresh command REF_R1.

[0150] The refresh manager 121 can determine the refresh target row addresses RA_TG for the fine-grained refresh command REF_F based on the updated refresh target pointer value PT_TG. For example, the refresh manager 121 can determine the number of refresh target row addresses RA_TG for the fine-grained refresh command REF_F based on the type of the storage cell array corresponding to the pointed row address RA_PTD and its subsequent row address (e.g., the row address immediately following the pointed row address in the refresh target determination list LSTa) (hereinafter, which can be referred to as the subsequent row address RA_SUBS).

[0151] In an embodiment, the number of refresh target row addresses RA_TG corresponding to one fine-grained refresh command REF_F can be referred to as the "number of fine-grained refresh targets." However, the scope of the present disclosure is not limited to these terms.

[0152] More specifically, when at least one of the pointing row address RA_PTD and the subsequent row address RA_SUBS corresponds to the edge cell type (e.g., if at least one of the pointing row address RA_PTD and the subsequent row address RA_SUBS points to a word line connected to the edge cell array), the refresh manager 121 can determine only the pointing row address RA_PTD as the refresh target row address RA_TG. More specifically, when the pointing row address RA_PTD corresponds to the edge cell type, the refresh manager 121 can perform a refresh operation on two cell rows MCR corresponding to the pointing row address RA_PTD (e.g., one cell row MCR included in the first cell array 141_1 and one cell row MCR included in the nth cell array 141_n) and increase the refresh target pointer value PT_TG by "1". When the pointing row address RA_PTD corresponds to the internal cell type and the subsequent row address RA_SUBS corresponds to the edge cell type, the refresh manager 121 can perform a refresh operation on one cell row MCR corresponding to the pointing row address RA_PTD and increase the refresh target pointer value PT_TG by "1".

[0153] On the other hand, when both the pointing row address RA_PTD and the subsequent row address RA_SUBS indicated by the refresh target pointer value PT_TG correspond to the internal cell type (e.g., when each of the pointing row address RA_PTD and the subsequent row address RA_SUBS points to a word line connected to the internal cell array), the refresh manager 121 can determine the pointing row address RA_PTD and the subsequent row address RA_SUBS as the refresh target row address RA_TG. In this case, the refresh manager 121 can perform a refresh operation on two cell rows MCR corresponding to the pointing row address RA_PTD and the subsequent row address RA_SUBS, respectively, and can increase the refresh target pointer value PT_TG by "2".

[0154] In other words, the number of row addresses RA on which the refresh manager 121 performs a refresh operation in response to the fine-grained refresh command REF_F can be determined based on the cell type corresponding to the pointing row address RA_PTD and the subsequent row address RA_SUBS.

[0155] In this way, the refresh manager 121 can determine the refresh target row address RA_TG for each of the first to third fine-grained refresh commands REF_F1 to REF_F3.

[0156] For example, each of the eighth row address RA8 and the ninth row address RA9 can correspond to an internal storage cell array. In this case, the refresh manager 121 can perform a refresh operation on the eighth row address RA8 to the ninth row address RA9 in response to the first fine-grained refresh command REF_F1, and then increase the refresh target pointer value PT_TG by "2" (i.e., update it to indicate the tenth row address RA10).

[0157] Each of the tenth row address RA10 and the eleventh row address RA11 can correspond to an internal storage cell array. In this case, the refresh manager 121 can perform a refresh operation on the tenth row address RA10 to the eleventh row address RA11 in response to the second fine-grained refresh command REF_F2, and then increase the refresh target pointer value PT_TG by "2" (i.e., update it to indicate the twelfth row address RA12).

[0158] One or more of the twelfth row address RA12 and the thirteenth row address RA13 can correspond to an edge storage cell array. For example, the twelfth row address RA12 can correspond to an edge storage cell array. In this case, the refresh manager 121 can perform a refresh operation on the twelfth row address RA12 in response to the third fine-grained refresh command REF_F3, and then increase the refresh target pointer value PT_TG by "1" (i.e., update it to indicate the thirteenth row address RA13).

[0159] Hereinafter, for a more concise explanation, a row address corresponding to an edge storage cell array can be referred to as an "edge row address" (or an outer row address, an outermost row address, etc.). A row address corresponding to an internal storage cell array can be referred to as an "internal row address" (or a normal row address, an inner row address, a non-edge row address, etc.).

[0160] In an embodiment, an edge row address can point to two storage cell rows, which respectively correspond to two edge storage cell arrays.

[0161] Thereafter, the refresh manager 121 can determine a refresh target row address RA_TG for the second regular refresh command REF_R2 based on the updated refresh target pointer value PT_TG. For example, the refresh manager 121 can determine a total of eight row addresses RA having a consecutive order starting from the pointed row address RA_PTD (e.g., the thirteenth row address RA13) as the refresh target row address RA_TG.

[0162] In this way, the refresh manager 121 can perform a refresh operation on each row address only once during one retention time tRT. In other words, according to the above-described embodiment, the refresh manager 121 can perform a refresh operation on each row address only once during one retention time tRT. Figure 10In the embodiment of FIG. 1, the host device 10 can increase the refresh deficit count DCNT by the skip cost CST_SKIP at each regular refresh cycle. For example, the host device 10 can increase the refresh deficit count DCNT by the skip cost CST_SKIP at the tenth time point t10, the eleventh time point t11, and the twelfth time point t12.

[0163] Continuing further reference to Figure 11 , the host device 10 can issue the regular refresh command REF R and the fine-grained refresh command REF F flexibly based on the refresh deficit count DCNT. Figure 11 The horizontal axis of the graph of FIG. 2 can represent time, and the vertical axis can represent the value of the refresh deficit count DCNT or the number of memory cell rows MCR refreshed per unit time.

[0164] The regular refresh cycle of the memory bank 140 can occur at the tenth time point t10, the eleventh time point t11, and the twelfth time point t12. For example, the regular refresh cycle of the memory bank 140 can start at the tenth time point t10, the eleventh time point t11, and the twelfth time point t12. For a more concise explanation, hereinafter, it is assumed that the refresh deficit count DCNT of the memory bank 140 is “0” before the tenth time point t10.

[0165] The host device 10 can increase the refresh deficit count DCNT by the skip cost CST_SKIP at each regular refresh cycle. For example, the host device 10 can increase the refresh deficit count DCNT by the skip cost CST_SKIP at the tenth time point t10, the eleventh time point t11, and the twelfth time point t12.

[0166] The host device 10 can decrease the refresh deficit count DCNT by the skip cost CST_SKIP each time the host device 10 issues the regular refresh command REF R. For example, at the thirteenth time point t13, the host device 10 can issue the first regular refresh command REF R1 and decrease the refresh deficit count DCNT to “0”.

[0167] The host device 10 can issue a plurality of fine-grained refresh commands REF F between the tenth time point t10 and the eleventh time point t11. For example, the host device 10 can issue first to third fine-grained refresh commands REF F1 to REF F3 at fourteenth to sixteenth time points t14 to t16, respectively.

[0168] The host device 10 can decrease the refresh deficit count DCNT by “a unit deduction cost (e.g., 1)” each time the host device 10 issues the fine-grained refresh command REF F. For example, the host device 10 can decrease the refresh deficit count DCNT by “1” at each of the fourteenth to sixteenth time points t14 to t16.

[0169] The host device 10 can issue a second regular refresh command REF_R2 at a seventeenth time point t17. In this case, similar to that described above with reference to the thirteenth time point t13, the host device 10 can decrease the refresh deficit count DCNT by the skip cost CST_SKIP at the seventeenth time point t17. That is, according to the embodiment of Figure 10 and Figure 11 the host device 10 can decrease the refresh deficit count DCNT by the skip cost CST_SKIP whenever the host device 10 issues the regular refresh command REF_R.

[0170] Meanwhile, the host device 10 can determine whether to skip issuing the regular refresh command REF_R based on the refresh deficit count DCNT. For example, the host device 10 can freely determine the timing of issuing the regular refresh command REF_R (e.g., for skipping or delaying), similar to that described above with reference to Figure 4 That is, the host device 10 can maintain the refresh deficit count DCNT not to exceed the predetermined refresh deficit count range (e.g., within the predetermined refresh deficit count range) at the regular refresh time point at which the regular refresh period starts, by flexibly issuing the regular refresh command REF_R and the fine-grained refresh command REF_F. For a more detailed example, the host device 10 can skip issuing the regular refresh command REF_R and maintain the refresh deficit count DCNT at an eighteenth time point t18.

[0171] In an embodiment, the predetermined refresh deficit count range can correspond to a range from a value smaller than "0" by as much as a product of the refresh fluctuation threshold and the skip cost CST_SKIP to a value larger than "0" by as much as the product of the refresh fluctuation threshold and the skip cost CST_SKIP. In this case, it is possible to prevent phenomena of excessively performing a refresh operation on the memory bank 140 and phenomena of insufficiently performing a refresh on the memory bank 140. However, the scope of the present disclosure is not limited thereto.

[0172] In an embodiment, the skip cost CST_SKIP can be determined based on a value obtained by dividing an average number of memory cell rows refreshed by the memory device 100 in response to the regular refresh command REF R by an average number of memory cell rows refreshed by the memory device 100 in response to the fine-grained refresh command REF F. For example, the skip cost CST_SKIP can be determined based on a result of rounding up the value obtained by dividing the average number of memory cell rows refreshed by the memory device 100 in response to the regular refresh command REF R by the average number of memory cell rows refreshed by the memory device 100 in response to the fine-grained refresh command REF F. For a more detailed example, if the average number of memory cell rows refreshed by the memory device 100 in response to the regular refresh command REF R is "8.1" and the average number of memory cell rows refreshed by the memory device 100 in response to the fine-grained refresh command REF F is 1.9, the skip cost CST_SKIP can be determined as "5 (e.g., rounding the result of 8.1 / 1.9 to the nearest integer)". However, the scope of the present disclosure is not limited thereto, and the skip cost CST_SKIP can also be determined in decimal units. That is, the scope of the present disclosure is not limited to the data type (e.g., integer, floating point, fixed point, etc.) of the skip cost CST_SKIP.

[0173] In an embodiment, the average number of memory cell rows refreshed by the memory device 100 in response to the regular refresh command REF R can be determined as a product of the number of row addresses RA for which the memory device 100 performs a refresh operation in response to the regular refresh command REF R and (n+2) / n (where "n" is the total number of memory cell arrays included in the memory bank 140).

[0174] In an embodiment, the average number of memory cell rows refreshed by the memory device 100 in response to the fine-grained refresh command REF F can be determined as the maximum number of word lines activated at the same time for the activation command or less.

[0175] In an embodiment, the average number of memory cell rows refreshed by the memory device 100 in response to the fine-grained refresh command REF F can be determined according to an arrangement (e.g., ordering) of a plurality of row addresses RA included in the refresh target determination list LST.

[0176] Figure 12 and Figure 13 are diagrams illustrating operations of a memory system according to an embodiment. Hereinafter, operations of the memory device 100 according to an embodiment will be described with reference to Figure 12 Operations of the memory device 100 according to an embodiment will be described, and operations of the host device 10 according to an embodiment will be described with reference to Figure 13 Operations of the memory device 100 according to an embodiment will be described, and operations of the host device 10 according to an embodiment will be described with reference to

[0177] First, reference will be made toFigures 1 to 9 and Figure 12 The refresh target determination list LST can be implemented as the following refresh target determination list LSTb.

[0178] The refresh target determination list LSTb can include a plurality of row addresses RA arranged in order. For example, the refresh target determination list LSTb can include the 0th to 18th row addresses RA0 to RA18.

[0179] The refresh manager 121 can perform a refresh operation on the plurality of row addresses RA in response to the regular refresh command REF R provided from the host device 10. The row addresses RA and the number of memory cell rows MCR refreshed by the refresh manager 121 in response to the regular refresh command REF R are similar to those described above with reference to Figure 10 , and thus a detailed description is omitted.

[0180] The refresh manager 121 can perform a refresh operation on one or more row addresses RA in response to the fine-grained refresh command REF F provided from the host device 10. The operation of the refresh manager 121 in response to the fine-grained refresh command REF F is similar to that described above with reference to Figure 10 , and thus a detailed description is omitted.

[0181] The refresh manager 121 can sequentially perform a refresh operation on the plurality of row addresses RA included in the refresh target determination list LSTb in response to the regular refresh command REF R and the fine-grained refresh command REF F. For example, the refresh manager 121 can determine one or more target row addresses RA_TG for the regular refresh command REF R and the fine-grained refresh command REF F based on the refresh target determination list LSTb and the refresh target pointer value PT_TG.

[0182] The refresh target determination list LSTb can include a plurality of row address groups RAG. Each of the plurality of row address groups RAG can exclusively include a plurality of row addresses RA arranged in order. That is, each of the plurality of row address groups RAG can include a different subset of the plurality of row addresses RA. In other words, the plurality of row addresses RA included in the refresh target determination list LSTb can be classified into the plurality of row address groups RAG.

[0183] Each of the plurality of row address groups RAG can include the same number of row addresses RA. For example, each of the plurality of row address groups RAG can include the same number of row addresses as the number of row addresses RA on which a refresh operation is performed in response to a single regular refresh command REF R (e.g., eight). For a more detailed example, the 0th to 7th row addresses RA0 to RA7 can be included in a first row address group RAGa, and the 8th to 15th row addresses RA8 to RA15 can be included in a second row address group RAGb.

[0184] The highest-ordered row address among the row addresses included in each of the plurality of row address groups RAG can be referred to as a "group head row address (which is shown as a striped pattern)." For example, the 0th row address RA0 can be referred to as a group head row address of the first row address group RAGa, and the 8th row address RA8 can be referred to as a group head row address of the second row address group RAGb.

[0185] The refresh manager 121 can determine the refresh target row addresses RA_TG of the fine-grained refresh commands REF_F in a similar manner to the above reference Figure 10 The refresh manager 121 can determine one or two row addresses as the refresh target row addresses RA_TG based on the refresh target pointer value PT_TG, for example. The refresh manager 121 can determine the refresh target row addresses RA_TG based on the unit of the row address group RAG corresponding to the refresh target pointer value PT_TG, for example.

[0186] The refresh manager 121 can determine the refresh target row addresses RA_TG for the regular refresh command REF_R based on the unit of the row address group RAG corresponding to the refresh target pointer value PT_TG. For example, the refresh manager 121 can determine all the row addresses RA included in one row address group RAG as the refresh target row addresses RA_TG in response to the regular refresh command REF_R.

[0187] Hereinafter, the operation of the refresh manager 121 when the first regular refresh command REF_R1, the first to third fine-grained refresh commands REF_F1 to REF_F3, and the second regular refresh command REF_R2 are sequentially received from the host device 10 in a state in which the refresh target pointer value PT_TG indicates the 0th row address RA0 (e.g., a state in which the refresh target pointer value PT_TG is "0") is exemplarily described. However, the scope of the present disclosure is not limited thereto.

[0188] The refresh manager 121 can determine the refresh target row addresses RA_TG for the first regular refresh command REF_R1 based on the refresh target pointer value PT_TG. For example, the refresh manager 121 can determine all the row addresses RA within the row address group RAG pointing to the row address RA_PTD as the refresh target row addresses RA_TG. For a more detailed example, if the pointing row address RA_PTD is the 0th row address RA0, the refresh manager 121 can determine the 0th to 7th row addresses RA0 to RA7 as the refresh target row addresses RA_TG for the first regular refresh command REF_R1.

[0189] After completing the refresh operation corresponding to the refresh target row address RA_TG for the first regular refresh command REF_R1, the refresh manager 121 can update the refresh target pointer value PT_TG to point to the group head row address of the next row address group RAG. For example, the refresh manager 121 can increase the refresh target pointer value PT_TG by "8" so that the refresh target pointer value PT_TG points to the eighth row address RA8 (which is the group head row address of the second row address group RAGb).

[0190] The refresh manager 121 can determine the refresh target row address RA_TG for each of the first to third fine-grained refresh commands REF_F1 to REF_F3. The refresh manager 121 can update the refresh target pointer value PT_TG after completing the fine-grained refresh operation for each of the first to third fine-grained refresh commands REF_F1 to REF_F3. In this case, the refresh target pointer value PT_TG can point to the thirteenth row address RA13 after the fine-grained refresh operation for the third fine-grained refresh command REF_F3 is completed. The operation of the refresh manager 121 in response to the first to third fine-grained refresh commands REF_F1 to REF_F3 is similar to that described above with reference to FIG. 4, and thus a detailed description is omitted. Figure 10

[0191] Thereafter, the refresh manager 121 can determine the refresh target row address RA_TG for the second regular refresh command REF_R2 based on the refresh target pointer value PT_TG. For example, the refresh manager 121 can determine all row addresses RA included in the second row address group RAGb (which includes the row address RA_PTD (i.e., the thirteenth row address RA13)) as the refresh target row address RA_TG. For a more detailed example, the refresh manager 121 can determine the eighth to fifteenth row addresses RA8 to RA15 as the refresh target row address RA_TG for the second regular refresh command REF_R2.

[0192] After completing the regular refresh operation for the second regular refresh command REF_R2, the refresh manager 121 can update the refresh target pointer value PT_TG to point to the group head row address of the next row address group RAG. For example, the refresh manager 121 can increase the refresh target pointer value PT_TG by "3" so that the refresh target pointer value PT_TG points to the sixteenth row address RA16.

[0193] That is, after completing the regular refresh operation for the regular refresh command REF_R, the refresh manager 121 can increase the refresh target pointer value PT_TG by "1" or more and "8 (e.g., the number of row addresses included in one row address group RAG)" or less.

[0194] According to​Figure 12 Embodiments of the present application, unlike the embodiments described above with reference to Figure 10 the refresh manager 121 can perform a regular refresh operation in units of row address groups RAGs. In this case, the refresh manager 121 can perform the operation based on the row address RA PTD in a more concise form, and thus the complexity of the circuit configuration and the production cost of the memory device 100 can be minimized. However, the scope of the present disclosure is not limited thereto.

[0195] With further reference to Figure 13 , the host device 10 can flexibly issue the regular refresh command REF R and the fine-grained refresh command REF F based on the refresh deficit count DCNT. Figure 13 The horizontal axis can represent time, and the vertical axis can represent the value of the refresh deficit count DCNT or the number of memory cell rows MCR refreshed per unit time.

[0196] The regular refresh period of the memory bank 140 can occur at the twentieth time point t20, the twenty-first time point t21, and the twenty-second time point t22. For example, the regular refresh period of the memory bank 140 can be at the twentieth time point t20, the twenty-first time point t21, and the twenty-second time point t22. For a more concise explanation, hereinafter, it is assumed that the refresh deficit count DCNT of the memory bank 140 is "0" before the twentieth time point t20.

[0197] The host device 10 can increase the refresh deficit count DCNT by the skip cost CST SKIP at each regular refresh period. For example, the host device 10 can increase the refresh deficit count DCNT by the skip cost CST SKIP at the twentieth time point t20, the twenty-first time point t21, and the twenty-second time point t22.

[0198] Each time the host device 10 issues the regular refresh command REF R, the host device 10 can decrease the refresh deficit count DCNT by an integer multiple of the skip cost CST SKIP. Specifically, each time the host device 10 issues the regular refresh command REF R, the host device 10 can decrease the refresh deficit count DCNT by "1" to "the skip cost CST SKIP". For example, at the twenty-third time point t23, the host device 10 can issue the first regular refresh command REF R1 and decrease the refresh deficit count DCNT by the skip cost CST SKIP.

[0199] The host device 10 can issue a plurality of fine-grained refresh commands REF F between the twentieth time point t20 and the twenty-first time point t21. For example, the host device 10 can issue first to third fine-grained refresh commands REF F1 to REF F3 at twenty-fourth to twenty-sixth time points t24 to t26, respectively.

[0200] Whenever the host device 10 issues the fine-grained refresh command REF_F, the host device 10 can decrease the refresh deficit count DCNT by "a unit deduction cost". For example, the host device 10 can decrease the refresh deficit count DCNT by "1" at each of the twenty-fourth to twenty-sixth time points t24to t26.

[0201] The host device 10 can issue the second regular refresh command REF_R2 at the twenty-seventh time point t27. In this case, the host device 10 can decrease the refresh deficit count DCNT by "1" to "a skip cost CST_SKIP", such that the refresh deficit count DCNT becomes an integer multiple of the skip cost CST_SKIP. For example, if the skip cost CST_SKIP is "5" and the refresh deficit count DCNT before the twenty-seventh time point t27 is "2", the host device 10 can decrease the refresh deficit count DCNT by "2", such that the refresh deficit count DCNT becomes "0" (i.e., 0 multiple of the skip cost CST_SKIP).

[0202] Meanwhile, the host device 10 can determine whether to skip issuing the regular refresh command REF_R based on the refresh deficit count DCNT. For example, the host device 10 can freely determine the timing of issuing the regular refresh command REF_R (e.g., for skipping or delaying), similar to the above-described with reference to Figure 4 That is, the host device 10 can maintain the refresh deficit count DCNT not to exceed a predetermined refresh deficit count range (e.g., within the predetermined refresh deficit count range) at the regular refresh time point at which the regular refresh period starts, by flexibly issuing the regular refresh command REF_R and the fine-grained refresh command REF_F. For a more detailed example, the host device 10 can skip issuing the regular refresh command REF_R at the twenty-eighth time point t28 and maintain the refresh deficit count DCNT.

[0203] In this way, the host device 10 can replace issuing the regular refresh command REF_R with issuing a plurality of fine-grained refresh commands REF_F. In this case, since the host device 10 can more flexibly perform refresh scheduling on the memory bank 140, the operation efficiency of the memory system MS can be improved. In addition, according to the embodiment of the disclosure, the time required for the host device 10 to perform the regular refresh operation can be minimized, such that the input / output performance of the memory bank 140 can be improved.

[0204] Figure 14 is a flowchart illustrating an operation method of a memory device in response to a regular refresh command. Referring to Figures 1 to 14At operation S110, the memory device 100 can receive a regular refresh command REF R. For example, the memory device 100 can receive the regular refresh command REF R for the memory bank 140 in the form of a command address signal CA.

[0205] At operation S120, the memory device 100 can identify a refresh target pointer value PT TG. For example, the refresh manager 121 can identify the refresh target pointer value PT TG that points to one of the plurality of row addresses RA included in the refresh target determination list LST for the memory bank 140.

[0206] At operation S130, the memory device 100 can identify a plurality of refresh target row addresses RA TG for the regular refresh command REF R based on the refresh target pointer value PT TG. For example, the refresh manager 121 can determine the plurality of refresh target row addresses RA TG in the manner described above with reference to Figure 10 At operation S130, the memory device 100 can identify a plurality of refresh target row addresses RA TG for the regular refresh command REF R based on the refresh target pointer value PT TG. For example, the refresh manager 121 can determine the plurality of refresh target row addresses RA TG in the manner described above with reference to Figure 12 At operation S130, the memory device 100 can identify a plurality of refresh target row addresses RA TG for the regular refresh command REF R based on the refresh target pointer value PT TG. For example, the refresh manager 121 can determine the plurality of refresh target row addresses RA TG in the manner described above with reference to

[0207] At operation S140, the memory device 100 can refresh the memory cell rows MCR corresponding to the plurality of refresh target row addresses RA TG. For example, the refresh manager 121 can refresh the memory cell rows MCR corresponding to the plurality of refresh target row addresses RA TG simultaneously or sequentially.

[0208] At operation S150, the memory device 100 can update the refresh target pointer value PT TG. For example, the refresh manager 121 can increase the refresh target pointer value PT TG by the total number of the plurality of refresh target row addresses RA TG determined in operation S130, similar to previously described with reference to Figure 10 At operation S150, the memory device 100 can update the refresh target pointer value PT TG. For example, the refresh manager 121 can increase the refresh target pointer value PT TG by the total number of the plurality of refresh target row addresses RA TG determined in operation S130, similar to previously described with reference to Figure 12 At operation S150, the memory device 100 can update the refresh target pointer value PT TG. For example, the refresh manager 121 can increase the refresh target pointer value PT TG by the total number of the plurality of refresh target row addresses RA TG determined in operation S130, similar to previously described with reference to

[0209] Figure 15 is a flowchart illustrating an operation method of a memory device in response to a fine-grained refresh command. Referring to Figures 1 to 15 At operation S210, the memory device 100 can receive a fine-grained refresh command REF F. At operation S220, the memory device 100 can identify a refresh target pointer value PT TG. Since operations S210 and S220 are similar to operations S110 and S120 described above with reference to Figure 14 At operation S210, the memory device 100 can receive a fine-grained refresh command REF F. At operation S220, the memory device 100 can identify a refresh target pointer value PT TG. Since operations S210 and S220 are similar to operations S110 and S120 described above with reference to

[0210] At operation S230, the memory device 100 can identify a pointing row address RA_PTD and a subsequent row address RA_SUBS corresponding to the refresh target pointer value PT_TG. For example, the refresh manager 121 can identify a row address RA pointed by the refresh target pointer value PT_TG as the pointing row address RA_PTD, and can identify a row address RA having a sequence next to the pointing row address RA_PTD within the refresh target determination list LST as the subsequent row address RA_SUBS.

[0211] At operation S240, the memory device 100 can determine whether the pointing row address RA_PTD or the subsequent row address RA_SUBS corresponds to an edge memory cell array. For example, the refresh manager 121 can determine a memory cell array type corresponding to each of the pointing row address RA_PTD and the subsequent row address RA_SUBS.

[0212] If it is determined that the pointing row address RA_PTD or the subsequent row address RA_SUBS corresponds to an edge memory cell array, operations S250 and S260 below can be performed. For example, if it is determined that at least one of the pointing row address RA_PTD and the subsequent row address RA_SUBS corresponds to an edge memory cell array type, the refresh manager 121 can perform operations S250 and S260 below.

[0213] If it is determined that the pointing row address RA_PTD and the subsequent row address RA_SUBS do not correspond to an edge memory cell array, operations S270 and S280 below can be performed. For example, if the pointing row address RA_PTD and the subsequent row address RA_SUBS are both determined to have an internal memory cell array type, the refresh manager 121 can perform operations S270 and S280 below.

[0214] At operation S250, the memory device 100 can refresh one or more memory cell rows MCRs corresponding to the pointing row address RA_PTD. For example, if the pointing row address RA_PTD corresponds to an edge memory cell array, the refresh manager 121 can refresh two memory cell rows MCRs. When the pointing row address RA_PTD corresponds to an internal memory cell array, the refresh manager 121 can refresh one memory cell row MCR.

[0215] At operation S260, the memory device 100 can increase the refresh target pointer value PT_TG by "1". For example, the refresh manager 121 can increase the refresh target pointer value PT_TG by "1".

[0216] At operation S270, the memory device 100 can refresh the two memory cell rows MCR respectively corresponding to the preceding row address RA PTD and the subsequent row address RA SUBS. For example, the refresh manager 121 can refresh one memory cell row MCR corresponding to the preceding row address RA PTD and one memory cell row MCR corresponding to the subsequent row address RA SUBS simultaneously.

[0217] At operation S280, the memory device 100 can increase the refresh target pointer value PT T by "2". For example, the refresh manager 121 can increase the refresh target pointer value PT T by "2".

[0218] Figure 16 and Figure 17 is a timing chart illustrating an operation of a memory system according to an embodiment. Figure 16 and Figure 17 The horizontal axis of

[0219] First, referring to Figures 1 to 16 When the memory device 100 is in an idle state, the host device 10 can refresh data stored in the memory bank 140 by issuing a regular refresh command REF R. For example, the host device 10 can issue the regular refresh command REF R at a thirtieth time point t30.

[0220] The memory device 100 can perform a regular refresh operation during a regular refresh consumption time tRFC R in response to the regular refresh command REF R. For example, the memory device 100 can perform the regular refresh operation between the thirtieth time point t30 and a thirty-first time point t31.

[0221] Meanwhile, the host device 10 can need to access the memory bank 140 between the thirtieth time point t30 and the thirty-first time point t31. However, during the regular refresh consumption time tRFC R, the host device 10 cannot issue an activate command ACT for the memory bank 140. For example, even though the need for the access of the memory bank 140 by the host device 10 occurs at a time point t32 between the thirtieth time point t30 and the thirty-first time point t31, the issuance of the activate command ACT for the memory bank 140 by the host device 10 can be prohibited until the thirty-first time point t31.

[0222] A time interval between the thirty-second time point t32 and the thirty-first time point t31 can be referred to as a first activate latency time tAL1. That is, the first activate latency time tAL1 for the access of the memory bank 140 by the host device 10 can occur due to the regular refresh operation.

[0223] On the other hand, further referring toFigure 17 When the memory device 100 is in the idle state, the host device 10 can sequentially refresh data stored in the memory bank 140 by issuing a plurality of fine-grained refresh commands REF F. That is, instead of issuing the regular refresh command REF R at the thirtieth time point t30, the host device 10 can sequentially issue a plurality of fine-grained refresh commands REF F. For example, the host device 10 can schedule to issue the fine-grained refresh command REF F whenever the fine-grained refresh consumption time tRFC F elapses from the thirtieth time point t30. For a more detailed example, the host device 10 can schedule to issue the fine-grained refresh command REF F at each of a thirty-third time point t33, a thirty-fourth time point t34, and a thirty-fifth time point t35.

[0224] Meanwhile, similar to the above explanation with reference to Figure 16 The need for the host device 10 to access the memory bank 140 can occur at the thirty-second time point t32. However, the host device 10 can be prohibited from issuing the activate command ACT until the fine-grained refresh operation is completed between the thirty-fourth time point t34 and the thirty-fifth time point t35. That is, the host device 10 can have to wait for the issuance of the activate command ACT until the fine-grained refresh consumption time tRFC F elapses from the thirty-fourth time point t34. In this case, at the thirty-fifth time point t35, the host device 10 can issue the activate command ACT instead of the fine-grained refresh command REF F.

[0225] The time interval between the thirty-second time point t32 and the thirty-fifth time point t35 can be referred to as a second activate latency time tAL2. That is, due to the fine-grained refresh operation, the second activate latency time tAL2 can occur for the host device 10 to access the memory bank 140.

[0226] The second activate latency time tAL2 can be shorter than the first activate latency time tAL1. That is, when the host device 10 controls the refresh operation on the memory bank 140 based on a plurality of fine-grained refresh commands REF F, the time for which the host device 10 should wait to issue the activate command ACT can be reduced compared to when the host device 10 controls the refresh operation on the memory bank 140 based on the regular refresh command REF R.

[0227] Figure 18 is a timing diagram illustrating an operation of a memory system according to an embodiment. Referring to Figures 1 to 18 At a fortieth time point t40, the host device 10 can issue a precharge command PREC for the memory bank 140. In this case, the memory bank 140 can enter the idle state.

[0228] The host device 10 can need to access the memory bank 140 at a forty-first point in time t41. At a forty-second point in time t42 between the fortieth point in time t40 and the forty-first point in time t41, the host device 10 can attempt to perform a refresh operation on the memory bank 140.

[0229] The interval between the forty-second point in time t42 and the forty-first point in time t41 can be shorter than the regular refresh consumption time tRFC R. For example, a forty-third point in time t43 after the elapse of the regular refresh consumption time tRFC R from the forty-second point in time t42 can be a point in time after the forty-first point in time t41. In this case, in order for the host device 10 to issue the activate command ACT at the forty-first point in time t41, the host device 10 should not issue the regular refresh command REF R at the forty-second point in time t42.

[0230] On the other hand, the interval between the forty-second point in time t42 and the forty-first point in time t41 can be longer than the fine-grained refresh consumption time tRFC F. In this case, even if the host device 10 issues the fine-grained refresh command REF F at the forty-second point in time t42, the host device 10 can be able to issue the activate command ACT at the forty-first point in time t41.

[0231] That is, according to the embodiment of the present disclosure, even when the time margin is not sufficient to guarantee to issue the regular refresh command REF R, the host device 10 can issue the fine-grained refresh command REF F. In this case, the length of time during which the memory bank 140 remains in the idle state can be minimized, and the operation efficiency of the memory system MS can be maximized.

[0232] Figure 19 is a graph showing the effect of the fine-grained refresh according to the embodiment of the present disclosure. Referring to Figures 1 to 19 , Figure 19 The horizontal axis of can represent the data transfer rate between the memory device 100 and the host device 10. Figure 19 The vertical axis of can represent the data bus efficiency. For example, Figure 19 The vertical axis of can represent the ratio of the time during which the data bus transfers data to the total operation time of the memory device 100.

[0233] The data bus efficiency when the host device 10 controls the refresh operation of the memory device 100 based on only the regular refresh command REF R is shown by a dotted line. The data bus efficiency when the host device 10 controls the refresh operation of the memory device 100 based on the regular refresh command REF R and the fine-grained refresh command REF F is shown by a solid line.

[0234] The host device 10 can refresh the memory bank 140 by issuing the regular refresh command REF R at every regular refresh period. In this case, for every regular refresh period, the host device 10 can not be able to access the memory device 100 for the regular refresh consumption time tRFC R.

[0235] The host device 10 can refresh the memory bank 140 by flexibly issuing the regular refresh command REF R and the fine-grained refresh command REF F. For example, the host device 10 can issue the regular refresh command REF R at every regular refresh period, or can issue a plurality of fine-grained refresh commands REF F instead of the regular refresh command REF R.

[0236] Accordingly, according to the embodiment of the disclosure, it is possible to minimize the phenomenon that the communication between the host device 10 and the memory device 100 is limited due to the regular refresh consumption time tRFC R. Accordingly, referring to both the graph indicated by the dotted line and the graph indicated by the solid line, it is possible to improve the data bus efficiency when the host device 10 controls the refresh operation of the memory device 100 based on the regular refresh command REF R and the fine-grained refresh command REF F.

[0237] Figure 20 is a flowchart illustrating a regular refresh scheduling of a host device according to an embodiment. Referring to Figures 1 to 20 At operation S310, the host device 10 can identify that the length of time corresponding to the regular refresh interval tREFI has elapsed. For example, the refresh scheduling circuit 14 can identify that a new regular refresh period has started based on the timer circuit 13.

[0238] At operation S320, the host device 10 can increase the refresh deficit count DCNT by the skip cost CST_SKIP. For example, the refresh deficit counter 12 can increase the refresh deficit count DCNT by the skip cost CST_SKIP.

[0239] At operation S330, the host device 10 can determine whether to issue the regular refresh command REF R based on the refresh deficit count DCNT. For example, the refresh scheduling circuit 14 can determine whether to issue the regular refresh command REF R as long as the refresh deficit count DCNT at the start of the next regular refresh period does not exceed the predetermined refresh deficit count range.

[0240] At operation S340, the host device 10 can determine whether it has decided to issue the regular refresh command REF R. If the host device 10 has decided to issue the regular refresh command REF R, operation S350 below can be performed. If the host device 10 has decided not to issue the regular refresh command REF R, operation S360 below can be performed.

[0241] At operation S350, the host device 10 can issue a regular refresh command REF R and decrease the refresh deficit count DCNT based on the skip cost CST SKIP. For example, if the memory system MS is implemented in the manner described above with reference to Figure 10 and Figure 11 implemented, the refresh deficit counter 12 can decrease the refresh deficit count DCNT by the skip cost CST SKIP. When the memory system MS is implemented in the manner described above with reference to Figure 12 and Figure 13 implemented, the refresh deficit counter 12 can decrease the refresh deficit count DCNT by the skip cost CST SKIP by "1" so that the refresh deficit count DCNT becomes an integer multiple of the skip cost CST SKIP.

[0242] At operation S360, the host device 10 can skip or postpone issuing the regular refresh command REF R and maintain the refresh deficit count DCNT. For example, if the regular refresh command REF R is not issued, the refresh deficit counter 12 can not change the refresh deficit count DCNT.

[0243] Figure 21 is a diagram illustrating fine-grained refresh scheduling of a host device according to an embodiment. Referring to Figures 1 to 21 At operation S410, the host device 10 can determine whether it is appropriate to issue a fine-grained refresh command REF F. For example, the refresh scheduling circuit 14 can determine whether it is appropriate to issue the fine-grained refresh command REF F based on various factors such as whether the memory bank 140 is being pre-charged, whether another command is scheduled to be issued for the memory bank 140 during a fine-grained refresh consumption time tRFC F from a time point at which operation S410 is executed, a size of the refresh deficit count DCNT, etc. However, the scope of the present disclosure is not limited thereto, and the host device 10 can manage a command queue that temporarily stores commands CMD to be issued to the memory device 100. In this case, the host device 10 can determine whether it is appropriate to issue the fine-grained refresh command REF F based on whether a command CMD for the memory bank 140 is queued in the command queue.

[0244] If it is determined that it is appropriate to issue the fine-grained refresh command REF F in operation S410, the host device 10 can perform operation S420 below. If it is determined that it is not appropriate to issue the fine-grained refresh command REF F in operation S410, the host device 10 can repeat operation S410. In this way, the host device 10 can wait for an appropriate time point to issue the fine-grained refresh command REF F and then perform operation S420 below.

[0245] At operation S420, the host device 10 can issue the fine-grained refresh command REF F. For example, the refresh scheduling circuit 14 can control the command issue circuit 11 to issue the fine-grained refresh command REF F for the memory bank 140.

[0246] At operation S430, the host device 10 can decrease the refresh deficit count DCNT by "1". For example, the refresh deficit counter 12 can decrease the refresh deficit count DCNT by "1".

[0247] In an embodiment, the host device 10 can repeat the operation S410 described above after performing the operation S430. That is, the host device 10 can repeat the issuance of the fine-grained refresh command REF F whenever it is appropriate to issue the fine-grained refresh command REF F. In this case, the probability that the host device 10 skips the issuance of the regular refresh command REF R in the operation S340 described above with reference to FIG. 3 can increase. Accordingly, according to the embodiment of the disclosure, the input / output performance degradation of the memory bank 140 due to the time tRFC R consumed by the regular refresh can be minimized. Figure 20

[0248] Figure 22 is a diagram illustrating an operation of a memory system according to an embodiment. Referring to Figures 1 to 9 and Figures 12 to 22 , the refresh target determination list LST can be implemented as the following refresh target determination list LSTc.

[0249] The refresh target determination list LSTc can include a plurality of row addresses RA. For example, the refresh target determination list LSTc can include first to eighth row addresses RAa to RAh.

[0250] Similar to the description above with reference to Figure 12 , the refresh target determination list LSTc can include a plurality of row address groups RAG. Each of the plurality of row address groups RAG can include a plurality of row addresses RA. For example, the third row address group RAGc can include the first to eighth row addresses RAa to RAh. In this case, the first row address RAa can be referred to as a group head row address of the third row address group RAGc. For brevity, Figure 22 only one row address group RAG is illustrated in

[0251] The refresh manager 121 can determine the refresh target row address RA TG of the regular refresh command REF R in a similar manner as described above with reference to Figure 12

[0252] ​​The refresh target determination list LSTc can be implemented such that the refresh manager 121 always performs a refresh operation on two memory cell rows in response to the fine-grained refresh command REF F. In other words, the refresh target determination list LSTc can be implemented to prevent a case in which the refresh manager 121 performs a refresh operation on only one memory cell row MCR in response to the fine-grained refresh command REF F (for example, when the pointing row address RA PTD corresponds to the inner memory cell array and the subsequent row address RA SUBS corresponds to the edge memory cell array).

[0253] More specifically, among the row addresses RA included in each row address group RAG in the refresh target determination list LSTc, there can be an even number of edge row addresses (for example, a multiple of 0 or 2); these edge row addresses can have consecutive orders to each other in the refresh target determination list LSTc; and the edge row address having the highest order among the edge row addresses in each row address group RAG can have an odd order in the row address group RAG. For example, among the first to eighth row addresses RAa to Rah included in the third row address group RAGc, the number of row addresses RA corresponding to the edge memory cell array can be even (for example, the fifth row address RAe and the sixth row address RAf, thus “2”); the fifth row address RAe and the sixth row address RAf can have consecutive orders within the refresh target determination list LSTc; and the fifth row address RAe (which has the highest order among the fifth row address RAe and the sixth row address RAf) can have an odd order within the row address group RAG (for example, fifth).

[0254] Accordingly, when the fine-grained refresh command REF F is received, either both the pointing row address RA PTD and the subsequent row address RA SUBS can correspond to the inner memory cell array, or the pointing row address RA PTD can correspond to the edge memory cell array. In other words, a case in which the pointing row address RA PTD corresponds to the inner memory cell array and only the subsequent row address RA SUBS corresponds to the edge memory cell array can be prevented. In this case, in response to the fine-grained refresh command REF F, the refresh manager 121 can perform a refresh operation on two row addresses corresponding to the inner memory cell array, or perform a refresh operation on one row address corresponding to the edge memory cell array.

[0255] For a more detailed example, when the first fine-grained refresh command REF_Fa is received, both the row address RA_PTD and the subsequent row address RA_SUBS can correspond to the internal memory cell array. In this case, the refresh manager 121 can perform refresh operations on the first row address RAa and the second row address RAb. Similarly, when the second fine-grained refresh command REF_Fb is received, the refresh manager 121 can perform refresh operations on the third row address RAc and the fourth row address RAd.

[0256] When the third fine-grained refresh command REF_Fc is received, both the row address RA_PTD (i.e., the fifth row address RAe) and the subsequent row address RA_SUBS (i.e., the sixth row address RAf) can correspond to the edge memory cell array. In this case, the refresh manager 121 can perform refresh operations on the two memory cell rows MCR corresponding to the fifth row address RAe.

[0257] When the fourth fine-grained refresh command REF_Fd is received, the row address RA_PTD (i.e., the sixth row address RAf) can correspond to the edge memory cell array, and the subsequent row address RA_SUBS (i.e., the seventh row address RAg) can correspond to the internal memory cell array. In this case, the refresh manager 121 can perform refresh operations on the two memory cell rows MCR corresponding to the sixth row address RAf.

[0258] Thereafter, when the fifth fine-grained refresh command REF_Fe is received, both the row address RA_PTD and the subsequent row address RA_SUBS can correspond to the internal memory cell array. In this case, the refresh manager 121 can perform refresh operations on the seventh row address RAg and the eighth row address RAh.

[0259] That is, according to the embodiment of Figure 22 , a constant number of memory cell rows MCR (e.g., two) can always be refreshed in response to a fine-grained refresh command REF_F. In this case, the number of fine-grained refresh commands REF_F that need to be issued to refresh a certain number of memory cell rows MCR can be minimized.

[0260] In an embodiment, among the row addresses RA included in one row address group RAG, the number of row addresses RA corresponding to the edge memory cell array can be 0 or 2. In this case, the number of memory cell rows MCR corresponding to each row address group RAG can be more uniform. For example, compared to a case where the number of row addresses RA corresponding to the edge memory cell array among the row addresses RA included in each row address group RAG is implemented as an arbitrary number such as 0, 2, 4, or 8, the deviation of the memory cell rows MCR corresponding to each row address group RAG can be smaller when the number of row addresses RA corresponding to the edge memory cell array among the row addresses RA included in each row address group RAG is implemented as only 0 or 2. Accordingly, according to the embodiment of the disclosure, the time and power required to perform a regular refresh operation on the memory bank 140 in response to a plurality of regular refresh commands REF_R can be relatively uniform.

[0261] In an embodiment, the refresh target determination list LST described with reference to Figures 1 to 9 and Figures 12 to 21 may be implemented in a manner described with reference to Figure 22 In this case, both the pointing row address RA_PTD and the subsequent row address RA_SUBS can correspond to the internal memory cell array, or at least the pointing row address RA_PTD can correspond to the edge memory cell array, when the fine-grained refresh command REF_F is received. Accordingly, the memory device 100 can determine whether to perform a refresh operation on one row address RA or two row addresses RA in response to the fine-grained refresh command REF_F by considering only the pointing row address RA_PTD (i.e., not considering the subsequent row address RA_SUBS).

[0262] Figure 23 is a flowchart illustrating an operation method of a memory device in response to a fine-grained refresh command when the refresh target determination list is implemented in a manner described with reference to Figure 22 . Referring to Figures 1 to 9 and Figures 12 to 23 , the refresh target determination list LST can be implemented as the refresh target determination list LSTc.

[0263] At operation S510, the memory device 100 can receive a fine-grained refresh command REF_F. At operation S520, the memory device 100 can identify a refresh target pointer value PT_TG. Since operations S510 and S520 are similar to operations S210 and S220 described above with reference to Figure 15 , a detailed description is omitted.

[0264] At operation S530, the memory device 100 can identify a pointing row address RA_PTD corresponding to the refresh target pointer value PT_TG. For example, the refresh manager 121 can identify the row address RA pointed by the refresh target pointer value PT_TG as the pointing row address RA_PTD.

[0265] At operation S540, the memory device 100 can determine whether the pointing row address RA_PTD corresponds to an edge memory cell array. For example, the refresh manager 121 can determine a memory cell array type corresponding to the pointing row address RA_PTD.

[0266] That is, unlike operations S230 and S240, the refresh manager 121 can determine only the memory cell array type of the pointing row address RA_PTD. In other words, even if the refresh manager 121 does not determine the memory cell array type of the subsequent row address RA_SUBS, the refresh manager 121 can be able to successfully determine whether the pointing row address RA_PTD or the subsequent row address RA_SUBS corresponds to an edge memory cell array, similar to that described above with reference to operations S230 and S240. In this case, the operational load of the refresh manager 121 can be reduced.

[0267] If it is determined that the pointing row address RA_PTD corresponds to an edge memory cell array, operations S550 and S560 below can be performed. If it is determined that the pointing row address RA_PTD corresponds to an internal memory cell array, operations S570 and S580 below can be performed.

[0268] At operation S550, the memory device 100 can refresh two memory cell rows MCR corresponding to the pointing row address RA_PTD. At operation S560, the memory device 100 can increase the refresh target pointer value PT_TG by "1".

[0269] At operation S570, the memory device 100 can refresh two memory cell rows MCR corresponding to the pointing row address RA_PTD and the subsequent row address RA_SUBS, respectively. At operation S580, the memory device 100 can increase the refresh target pointer value PT_TG by "2".

[0270] Figure 24 is a block diagram illustrating a memory system according to an embodiment. Referring to Figures 1 to 24 , the memory system MS can include a host device 20 and a memory device 200. The host device 20 can include a command issuing circuit 21 and a refresh scheduling circuit 24. The memory device 200 can include a refresh manager 221 and a memory bank 240.

[0271] The command issue circuit 21 can issue a regular refresh command REF_R and a fine-grained refresh command REF_F.

[0272] The refresh manager 221 can manage the refresh target determination list LST, the refresh target pointer value PT_TG, and the refresh credit count CRDT. The refresh target determination list LST and the refresh target pointer value PT_TG are used in a manner similar to that described above with reference to Figures 1 to 23 The detailed description is thus omitted.

[0273] The refresh credit count CRDT can indicate the degree to which refresh operations have been performed in advance on the memory bank 240. For example, the refresh manager 221 can decrease the refresh credit count CRDT at each regular refresh period, and can increase the refresh credit count CRDT each time a regular refresh command REF_R or a fine-grained refresh command REF_F is received from the host device 10.

[0274] The refresh scheduling circuit 24 can control the command issue circuit 21 to issue a credit count read command RD_CRDT. That is, the command issue circuit 21 can issue the credit count read command RD_CRDT in response to control by the refresh scheduling circuit 24. The refresh manager 221 can provide the refresh credit count CRDT to the host device 20 in response to the credit count read command RD_CRDT.

[0275] In an embodiment, the command issue circuit 21 can issue the credit count read command RD_CRDT periodically in response to control by the refresh scheduling circuit 24. For example, the command issue circuit 21 can issue the credit count read command RD_CRDT at each regular refresh interval tREFI, or each time a length of time corresponds to a product of a refresh fluctuation threshold and the regular refresh interval tREFI. However, the scope of the present disclosure is not limited thereto. For example, the command issue circuit 21 can issue the credit count read command RD_CRDT irregularly in response to control by the refresh scheduling circuit 24.

[0276] In an embodiment, the refresh manager 221 can store the refresh credit count CRDT in a mode register of the memory device 200. In this case, the credit count read command RD_CRDT can have the form of a mode register read (MRR) command. However, the scope of the present disclosure is not limited thereto.

[0277] The refresh scheduling circuit 24 can control the operation of the command issue circuit 21 based on the refresh credit count CRDT. For example, the refresh scheduling circuit 24 can determine when the command issue circuit 21 issues the regular refresh command REF_R and the fine-grained refresh command REF_F based on the refresh credit count CRDT.

[0278] That is, according to Figure 24 the embodiment of the present disclosure, unlike the above-described Figures 1 to 23 , the memory device 200 can manage the extent to which the refresh operation has been performed on the memory bank 240 instead of the host device 20. In this case, the operation load of the host device 20 can be reduced because the host device 20 can not manage the refresh undercount count DCNT. However, the scope of the present disclosure is not limited thereto, and the host device 20 can also manage the refresh undercount count DCNT similarly to the above-described Figures 1 to 23 , and the memory device 200 can manage the refresh credit count CRDT. In this case, the refresh scheduling circuit 24 will be able to perform refresh scheduling more efficiently.

[0279] For a more concise explanation, Figure 24 an embodiment in which the host device 20 reads the refresh credit count CRDT from the memory device 200 is shown, but the scope of the present disclosure is not limited thereto. For example, instead of directly reading the refresh credit count CRDT from the memory device 200, the host device 20 can be implemented to read various types of data generated based on the refresh credit count CRDT, or can be implemented to read the refresh target pointer value PT_TG from the memory device 200. That is, the scope of the present disclosure is not limited to the format of the specific data used by the host device 20 for refresh scheduling.

[0280] In addition, for a more concise explanation, Figure 24 an embodiment in which the host device 20 issues the credit count read command RD_CRDT is described, but the scope of the present disclosure is not limited thereto. For example, instead of issuing the command CMD, the host device 20 can be implemented to read the refresh credit count CRDT from the memory device 200 through various paths such as a sideband channel.

[0281] Figure 25 is a timing diagram showing how the memory device 200 manages the refresh credit count. Figure 24 The horizontal axis of Figure 25 may represent time, and the vertical axis can represent the value of the refresh credit count CRDT or the number of memory cell rows MCR refreshed per unit time.

[0282] Referring to Figures 1 to 25 , the memory device 200 can sequentially receive a plurality of regular refresh commands REF_R and a plurality of fine-grained refresh commands REF_F from the host device 20.

[0283] A regular refresh cycle of the memory bank 240 can occur at a fiftieth time point t50, a fifty-first time point t51, and a fifty-second time point t52. For example, the regular refresh cycle of the memory bank 240 can start at the fiftieth time point t50, the fifty-first time point t51, and the fifty-second time point t52. For a more concise explanation, hereinafter, it is assumed that the refresh credit count CRDT of the memory bank 240 is "0" before the fiftieth time point t50.

[0284] The refresh manager 221 can decrease the refresh credit count CRDT by the skip cost CST_SKIP at each regular refresh cycle. For example, the host device 20 can decrease the refresh credit count CRDT by the skip cost CST_SKIP at each of the fiftieth time point t50, the fifty-first time point t51, and the fifty-second time point t52.

[0285] The refresh manager 221 can increase the refresh credit count CRDT by the skip cost CST_SKIP each time the regular refresh command REF R is received. For example, the refresh manager 221 can receive the regular refresh command REF R at a fifty-third time point t53. In this case, the refresh manager 221 can increase the refresh credit count CRDT to "0".

[0286] The refresh manager 221 can sequentially receive a plurality of fine-grained refresh commands REF F between the fiftieth time point t50 and the fifty-first time point t51. For example, the refresh manager 221 can receive the fine-grained refresh command REF F at each of the fifty-fourth to fifty-sixth time points t54 to t56.

[0287] The refresh manager 221 can increase the refresh credit count CRDT by "1" each time the fine-grained refresh command REF F is received. For example, the refresh manager 221 can increase the refresh credit count CRDT by "1" at each of the fifty-fourth to fifty-sixth time points t54 to t56.

[0288] The refresh manager 221 can receive the regular refresh command REF R at a fifty-seventh time point t57. In this case, the refresh manager 221 can increase the refresh credit count CRDT by the skip cost CST_SKIP. However, the scope of the present disclosure is not limited thereto, and the size of how much the refresh manager 221 increases the refresh credit count CRDT in response to the regular refresh command REF R can vary depending on the operation of the refresh manager 221 determining the list LST based on the refresh target. For example, if the memory device 200 is implemented to respond to the regular refresh command REF R to perform the above-described operation with reference to FIG. 6 in the case where the refresh credit count CRDT is "0" at the fiftieth time point t50, the refresh manager 221 can increase the refresh credit count CRDT by "1" in response to the regular refresh command REF R at the fifty-seventh time point t57. Figure 10The described manner determines the refresh target row address RA_TG, and then the refresh manager 221 can increase the refresh credit count CRDT by the skip cost CST_SKIP. If the memory device 200 is implemented to respond to the regular refresh command REF_R with the above reference Figure 12 The described manner determines the refresh target row address RA_TG, and then the refresh manager 221 can increase the refresh credit count CRDT by the skip cost CST_SKIP. If the memory device 200 is implemented to respond to the regular refresh command REF_R with the above reference

[0289] Meanwhile, the host device 20 can determine whether to skip issuing the regular refresh command REF_R based on the refresh credit count CRDT. For example, the host device 20 can freely determine the timing of issuing the regular refresh command REF_R (e.g., by skipping or delaying), similar to the above reference Figure 4 described above. For a more detailed example, the host device 20 can skip issuing the regular refresh command REF_R at the fifty-eighth time point t58. In this case, the refresh manager 221 can maintain the refresh credit count CRDT.

[0290] Figure 26 is a block diagram illustrating a memory system according to an embodiment. Referring to Figures 1 to 23 and Figure 26 , the memory system MS can include a host device 30 and a memory device 300.

[0291] The memory device 300 can include a plurality of memory banks BNK. For example, the memory device 300 can include first to fourth memory banks BNKa to BNKd. However, the scope of the present disclosure is not limited to the number of memory banks BNKs included in the memory device 300.

[0292] In an embodiment, one of the plurality of memory banks BNK can correspond to the memory bank 140 described above with reference to Figures 1 to 23 .

[0293] The memory device 300 can include a control logic circuit 320. The control logic circuit 320 can include a refresh manager 321. The refresh manager 321 can determine a refresh order of memory cells included in each of the plurality of memory banks BNK.

[0294] The host device 30 can include a command issuing circuit 31, a refresh deficit counter 32, a timer circuit 33, and a refresh scheduling circuit 34. The functions of the command issuing circuit 31, the timer circuit 33, and the refresh scheduling circuit 34 are similar to those of the above reference Figures 1 to 23The functions of the command issuance circuit 11, the timer circuit 13, and the refresh scheduling circuit 14 described are thus omitted from detailed description.

[0295] The refresh deficit counter 32 can manage a plurality of refresh deficit counts DCNT corresponding to the plurality of memory banks BNK, respectively. For example, the refresh deficit counter 32 can manage first to fourth refresh deficit counts DCNT1 to DCNT4 corresponding to the first to fourth memory banks BNKa to BNKd, respectively.

[0296] For a more detailed example, the refresh deficit counter 32 can increase the first to fourth refresh deficit counts DCNT1 to DCNT4 at each regular refresh period. The refresh deficit counter 32 can decrease the refresh deficit count DCNT corresponding to the memory bank BNK corresponding to the regular refresh command REF_R and the fine-grained refresh command REF_F issued by the command issuance circuit 31. For example, when the command issuance circuit 31 issues the regular refresh command REF_R or the fine-grained refresh command REF_F for the first memory bank BNKa, the refresh deficit counter 32 can decrease the first refresh deficit count DCNT1. On the other hand, when the command issuance circuit 31 issues the regular refresh command REF_R or the fine-grained refresh command REF_F for the second memory bank BNKb, the refresh deficit counter 32 can decrease the second refresh deficit count DCNT2.

[0297] The refresh scheduling circuit 34 can control the operation of the command issuance circuit 31 based on the plurality of refresh deficit counts DCNT. For example, the refresh scheduling circuit 34 can determine the issuance schedule of the command issuance circuit 31 with respect to the regular refresh command REF_R and the fine-grained refresh command REF_F for each memory bank BNK based on the plurality of refresh deficit counts DCNT.

[0298] Figure 27 is a timing chart illustrating the operation of the memory system according to the embodiment of Figure 26 Figure 27 The horizontal axis of the timing chart of FIG. 10 can represent time.

[0299] Referring to Figures 1 to 23 and Figures 26 to 27 At the sixtieth time point t60, the host device 30 can issue the fine-grained refresh command REF_F for the first memory bank BNKa. In this case, the memory device 300 can perform the fine-grained refresh operation on the first memory bank BNKa between the sixtieth time point t60 and the sixty-first time point t61. The time interval between the sixtieth time point t60 and the sixty-first time point t61 can be the fine-grained refresh consumption time tRFC_F.

[0300] ​After the sixtieth time point t60, the control of the memory banks other than the first memory bank BNKa by the host device 30 can be prohibited for a certain length of time. For example, after the sixtieth time point t60, the host device 30 can be prohibited from issuing the fine-grained refresh command REF_F and the activate command ACT to the other memory banks for "other bank control delay after fine-grained refresh tDBCD_F". For a more detailed example, the host device 30 issuing the fine-grained refresh command REF_F and the activate command ACT to the second memory bank BNKb can be prohibited from the sixtieth time point t60 to the sixty-second time point t62 after "other bank control delay after fine-grained refresh tDBCD_F" has elapsed.

[0301] In an embodiment, "other bank control delay after fine-grained refresh tDBCD_F" can have the same length as "activate-to-activate delay of other banks tRRD". However, the scope of the present disclosure is not limited thereto, and "other bank control delay after fine-grained refresh tDBCD_F" can have a length similar to "activate-to-activate delay of other banks tRRD".

[0302] In an embodiment, "activate-to-activate delay of other banks tRRD" can refer to the minimum time interval required when the host device 30 issues an activate command CMD for a certain memory bank and then issues an activate command CMD for another memory bank.

[0303] The host device 30 can issue the fine-grained refresh command REF_F or the activate command ACT to the second memory bank BNKb after the sixty-second time point t62. For example, the host device 30 can issue the fine-grained refresh command REF_F or the activate command ACT for the second memory bank BNKb at the sixty-third time point t63. In this case, the memory device 300 can perform the fine-grained refresh operation or the activate operation on the second memory bank BNKb between the sixty-third time point t63 and the sixty-fourth time point t64. In this case, the time interval between the sixty-third time point t63 and the sixty-fourth time point t64 can be the fine-grained refresh consumption time tRFC_F or the same bank activate minimum interval tRC described above.

[0304] In an embodiment, the time interval between the sixtieth time point t60 and the sixty-third time point t63 can be equal to or longer than "activate-to-activate delay of other banks tRRD".

[0305] In an embodiment, the time interval between the sixtieth time point t60 and the sixty-third time point t63 can be shorter than the fine granularity refresh consumption time tRFC_F. For example, the host device 30 can issue a fine granularity refresh command REF_F for a specific memory bank BNK, and then the host device 30 can issue a fine granularity refresh command REF_F or an activate command ACT for another memory bank BNK before completing the refresh operation for the memory bank BNK.

[0306] In an embodiment, the time interval between the sixtieth time point t60 and the sixty-third time point t63 can be shorter than "regular refresh - regular refresh delay of other banks (e.g., which can be referred to as "tpbR2pbR"). That is, when the host device 30 is implemented to issue a fine granularity refresh command REF_F according to an embodiment of the present disclosure, it is possible to prevent the phenomenon that the host device 30 is delayed in issuing a regular refresh command REF_R for a specific memory bank, which occurs in order for the host device 30 to issue a regular refresh command REF_R for other memory banks. Accordingly, according to an embodiment of the present disclosure, it is possible to improve the operation efficiency of the memory system MS.

[0307] The above description is a detailed embodiment for practicing the present disclosure. However, the scope of the present disclosure is not limited thereto, and should be determined based on the appended claims and their equivalents.

[0308] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0095546, filed on July 19, 2024, Korean Patent Application No. 10-2024-0128572, filed on September 23, 2024, Korean Patent Application No. 10-2024-0149507, filed on October 29, 2024, Korean Patent Application No. 10-2025-0026207, filed on February 27, 2025, and Korean Patent Application No. 10-2025-0081281, filed on June 19, 2025, the entire contents of which are incorporated herein by reference.

Claims

1. A method of operation of a memory device including a memory bank, the memory bank including a plurality of edge memory cell arrays and a plurality of internal memory cell arrays arranged between the plurality of edge memory cell arrays, the method of operation comprising: receiving a fine-grained refresh command; identifying a refresh target pointer value for a refresh target determination list, the refresh target determination list including a plurality of row addresses of the memory bank; identifying, among the plurality of row addresses, a pointed row address corresponding to the refresh target pointer value; determining a first memory cell array type corresponding to the pointed row address; and performing a first refresh operation for a refresh target number of fine-grained refresh target row addresses, wherein the refresh target number is determined based on the first memory cell array type.

2. The method of operation of claim 1, wherein: the first refresh operation is performed simultaneously for as many memory cell rows as a maximum number of word lines activated simultaneously for an activate command. when the first memory cell array type is an edge memory cell array type corresponding to the plurality of edge memory cell arrays, the performing includes:

3. The operating method of claim 1, wherein, determining the pointed row address as a first fine-grained refresh target row address; and refreshing simultaneously a first memory cell row and a second memory cell row corresponding to the first fine-grained refresh target row address. when the first memory cell array type is an internal memory cell array type corresponding to the plurality of internal memory cell arrays, the performing includes:

4. The operating method of claim 1, wherein, determining the pointed row address as a second fine-grained refresh target row address; determining a subsequent row address of the pointed row address as a third fine-grained refresh target row address; and refreshing simultaneously a third memory cell row corresponding to the second fine-grained refresh target row address and a fourth memory cell row corresponding to the third fine-grained refresh target row address.

5. The method of operation of claim 1, further comprising: generating an updated refresh target pointer value by updating the refresh target pointer value based on the first memory cell array type.

6. The method of operation of claim 5, wherein the generating includes: when the first memory cell array type is an edge memory cell array type corresponding to the plurality of edge memory cell arrays, increasing the refresh target pointer value by a first value; and when the first memory cell array type is an internal memory cell array type corresponding to the plurality of internal memory cell arrays, increasing the refresh target pointer value by a second value greater than the first value.

7. The method of operation of claim 5, further comprising: receiving a regular refresh command; identifying the updated refresh target pointer value; and determining a plurality of regular refresh target row addresses based on the updated refresh target pointer value and the refresh target determination list; and performing a second refresh operation on the plurality of regular refresh target row addresses.

8. The method of operation of claim 7, wherein: a first refresh consumption time of the first refresh operation is shorter than a second refresh consumption time of the second refresh operation.

9. The method of operation of claim 1, further comprising: ​ ​ ​ ​ identifying a subsequent row address pointed to by the pointed-to row address; and determining a second memory cell array type corresponding to the subsequent row address, wherein the number of refresh targets is determined further based on the second memory cell array type.

10. A memory device in communication with an external device, the memory device comprising: a memory bank; a row decoder connected to the memory bank; and control logic circuitry configured to manage a refresh target pointer value and a refresh target determination list comprising a plurality of row addresses, wherein the control logic circuitry is configured to: determine, based on the refresh target pointer value and the refresh target determination list, a plurality of regular refresh target row addresses corresponding to a regular refresh command provided from the external device; and determine, based on the refresh target pointer value and the refresh target determination list, one or more fine-grained refresh target row addresses corresponding to a fine-grained refresh command provided from the external device, wherein a number of the plurality of regular refresh target row addresses is greater than a number of the one or more fine-grained refresh target row addresses.

11. The memory device of claim 10, wherein the control logic circuitry is configured to: increment the refresh target pointer value each time the regular refresh command is received and each time the fine-grained refresh command is received.

12. The memory device of claim 11, wherein: the refresh target determination list comprises a plurality of groups of row addresses, each of the plurality of groups of row addresses comprises a different subset of the plurality of row addresses, the control logic circuitry is configured to determine, as the plurality of regular refresh target row addresses, row addresses included in a group of row addresses corresponding to the refresh target pointer value, the group of row addresses being one of the plurality of groups of row addresses.

13. The memory device of claim 12, wherein: the memory bank comprises a plurality of edge memory cell arrays and a plurality of internal memory cell arrays arranged between the plurality of edge memory cell arrays, each of the plurality of groups of row addresses comprises an even number of edge row addresses corresponding to the plurality of edge memory cell arrays, and the edge row addresses included in a same group of row addresses have a consecutive order within the refresh target determination list. each of the edge row addresses having a highest order within each group of row addresses among the edge row addresses included in the plurality of groups of row addresses has:

14. The memory device of claim 13, wherein, an odd-numbered order within a corresponding group of row addresses.

15. The memory device of claim 13, wherein: each of the plurality of groups of row addresses comprises zero or two edge row addresses.

16. The memory device of claim 14, wherein the control logic circuitry is configured to: determine, as the one or more fine-grained refresh target row addresses, a pointed-to row address corresponding to the refresh target pointer value when the pointed-to row address corresponds to the plurality of edge memory cell arrays, and determine, as the one or more fine-grained refresh target row addresses, a pointed-to row address corresponding to the refresh target pointer value when the pointed-to row address corresponds to the plurality of internal memory cell arrays. when the pointing row address corresponds to a plurality of internal storage unit rows, determining the pointing row address and a subsequent row address of the pointing row address as the one or more fine-grained refresh target row addresses.

17. The memory device of claim 12, wherein the control logic circuit is configured to: each time the regular refresh command is received, increase the refresh target pointer value to an integer multiple of a first number of row addresses included in the subset by increasing the refresh target pointer value by a first value, the first value being a value between "1" and the first number, each time the fine-grained refresh command is received, increase the refresh target pointer value by a second number of row addresses determined as the one or more fine-grained refresh target row addresses.

18. A memory device, comprising: a first memory bank; a row decoder connected to the first memory bank; and a control logic circuit configured to: perform a regular refresh operation on the first memory bank for a first time period by controlling the row decoder in response to a first regular refresh command for the first memory bank; and perform a fine-grained refresh operation on the first memory bank for a second time period shorter than the first time period by controlling the row decoder in response to a first fine-grained refresh command for the first memory bank.

19. The memory device of claim 18, wherein: a length of the second time period corresponds to a same bank activation minimum interval for the first memory bank.

20. The memory device of claim 18, further comprising a second memory bank, wherein the control logic circuit is configured to: receive a second fine-grained refresh command for the second memory bank or a second regular refresh command for the second memory bank at a second time point after a first time length from a first time point at which the first fine-grained refresh command is received, the first time length being longer than a bank-to-bank delay and shorter than a regular refresh-regular refresh delay of other banks.

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