Vertical Stacked FinFETs and Shared Gate Patterning

Abstract

The stacked finFET structure includes fins having at least a first layer of semiconductor material stacked above or below a second layer of semiconductor material. The first and second layers may include, for example, a group-IV semiconductor material layer and a group-III-V semiconductor material layer. The stacked finFET may include an N-type finFET stacked above or below a P-type finFET, and the two finFETs may have channel portions within different semiconductor material layers. The channel portions of the first and second layers of semiconductor material may be coupled to vertically aligned independent gate electrodes. The channel portions of the first and second layers of semiconductor material may be vertically separated by sub-fin portions of the first and second layers. Different layers of dielectric material adjacent to the sub-fin portions may improve electrical isolation between the channel portions, for example, as a source of fixed charges or impurity dopants.

Description

Background Art

[0001] The device density of integrated circuits (ICs) has increased following Moore's Law for decades. However, as the lateral dimensions of device structures shrink with each technology generation, it has become increasingly difficult to further reduce the structure size.

[0002] Three-dimensional (3D) scaling is now receiving significant attention because a reduction in the z-height (device thickness) provides another way to increase the overall device density and IC performance. 3D scaling can take the form of, for example, chip stacking or packaged IC stacking. Known 3D integration techniques are expensive and may only provide incremental improvements in terms of z-height and device density. For example, most of the chip thickness may be non-active substrate material. A stack of such chips can employ through-substrate via (TSV) technology as a means of vertically interconnecting the chip stack. TSVs typically penetrate 20 - 50 μm or more of the substrate material and thus generally limit the via diameter to the micron scale. As a result, the TSV density is limited to well below the density of most device (e.g., transistor, memory) cells. Brief Description of the Drawings

[0003] The materials described herein are illustrated in the drawings by way of example and not limitation. For the sake of brevity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, for clarity, the dimensions of some elements may be exaggerated relative to other elements. Additionally, for the sake of clarity of discussion, various physical features may be represented in their simplified "ideal form" and geometry, but nevertheless, it is to be understood that actual implementations may only approximate the ideal cases shown. For example, smooth surfaces and square intersections may be drawn without regard to the wire roughness, rounded corners, and defective corner intersection structure characteristics formed by nanomanufacturing techniques. Further, where considered appropriate, reference numerals are repeated between the drawings to indicate corresponding or similar elements. In the drawings:

[0004] Figure 1A is an isometric view of vertically stacked CMOS finFETs in accordance with some embodiments;

[0005] Figure 1B is an isometric view of vertically stacked CMOS finFETs in accordance with some embodiments;

[0006] Figure 1C is a cross-sectional view of the lateral width of vertically stacked CMOS finFETs in accordance with some embodiments;

[0007] Figure 1D is a cross-sectional view of the longitudinal length of vertically stacked CMOS finFETs in accordance with some embodiments;

[0008] Figure 2 is a flowchart showing a method of sharing gate terminal patterning between top and bottom stacked finFETs in accordance with some embodiments;

[0009] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F 、 Figure 3G and Figure 3H are cross-sectional views of a stacked finFET evolving as selected operations in the method shown in Figure 2 are performed in accordance with some embodiments;

[0010] Figure 4 is a flowchart showing a method of fabricating a stacked CMOS finFET in accordance with some embodiments.

[0011] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D and Figure 5E are cross-sectional views of a stacked finFET evolving as selected operations in the method shown in Figure 4 are performed in accordance with some embodiments;

[0012] Figure 6 is a flowchart showing a method of fabricating a stacked CMOS finFET in accordance with some alternative embodiments;

[0013] Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D and Figure 7E are cross-sectional views of a stacked finFET evolving as selected operations in the method shown in Figure 6 are performed in accordance with some embodiments;

[0014] Figure 8 is a flowchart showing a method of fabricating a stacked CMOS finFET in accordance with some alternative embodiments;

[0015] Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D are cross-sectional views of a stacked finFET evolving as selected operations in the method shown in Figure 8 are performed in accordance with some embodiments;

[0016] Figure 10 is a flowchart showing a method of electrically isolating a stacked finFET in accordance with some embodiments;

[0017] Figure 11is a flow chart showing a method of electrically isolating stacked finFETs according to some embodiments;

[0018] Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 12E 、 Figure 12F 、 Figure 12G and Figure 12H are cross-sectional views of a stacked finFET evolving as selected operations in the method shown in Figure 11 are performed according to some embodiments;

[0019] Figure 13 is a flow chart showing a method of electrically isolating stacked finFETs according to some embodiments;

[0020] Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 14D 、 Figure 14E 、 Figure 14F 、 Figure 14G 、 Figure 14H and Figure 14I are cross-sectional views of a stacked finFET evolving as selected operations in the method shown in Figure 13 are performed according to some embodiments;

[0021] Figure 15 is a cross-sectional view of the lateral width of a vertically stacked CMOS finFET according to some embodiments, showing a sub-fin electrical isolation structure;

[0022] Figure 16 is a flow chart showing a method of electrically isolating stacked finFETs according to some embodiments;

[0023] Figure 17A 、 Figure 17B and Figure 17C are cross-sectional views of a stacked finFET evolving as selected operations in the method shown in Figure 16 are performed according to some embodiments;

[0024] Figure 18 shows a mobile computing platform and a data server machine employing an IC with stacked CMOS finFETs according to an embodiment; and

[0025] Figure 19 is a functional block diagram of an electronic computing device according to some embodiments. DETAILED DESCRIPTION

[0026] One or more embodiments will be described with reference to the accompanying drawings. Although specific configurations and arrangements are shown and discussed in detail, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of this description. Those skilled in the relevant art will understand that the techniques and / or arrangements described herein can be used in a variety of other systems and applications in addition to those described in detail herein.

[0027] Reference is made to the accompanying drawings in the following detailed description, which form a part hereof and show exemplary embodiments. It is further understood that other embodiments may be utilized and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and reference numerals (e.g., up, down, top, bottom, etc.) may be used only to facilitate the description of features in the drawings. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and their equivalents.

[0028] In the following description, numerous details are set forth. However, those skilled in the art will understand that the invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form rather than in detail to avoid obscuring the invention. Throughout this specification, references to "an embodiment" or "one embodiment" or "some embodiments" mean that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, in any case where a particular feature, structure, function, or characteristic associated with two embodiments is not mutually exclusive, the first embodiment may be combined with the second embodiment.

[0029] As used in this description and the appended claims, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0030] The terms "coupled" and "connected" along with their derivatives may be used in this document to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Instead, in a particular embodiment, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intervening elements between them), and / or (e.g., in accordance with a causal relationship) two or more elements cooperate or interact with each other.

[0031] As used herein, the terms "above", "below", "between", and "on" refer to the relative position of one component or material with respect to other components or materials, where such physical relationships are of interest. For example, in the context of materials, one material or a material disposed above or below another material may be in direct contact or may have one or more intervening materials. Additionally, a material disposed between two materials may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material / material. Similar distinctions will be made in the context of component assemblies.

[0032] As used throughout this description and the claims, a list of items joined by the terms "at least one of..." or "one or more of..." can represent any combination of the listed terms. For example, the phrase "at least one of A, B, or C" can represent: A; B; C; A and B; A and C; B and C; or A, B, and C.

[0033] This document describes stacked finFET structures and techniques for fabricating such structures. As used herein, a "stacked finFET" structure includes two field effect transistors (FETs) at opposite (e.g., top and bottom) ends of the same "stacked fin." As used herein, a "stacked fin" includes at least two layers of semiconductor material vertically stacked within the lateral extent of the fin. The layers of semiconductor material are used for at least the channels of the stacked finFETs and may have the same or different semiconductor compositions. In some embodiments, at least two separate gates of the stacked finFET are adjacent to the sidewalls of the fin. Although the gates are vertically separated, they may be vertically aligned with respect to each other in a manner indicative of a gate patterning process. As further described herein, a shared gate patterning process may reduce fabrication costs and simplify the fabrication of multiple FETs on a stacked fin. In some embodiments, the stacked finFET is a stacked CMOS finFET that includes a first FET of a first conduction type (e.g., N-type or NMOSFET) and a second FET of a second complementary conduction type (e.g., P-type or PMOSFET). In some embodiments, the stacked finFET is a stacked heterostructure that includes: a first FET having at least a channel in a first semiconductor layer of the fin; and a second FET having at least a channel in a second semiconductor layer of the fin, wherein the first and second layers form a heterojunction or form two or more heterojunctions with one or more intermediate semiconductor layers.

[0034] In some embodiments, sub-fin portions of the stacked fin provide electrical separation and / or isolation between vertically separated channel portions of the fin gated by respective independent gate electrodes. Sub-fin electrical separation may reduce the electrical coupling between stacked finFETs to a level sufficient to allow the stacked FETs to operate independently. As further described below, one or more of junction isolation by field effect or carrier depletion may be used for electrical separation and / or isolation of stacked semiconductor channel portions.

[0035] Figure 1A is an isometric view of a vertically stacked CMOS finFET structure 101 according to some embodiments. Figure 1A represents any volume within an integrated circuit (IC). Figure 1A The volume shown may extend over any large occupied area in the x-y plane of the IC, as the embodiments herein are not limited to this context. Figure 1A The volume shown may be surrounded by any number of interconnect metallization levels (not shown) above (+z direction) and / or below (-z direction), as the embodiments herein are not limited to this context. Figure 1AThe volume shown can be mechanically supported by any substrate or carrier (not shown), as the embodiments herein are not limited to this context. The stacked CMOS finFET structure 101 includes five rows of stacked finFETs 110. Within each row of the five rows, there are two columns of stacked finFETs 110. Thus, within the volume shown, there are ten stacked CMOS finFETs 110. Each stacked CMOS finFET 110 includes a finFET 106 of a first conduction type (e.g., N-type or NMOSFET), which is stacked on top of a finFET 107 of a second conduction type (e.g., P-type or PMOSFET). Within the volume shown, there are thus ten PMOS finFETs and ten NMOS finFETs, for a total of twenty FETs. Dielectric material 180 separates the rows of stacked CMOS finFETs 110. Dielectric material 180 contacts any semiconductor sidewalls of the stacked fins that are not covered by another material. Dielectric material 180 can be one or more layers of any material known to be suitable as shallow trench isolation (STI). Dielectric material 180 can be a low-k (e.g., less than 3.5) or a medium-k dielectric (e.g., between 3.5 and 8) dielectric material. Exemplary dielectric materials include, but are not limited to, silicon nitride (SiN), silicon oxide (SiO), silicon dioxide (SiO2), carbon-doped silicon (SiOC(H)), silicon oxynitride (SiON), HSQ, MSQ, or porous dielectrics.

[0036] As further shown, finFET 106 includes source and drain contact metallizations 151, which are coupled to opposite ends of the semiconductor channel through source and drain semiconductors 141. Source and drain semiconductors 141 have a certain concentration of impurity atoms (e.g., donors), which create a density of states of charge carriers (e.g., electrons) corresponding to the conduction type (e.g., N-type) of the finFET. Advantageously, source and drain semiconductors 141 are substantially single crystal, but can also be polycrystalline. Source and drain semiconductors 141 can be any semiconductor material that has any suitable majority lattice atoms and any impurity dopant atoms suitable for the majority lattice atoms. Source and drain contact metallizations 151 can be any elemental metal, metal alloy, or metal compound that provides an ohmic or non-ohmic (e.g., tunneling) contact to source and drain semiconductors 141. Although each finFET 106 has independent source and drain contact metallizations 151, source and drain contact metallizations 151 can be continuous such that two or more finFETs 106 can share the same contact metallization 151.

[0037] As further shown, finFET 107 also includes source and drain contact metallizations 152, which are coupled to opposite ends of the semiconductor channel through source and drain semiconductors 142. The source and drain semiconductors 142 have a certain concentration of impurity atoms (such as acceptors), which generate a state density of charge carriers (such as holes) corresponding to the complementary conduction type (such as P-type) of the finFET. The source and drain contact metallizations 152 can be any elemental metal, metal alloy, or metal compound that provides an ohmic or non-ohmic contact with the source and drain semiconductors 142. Due to the different conduction types of the source and drain semiconductors 141, 142, the source and drain contact metallizations 152 can have a different composition from the source and drain contact metallizations 151. Although each finFET 107 has independent source and drain contact metallizations 152, the source and drain contact metallizations 152 can be continuous in the x or y dimension, such that two or more finFETs 107 share the same contact metallization 152. One or more of the source and drain contact metallizations 151 and 152 can also be merged in the z dimension, such that the source or drain of one or more of the finFETs 106 can have electrical continuity with the source or drain of one or more of the finFETs 107.

[0038] The source and drain semiconductors 141 are over the sub-fin portion 111. In some embodiments, the sub-fin portion 111 includes a first semiconductor. Advantageously, the sub-fin portion 111 is substantially single-crystalline, but the defect density may be significant. Another sub-fin portion 112 is between the sub-fin portion 111 and the source and drain semiconductors 142. Advantageously, the sub-fin portion 112 is also substantially single-crystalline, but the defect density may again be significant, at least near the interface with the sub-fin portion 111. In some embodiments, the majority of the lattice atoms of the sub-fin portions 111 and 112 are different, such that there is a heterojunction between the sub-fin portions 111 and 112. In alternative embodiments, the majority of the lattice atoms of the sub-fin portions 111 and 112 are the same, such that there is a homojunction between the sub-fin portions 111 and 112. For the heterojunction or homojunction embodiments, the impurity dopants within the sub-fin portion 111 can be different from the impurity dopants within the sub-fin portion 112.

[0039] Each of the sub-fin portions 111 and 112 may include one or more layers of Group-IV semiconductors (such as silicon, germanium, or their alloys) and / or one or more layers of Group-III-V binary, ternary, or quaternary semiconductors (such as a first sub-lattice of at least one element from Group III of the periodic table (such as Al, Ga, or In) and a second sub-lattice of at least one element from Group V of the periodic table (such as P, As, or Sb)). Alternatively, each of the sub-fin portions 111 and 112 may include one or more layers of Group-III-N binary, ternary, or quaternary semiconductors (such as GaN, AlGaN, InAlGaN). Group-II-VI semiconductor layers are also possible. In some exemplary embodiments where the sub-fin portions 111 and 112 have different majority lattice atoms, the first of the sub-fin portions 111, 112 includes a Group-IV semiconductor, while the second of the sub-fin portions 111, 112 includes a Group-III-V semiconductor. In finFET 106 ( Figure 1A ), in some embodiments where finFET 106 is N-type and finFET 107 is P-type, the sub-fin portion 111 includes a Group-III-V semiconductor, while the sub-fin portion 112 includes a Group-IV semiconductor. In some other embodiments where finFET 106 is N-type and finFET 107 is P-type, the sub-fin portion 111 includes a first Group-IV semiconductor (such as silicon), while the sub-fin portion 112 includes a second Group-IV semiconductor (such as germanium). In still some other embodiments where finFET 106 is N-type and finFET 107 is P-type, the sub-fin portion 111 includes a first Group-IV alloy semiconductor (such as Si 1-x Ge x ), while the sub-fin portion 112 includes a second Group-IV alloy semiconductor (such as Si 1- y Ge y ), where x and y are different.

[0040] The FinFET 106 includes a gate electrode 131 between source and drain contact metallizations 151. The FinFET 107 includes a gate electrode 132 between source and drain contact metallizations 152. The gate electrodes 131 and 132 extend at least along sidewalls of a channel portion located at opposite ends or sides (e.g., top or bottom) of each stacked finFET 105. The gate electrodes 131 and 132 can include any metal, metal alloy, or metal compound having an appropriate work function. The gate electrode 131 can include, for example, at least a first work function metal (e.g., an N-type work function metal where the FinFET 106 is an NMOS device), while the gate electrode 131 includes a second work function metal (e.g., a P-type work function metal where the FinFET 107 is a PMOS device). Exemplary P-type work function metals include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). Exemplary N-type work function metals include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrodes 131, 132 include a stack of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional gate electrode layers, such as a diffusion barrier layer and / or an adhesion layer, can be included.

[0041] Figure 1B is an isometric view of a vertically stacked CMOS finFET 101. The source and drain metallizations 151, 152 and the dielectric isolation 180 are not drawn to further illustrate the stacked semiconductor fins 108 in accordance with some embodiments. Although the stacked CMOS finFET 101 is shown as having a rectangular cross-section in the z-x plane of a reference coordinate system, the stacked fins can alternatively have a cross-section that is circular or tapered at one or more ends of the fin, which can result in a cross-sectional profile in the z-x plane that is rectangular, hourglass-shaped, trapezoidal, etc. For example, the "top" of the stacked semiconductor fin 108 can be narrower than the "bottom" of the fin, and the gate stack 131 can conform to this circular or tapered fin shape. Although including two or more semiconductor layers, advantageously, the stacked semiconductor fins 108 are substantially single crystal, at least within the channel portions separated by the sub-fin portions 111, 112. As shown, the gate electrodes 131, 132 extend at least over sidewalls of the channel portions of the stacked semiconductor fins 108, where the sub-fin portions 111, 112 are located between the gate electrode 131 and the gate electrode 132. For each finFET, the transistor channel resides within the channel portions of the stacked semiconductor fins. These channel portions are at least under the gate electrode 131 or the gate electrode 132. The gate dielectric 125 is between the channel portions and the gate electrodes 131, 132.

[0042] The gate dielectric 125 can be any material suitable for a MOSFET, including dielectrics having a medium relative permittivity (e.g., a k between 3.5 and 9) or having a high relative permittivity (e.g., a k greater than 9). For example, the gate dielectric 125 can include one or more of the dielectric materials discussed herein with reference to isolation 180. In other examples, the gate dielectric 125 can include hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. For clarity, the gate dielectric 125 is shown only as a line in Figure 1B because it can be very thin relative to the gate electrodes 131, 132, etc. (e.g., between 0.5 nanometers and 3 nanometers, including all values and ranges therein). In the illustrated embodiment, the gate electrodes 131, 132 are separated from the source and drain semiconductors 141, 142 by dielectric gate spacers, which, although not shown in Figure 1B , are located above the semiconductor region 127. The gate spacers can be, for example, any of the dielectric materials described herein with reference to dielectric material 180. In some embodiments, the semiconductor region 127 has the same composition as the channel semiconductor under the gate electrode 131. In other embodiments, the semiconductor region 127 includes impurity dopants that do not appear to the same extent in the channel semiconductor under the gate electrode 131.

[0043] As Figure 1B further shown, the stacked finFETs within a row of stacked finFETs are separated by plugs 113. In the illustrated example, the plugs 113 are a dielectric material that extends along the entire vertical (e.g., z-dimension) height of the stacked semiconductor fins 108. For such embodiments, the plugs 113 can be, for example, any of the dielectric materials described herein with reference to dielectric material 180. In other embodiments, the plugs 113 include a stack of semiconductor material layers, for example having at least the same majority lattice atoms as the sub-fin portions 111, 112. For such embodiments, the plugs 113 can be another substantially single-crystalline portion of the stacked semiconductor fins 108.

[0044] Figure 1C is shown in accordance with some embodiments through Figure 1BCross-sectional view of the lateral width of a vertically stacked CMOS finFET 101 in the A-A' plane shown in the figure. As shown, the stacked semiconductor fin 108 includes a first channel portion 121 and a second channel portion 122 separated by sub-fin portions 111, 112. Advantageously, the channel portions 121 and 122 are single-crystalline. Each of the channel portions 121, 122 can be, for example, any of the semiconductor materials described above in the context of the sub-fin portions 111, 112. In some embodiments, the channel portion 121 has the same composition as the sub-fin portion 111. In some embodiments, the channel portion 122 has the same composition as the sub-fin portion 112. In the case where both of the channel portions 121, 122 have the same composition as the sub-fin portions 111, 112 respectively, the stacked semiconductor fin 108 has only one metallurgical junction (homojunction or heterojunction) at the interface of the sub-fin portions 111 and 112. In the case where one or more of the channel portions 121 and 122 have compositions different from those of the sub-fin portions 111 and 112 respectively, the stacked semiconductor fin 108 can have two or three junctions (homojunctions and / or heterojunctions). The stacked semiconductor fin can be a homojunction structure in which the two channel portions 121, 122 differ only in terms of impurity dopants (e.g., N-type and P-type). Alternatively, the stacked semiconductor fin 108 can be a triple heterojunction structure in which there is a heterojunction between the sub-fin portions 111 and 112, and each of the channel portions 121, 122 has a majority lattice atom different from those of the sub-fin portions 111, 112. The stacked semiconductor fin can also be a double heterojunction in which only one of the channel portions 121, 122 has a majority lattice atom different from that of the sub-fin portion 111 or 112.

[0045] In the example shown, the stacked semiconductor fin 108 includes at least two semiconductor layers having different majority lattice atoms. In some embodiments, the channel portion 121 has at least the same majority lattice atoms as the sub-fin portion 111. The channel portion 122 can also have at least the same majority lattice atoms as the sub-fin portion 112. For embodiments in which both of the channel portions 121 and 122 have the same majority lattice atoms as the sub-fin portions 111 and 112 respectively, the stacked semiconductor fin 108 has a single heterojunction located between the sub-fin portions 111 and 112.

[0046] In the finFET 106 ( Figure 1AIn some exemplary embodiments where the finFET is N-type, the channel portion 121 is a Group III-V semiconductor having good electron transport characteristics. For some exemplary N-type transistor embodiments, advantageously, the channel portion 121 is a Group III-V material having a high electron mobility, such as but not limited to InGaAs, InP, InSb, or InAs. For some such embodiments, the channel portion 121 is a quaternary Group III-V alloy, such as but not limited to InGaAs. For some In x Ga 1-x As embodiments, the In content (x) is between 0.6 and 0.9, and advantageously is at least 0.7 (e.g., In 0.7 Ga 0.3 As). The sub-fin portion 111 can also be this same Group III-V semiconductor or another Group III-V semiconductor having a conduction band offset with respect to the channel portion 121. For example, the sub-fin portion 111 can be a Group III-V material having a significant band offset (e.g., the conduction band offset of an N-type device) with respect to the channel portion 121. Exemplary materials include but are not limited to GaAs, GaSb, GaAsSb, GaP, InAlAs, AlAs, AlP, AlSb, InSb, and AlGaAs. In some N-type transistor embodiments where the channel portion 121 is InGaAs, the sub-fin portion 111 is GaAs.

[0047] In some embodiments where the finFET 107 is P-type, the channel portion 122 is, for example, a Group IV semiconductor (e.g., silicon, germanium, or an alloy thereof) having good hole transport characteristics. The sub-fin portion 112 can also be this same Group IV semiconductor or another Group IV semiconductor having a valence band offset with respect to the channel portion 122. In exemplary P-type transistor embodiments, the channel portion 122 is advantageously Ge or a Ge-rich SiGe alloy. For some exemplary embodiments, the channel portion 122 has a Ge content between 0.6 and 0.9 and advantageously is at least 0.7. In alternative P-type transistor embodiments, the channel portion 122 is a compound semiconductor, such as but not limited to a Group III-V semiconductor (e.g., InGaSb) or a Group II-VI semiconductor (e.g., PbTe).

[0048] In some embodiments where finFET 106 is N-type and finFET 107 is P-type, channel portion 121 is a Group III-V semiconductor, and channel portion 122 is a Group IV semiconductor. In some other embodiments where finFET 106 is N-type and finFET 107 is P-type, channel portion 121 is a first Group III-V semiconductor, and channel portion 122 is a second Group III-V alloy semiconductor. In still some other embodiments where finFET 106 is N-type and finFET 107 is P-type, channel portion 121 is a first Group IV semiconductor (e.g., silicon), and channel portion 122 is a second Group IV semiconductor (e.g., germanium). Sub-fin portion 111 may also be this first Group IV semiconductor (e.g., silicon), and sub-fin portion 112 is also this second Group IV semiconductor (e.g., germanium). In other embodiments where finFET 106 is N-type and finFET 107 is P-type, channel portion 121 is a first Group IV alloy semiconductor (e.g., Si 1- x Ge x ), and channel portion 122 is a second Group IV alloy semiconductor (e.g., Si 1-y Ge y ), where x and y are different. Sub-fin portion 111 may also be this first Group IV alloy semiconductor (e.g., Si 1-x Ge x ), and sub-fin portion 112 is also this second Group IV alloy semiconductor (e.g., Si 1-y Ge y ).

[0049] In some embodiments, at least the impurity dopant species and / or impurity dopant levels are different between channel portions 121, 122 and sub-fin portions 111, 112. For example, the impurity concentration levels within channel portions 121, 122 are advantageously lower than those in sub-fin portions 111, 112. Higher majority carrier mobility can be achieved with the lowest practical impurity levels (e.g., intrinsic or non-intentional impurity dopant levels) within channel portions 121, 122. In some embodiments with the highest mobility, channel portions 121, 122 are intrinsic materials and are not intentionally doped with any electrically active impurities. In alternative embodiments, nominal impurity dopant levels may be present within channel portions 121, 122, e.g., to set the threshold voltage (V t ), or to provide a pocket implant, etc. However, even for impurity doping embodiments, advantageously, the impurity dopant levels within channel portions 121, 122 are relatively low, e.g., less than 1x10 17 cm -3. To provide electrical isolation between stacked finFETs, impurity dopants may be intentionally introduced into the sub-fin portions 111 and 112 such that, regardless of the conduction type, the impurity concentration is higher than that in the channel portions 121 and 122 (e.g., having an impurity concentration between 5x10 17 cm -3 and 1x10 19 cm -3 ).

[0050] Figure 1C In, the hatched notation at the heterojunction between the sub-fin portions 111 and 112 represents a high defect density region associated with a semiconductor lattice mismatch. In advantageous embodiments, such a high defect density region is mainly contained within the sub-fin portion 111 and / or the sub-fin portion 112. The stacked semiconductor fins 108 have a vertical height (e.g., in the z-dimension) H stacked fin , and this vertical height H stacked fin is equal to the sum of the first channel portion height H fin,1 , the second channel portion height H fin,2 and the sub-fin portion height H subfin . In some exemplary embodiments, the channel portion heights H fin,1 and H fin,2 are each less than 200 nm, advantageously less than 150 nm, and more advantageously between 20 nm and 150 nm. The sub-fin height H subfin may vary with the composition of the sub-fin portions 111, 112. For example, in some embodiments described below, the sub-fin height H subfin can be several hundred nanometers (e.g., 300 nm or greater) to contain the high defect density region within the sub-fin portions 111 and 112: In these embodiments, the sub-fin portions 111 and 112 are two different crystalline semiconductors having lattice constants so different that the stacked semiconductor fins 108 are a metamorphic heterostructure. In other embodiments where the sub-fin portions 111 and 112 have a sufficient match such that the stacked semiconductor fins 108 are a pseudomorphic heterostructure lattice parameter, the sub-fin height H subfin can be 150 nanometers or less.

[0051] As further shown in Figure 1C , the stacked semiconductor fins 108 have a lateral width of a critical dimension CD stacked fin , and this lateral width may vary with the stacked fin height H stacked finChange. In some embodiments, fin 108 has a minimum fin width of less than 50 nm, advantageously less than 30 nm, and more advantageously less than 20 nm. Thus, channel portion 121 may have a different width than channel portion 122. It is noted, however, that both channel portions 121 and 122 share a common longitudinal centerline that also passes through the centers of sub-fin portions 111 and 112. Thus, stacked semiconductor fin 108 may have any physical characteristics of a homogeneous or monolithic fin of comparable dimensions (e.g., CD stacked fin and H stacked fin ). At least for this reason, stacked semiconductor fin 108 is better characterized as a single fin structure in which there are two or more semiconductor layers rather than a stack of two or more fins.

[0052] For Figure 1C the embodiment shown, while dielectric material 180 is adjacent to the sidewalls of sub-fin portions 111 and 112, another dielectric layer 181 is adjacent to the sidewall of electrode 131, and a third dielectric layer 182 is adjacent to the sidewall of electrode 131. Although each of dielectric layers 181, 182 can be any of the materials described above for dielectric material 180, even in the case where either or both of dielectric materials 181, 182 have the same composition as dielectric material 180, the interface between these material layers can be identifiable and indicative of one or more of the fabrication processes described further below.

[0053] Figure 1D is a cross-sectional view showing the longitudinal length of vertical stacked CMOS finFET 101 through the Figure 1B B plane shown in accordance with some embodiments. As Figure 1D shown, sub-fin portions 111, 112 extend the full longitudinal length of a single finFET. Channel portions 121 and 122 extend between source and drain semiconductors 141 and 142, respectively. If the ends of channel portions 121, 122 are replaced, for example, by source and drain semiconductors 141, 142 through recess etching and epitaxial regrowth, then channel portions 121, 122 may be masked by source and drain semiconductors 141, 142. Gate electrodes 131 and 132 have a critical dimension CD gate associated with the channel length of the stacked finFET. In some exemplary embodiments, gate electrode 131 has a critical dimension CD equal to that of gate electrode 132 gate . Even in the case where gate electrodes 131 and 132 do not have exactly the same critical dimension CD gate , the centerline of gate electrode 131 is vertically aligned with the centerline of gate electrode 132, as Figure 1DAs shown. This vertical alignment of the gate electrodes 131 and 132 indicates the characteristics of a shared gate patterning process, as further described below. For such embodiments, although the gate electrodes 131 and 132 are separated by a vertical height H subfin , they may otherwise have any of the physical characteristics of a homogeneous or monolithic gate electrode that extends over the sidewalls of fins of comparable dimensions (such as CD stacked fin and H stacked fin ).

[0054] The above transistor structures can be fabricated using various techniques and unit processes. Some exemplary fabrication methods are described below to further illustrate the properties of the structural features introduced above. Figure 2 is a flowchart showing a method 201 for fabricating a stacked finFET that patterns the gate terminals between a shared top and bottom stacked finFET according to some embodiments. Figures 3A - 3H is a cross-sectional view of a stacked finFET evolving as selected operations in method 201 are performed according to some embodiments.

[0055] First referring to Figure 2 , method 201 begins at operation 210, where fins are fabricated that include one or more layers of semiconductor material. Any of the methods further described below can be implemented, for example, at operation 210. The fins generated at operation 210 can have one or more of the properties of the stacked semiconductor fins 108 described above. However, it is noted that method 201 does not require multiple semiconductor layers, and the fins fabricated at operation 210 can include only a single semiconductor layer (i.e., a homogeneous semiconductor fin). The fins fabricated at operation 210 have sufficient height to ultimately accommodate two stacked transistors, namely, one transistor using the top portion of the fin and a second transistor using the bottom portion of the fin. At operation 220, a dielectric gate mandrel is formed over the fins, and the resulting structure is planarized or gap-filled with a dielectric material. Advantageously, for embodiments where a portion of the gate mandrel can be retained in the final device structure (i.e., the gate mandrel is not completely sacrificial), the gate mandrel can have a sufficiently resistive material to avoid electrical shorting between subsequently fabricated stacked gate electrodes, as further described below.

[0056] Figure 3A Shows an example where a homogeneous semiconductor substrate 301 is patterned into fins 308. The substrate 301 can be any semiconductor known to be suitable for the fabrication of FETs. The substrate 301 can be, for example, any of the group-IV, III-V, or III-N semiconductors described above. Any conventional patterning process known to be suitable for fin fabrication can be used to pattern the fins 308. For example, a photolithographic mask patterning and anisotropic semiconductor etching process can be employed. Figure 3AIn [the figure], the gate core axis 330 is a continuous strip extending over multiple fins. The gate core axis 330 can be any material with sufficient resistivity. The gate core axis 330 can be a low-k, medium-k, or high-k dielectric material, such as but not limited to SiN, SiO x , SiON, HSQ, MSQ, carbon alloys (such as SiOC(H)). The gate core axis 330 can also be a resistive metal oxide (such as AlO x , HfO x , TaO x , TiO x , WO x ), or a resistive metal silicate.

[0057] As Figure 3A shown in [the figure], the gate core axis layer is deposited over the fin sidewalls to a thickness that ensures a gap or space remains between adjacent fins. For example, the gate core axis layer can be deposited using a substantially conformal process, such as atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD). The gate core axis layer can then be patterned using any known photolithographic masking technique and any anisotropic etching process known to be suitable for the selected gate core axis material. Gate core axis patterning will ultimately set the CD of the gate electrode, and any multi-patterning technique known to be suitable for gate lithography can be used to pattern the gate core axis. In the example shown, the gate core axis 330 has been patterned into a strip that has a longitudinal length extending in a direction substantially orthogonal to the fins 308. The lateral width of the gate core axis 330 can be approximately equal to the expected gate electrode critical dimension.

[0058] As Figure 3B further shown in [the figure], a dielectric material 335 is deposited over the fins 308 and the gate core axis 330. The dielectric material 335 can be a dielectric material, such as any of the materials described above for the gate core axis 330. However, advantageously, the dielectric material 335 is a different material from the gate core axis 330 to facilitate subsequent selective etching of the gate core axis 330. The dielectric material 335 can be deposited using any deposition process that provides adequate gap filling and / or planarization. In some exemplary embodiments, the dielectric material 335 is deposited using a flow CVD (fCVD) process. In other embodiments, a spin-on technique is used to apply the dielectric material 335. In some embodiments, the dielectric material 335 is planarized using any suitable chemical mechanical planarization (CMP) process to expose the top surface of the gate core axis 330, as Figure 3B shown in [the figure].

[0059] Returning to Figure 2, Method 200 continues at operation 230 where the gate mandrel is recessed a predetermined amount. Advantageously, the gate mandrel recess etch is selective to the surrounding dielectric material and the fin semiconductor. By exposing a certain amount of the fin semiconductor sidewalls, the mandrel recess defines the finFET channel width. Then, the portion of the gate mandrel material removed is replaced with a gate stack. The evacuated portion of the gate mandrel can be directly replaced with a permanent gate stack (which includes a gate dielectric and a work function metal), or it can be replaced with an intermediate sacrificial gate such as, for example, polysilicon. In Figure 3C the example shown, the gate mandrel 330 is selectively recessed relative to the dielectric material 335 to create a top-side recess 341 that exposes the sidewalls of the channel portion 311. Any suitable isotropic or anisotropic etch process with appropriate selectivity can be employed. The recess etch can be an unmasked (covered) etch-back. As Figure 3D further shown in

[0060] where a gate electrode has been fabricated at this point, method 201 ( Figure 2 ) continues at operation 240 where the bottom of the semiconductor fin and the gate mandrel are exposed. In some exemplary embodiments, exposing the backside of the device structure requires wafer-level backside processing. During such processing, the front side of the workpiece can be bonded to a carrier while the thickness of the backside substrate is polished to completion (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etch process. Any grinding, polishing, and / or wet / dry masked or unmasked etch process known to be suitable for the composition of the substrate can be employed at operation 240. For example, in the case where the backside substrate is a Group-IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning the semiconductor can be employed at operation 240. Similarly, any wet etchant or plasma etch process known to be suitable for etching a Group-IV semiconductor can also be employed at operation 240. Examples include any known through-substrate via etch process. Depending on the substrate removal technique, the substrate removal can be global, across the entire surface of the substrate, or localized, as controlled by an etch mask applied over the substrate surface. In Figure 3E the example shown, the backside removal process penetrates to the bottom of the gate mandrel 330, exposing the bottom of the dielectric material 335. Then, any suitable semiconductor etch process is employed to selectively recess the bottom portion of the fin 308 relative to the dielectric material 335 to form a fin recess 350.

[0061] Returning toFigure 2 After the semiconductor fin and the gate mandrel are exposed, the partial gate mandrel replacement technique for forming the first gate electrode is fully repeated to form the second gate electrode in operation 250. In Figure 3F the example further shown in, a recess etching is performed on the gate mandrel 330 using an etching process that is selective for the gate mandrel material with respect to the dielectric material 335. The gate mandrel recess 342 exposes the semiconductor sidewalls of the channel portion 322. As shown, not all of the gate mandrel 330 is removed to avoid exposing the gate electrode 131. The remaining portion of the gate mandrel 330 is to electrically isolate the gate electrode 131 from the second gate electrode subsequently formed in the gate mandrel recess 342. As Figure 3G shown, a gate dielectric and a gate electrode 132 are deposited in the gate mandrel recess 342. Then, the overburden is planarized with the top surface of the dielectric material 335 to electrically isolate individual finFET gates, as Figure 3H further shown in. In the fabrication process, at this time, the stacked finFET channels and gate electrodes are fabricated.

[0062] Return to reference Figure 2 , method 201 ends at operation 260, where the remaining transistor terminals are fabricated. The source and drain terminals of the first and second finFETs can be fabricated according to any suitable technique. For example, to form the source and drain regions, dopants (such as boron, aluminum, antimony, phosphorus, arsenic, etc.) can be ion implanted into the end regions of the channel portion. An annealing process to activate the dopants can follow the ion implantation process. These same dopants can also be deposited in-situ with the majority component during epitaxial regrowth from the end regions of the sub-fin portion and the channel portion. For example, the channel portion can first be etched to form a recess where the source and drain regions will be formed. Then, an epitaxial growth or material deposition process can be performed to fill the recess with the material used as the source and drain regions. In some embodiments, the source and drain regions can be fabricated using a silicon alloy (such as silicon germanium or silicon carbide) at operation 260. The deposited alloy can be in-situ doped with any impurities. In additional embodiments, the source and drain regions can be formed using one or more semiconductor materials other than the material of the channel portion such that a heterojunction is formed between the channel portion and the source / drain regions.

[0063] One or more layers of metal and / or metal alloy for forming the source and drain contacts can also be formed at operation 260 according to any suitable technique. One or more levels of interlayer dielectric (ILD) and interconnect metallization can also be fabricated at operation 260 according to any suitable technique. It is noted that operation 260 can be performed on both the front and back sides of the stacked finFETs. This front-side processing can be performed before the back-side exposure operation 240, or it can be performed after forming the two stacked gate electrodes. This back-side processing can be performed after the back-side exposure operation 240, and for example, it can be performed after forming the two stacked gate electrodes.

[0064] It should be noted that the back side of the semiconductor fin can be exposed at any point during the fabrication of the stacked CMOS finFET structure. In method 201, the back side of the semiconductor fin can be exposed later in the fabrication process, such as after the formation of the stacked semiconductor fins, the front transistor terminals, and the first or multiple levels of front interconnect metallization. Alternatively, the back side of the semiconductor fin can be exposed earlier in the fabrication process, such as to facilitate the formation of the stacked semiconductor fins. For such embodiments, the stacked semiconductor fins can be fabricated after the front side fabrication of the first finFET, after the front side fabrication of the source and drain terminals, or even after the front side fabrication of the front interconnect metallization.

[0065] As described above, method 201 can also be implemented with stacked semiconductor fins to obtain Figures 1A - 1D the stacked CMOS finFET structure shown. Such stacked semiconductor fins can be fabricated using unique front side processing or using a hybrid process including back side processing. Figure 4 is a flow chart showing method 401 for fabricating stacked semiconductor fins suitable for incorporation into a stacked CMOS finFET structure according to some additional embodiments. Method 401 employs only front side processing. Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E are cross-sectional views of a stacked fin structure evolving as selected operations in method 401 are performed according to some exemplary embodiments.

[0066] First referring to Figure 4 , method 401 begins at operation 405 to form fins including a first semiconductor. At operation 405, the fins can be fabricated into the surface of a bulk single crystal semiconductor substrate or into a single crystal semiconductor layer of a stack of semiconductor material layers. After fin formation, at operation 410 mask material is deposited and planarized around the fins. In the Figure 5A example shown, fin 308 is etched into substrate 301. Substrate 301 can be a single crystal or SOI substrate, such as including any of the group IV, III-V, III-N semiconductor materials described above. Any conventional patterning process known to be suitable for fin fabrication can be used to pattern fin 308. For example, one or more photolithographic masking operations and anisotropic semiconductor etching processes can be used to delineate fins with a fin height of H fin . The fin height H fin can be a predetermined height sufficient to contain two stacked finFETs. As Figure 5BAs further shown, a dielectric material 180 is deposited over the sidewalls of the fins 308, at least partially backfilling the space between adjacent fins and masking all portions except the top surfaces of the fins 308. The dielectric material 180 can be any of the materials described above. After planarization (e.g., CMP), the top surfaces of the fins 308 are exposed and are substantially planar with the top surface of the isolation dielectric 180.

[0067] Returning to Figure 4 , method 401 continues at operation 420, where the top portions of the semiconductor fins are selectively etched relative to the surrounding masking material so as to recess the surfaces of the semiconductor fins below the top surface of the isolation dielectric. Thus, a portion of the first semiconductor that was formed into the fins at operation 405 is sacrificial. Any one or more etching processes known to be suitable for recessing a particular semiconductor composition can be employed at operation 420. For example, in the case where the fins are silicon and the surrounding masking material is silicon dioxide, the one or more etching processes can require isotropic and / or anisotropic chemical etching processes that are highly selective relative to the dielectric material (e.g., HBr, Cl2, HMDS, etc.). The recess etching can be, for example, a blanket (unmasked) isotropic or anisotropic etching. The recess etching process can be a timed process for a predetermined duration to recess the semiconductor fins to a target depth. In Figure 5C the example shown, the top portions of the fins 308 have been etched to form fin recesses 550 between portions of the isolation dielectric 180. The remaining remnants of the recessed semiconductor fins become the channel portions 122 of the stacked semiconductor fins. As shown, the recess 550 has a recess height H r,1 . The recess height H r,1 can be for a depth that is at least equal to the expected fin height H fin,1 . In the example shown, the recess height H r,1 is greater than the expected fin height H fin,1 .

[0068] Returning to Figure 4, Method 401 continues at operation 430, where one or more second layers of semiconductor material are formed within the recesses created at operation 420, thereby effectively replacing a portion of the first semiconductor with an alternative semiconductor composition that is more suitable for one of the stacked finFETs. In some embodiments, an epitaxial growth process is performed at operation 430 to grow one or more crystalline semiconductor layers over the seeding surface of the remaining portion of the first semiconductor. During such epitaxial (re)growth of the fin semiconductor, the surrounding dielectric material can provide sidewalls of sufficient height above the semiconductor growth surface to implement aspect ratio trapping (ART) during the epitaxial growth process. With ART, defects propagating from the growth plane can preferentially terminate at the sidewalls of the epitaxial semiconductor layer that intersects the sidewalls of the isolation dielectric, thereby reducing the defect count in the uppermost portion of the regrown semiconductor. The ART technique can achieve an acceptable crystal quality within the heteroepitaxial material and is an example of a locally additive heteroepitaxial stacked semiconductor fabrication, which can advantageously reduce the impact of lattice mismatch across various heterojunctions within the stacked fins. In some alternative embodiments, operation 430 includes deposition of an amorphous or polycrystalline semiconductor material. This material can then be melted and (re)crystallized to match the crystallinity to the seeding surface during thermal annealing. Any such solid-phase epitaxial process known to be suitable for a given semiconductor composition can be implemented at operation 430. Any overcoat associated with the (one or more) epitaxial growth or deposition process can be planarized with the surrounding isolation dielectric using any suitable technique (e.g., CMP).

[0069] In Figure 5D the example shown, a stacked semiconductor fin 108 is formed by backfilling fin recess 550 with channel portion 121, which includes one or more second layers of semiconductor material. Channel portion 121 can include, for example, any of the semiconductor materials described above in the Figure 1B context. As shown, the thickness of the second semiconductor layer grown within the recess is approximately equal to the fin recess height H r,1 . The uppermost region of channel portion 121 (e.g., associated with fin height H fin, 1 ) has a good crystal quality and the highest defect density found within the sub-fin portion 111 at the interface closest to fin 308. At this point, the stacked semiconductor fin 108 is substantially complete. In the case where the semiconductor fin process is complete, lower temperature processing (e.g., below the epitaxial growth) can subsequently be performed during the fabrication of the stacked CMOS finFets. For example, the stacked semiconductor fin 108 fabricated by method 401 can be used in method 201 to arrive at the Figure 5E device structure shown in. In Figure 5EIn the example shown, in the channel region of the stacked CMOS finFET 105, the dielectric material 180 has been further patterned (e.g., recess etched) from the front and back of the stacked semiconductor fins to expose the channel portions 121 and 122. Gate stacks 131 and 132 have been fabricated over the exposed channel portions 121 and 122. Thus, the dielectric material 180 remains adjacent to the sidewalls of the sub-fin portions 111 and 112, while additional isolation dielectrics 181 and 182 have been subsequently deposited to occupy the spaces between the adjacent gate stacks 131 and 132, respectively. For embodiments in which the gate stacks 131 and 132 have been fabricated in a self-aligned manner (e.g., in accordance with method 201), Figure 5E The example shown is substantially as described above in Figure 1C for the vertical stacked CMOS finFET structure 101.

[0070] Figure 6 FIG. 6 is a flow chart of a method 601 for fabricating a stacked semiconductor fin for some alternative embodiments for forming a stacked semiconductor fin according to backside processing. In this example, after the backside of the semiconductor fin is exposed, front and back transistor terminals are fabricated so as to limit the high-temperature epitaxial process to the front end of the fabrication process. In the case where the epitaxial process has a sufficiently low temperature (e.g., Ge growth), the front transistor terminal fabrication can be changed to be completed before replacing a portion of the semiconductor fin with an epitaxial growth material layer.

[0071] Method 601 begins at operation 405, where a fin including a first semiconductor is fabricated, for example, substantially as described above in the context of method 401. Method 601 continues at operation 410, where a masking material is formed around the fin, for example, substantially as described above in the context of method 401. In Figure 7A the example shown, the semiconductor fin 308 has a fin height H fin and is covered with a planarized dielectric material 180. At this time, the dielectric material 180 can be bonded to a suitable front carrier (not shown).

[0072] Returning to Figure 6 , method 601 continues at operation 620, where the bottom of the semiconductor fin is exposed by backside processing. Any suitable technique can be performed at operation 620, such as but not limited to splitting, grinding, lapping, polishing, masked etching, and unmasked etching. In Figure 7B the example shown, the body portion of the substrate 301 has been removed by backside processing, thereby exposing the bottom portion of the semiconductor fin 308. Method 601 ( Figure 6) Continuing at operation 630, the bottom portion of the semiconductor fin is selectively etched relative to the surrounding mask material, thereby recessing the surface of the semiconductor fin below the top surface of the mask material. Accordingly, a portion of the semiconductor that was formed into the fin at operation 405 is sacrificial. Any one or more etching processes known to be suitable for recessing a particular semiconductor composition may be employed at operation 630. For example, in the case where the fin is silicon and the surrounding mask material is silicon dioxide, the one or more etching processes may require an isotropic and / or anisotropic chemical etching process that is highly selective relative to the isolation dielectric (e.g., HBr, Cl2, HMDS, etc.). The recess etching may be, for example, a blanket (unmasked) isotropic or anisotropic etching. The recess etching process may be a timed process for a predetermined duration to recess the semiconductor fin to a target depth.

[0073] In Figure 7C the example shown, the bottom portion of the semiconductor fin has been etched to form a fin recess 750 between portions of the dielectric material 180. The remaining residue of the recessed semiconductor fin becomes the channel portion 121 of the stacked semiconductor fin. As shown, the recess 750 has a recess height H r,1 . The recess height H r,1 may be for a depth of at least equal to the expected fin height H fin,1 . In the example shown, the recess height H r,1 is greater than the expected fin height H fin,1 .

[0074] Returning to Figure 6 , method 601 continues at operation 640, where one or more second semiconductor layers are formed within the recess created at operation 630, thereby effectively replacing a portion of the first semiconductor with an alternative semiconductor composition that is more suitable for one of the stacked finFETs. In some embodiments, an epitaxial growth process is performed at operation 640 to grow one or more crystalline semiconductor layers over the seed surface of the remaining portion of the first semiconductor. During such epitaxial (re)growth of the fin semiconductor, the surrounding dielectric material may provide sidewalls of a sufficient height above the semiconductor growth surface to implement aspect ratio trapping (ART) during the epitaxial process.

[0075] In Figure 7D the example shown, a stacked semiconductor fin 108 is formed by backfilling the fin recess 750 with the channel portion 122, which includes one or more second semiconductor materials. The channel portion 122 may include, for example, any of the semiconductor materials described above in the context of Figure 1B . As shown, the thickness of the second layer of semiconductor material grown within the recess is approximately equal to the fin recess height H r,1 . The uppermost region of the channel portion 122 (e.g., in relation to the fin height H fin, 1associated) has the highest defect density found within the sub-fin portion 112 that has good crystal quality and an interface closest to the channel portion 121. At this point, the stacked semiconductor fins 108 are substantially complete. A lower temperature process (e.g., below epitaxial growth) can then be performed during the fabrication of the stacked CMOS finFETs. For example, the stacked semiconductor fins 108 can be fabricated according to method 601 at operation 210 ( Figure 2 ) and subsequently used in method 201.

[0076] The stacked semiconductor fins 108 fabricated by method 601 can be used in method 201 to arrive at Figure 7E the device structure shown. In this example, within the channel region of the stacked CMOS finFET 105, the dielectric material 180 has been patterned (e.g., recess etched) from both the front and back of the stacked semiconductor fins to expose the channel portions 121 and 122. Gate stacks 131 and 132 have been fabricated over the exposed channel portions 121 and 122. Thus, the dielectric material 180 remains adjacent to the sidewalls of the sub-fin portions 111 and 112, and additional layers of dielectric materials 181 and 182 are subsequently deposited over the dielectric material 180 to occupy the spaces between the adjacent gate stacks 131 and 132, respectively. For embodiments where the gate stacks 131 and 132 have been fabricated in a self-aligned manner (e.g., according to method 201), Figure 7E the example shown is substantially as described above in Figure 1C for the vertical stacked CMOS finFET structure 101.

[0077] In some embodiments, the stacked semiconductor fins are fabricated by patterning fins from a multi-layer semiconductor stack that has been epitaxially grown or laminated (e.g., by a transfer process). Figure 8 is a flow chart showing a method 801 for fabricating stacked semiconductor fins according to some alternative embodiments. Method 801 again uses only front-side processing to fabricate stacked semiconductor fins suitable for forming a stacked CMOS finFET structure. Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D are cross-sectional views of stacked fin structures evolving as selected operations in the method shown in Figure 8 are performed according to some embodiments.

[0078] First, referring to Figure 8, Method 801 begins at operation 805 to form a semiconductor film stack including a plurality of semiconductor layers, where at least two of such layers are suitable as FET channel materials. In the case of epitaxial growth being employed at operation 805, a pseudomorphic or metamorphic semiconductor layer having a composition suitable for a first FET can be grown from a crystalline growth substrate having a composition suitable for a second FET. The growth substrate can have any suitable lattice structure, such as but not limited to cubic or tetragonal. Any suitable epitaxial growth process can be used to grow the second semiconductor layer.

[0079] In Figure 9A the example shown, a crystalline semiconductor layer 905 is epitaxially grown on a substrate 301. The substrate 301 can be any semiconductor known to be suitable for the fabrication of FETs. The substrate 301 can be, for example, any one of the group-IV, III-V, III-N, or II-VI semiconductors described above. The crystalline semiconductor layer 905 can be any semiconductor known to be suitable for the fabrication of FETs. The semiconductor layer 905 can be, for example, any one of the group-IV, III-V, III-N, or II-VI semiconductors described above. Depending on the degree of material layer mismatch (e.g., lattice mismatch and / or CTE mismatch) between the first and second semiconductor layers, crystal defects can exist within the semiconductor layer 905. In the absence of the beneficial effects of ART, high defect density regions can extend over a greater thickness T1 of the semiconductor layer 905. Such defective regions are generally not suitable for FETs and should be included within a fin portion. In the case of a greater thickness of the semiconductor layer 905, higher fins may be required, where the greater volume of such fins is not suitable for FETs.

[0080] In some alternative embodiments, a crystalline semiconductor layer is bonded to a crystalline semiconductor substrate layer. Relative to heteroepitaxial growth of a highly mismatched epitaxial layer, the bonding process can allow for a thinner semiconductor layer of high crystal quality and achieve reduced height fins. Any layer transfer process known to be suitable for bonding two layers can be used to form the semiconductor film stack. For a stack formed by such a process, one or more intermediate bonding layers (e.g., silicon dioxide or another dielectric) can be present between the two crystalline semiconductor layers.

[0081] Returning to Figure 8 , Method 801 continues at operation 810, where the semiconductor material stack is patterned into fins, the fins including two or more semiconductor layers. Any (one or more) masking (e.g., lithography) process and (one or more) anisotropic etching process can be used to define the fins from the epitaxial semiconductor layer ， and extending to a predetermined depth into the substrate. Then at operation 820, for example, any suitable shallow trench isolation technique is used to form a dielectric material around the fins. In Figure 9B the example shown, the recess 950 has a height Hr and the height H r extends through the entire thickness of the semiconductor layer 905, thereby defining a channel portion 121 having a fin height H fin,1 and a sub-fin portion 111 having a thickness T1. The recess 950 stops within the substrate 301 at a predetermined target depth sufficient to form an FET within the channel portion 122. As shown, the resulting stacked fin 108 is asymmetric with respect to the junction between the two semiconductor layers, wherein the thickness of the sub-fin portion 111 is significantly greater than that of the sub-fin portion 112 due to a greater thickness associated with a high defect density region within the epitaxial layer. This asymmetry is in contrast to embodiments employing ART, in which the high defect density can be so thin that the sub-fin portions 111 and 112 can be of substantially the same thickness, which is limited by constraints imposed, for example, by the need for electrical isolation between the channel portions. In Figure 9C the example shown, a dielectric material 180 has been deposited over the stacked semiconductor fins 108, thereby backfilling the recess 950. Any suitable planarization process can be used to planarize the top surface of the dielectric material 180 and the top surface of the stacked semiconductor fins 108.

[0082] At this point, the stacked semiconductor fins 108 are substantially complete. In the case where the semiconductor fin process is complete, lower temperature processing (e.g., below the epitaxial growth) can be performed during the fabrication of the stacked CMOS finFet. For example, the stacked semiconductor fins 108 fabricated as by method 801 can be used in method 201 to arrive at Figure 9D the device structure shown in Figure 9D In the example shown in, within the channel region of the stacked CMOS finFET 105, the dielectric material 180 has been patterned (e.g., recess etched) from both the front and back of the stacked semiconductor fins to expose the channel portions 121 and 122. Gate stacks 131 and 132 have been fabricated over the exposed channel portions 121 and 122. Thus, the dielectric material 180 remains adjacent to the sidewalls of the sub-fin portions 111 and 112, while additional layers of dielectric materials 181 and 182 have been subsequently deposited over the dielectric material 180 to occupy the spaces between the adjacent gate stacks 131 and 132, respectively. For embodiments in which the gate stacks 131 and 132 have been fabricated in a self-aligned manner (e.g., in accordance with method 201), Figure 9D the example shown in is substantially as described above for the vertical stacked CMOS finFET structure 101 in Figure 1C

[0083] ​As described above, the sub-fin portions of the stacked semiconductor fins physically separate the two gated channel portions of the stacked finFETs. One or more sub-fin portions of the stacked semiconductor fins can provide intra-fin electrical isolation between the two gated channel portions. In some embodiments, for example, bandgap engineering can be used to impart a conduction band and / or valence band offset between the channel semiconductor and the sub-fin portions of the stacked semiconductor fins. Impurity doping can also be used to provide junction isolation between two adjacent sub-fin portions or between a sub-fin portion and the channel semiconductor. Such compositional differentiation can be achieved, for example, during the epitaxial growth of the stacked semiconductor fins. Alternatively, ex-situ techniques can be used to enhance the electrical isolation between two stacked finFETs. Exemplary ex-situ techniques include solid-phase dopant diffusion and ion implantation / activation. Intra-fin isolation between two stacked CMOS FETs can also be provided by introducing fixed charges adjacent to portions of the stacked semiconductor fins. Examples of these techniques are described further below.

[0084] Figure 10 is a flow chart showing a method 1001 for electrically isolating stacked finFETs according to some embodiments. Method 1001 begins at operation 1005 to receive a workpiece having stacked semiconductor fins, the stacked semiconductor fins including a first semiconductor layer and a second semiconductor layer. For example, any of the stacked semiconductor fin structures described above can be received at operation 1005. In some embodiments, the received workpiece includes stacked semiconductor fins that further include a first semiconductor layer suitable for an NMOS FET and a second semiconductor layer suitable for a PMOS FET. At operation 1010, a first dielectric material layer is formed over the sidewalls of the sub-fin portions of the first semiconductor layer. At operation 1020, a second dielectric material layer is formed over the sidewalls of the sub-fin portions of the second semiconductor layer. In some embodiments, the first dielectric material layer is associated with a fixed charge amount of a first polarity. Similarly, the second dielectric material layer is associated with a fixed charge amount of a second opposite polarity. This stack of fixed charge layers adjacent to the vertically stacked sub-fin portions of the semiconductor fins can induce depletion regions within the sub-fin portions. In some other embodiments, the first dielectric material layer includes one or more components that can become electrically active impurities within the first semiconductor layer. Similarly, the second dielectric material layer includes one or more components that can become electrically active impurities within the second semiconductor layer. For such embodiments, the stack of the first and second dielectric material layers acts as a solid-state diffusion source of impurities that can diffuse through the fin sidewalls into the sub-fin portions of the stacked semiconductor fins. Examples of such solid-state diffusion sources include, but are not limited to, borosilicate glass (BSG), phosphosilicate glass (PSG), and arsenosilicate glass.

[0085] Then, method 1001 continues at operation 1030 to form a first gate stack over the sidewalls of the channel portion of the first semiconductor layer. A second gate stack is similarly formed over the sidewalls of the channel portion of the second semiconductor layer at operation 1040. In some examples, one or more of the techniques described elsewhere herein are used to form the first and second gate stacks. Then, method 1001 completes the formation of the remaining transistor terminals (e.g., source and drain) at operation 260. The transistor terminals may then be interconnected into the circuit using one or more levels of interconnect metallization.

[0086] Figure 11 FIG. 11 is a flowchart showing a method 1101 for electrically isolating stacked finFETs in accordance with some embodiments. Method 1101 may be considered a particular implementation of method 1001. Method 1101 shows how front and backside processing can be used to introduce structural features that can improve the isolation between stacked CMOS finFETs. Figure 12A -12I is a cross-sectional view of a stacked finFET evolving as selected operations of the method shown in FIG. Figure 11 are performed, and further shows exemplary isolation structures, the stacked finFET structure having one or more of the features described for the stacked finFET structure 101 (e.g., Figures 1A - 1C ).

[0087] First referring to Figure 11 , method 1101 begins at operation 1005 to receive a workpiece having stacked semiconductor fins, the stacked semiconductor fins including a first semiconductor layer and a second semiconductor layer. Any of the stacked semiconductor fin structures described above may be received at operation 1005. In some embodiments, the received workpiece includes stacked semiconductor fins that further include a first semiconductor layer suitable for an NMOS FET and a second semiconductor layer suitable for a PMOS FET. In some exemplary embodiments, the stacked semiconductor fins are surrounded by a dielectric material (e.g., STI material) or embedded in a dielectric material. In the example shown in Figure 12A , stacked semiconductor fins 108 including sub-fin portions 111 and 112 extend from a substrate 301. Dielectric material 180 is located in the space between adjacent stacked semiconductor fins 108. Substrate 301, sub-fin portions 111 and 112, and dielectric material 180 may have any of the compositions described previously.

[0088] Returning to Figure 11, Method 1101 continues at operation 1120, where a portion of the dielectric material is selectively recessed relative to the stacked semiconductor fins. The recessing of the dielectric material can be performed using masked or maskless etching for a predetermined duration sufficient to expose at least one of the sub-fin regions. In some embodiments, the exposed sub-fin region has a composition suitable for an N-type FET. Any known isotropic or anisotropic etching process for isolation dielectrics with favorable selectivity can be employed at operation 1120. In Figure 12B the example shown, isolation recess 1250 substantially exposes all of one semiconductor layer within stacked semiconductor fins 108. Isolation recess 1250 substantially exposes all of sub-fin portion 111, whereas isolation recess 1250 does not expose sub-fin portion 112.

[0089] Returning to Figure 11 , Method 1101 continues at operation 1130, where a first dielectric suitable for introducing fixed charges of a first polarity is deposited over the sidewalls of the stacked semiconductor fins exposed by recessing the isolation dielectric. Generally, the first dielectric material contains fixed charges (i.e., immobile charges), which may be positive or negative charges depending on the bandgap of the dielectric material and on how the dielectric material was formed / processed. The concentration of fixed charges in the first dielectric material is higher than the concentration associated with unintentional fixed charges that may otherwise be present in such a material. For example, the concentration of fixed charges in the first dielectric material can be 10 12 or more per square centimeter. Positive fixed charges can be generated when there are donor-type unoccupied electron states in the first dielectric layer, which have an energy higher than the conduction band of the adjacent sub-fin semiconductor. Similarly, negative fixed charges can be generated when there are acceptor-type occupied electron states in the first dielectric layer, which have an energy lower than the valence band of the sub-fin semiconductor.

[0090] In an exemplary embodiment where the first semiconductor layer is suitable for an N-type FET, the first dielectric material contains fixed negative (electron) charges. In the case where the first dielectric material has negative fixed charges, the mobile electrons that may be present in the fin portion of the first semiconductor layer will repel the negative fixed charges (e.g., by Coulomb force), thereby causing depletion of the mobile electrons from the fin portion of the first semiconductor layer (or attraction of positive charge hole-type carriers in an adjacent semiconductor region), where the negative fixed charges are adjacent to the sidewalls of the fin portion of the first semiconductor layer, and the fin portion of the first semiconductor layer is suitable for an FET channel in which electrons are the majority carriers (i.e., an N-type FET). In an alternative embodiment where the first semiconductor layer is suitable for a P-type FET, the first dielectric material contains fixed positive (hole) charges. In the case where the first dielectric material has positive fixed charges, any mobile carriers present in the fin portion of the first semiconductor layer will attract or repel the positive fixed charges (e.g., by Coulomb force), thereby causing depletion of the mobile holes / migration of electrons in the fin portion of the first semiconductor layer, where the positive fixed charges are adjacent to the sidewalls of the fin portion of the first semiconductor layer, and the fin portion of the first semiconductor layer is suitable for an FET channel in which holes are the majority carriers (i.e., a P-type FET). Thus, there are fewer (if any) mobile carriers present in the fin portion that can penetrate into the second semiconductor layer (where they can contribute to leakage current). Therefore, the first dielectric layer can significantly reduce current leakage from the first FET fabricated in the first semiconductor layer of the stacked semiconductor fins to the second FET fabricated in the second semiconductor layer of the stacked semiconductor fins.

[0091] In Figure 12C the example shown, the fixed charge layer 1221 is deposited over the exposed sidewalls of the stacked semiconductor fins 108, and more specifically over at least the fin portion 111. The fixed charge layer 1221 can include one or more dielectric material layers such as, but not limited to, SiO x , SiN x , AlO x , LaO x , ZrO x , TaO x , GaO x , GdO x or HfO xAll of SiO2, Si3N4, Al2O3, La2O3, ZrO2, Ta2O5, Ga2O3, and Gd2O3. These materials can have a sufficiently large valence band offset with various semiconductor materials (such as Si, SiGe, InGaAs) to be suitable for providing negative fixed charges. The stoichiometry of the fixed charge layer can be varied, and / or the suitability of the various materials of the above exemplary materials can vary with the polarity of the FET to be fabricated within the exposed portion of the semiconductor fin. The fixed charge layer 1221 can be deposited to any thickness sufficient to achieve proper electrical isolation. In some embodiments, the fixed charge layer 1221 is at least 5 nm and can be between 7 nm and 10 nm, for example, where a greater thickness increases the amount of fixed charge and provides a higher level of carrier depletion within the semiconductor fin.

[0092] Then, the fixed charge layer 1221 can be confined adjacent to the sidewalls of the sub-fin portion 111. In some embodiments, an isolation dielectric can be deposited over the fixed charge layer 1221. As needed, before depositing the dielectric material 183 that can fill the space between adjacent fins, the fixed charge layer 1221 can be anisotropically etched to form fixed charge spacers 1231. The dielectric material 183 can also be planarized with the top surface of the stacked semiconductor fins 108. Once planarized, any recess etching process (such as isotropic or anisotropic, wet or dry) can be used to recess the dielectric material 183 to a predetermined level for the interface between the channel portion 121 and the sub-fin portion 111. Then, any exposed portions of the fixed charge layer remaining after the recess etching of the dielectric material 183 can be removed from the semiconductor fins. In Figure 12D the example shown, the dielectric material 183 has been recessed to remain adjacent only to the sub-fin portion 111. Then, the dielectric material 183 acts as a mask protecting a portion of the fixed charge spacer 1231 adjacent to the sole sub-fin portion 111. The portion of the fixed charge spacer 1231 not protected by the dielectric material 183 is removed (etched).

[0093] Returning to Figure 11 , method 1101 continues at operation 1140, where another dielectric material is deposited over the exposed portions of the stacked semiconductor fins, for example, in preparation for the fabrication of the first gate stack. In Figure 12E the example shown, the dielectric material 181 is deposited over the fin portion 121, thereby filling the space between adjacent fins. The dielectric material 181 is further planarized with the top surface of the stacked semiconductor fins 108. At this point in the fabrication process, the gate electrode 131 can be fabricated, for example, in accordance with any suitable technique, to be coupled to the channel portion 121. The other terminals of the first finFET can also be fabricated in accordance with any suitable technique, and one or more levels of interconnect metallization can couple multiple first finFETs together into an integrated circuit.

[0094] Return to Figure 11 , method 1101 continues at operation 1150, where, for example, the bottom of the stacked semiconductor fins is exposed according to any of the techniques described elsewhere herein. At operation 1160, the dielectric material surrounding the semiconductor fins is exposed, for example, using any etching process suitable for a dielectric composition having sufficient selectivity to a particular semiconductor composition. In the example shown in Figure 12F , the dielectric material 180 has been completely removed, thereby exposing the dielectric material 183 and portions of the stacked semiconductor fins 108 that extend beyond the dielectric material 183.

[0095] Return to Figure 11 , method 1101 continues at operation 1170, where a second layer of dielectric material having an appropriate fixed charge is deposited over the sidewalls of the sub-fin portions. For some exemplary CMOS embodiments of FETs suitable for polar complementary polarities (e.g., PMOS) for the portions of the stacked semiconductor fins exposed at operation 1160, the fixed charge is advantageously a hole charge (+). As described above, a positive fixed charge can prevent majority carriers of the PMOS FET from passing through the sub-fin portions. Thus, the (e.g., positive) fixed charge introduced at operation 1170 can be complementary to the (e.g., negative) fixed charge introduced at operation 1130 to reduce the component of the leakage current between the top and bottom of the CMOS stacked finFET structure.

[0096] At Figure 12G the example shown, a fixed charge layer 1222 is deposited over the exposed sidewalls of the stacked semiconductor fins 108, and more specifically over at least the sub-fin portions 112. The fixed charge layer 1222 can include one or more dielectric material layers, such as but not limited to SiO x , SiN x , AlO x , LaO x , ZrO x , TaO x , GaO x , GdO x or HfO xAll of SiO2, Si3N4, Al2O3, La2O3, ZrO2, Ta2O5, Ga2O3, and Gd2O3. Many of these materials have a sufficiently large conduction band offset with various semiconductor materials (e.g., Si, SiGe, InGaAs) such that they are suitable for providing positive fixed charge. The stoichiometry of the fixed charge layer can be varied, and / or the suitability of the various materials of the above exemplary materials can vary with the polarity of the FETs to be fabricated within the exposed portion of the semiconductor fin. For example, for embodiments where holes, the majority carriers, traverse the channel portion 122 during operation of a P-type FET, tantalum pentoxide may be more suitable than gallium oxide. The fixed charge layer 1222 can be deposited to any thickness sufficient to achieve proper electrical isolation. In some embodiments, the fixed charge layer 1222 is at least 5 nm and can be between 7 and 10 nm, for example, where a greater thickness increases the amount of fixed charge and provides a higher level of carrier depletion within the semiconductor fin.

[0097] Then, the fixed charge layer 1222 can be confined adjacent to the sidewalls of the sub-fin portion 112 in a manner similar to the fixed charge layer 1221. In some embodiments, another dielectric material can be deposited over the fixed charge layer 1222 to fill the space between adjacent fins. As needed, the fixed charge layer 1222 can be anisotropically etched prior to depositing the dielectric material 183 to form a fixed charge spacer 1232. The dielectric material 183 can also be planarized with the top surface of the stacked semiconductor fins 108. Once planarized, any recess etch process (e.g., isotropic or anisotropic, wet or dry) can be used to recess the dielectric material 183 to a predetermined level for the interface between the channel portion 122 and the sub-fin portion 112. Any exposed portions of the fixed charge layer remaining after the recess etch can then be removed from the semiconductor fins. Method 1101 continues at operation 1180 where another dielectric material is deposited over the exposed portions of the stacked semiconductor fins, e.g., in preparation for the fabrication of a second gate stack. Then, method 1101 ( Figure 11 ) is completed at operation 260 where transistor terminals can be fabricated and interconnected into the IC.

[0098] Figure 12H An example of a stacked CMOS finFET is shown having the features described above in the context of the stacked CMOS finFET structure 101 and further including fixed charge spacers suitable for electrical isolation. Figure 12HIn [description], the dielectric material 184 is recessed to remain adjacent only to the sub-fin portion 111. Then, the dielectric material 184 acts as a mask to protect the fixed charge spacer 1232 that is adjacent only to the sub-fin portion 112. The portion of the fixed charge spacer 1232 that is not protected by the isolation dielectric 184 has been removed (etched). The dielectric material 182 has been deposited over the channel portion 122 to fill the space between adjacent fins. The dielectric material 182 may be planarized, for example, with the top surface of the stacked semiconductor fins 108. The fixed charge spacers 1231 and 1232 may be positioned adjacent to portions of the stacked semiconductor fins 108 that are subject to a high defect density. For example, the fixed charge spacers 1231 and 1232 may be incorporated into the vertical stacked CMOS finFET structure 101 (e.g., Figure 1C ) as an exemplary means of reducing the leakage current across the vertical height of the stacked semiconductor fins.

[0099] Figure 13 is a flow chart showing a method 1301 for electrically isolating stacked finFETs according to some alternative embodiments. The method 1301 may be considered a specific implementation of the method 1001. The method 1301 shows structural features that may improve the isolation between stacked CMOS finFETs and can be introduced using a unique front-end process. Notably, the isolation structure fabricated by the method 1301 can be substantially the same as the isolation structure fabricated by the method 1201. Figure 14A -14J is a cross-sectional view of a stacked finFET evolving as selected operations in the method shown in [description] are performed, according to some embodiments, which result in a stacked finFET structure having one or more of the features described above in the context of the stacked finFET structure 10 and further including an exemplary isolation structure. Figure 13 in the method shown.

[0100] First, referring to Figure 13 , the method 1301 begins at operation 1005, where a workpiece including stacked fins having at least first and second semiconductor layers is received. In some embodiments, the received workpiece includes stacked semiconductor fins that further include a first semiconductor layer suitable for an NMOS FET and a second semiconductor layer suitable for a PMOS FET. In some exemplary embodiments, the stacked semiconductor fins are surrounded by a dielectric material (e.g., STI material) or embedded in a dielectric material. In the example shown in Figure 14A , the stacked semiconductor fins 108 including the sub-fin portions 111 and 112 extend from the substrate 301. The dielectric material 180 is located in the space between adjacent stacked semiconductor fins 108. The substrate 301, the sub-fin portions 111 and 112, and the dielectric material 180 may have any of the compositions described previously. Returning to Figure 13, Method 1301 continues at operation 1320, where a portion of the dielectric material is selectively recessed relative to the stacked semiconductor fins. The recessing can be performed using a masked or maskless etch for a predetermined duration sufficient to expose two fin portions. In some embodiments, one of the exposed sub-fin portions is semiconductor material suitable for an N-type FET, and the other of the exposed sub-fin portions is semiconductor material suitable for a P-type FET. Any known isotropic or anisotropic etch process with favorable selectivity can be employed at operation 1320. In Figure 14B In the example shown, recess 1450 substantially exposes all of one semiconductor layer and only the sub-fin portion of a second semiconductor layer within stacked semiconductor fins 109. Although recess 1450 substantially exposes all of sub-fin portion 112, recess 1450 does not expose channel portion 122. Returning to Figure 13 , Method 1301 continues at operation 1330, where a first layer of dielectric material suitable for introducing fixed charges of a first polarity is deposited over the sidewalls of the stacked semiconductor fins exposed by the recessed isolation dielectric. Generally, the first layer of dielectric material contains fixed charges (i.e., immobile charges), which may be positive or negative charges depending on the bandgap of the dielectric material and on how the dielectric material was formed / processed. The concentration of fixed charges in the first layer of dielectric material is higher than the concentration associated with unintentional fixed charges that might otherwise be present in such material. For example, the concentration of fixed charges in the first layer of dielectric material can be 1×10 per square centimeter 12 or higher.

[0101] In an exemplary embodiment, the first layer of dielectric material deposited at operation 1330 introduces fixed positive (hole) charges. In Figure 14C In the example shown, fixed charge layer 1222 is deposited over the exposed sidewalls of stacked semiconductor fins 108, and more specifically over at least fin portion 112. Fixed charge layer 1222 can include one or more layers of dielectric material, such as, but not limited to, any of the dielectric material layers described above as suitable for providing positive fixed charges. The stoichiometry of fixed charge layer 1222 can vary, and / or the suitability of the various materials of the above-described exemplary materials can vary with the polarity of the FETs to be fabricated within the exposed portions of the semiconductor fins. Fixed charge layer 1222 can again be deposited to any thickness sufficient to achieve proper electrical isolation. In some embodiments, fixed charge layer 1222 is at least 5 nm and can be between 7 and 10 nm, for example where a greater thickness increases the amount of fixed charge and provides a higher level of carrier depletion within the semiconductor fins.

[0102] Then, fixed charge layer 1222 can be confined adjacent to the sidewalls of sub-fin portion 112. For example, method 1301 ( Figure 13)Continue with operations 1340 and 1350, where first the mask material around the recess is formed, and any of the fixed charge layers not protected by the mask material is removed. In Figure 14D In the example further shown in, a dielectric material 183 may be deposited over the fixed charge layer 1222. Optionally, before depositing the dielectric material 183 that can fill the space between adjacent fins, the fixed charge layer 1222 may be anisotropically etched to form fixed charge spacers 1231. The dielectric material 183 is planarized with the top surface of the stacked semiconductor fins 108. Once planarized, any recess etching process (e.g., isotropic or anisotropic, wet or dry) may be used to recess the dielectric material 183 to a predetermined level for the interface between sub-fin portions 111 and 112. Then any exposed portions of the fixed charge layer remaining after the recess etching may be removed from the semiconductor fins. In Figure 14E In the example shown in, the dielectric material 183 has been recessed to remain adjacent to only the sub-fin portion 112. Then, the dielectric material 183 acts as a mask protecting a portion of the fixed charge spacer 1232 adjacent to only the sub-fin portion 112. The portion of the fixed charge spacer 1232 not protected by the dielectric material 183 is removed (etched).

[0103] Returning to Figure 13 , method 1301 continues at operation 1360, where a second dielectric layer with an appropriate fixed charge is deposited over the sidewalls of the sub-fin portions. Any conformal or non-conformal deposition process known to be suitable for the particular dielectric material may be employed at operation 1360. For some exemplary CMOS embodiments of FETs suitable for polar complementary polarities (e.g., NMOS) for the portions of the stacked semiconductor fins exposed at operation 1360, the fixed charge is advantageously an electronic charge (-). As described above, the negative fixed charge may prevent majority carriers of the NMOS FET from passing through the sub-fin portions. Thus, the (e.g., negative) fixed charge introduced at operation 1360 may be complementary to the (e.g., positive) fixed charge introduced at operation 1330 to reduce the component of the leakage current between the top and bottom of the stacked CMOS finFET structure. In Figure 14F In the exemplary embodiment shown in, a fixed charge layer 1221 is deposited over the exposed semiconductor portions of the stacked semiconductor fins.

[0104] Then, the fixed charge layer 1221 can be restricted to be adjacent to the sidewall of the sub-fin portion 111 in a manner similar to the fixed charge layer 1222. For example, method 1301 continues at operation 1370, where a dielectric material is deposited over the fixed charge layer. This dielectric material can fill the space between adjacent fins. This dielectric material can also be planarized with the top surface of the stacked semiconductor fins. Once planarized, any recess etching process (e.g., isotropic or anisotropic, wet or dry) can be performed at operation 1380 to recess the dielectric material to a predetermined level. In Figure 14G In the example shown, the dielectric material 184 is recessed to a target that defines the interface of the channel portion 121 and the fin portion 111. Optionally, the fixed charge layer 1221 can be anisotropically etched to form a fixed charge spacer 1231 before depositing the dielectric material 184. Then, any exposed portion of the fixed charge layer remaining after the recess etching can be removed from the semiconductor fins. In Figure 14H In the example shown, the dielectric material 184 has been recessed to remain adjacent only to the sub-fin portion 111. Then, the dielectric material 184 acts as a mask to protect the fixed charge spacer 1231 that is adjacent only to the sub-fin portion 111. The portion of the fixed charge spacer 1231 that is not protected by the dielectric material 184 is removed (etched).

[0105] Returning to Figure 13 , method 1301 continues at operation 1390, where another dielectric material is deposited over the exposed portion of the stacked semiconductor fins, e.g., in preparation for fabricating a second gate stack. Then method 1301 is completed at operation 260, where transistor terminals can be fabricated and interconnected into the IC. In Figure 14H In the example shown, the dielectric material 182 has been deposited over the channel portion 122, thereby filling the space between adjacent fins. The dielectric material 182 can be planarized, for example, with the top surface of the stacked semiconductor fins 108. Figure 14I FIG. shows an example of a stacked CMOS finFET structure that has the features described above in the context of the stacked CMOS finFET structure 101 ( Figures 1A - 1B ), and further includes fixed charge spacers suitable for electrical isolation.

[0106] In some additional embodiments, two stacked fixed charge materials are separated by an intermediate barrier layer. The barrier layer can be used to decouple the two fixed charge materials, potentially mitigating unwanted interactions. Such a barrier layer can, for example, help maintain the chemical integrity of the compounds used as fixed charge layers. Such a barrier can, for example, limit the interdiffusion of the fixed charge layers and promote a more abrupt transition between sub-fin portions. Figure 15A further example of a stacked CMOS finFET structure is shown, which has the features described above in the context of the stacked CMOS finFET structure 101 and further includes fixed charge spacers separated by an intermediate barrier layer 1241. Figure 15 The structure shown in Figure 12H and Figure 14I is the same as the structure shown therein, except that the barrier layer 1241 is added. The barrier layer 1241 can be any material known as a suitable diffusion barrier, such as but not limited to a carbon-containing dielectric (e.g., SiC), a carbon-containing metal (e.g., TaC), an oxygen-containing dielectric (e.g., SiO, SiON), a metal layer (e.g., at least containing Ti, Ta, W), or a metal nitride (at least containing TiN, TaN, etc.). The barrier layer 1241 can be formed, for example, together with the fixed charge spacers 1231, 1232 in the implementation of method 1101 or method 1301.

[0107] The fabrication of the barrier layer 1241 and the fixed charge spacers 1231 and 1232 can also be integrated into the formation of the stacked semiconductor fins. For example, the fixed charge spacers 1231, 1232 and / or the barrier layer 1241 can be introduced before the epitaxial growth of one or more semiconductor fin portions. For example, in the structure shown in Figure 7C , the recess 750 can be lined with both the barrier layer 1241 and a layer of fixed charge material. Then, the fixed charge material can be anisotropically etched into the first spacer and then the barrier layer 1241 is etched to expose the crystalline seed surface to prepare for the epitaxial growth of the semiconductor.

[0108] The fabrication techniques described above for the fixed charge isolation structure can also be applied to alternative isolation embodiments that employ solid-state isolation well doping. For such embodiments, the resulting isolation structure can be the same as the structure described above, except that the sidewall spacer adjacent to the sub-fin portion is not a fixed charge source but rather a source of impurities that will diffuse into the adjacent sub-fin portions of the stacked semiconductor fins. Once doped and activated, the sub-fin portions of the stacked semiconductor can act as deep opposing doped "wells" that provide isolation between the channel portions of the fins. For the dielectric materials that act as the first and second impurity source films, the dielectric material surrounding the sub-fin portions is doped with electro-active impurities that are desired in the low sub-fin regions, such as but not limited to phosphorus, arsenic, antimony (n-type dopants for silicon), and boron, indium, or gallium (p-type dopants for silicon). As with the complementary types of fixed charges, complementary impurity doping can be achieved with two dielectric layers, each layer being restricted to be adjacent to only one sub-fin portion, for example, substantially as described above. Thus, the first impurity source material can be adjacent to the sidewall of the first sub-fin portion, while the second impurity source material is adjacent to the sidewall of the second sub-fin portion. The first impurity source material is doped with a first impurity that imparts a first conductivity type to the first sub-fin portion, and the second impurity source material is doped with a second impurity that imparts a second conductivity type to the second sub-fin portion. In some embodiments, boron-doped silicate glass (BSG) is deposited adjacent to the first sub-fin portion, while phosphorus-doped silicate glass (PSG) is deposited adjacent to the second sub-fin portion. Other options include doped nitrides and doped metal oxides.

[0109] In one exemplary embodiment, the first sub-fin portion that separates the P-type FET from the second sub-fin portion is impurity-doped N-type, where the impurities such as phosphorus, for example, have a concentration between 5x10 17 cm -3 and 1x10 19 cm -3 The adjacent impurity source material should have a sufficiently high as-deposited impurity concentration and film thickness to provide the desired impurity concentration within the first sub-fin portion. As an example, the impurity source material is a 1-5 nm thick PSG film doped with phosphorus to 1×10 20 -10 21 cm -3 The second sub-fin portion that separates the first sub-fin portion from the N-type FET is impurity-doped P-type, where the impurities such as boron, for example, reach a concentration between 5x10 17 cm -3 and 1x10 19 cm -3The impurity concentration therebetween. Adjacent impurity source materials should have a sufficiently high deposited impurity concentration and film thickness to provide the desired impurity concentration within adjacent sub-fin portions. As an example, the impurity source film material can be a 1 - 5 nm thick BSG film doped with boron to 1×10 20 -10 21 cm -3 .

[0110] In some additional embodiments, two stacked dielectric materials doped with acceptor and donor impurities are separated by an intermediate barrier layer. The barrier layer can be substantially as described above in the context of the fixed charge layer to decouple the two impurity dopant source materials, potentially mitigating unwanted interactions. Such a barrier layer can, for example, help maintain the chemical integrity of the compounds used as impurity dopant source materials. Such a barrier can, for example, limit the interdiffusion of impurity dopants and promote a more abrupt transition between sub-fin portions.

[0111] As described above, ion implantation can also be used to provide isolation between two stacked finFETs. Ion implantation can be performed from the front of the wafer, the back of the wafer, or from both sides. Ion implantation can be performed during what would typically be a retro-well or threshold voltage adjustment implantation, after fin recess, or before isolation dielectric deposition, or any combination thereof. Figure 16 is a flowchart showing a method 1601 for electrically isolating stacked finFETs in accordance with some embodiments employing ion implantation. Figures 17A - 17C is a cross-sectional view of a stacked finFET evolving as selected operations in method 1601 are performed in accordance with some exemplary embodiments.

[0112] First referring to Figure 16 , method 1601 begins at operation 1005 by receiving a stacked semiconductor fin having at least first and second semiconductor layers, for example, substantially as described above. At operation 1620, a first impurity ion is implanted on a first side of a junction between the first and second semiconductor layers. At operation 1630, a second impurity ion is implanted on a second side of the junction between the first and second semiconductor layers. Then, transistor terminals are completed at operation 260 and interconnected into the IC.

[0113] In the example shown in Figure 17A , the first impurity is implanted into an individual fin, and more specifically into sub-fin portion 112. The type of impurity implanted into sub-fin portion 112 depends on the polarity of the device to be formed in channel portion 122. For example, in the case where an N-type FET is to be formed in channel portion 122, the impurity implanted into sub-fin portion 112 can be any acceptor component suitable for making sub-fin portion 112 P-type. In one such embodiment where sub-fin portion 112 is a Group-IV semiconductor, arsenic or boron is implanted. AsFigure 17B As further shown, a second impurity is implanted into the individual fin, and more specifically into the sub-fin portion 111. The type of impurity implanted into the sub-fin portion 111 depends on the polarity of the device to be formed in the channel portion 121. For example, in the case where a P-type FET is to be formed in the channel portion 121, the impurity implanted into the sub-fin portion 111 can be any one suitable for making the sub-fin portion 112 N-type. In one such embodiment where the sub-fin portion 111 is a Group-IV semiconductor, phosphorus is implanted. After implantation, activation annealing can be performed, for example, according to any technique known to be suitable for doping semiconductor fins. Figure 17C An example of a stacked CMOS finFET is shown having the features described above in the context of the stacked CMOS finFET structure 101 ( Figures 1A - 1B ), and further highlighting counter doping of impurities for electrical isolation within the transistor stack.

[0114] In an alternative to method 1601, two sub-fin portions can be implanted through a dielectric material that is flush with the top of the fin. Then, the implantation range of one component is targeted to be deeper than the implantation range of the second component. Any of these isolation techniques can be used to form an electrical isolation structure in a stacked CMOS finFET structure according to embodiments herein.

[0115] Figure 18 A system 1800 is shown, in which a mobile computing platform 1805 and / or a data server machine 1806 employs circuitry including at least one stacked CMOS finFET according to some embodiments. The server machine 1806 can be any commercial server, such as any number of high-performance computing platforms arranged within a rack and interconnected for electronic data processing, which includes circuitry 1850 in this exemplary embodiment. The mobile computing platform 1805 can be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, etc. For example, the mobile computing platform 1805 can be any one of a tablet, a smart phone, a laptop computer, etc., and can include a display screen (such as a capacitive, inductive, resistive, or optical touch screen), a chip-level or package-level integrated system 1810, and a battery 1815.

[0116] Whether disposed within the integrated system 1810 shown in the expanded view 1820 or as a stand-alone packaged chip within the server machine 1806, the IC includes at least one III-N heterostructure diode as described elsewhere herein, for example. The circuitry 1850 may be further fixed to a board, substrate, or inserter 1860 together with a power management integrated circuit (PMIC). Functionally, the PMIC 1830 may perform battery power regulation, DC-DC conversion, etc., and thus has an input coupled to the battery 1815 and an output that provides a current supply to other functional modules.

[0117] In some embodiments, the circuitry 1850 includes a RF (radio frequency) integrated circuit (RFIC), which further includes a broadband RF (radio frequency) transmitter and / or receiver (TX / RX includes a digital baseband and an analog front-end module, which includes a power amplifier in the transmit path and a low-noise amplifier in the receive path). The RFIC includes at least one stacked CMOS finFET in an overvoltage protection circuit as described elsewhere herein, for example. The RFIC has an output coupled to an antenna (not shown) to enable any one of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocol represented as 3G, 4G, 5G, and above.

[0118] Figure 19 is a functional block diagram of a computing device 1900 arranged in accordance with at least some implementations of the present disclosure. The computing device 1900 may be present, for example, within the platform 1805 or the server machine 1806. The device 1900 further includes a motherboard 1902 that hosts a plurality of components, such as but not limited to a processor 1904 (e.g., an application processor), which may further incorporate at least one stacked CMOS finFET in accordance with an embodiment of the present invention. The processor 1904 may be physically and / or electrically coupled to the motherboard 1902. In some examples, the processor 1904 includes an integrated circuit die encapsulated within the processor 1904. Generally, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may also be stored in registers and / or memory.

[0119] In various examples, one or more communication chips 1906 may also be physically and / or electrically coupled to the motherboard 1902. In additional implementations, the communication chip 1906 may be a component of the processor 1904. Depending on its application, the computing device 1900 may include other components, which may or may not be physically and electrically coupled to the motherboard 1902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chip sets, antennas, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, photographic devices, and mass storage devices (e.g., hard disk drives, solid state drives (SSDs), compact discs (CDs), digital versatile discs (DVDs), etc.). The communication chip 1906 may implement wireless communication for transferring data to / from the computing device 1900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transfer data by using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 1906 may implement any of a variety of wireless standards or protocols, including but not limited to those described elsewhere in this document. As discussed, the computing device 1900 may include multiple communication chips 1906. For example, a first communication chip may be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0120] Although certain features presented herein have been described with reference to various implementations, the description should not be construed in a limiting sense. Accordingly, various modifications to the implementations described herein, as well as other implementations that are apparent to those skilled in the art to which the present disclosure pertains, are considered to be within the spirit and scope of the present disclosure.

[0121] It will be recognized that the present invention is not limited to the embodiments so described, but is capable of being practiced with modifications and alterations without departing from the scope of the appended claims. For example, the above-described embodiments may include specific combinations of features as further provided below.

[0122] In one or more first examples, a transistor structure includes a fin that includes a first layer of semiconductor material beneath or above a second layer of semiconductor material. The transistor structure includes a first gate stack above one or more sidewalls of the fin and adjacent to the first layer of semiconductor material, where the first gate stack includes a first gate electrode and a first gate dielectric layer. The transistor structure includes a first source terminal and a first drain terminal coupled to the first layer of semiconductor material and on opposite sides of the first gate stack, where the first source terminal and drain terminal include an N-type semiconductor. The transistor structure includes a second gate stack above one or more sidewalls of the fin and adjacent to the second layer of semiconductor material, where the second gate stack includes a second gate electrode and a second gate dielectric layer. The transistor structure includes a second source terminal and a second drain terminal coupled to the second layer of semiconductor and on opposite sides of the second gate stack, where the second source and drain terminals include a P-type semiconductor.

[0123] In one or more second examples, for any of the first examples, a centerline of the first gate electrode is vertically aligned with a centerline of the second gate electrode.

[0124] In one or more third examples, for any of the first to second examples, the fin has a total height equal to the sum of a first channel height, a second channel height, and a sub-fin height therebetween. The first channel height is equal to the height of the fin adjacent to the first gate stack. The second channel height is equal to the height of the fin adjacent to the first gate stack. The sub-fin height is equal to the vertical spacing between the first and second gate stacks.

[0125] In one or more fourth examples, for any of the first to third examples, the transistor structure includes a first layer of dielectric material adjacent to a sub-fin portion of the fin and between the first and second gate electrodes. The transistor structure includes a second layer of dielectric material adjacent to the first layer of dielectric material, adjacent to sidewalls of the first gate electrode, and adjacent to sidewalls of the second gate electrode.

[0126] In one or more fifth examples, for any of the fourth examples, the fin is a first fin, and the structure further includes: a second fin that includes a first layer of semiconductor material and a second layer of semiconductor material; a third gate stack above one or more sidewalls of the second fin and adjacent to the first layer of semiconductor material; and a fourth gate stack above one or more sidewalls of the second fin and adjacent to the second layer of semiconductor material. The first layer of dielectric material is adjacent to a sub-fin portion of the second fin between the third and fourth gate stacks. The second layer of dielectric material separates the first gate stack from the third gate stack and separates the second gate stack from the fourth gate stack. The second layer of dielectric material separates the first layer of dielectric material adjacent to the second fin from the first layer of dielectric material adjacent to the first fin.

[0127] In one or more sixth examples, for any of the fourth to fifth examples, a first layer of dielectric material is adjacent to a fin portion of a first layer of semiconductor material. The structure further includes a third layer of dielectric material that is adjacent to a fin portion of a second layer of semiconductor material. ， And a second layer of dielectric material is adjacent to both the first and third layers of dielectric material.

[0128] In one or more seventh examples, for any of the sixth examples, the first layer of dielectric material has fixed charges of a first polarity, while the third layer of dielectric material has fixed charges of a second polarity that is complementary to the first polarity.

[0129] In one or more eighth examples, for any of the sixth or seventh examples, the first layer of dielectric material has negative fixed charges, while the third layer of dielectric material has positive fixed charges. In one or more ninth examples, for any of the sixth or seventh examples, the first layer of dielectric material has a concentration of fixed charges of at least 1×10 per square centimeter 12 and the second layer of dielectric material has a concentration of fixed charges of at least 1×10 per square centimeter. 12

[0130] In one or more tenth examples, for any of the sixth examples, the first layer of dielectric material includes one or more acceptor impurities that are also present in the fin portion of the first layer of semiconductor material, and wherein the second layer of dielectric material includes one or more donor impurities that are also present in the fin portion of the second layer of semiconductor material. In one or more eleventh examples, for any of the eleventh examples, the second layer of dielectric material includes phosphorous doped silicate glass (PSG).

[0131] In one or more twelfth examples, for any of the sixth examples, the transistor structure further includes a barrier layer located between the first and second layers of dielectric material.

[0132] In one or more thirteenth examples, for any of the transistor structures in any of the first to twelfth examples 1-12, the first layer of semiconductor material includes a III-V semiconductor. The second layer of semiconductor material includes a Group-IV semiconductor.

[0133] In one or more fourteenth examples, a system includes an electronic memory and a processor coupled to the memory. The processor includes a CMOS circuit that includes a plurality of NMOS and PMOS field effect transistors (FETs). The first of the NMOS and PMOS FETs further includes the transistor structure of any of the first to thirteenth examples.

[0134] In one or more fifteenth examples, for any of the fourteenth examples, the system further includes a wireless communication antenna coupled to the processor and a battery coupled to at least one of the processor and the memory. In one or more sixteenth examples, the system includes a data storage component and a processing component. The processing component includes a CMOS circuit that includes a plurality of NMOS and PMOS field effect transistors (FETs). The first of the NMOS and PMOS FETs further includes: a fin that includes a first layer of semiconductor material below or above a second layer of semiconductor material; a first gate stack above one or more sidewalls of the fin and adjacent to the first layer of semiconductor material, where the first gate stack includes a first gate electrode and a first layer of gate dielectric material. The first of the NMOS and PMOS FETs further includes a first source terminal and a first drain terminal coupled to the first layer of semiconductor material and on opposite sides of the first gate stack, where the first source terminal and drain terminal include N-type semiconductor. The second of the NMOS and PMOS FETs further includes a second gate stack above one or more sidewalls of the fin and adjacent to the second layer of semiconductor material, where the second gate stack includes a second gate electrode and a second layer of gate dielectric material. The second of the NMOS and PMOS FETs further includes a second source terminal and a second drain terminal coupled to the second layer of semiconductor material and on opposite sides of the second gate stack, where the second source terminal and drain terminal include P-type semiconductor.

[0135] In one or more seventeenth examples, for any of the sixteenth examples, the first layer of semiconductor material includes a III-V semiconductor. The second layer of semiconductor material includes a Group-IV semiconductor. The fin has a total height equal to the sum of a first channel height, a second channel height, and a sub-fin height therebetween. The first channel height is equal to the height of the fin adjacent to the first gate stack. The second channel height is equal to the height of the fin adjacent to the first gate stack. The sub-fin height is equal to the vertical spacing between the first and second gate stacks.

[0136] In one or more eighteenth examples, for any of the sixteenth to seventeenth examples, the system further includes: a first layer of dielectric material adjacent to a sub-fin portion of a fin and between a first and a second gate electrode; and a second layer of dielectric material adjacent to the first layer of dielectric material, adjacent to sidewalls of the first gate electrode, and adjacent to sidewalls of the second gate electrode. In one or more nineteenth examples, a method of fabricating a transistor structure includes forming a fin that includes a first layer of semiconductor material below or above a second layer of semiconductor material. The method includes forming a gate mandrel over the fin. The method includes forming an isolation dielectric surrounding the gate mandrel and the fin. The method includes replacing a top portion of the gate mandrel with a first gate stack that includes a first layer of gate dielectric material and a first gate electrode. The method includes exposing a bottom portion of the gate mandrel. The method includes replacing the bottom portion of the gate mandrel with a second gate stack that includes a second layer of gate dielectric material and a second gate electrode. The method includes forming a first source terminal and a first drain terminal coupled to the first layer of semiconductor material and on opposite sides of the first gate stack, wherein the first source terminal and drain terminal include an N-type semiconductor. The method includes forming a second source terminal and a second drain terminal coupled to the first layer of semiconductor material and on opposite sides of the first gate stack, wherein the second source terminal and drain terminal include a P-type semiconductor.

[0137] In one or more twentieth examples, for any of the nineteenth examples, forming the gate mandrel further includes depositing a first layer of dielectric material over the fin, and replacing the top portion of the gate mandrel with the first gate stack further includes: forming a recess by selectively etching the first layer of dielectric material with respect to the first layer of semiconductor material, the recess exposing sidewalls of the first layer of semiconductor material; depositing the first layer of gate dielectric material within the recess and in contact with the sidewalls of the first layer of semiconductor material; and forming a gate electrode within the recess and in contact with the first layer of gate dielectric material.

[0138] In one or more twenty-first examples, replacing the top portion of the gate mandrel with the second gate stack further includes: forming a second recess by selectively etching the first layer of dielectric material with respect to the second layer of semiconductor material, the second recess exposing sidewalls of the second layer of semiconductor material; depositing the second layer of gate dielectric material within the second recess and in contact with the sidewalls of the second layer of semiconductor material; and forming a second gate electrode within the second recess and in contact with the second layer of gate dielectric material.

[0139] In one or more twenty-second examples, forming the fin further includes: forming a precursor fin that includes a first layer of semiconductor material; forming a mask material around the fin; forming a recess within the mask material by selectively recess-etching the first layer of semiconductor material with respect to the mask material; and epitaxially growing a second layer of semiconductor material within the recess.

[0140] In one or more twenty-third examples, a method of fabricating a transistor structure includes forming a first layer of a dielectric material over sidewalls of a sub-fin portion of a first layer of a semiconductor material. The method includes forming a second layer of a dielectric material over sidewalls of a sub-fin portion of a second layer of a semiconductor material. The method includes forming a first gate stack over sidewalls of a channel portion of the first layer of the semiconductor material, wherein the first gate stack includes a first layer of a gate dielectric material and a first gate electrode. The method includes forming a second gate stack over sidewalls of a channel portion of the second layer of the semiconductor material, wherein the second gate stack includes a second layer of a gate dielectric material and a second gate electrode, and the channel portions of the first and second layers of the semiconductor material are separated by the sub-fin portions of the first and second layers of the semiconductor material. The method includes forming a first source terminal and a first drain terminal coupled to the first layer of the semiconductor material and on opposite sides of the first gate stack, wherein the first source terminal and the drain terminal include an N-type semiconductor. The method includes forming a second source terminal and a second drain terminal coupled to the first layer of the semiconductor material and on opposite sides of the first gate stack, wherein the second source terminal and the drain terminal include a P-type semiconductor.

[0141] In one or more twenty-fourth examples, for any of the twenty-third examples, the first layer of the dielectric material has a negative fixed charge, and the third layer of the dielectric material has a positive fixed charge.

[0142] In one or more twenty-fifth examples, for any of the twenty-third to twenty-fourth examples, the first layer of the dielectric material includes one or more acceptor impurities that are also present in the sub-fin portion of the first layer of the semiconductor material, and wherein the second layer of the dielectric material includes one or more donor impurities that are also present in the sub-fin portion of the second layer of the semiconductor material.

[0143] However, the above embodiments are not limited to this aspect, and in various implementations, the above embodiments may include only a subset of such features, a different order of such features, a different combination of such features, and / or additional features other than those explicitly listed. Accordingly, the scope of the present invention should be determined with reference to the appended claims along with the full scope of equivalents to which such claims are entitled.

Claims

1. A transistor structure, comprising: a fin, the fin comprising a first layer of semiconductor material below or above a second layer of semiconductor material; a first gate stack on one or more sidewalls of the fin and adjacent to the first layer of semiconductor material, wherein the first gate stack comprises a first gate electrode and a first gate dielectric layer; a first source terminal and a first drain terminal, the first source terminal and the first drain terminal being coupled to the first layer of semiconductor material and on opposite sides of the first gate stack, wherein the first source and drain terminals comprise an N-type semiconductor; a second gate stack on one or more sidewalls of the fin and adjacent to the second layer of semiconductor material, wherein the second gate stack comprises a second gate electrode and a second gate dielectric layer; and a second source terminal and a second drain terminal, the second source terminal and the second drain terminal being coupled to the second layer of semiconductor material and on opposite sides of the second gate stack, wherein the second source and drain terminals comprise a P-type semiconductor, wherein a center line of the first gate electrode is vertically aligned with a center line of the second gate electrode.

2. The transistor structure of claim 1, wherein: the fin has a total height equal to the sum of a first channel height, a second channel height, and a sub-fin height therebetween; the first channel height is equal to the height of the fin adjacent to the first gate stack; the second channel height is equal to the height of the fin adjacent to the second gate stack; and the sub-fin height is equal to a vertical spacing between the first and second gate stacks.

3. The transistor structure of claim 1, further comprising: a first layer of dielectric material, adjacent to a sub-fin portion of the fin and between the first and second gate electrodes; and a second layer of dielectric material, adjacent to the first layer of dielectric material, adjacent to sidewalls of the first gate electrode, and adjacent to sidewalls of the second gate electrode.

4. The transistor structure of claim 3, wherein the fin is a first fin, and the structure further comprises: a second fin, comprising the first layer of semiconductor material and the second layer of semiconductor material; a third gate stack on one or more sidewalls of the second fin and adjacent to the first layer of semiconductor material; a fourth gate stack on one or more sidewalls of the second fin and adjacent to the second layer of semiconductor material; and wherein: the first layer of dielectric material is adjacent to a sub-fin portion of the second fin located between the third and fourth gate stacks; the second layer of dielectric material separates the first gate stack from the third gate stack and separates the second gate stack from the fourth gate stack; and the second layer of dielectric material separates the first layer of dielectric material adjacent to the second fin from the first layer of dielectric material adjacent to the first fin.

5. The transistor structure of claim 3, wherein: the first layer of dielectric material is adjacent to a sub-fin portion of the first layer of semiconductor material; the structure further comprises a third layer of dielectric material adjacent to a sub-fin portion of the second layer of semiconductor material; and The second layer of the dielectric material is adjacent to the first layer and the third layer of the semiconductor material.

6. The transistor structure according to claim 5, wherein the first layer of the dielectric material has fixed charges of a first polarity, and the third layer of the dielectric material has fixed charges of a second polarity complementary to the first polarity.

7. The transistor structure according to claim 6, wherein the first layer of the dielectric material has negative fixed charges, and the third layer of the dielectric material has positive fixed charges.

8. The transistor structure according to claim 6, wherein the first layer of the dielectric material has a concentration of fixed charges of at least 10 per square centimeter 12 , and the second layer of the dielectric material has a concentration of fixed charges of at least 10 12 per square centimeter.

9. The transistor structure according to claim 5, wherein the first layer of the dielectric material includes one or more acceptor impurities, and the one or more acceptor impurities are also present in the sub-fin portion of the first layer of the semiconductor material, and wherein the second layer of the dielectric material includes one or more donor impurities, and the one or more donor impurities are also present in the sub-fin portion of the second layer of the semiconductor material.

10. The transistor structure according to claim 6, wherein the second layer of the dielectric material includes phosphorus-doped silicate glass (PSG).

11. The transistor structure according to claim 5, further comprising a barrier layer between the first layer and the second layer of the dielectric material.

12. The transistor structure according to any one of claims 1-11, wherein: The first layer of the semiconductor material includes a III-V semiconductor; and The second layer of the semiconductor material includes a group-IV semiconductor.

13. A system, comprising: An electronic memory; And A processor coupled to the memory, the processor including a CMOS circuit, the CMOS circuit including a plurality of NMOS and PMOS field effect transistors (FETs), wherein the first of the NMOS and PMOS FETs further includes the transistor structure according to any one of claims 1-12.

14. The system according to claim 13, further comprising: A wireless communication antenna, coupled to the processor; And A battery, coupled to at least one of the processor and the memory.

15. A system, comprising: A data storage component; And A processing component, the processing component including a CMOS circuit, the CMOS circuit including a plurality of NMOS and PMOS field effect transistors (FETs), wherein the NMOS FET further includes: A fin, the fin including a first layer of semiconductor material below or above a second layer of semiconductor material; A first gate stack above one or more sidewalls of the fin and adjacent to the first layer of the semiconductor material, wherein the first gate stack includes a first gate electrode and a first layer of gate dielectric material; A first source terminal and a first drain terminal, the first source terminal and the first drain terminal being coupled to the first layer of the semiconductor material and on opposite sides of the first gate stack, wherein the first source and drain terminals include an N-type semiconductor; and Wherein the PMOS FET further includes: A second gate stack above one or more sidewalls of the fin and adjacent to the second layer of the semiconductor material, wherein the second gate stack includes a second gate electrode and a second layer of gate dielectric material; and A second source terminal and a second drain terminal, the second source terminal and the second drain terminal being coupled to the second layer of semiconductor material and on opposite sides of the second gate stack, wherein the second source and drain terminals comprise a P-type semiconductor, and wherein a centerline of the first gate electrode is vertically aligned with a centerline of the second gate electrode.

16. The system of claim 15, wherein: The first layer of semiconductor material comprises a III-V semiconductor; The second layer of semiconductor material comprises a Group-IV semiconductor; The fin has a total height equal to the sum of a first channel height, a second channel height, and a sub-fin height therebetween; The first channel height is equal to the height of the fin adjacent to the first gate stack; The second channel height is equal to the height of the fin adjacent to the second gate stack; and The sub-fin height is equal to the vertical spacing between the first and second gate stacks.

17. The system of claim 16, further comprising: A first layer of dielectric material, adjacent to a sub-fin portion of the fin and between the first and second gate electrodes; And A second layer of dielectric material, adjacent to the first layer of dielectric material, adjacent to sidewalls of the first gate electrode, and adjacent to sidewalls of the second gate electrode.

18. A method of fabricating a transistor structure, the method comprising: Forming a fin comprising a first layer of semiconductor material below or above a second layer of semiconductor material; Forming a gate core on the fin; Forming an isolation dielectric surrounding the gate core and the fin; Replacing a top portion of the gate core with a first gate stack comprising a first layer of gate dielectric material and a first gate electrode; Exposing a bottom portion of the gate core; Replacing the bottom portion of the gate core with a second gate stack comprising a second layer of gate dielectric material and a second gate electrode; Forming a first source terminal and a first drain terminal coupled to the first layer of semiconductor material and on opposite sides of the first gate stack, wherein the first source and drain terminals comprise an N-type semiconductor; And Forming a second source terminal and a second drain terminal coupled to the first layer of semiconductor material and on opposite sides of the first gate stack, wherein the second source and drain terminals comprise a P-type semiconductor.

19. The method of claim 18, wherein: Forming the gate core further comprises depositing a first layer of dielectric material on the fin; And Replacing the top portion of the gate core with the first gate stack further comprises: Forming a recess by selectively etching the first layer of dielectric material with respect to the first layer of semiconductor material, the recess exposing sidewalls of the first layer of semiconductor material; Depositing the first layer of gate dielectric material within the recess and in contact with the sidewalls of the first layer of semiconductor material; and Forming the gate electrode within the recess and in contact with the first layer of gate dielectric material.

20. The method of claim 19, wherein replacing the top portion of the gate core with the second gate stack further comprises: A second recess is formed by selectively etching the first layer of dielectric material over the second layer of semiconductor material, the second recess exposing sidewalls of the second layer of semiconductor material; Depositing the second layer of gate dielectric material within the second recess and in contact with the sidewalls of the second layer of semiconductor material; And Forming the second gate electrode within the second recess and in contact with the second layer of gate dielectric material.

21. The method of claim 19, wherein forming the fin further comprises: Forming a precursor fin comprising the first layer of semiconductor material; Forming a mask material around the fin; Forming a recess within the mask material by selectively recess-etching the first layer of semiconductor material through the mask material; And Epitaxially growing the second layer of semiconductor material within the recess.

22. A method of fabricating a transistor structure, the method comprising: Forming a first layer of dielectric material over sidewalls of a sub-fin portion of a first layer of semiconductor material; Forming a second layer of dielectric material over sidewalls of a sub-fin portion of a second layer of semiconductor material; Forming a first gate stack over sidewalls of a channel portion of the first layer of semiconductor material, wherein the first gate stack comprises a first layer of gate dielectric material and a first gate electrode; Forming a second gate stack over sidewalls of a channel portion of the second layer of semiconductor material, wherein the second gate stack comprises a second layer of gate dielectric material and a second gate electrode, and wherein the channel portions of the first and second layers of semiconductor material are separated by the sub-fin portions of the first and second layers of semiconductor material; Forming a first source terminal and a first drain terminal coupled to the first layer of semiconductor material and on opposite sides of the first gate stack, wherein the first source and drain terminals comprise an N-type semiconductor; And Forming a second source terminal and a second drain terminal coupled to the first layer of semiconductor material and on opposite sides of the first gate stack, wherein the second source and drain terminals comprise a P-type semiconductor.

23. The method of claim 22, wherein the transistor structure further comprises a third layer of dielectric material adjacent to the sub-fin portion of the second layer of semiconductor material, wherein the first layer of dielectric material has a negative fixed charge and the third layer of dielectric material has a positive fixed charge.

24. The method of claim 22, wherein the first layer of dielectric material comprises one or more acceptor impurities that are also present in the sub-fin portion of the first layer of semiconductor material, and wherein the second layer of dielectric material comprises one or more donor impurities that are also present in the sub-fin portion of the second layer of semiconductor material.

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