Transistor, method for manufacturing transistor, and display device using the same

Abstract

The transistor of the present invention comprises: an oxide semiconductor layer, which is arranged on a substrate and includes a first region close to the substrate, and a second region arranged on the surface of the first region opposite to the substrate side and having a carrier concentration lower than that of the first region; a first gate electrode, which has a region overlapping with the oxide semiconductor layer and is arranged on the surface of the oxide semiconductor layer opposite to the substrate side; a first insulating layer located between the first gate electrode and the oxide semiconductor layer; and a first oxide conductive layer and a second oxide conductive layer, which are arranged between the oxide semiconductor layer and the substrate and include a region in contact with the oxide semiconductor layer.

Description

[0001] [Cross-reference to related applications]

[0002] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2018-180487, filed on September 26, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One embodiment of the present invention relates to a transistor including an oxide semiconductor, a method for manufacturing the same, and a display device in which pixels are formed using the transistor including the oxide semiconductor. Background Art

[0004] Active-matrix display devices have a display element and a transistor that drives the display element in each pixel. Display elements include liquid crystal elements (LC elements) in which a liquid crystal layer is provided between a set of electrodes, and organic electroluminescent elements (hereinafter referred to as "organic EL elements") in which a layer containing an organic electroluminescent material is provided between electrodes called cathodes and anodes. Transistors include thin-film transistors using amorphous silicon semiconductors or polycrystalline silicon semiconductors, and in recent years, thin-film transistors using oxide semiconductors.

[0005] Although amorphous silicon semiconductor films can be easily formed on large-area substrates, there is a problem of low field-effect mobility when forming thin-film transistors. On the other hand, although thin-film transistors made using polycrystalline silicon semiconductor films have high field-effect mobility, due to the necessary crystallization processes such as laser annealing, it is difficult to form uniform polycrystalline for large-area substrates, and there is a problem of uneven threshold voltage. Thin-film transistors made using oxide semiconductors have high field-effect mobility compared to those made using amorphous silicon semiconductor films. In addition, compared to the case of using polycrystalline silicon semiconductors to make thin-film transistors, it has the advantages of being easy to cope with large-area substrates and not requiring a crystallization process. However, oxide semiconductor films have problems such as changing composition depending on film formation conditions or thin-film transistor manufacturing conditions, causing defects, and thus easily changing electrical characteristics.

[0006] For example, JP Patent Gazette No. 2010-153842 discloses that in a thin film transistor using a first oxide semiconductor region as an active layer, a second oxide semiconductor region having a lower conductivity than the first oxide semiconductor and functioning as a protective layer is formed between the first oxide semiconductor region and a protective insulating layer of the thin film transistor, thereby preventing composition changes and film quality degradation in the first oxide semiconductor region and stabilizing the electrical characteristics of the thin film transistor. Summary of the Invention

[0007] A transistor according to one embodiment of the present invention comprises: an oxide semiconductor layer, which is arranged on a substrate and includes a first region close to the substrate, and a second region arranged on a surface of the first region opposite to the substrate side and having a carrier concentration lower than that of the first region; a first gate electrode, which has a region overlapping with the oxide semiconductor layer and is arranged on a surface of the oxide semiconductor layer opposite to the substrate side; a first insulating layer located between the first gate electrode and the oxide semiconductor layer; and a first oxide conductive layer and a second oxide conductive layer, which are arranged between the oxide semiconductor layer and the substrate and include a region in contact with the oxide semiconductor layer.

[0008] A display device according to one embodiment of the present invention includes a pixel including at least the above-mentioned transistor and a display element electrically connected to the transistor.

[0009] A method for manufacturing a transistor according to one embodiment of the present invention includes: forming a first oxide conductive layer and a second oxide conductive layer on a substrate; forming an oxide semiconductor layer, the oxide semiconductor layer including a first region in contact with the first oxide conductive layer and the second oxide conductive layer, and a second region arranged on a surface of the first region opposite to the substrate side and having a carrier concentration lower than that of the first region; forming a first insulating layer in a manner covering the oxide semiconductor layer; and forming a first gate electrode, the first gate electrode being arranged on the first insulating layer and having a region overlapping with the oxide semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional view showing the structure of a transistor according to one embodiment of the present invention;

[0011] Figure 2A and Figure 2B is an energy band diagram of an oxide semiconductor layer according to one embodiment of the present invention;

[0012] Figure 3 is a diagram showing electrical characteristics of a transistor according to one embodiment of the present invention;

[0013] Figure 4A and Figure 4B is a diagram illustrating a method for manufacturing a transistor according to one embodiment of the present invention. Figure 4A It shows the stage of forming the second insulating layer, the second conductive film, and the third conductive film. Figure 4B This indicates the stage of forming a photoresist film and performing exposure using a multi-stage photomask;

[0014] Figure 5A and Figure 5Bis a diagram illustrating a method for manufacturing a transistor according to one embodiment of the present invention. Figure 5A Indicates the stage of forming a photoresist mask, Figure 5B It shows the stage of etching the third conductive film and the second conductive film;

[0015] Figure 6A and Figure 6B is a diagram illustrating a method for manufacturing a transistor according to one embodiment of the present invention. Figure 6A It shows the stage of etching the third conductive film. Figure 6B represents a stage of forming an oxide semiconductor layer;

[0016] Figure 7A and Figure 7B is a diagram illustrating a method for manufacturing a transistor according to one embodiment of the present invention. Figure 7A It shows the stage of forming the first insulating layer and the fourth conductive film, Figure 7B Represents the structure of a transistor;

[0017] Figure 8 is a diagram illustrating a configuration of a display device according to an embodiment of the present invention;

[0018] Figure 9 An equivalent circuit of a pixel of a display device according to one embodiment of the present invention is shown;

[0019] Figure 10 A plan view illustrating a configuration of a pixel of a display device according to an embodiment of the present invention is shown;

[0020] Figure 11A and Figure 11B is a cross-sectional view showing the structure of a pixel of a display device according to one embodiment of the present invention. Figure 11A Indicates along Figure 10 The cross-sectional structure of the line A1-A2 shown in FIG. Figure 11B Indicates along Figure 10 The cross-sectional structure of B1-B2 shown;

[0021] Figure 12A The structure of a bottom-contact bottom-gate transistor and the influence of charge during operation are shown. Figure 12B Describe the structure of a top-contact bottom-gate transistor and the effects of charge during operation.

[0022] Figure 13 shows a cross-sectional structure of a transistor according to one embodiment of the present invention;

[0023] Figure 14 A plan view illustrating a method for manufacturing a display device according to an embodiment of the present invention is shown;

[0024] FIG15 is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figure 15A Indicates along Figure 14 The cross-sectional structure of the line A1-A2 shown in FIG. Figure 15B Indicates along Figure 14 The cross-sectional structure of B1-B2 shown;

[0025] FIG16 is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figure 16A Represents Figure 14 The cross-sectional structure of the area corresponding to the line A1-A2 shown, Figure 16B Represents Figure 14 The cross-sectional structure of the region corresponding to line B1-B2 is shown;

[0026] Figure 17 A plan view illustrating a method for manufacturing a display device according to an embodiment of the present invention is shown;

[0027] FIG18 is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figure 18A Indicates along Figure 17 The cross-sectional structure of the line A1-A2 shown in FIG. Figure 18B Indicates along Figure 17 The cross-sectional structure of B1-B2 shown;

[0028] Figure 19 A plan view illustrating a method for manufacturing a display device according to an embodiment of the present invention is shown;

[0029] FIG20 is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figure 20A Indicates along Figure 19 The cross-sectional structure of the line A1-A2 shown in FIG. Figure 20B Indicates along Figure 19 The cross-sectional structure of B1-B2 shown;

[0030] Figure 21 A plan view illustrating a method for manufacturing a display device according to an embodiment of the present invention is shown;

[0031] FIG22 is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figure 22A Indicates along Figure 21 The cross-sectional structure of the line A1-A2 shown in FIG. Figure 22B Indicates along Figure 21 The cross-sectional structure of B1-B2 shown;

[0032] FIG23 is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figure 23A Represents Figure 21 The cross-sectional structure of the area corresponding to the line A1-A2 shown, Figure 23B Represents Figure 21 The cross-sectional structure of the region corresponding to line B1-B2 is shown;

[0033] FIG24 is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figure 24A Represents Figure 21 The cross-sectional structure of the area corresponding to the line A1-A2 shown, Figure 24B Represents Figure 21 The cross-sectional structure of the region corresponding to line B1-B2 is shown;

[0034] Figures 25A to 25C A plan view showing a photomask used for manufacturing a display device according to an embodiment of the present invention;

[0035] Figure 26 is a cross-sectional view showing the structure of a transistor according to one embodiment of the present invention;

[0036] Figure 27 An equivalent circuit of a pixel of a display device according to one embodiment of the present invention is shown;

[0037] Figure 28 A plan view illustrating a configuration of a pixel of a display device according to an embodiment of the present invention is shown;

[0038] Figure 29A and Figure 29B is a cross-sectional view showing the structure of a pixel of a display device according to one embodiment of the present invention. Figure 29A Indicates along Figure 28 The cross-sectional structure of the line A1-A2 shown in FIG. Figure 29B Indicates along Figure 28 The cross-sectional structure of B1-B2 shown;

[0039] Figure 30A and Figure 30B 1 shows the structure of a transistor according to one embodiment of the present invention, Figure 30A and Figure 30B Represents the cross-sectional structure;

[0040] Figure 31A and Figure 31B A plan view showing a photomask used for manufacturing a display device according to an embodiment of the present invention;

[0041] Figure 32 is a cross-sectional view showing the structure of a transistor according to one embodiment of the present invention;

[0042] Figure 33is a cross-sectional view showing the structure of a transistor according to one embodiment of the present invention. DETAILED DESCRIPTION

[0043] Hereinafter, the embodiments of the present invention will be described with reference to the accompanying drawings and the like. However, the present invention includes a variety of different forms and should not be interpreted as being limited to the embodiments illustrated below. In the drawings attached to this specification, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically represented compared to the actual form, but this is only an example and does not necessarily limit the content of the present invention. In addition, in the present invention, when a specific element recorded in a certain drawing is the same as or corresponds to a specific element recorded in another drawing, the same symbol is sometimes marked (or a, b, etc. are marked after the number recorded as the symbol), and repeated descriptions are appropriately omitted. Furthermore, the words "first" and "second" marked on each element are convenient marks for distinguishing each element, and have no further meaning unless otherwise specified.

[0044] In this specification, when a component or region is located "above (or below)" another component or region, unless otherwise specified, this includes not only the case where it is located directly above (or below) the other component or region, but also the case where it is located above (or below) the other component or region. In other words, this also includes the case where another component is located between the above (or below) the other component or region and the component or region.

[0045] Oxide semiconductors are a type of compound semiconductor containing metal and oxygen. Therefore, in the manufacturing process of thin-film transistors, it is necessary to control the composition of the oxide semiconductor, control oxygen vacancies, and control impurities. The bottom-gate thin-film transistor element described in JP Patent Publication No. 2010-153842 has the following fatal disadvantages: the potential on the back channel side is easily affected by the common potential in liquid crystal display devices. In organic EL display devices, when an organic EL element with an inverted stacked structure is set in a pixel, the potential on the back channel side is easily affected by the positive potential of the anode electrode. Furthermore, when copper (Cu) is used for the source and drain electrodes, the copper (Cu) atoms mainly act as a carrier (electron) killer for the n-type oxide semiconductor. In the structure of JP Patent Publication No. 2010-153842, the problem of copper (Cu) atoms contaminating the channel region will occur. On the other hand, in order to control the characteristics of thin-film transistors by device structure, it is believed that, for example, the provision of a back gate is effective. However, thin-film transistors with a back gate have problems such as a complex structure and an increased number of photomasks required for manufacturing. In some of the embodiments described below, a form of a display device that can overcome one or more of these problems is shown.

[0046] First embodiment:

[0047] 1-1. Transistor Structure

[0048] Figure 1 The structure of a transistor 100 a according to one embodiment of the present invention is shown in a cross-sectional view. The transistor 100 a includes a second insulating layer 106 , an oxide semiconductor layer 112 , a first insulating layer 114 , and a first gate electrode 116 , which are provided on a substrate 102 having an insulating surface.

[0049] The first gate electrode 116 is disposed on one surface side of the oxide semiconductor layer 112 (the side opposite to the substrate 102). The first insulating layer 114 is disposed between the oxide semiconductor layer 112 and the first gate electrode 116. The first gate electrode 116 and the oxide semiconductor layer 112 are disposed so as to include an overlapping region with the first insulating layer 114 interposed therebetween. The transistor 100a forms a channel in the region where the oxide semiconductor layer 112 and the first gate electrode 116 overlap. The first insulating layer 114 functions as a gate insulating film in the region where the oxide semiconductor layer 112 and the first gate electrode 116 overlap.

[0050] A second insulating layer 106 is disposed between the oxide semiconductor layer 112 and the substrate 102. A first oxide conductive layer 108a and a second oxide conductive layer 108b are disposed between the oxide semiconductor layer 112 and the second insulating layer 106. The first oxide conductive layer 108a and the second oxide conductive layer 108b are disposed in contact with the oxide semiconductor layer 112. One end of the first oxide conductive layer 108a and one end of the second oxide conductive layer 108b are disposed so as to overlap with the first gate electrode 116. One of the first oxide conductive layer 108a and the second oxide conductive layer 108b functions as a source region, and the other functions as a drain region. Figure 1 In the structure shown, one end of the first oxide conductive layer 108 a and the second oxide conductive layer 108 b is arranged to overlap with the first gate electrode 116 , thereby preventing an offset region (region with high resistance) from being formed in the oxide semiconductor layer 112 , thereby increasing the on-current.

[0051] A first wiring 110a is provided in contact with the first oxide conductive layer 108a, and a second wiring 110b is provided in contact with the second oxide conductive layer 108b. The first wiring 110a is arranged between the first oxide conductive layer 108a and the oxide semiconductor layer 112, and the second wiring 110b is arranged between the second oxide conductive layer 108b and the oxide semiconductor layer 112. Providing the first wiring 110a and the second wiring 110b in contact with the first oxide conductive layer 108a and the second oxide conductive layer 108b, respectively, can reduce the number of photolithography steps as described below.

[0052] 1-2. Oxide semiconductor layer

[0053] The oxide semiconductor layer 112 is a transparent oxide semiconductor containing one or more elements selected from indium (In), zinc (Zn), gallium (Ga), tin (Sn), aluminum (Al), tungsten (W), and silicon (Si). For example, as the oxide semiconductor material forming the oxide semiconductor layer 112, a quaternary oxide material, a ternary oxide material, or a binary oxide material exhibiting semiconductor characteristics can be used. For example, as the quaternary oxide material, an In2O3-Ga2O3-SnO2-ZnO series oxide material can be used, and as the ternary oxide material, an In2O3-Ga2O3-SnO2 series oxide material, an In2O3-Ga2O3-ZnO series oxide material, an In2O3-SnO2-ZnO series oxide material, an In2O3-SnO2-ZnO series oxide material, an In2O3-Al2O3-ZnO series oxide material, a Ga2O3-SnO2-ZnO series oxide material, a Ga2O3-Al2O3-ZnO series oxide material, or a ZnO series oxide material can be used. Oxide materials, SnO2-Al2O3-ZnO series oxide materials, as binary oxide materials, In2O3-SnO2 series oxide materials, In2O3-ZnO series oxide materials, SnO2-ZnO series oxide materials, Al2O3-ZnO series oxide materials, Ga2O3-ZnO series oxide materials, SnO2-SiO2 series oxide materials, In2O3-W2O3 series oxide materials, etc. can be used, and In2O3-Ga2O3-SnO2 series oxide materials are particularly preferred. In addition, the above-mentioned oxide semiconductors may contain tantalum (Ta), scandium (Sc), nickel (Ni), lanthanum (La), magnesium (Mg), hafnium (Hf), yttrium (Y), and titanium (Ti). In addition, for example, the In-Ga-Sn-O series oxide material shown above is an oxide material containing at least In, Ga, and Sn, and its composition ratio is not particularly limited. The composition ratio of the In-Ga-Sn-O-based oxide material is preferably such that, relative to In, Ga, and Sn, the atomic composition percentage of In is 60 atm% to 70 atm%, the atomic composition percentage of Ga is 10 atm% to 25 atm%, and the atomic composition percentage of Sn is 5 atm% to 30 atm%. Alternatively, if another expression is used, the oxide semiconductor layer 112 may use a material having the chemical formula InMO3(ZnO) m (m>0). Here, M represents one or more metal elements selected from Sn, Ga, Zn, Sc, La, Y, Ni, Al, Mg, Ti, Ta, W, Hf, and Si. Furthermore, the quaternary oxide materials, ternary oxide materials, and binary oxide materials are not limited to those containing oxides having a stoichiometric composition, but may also be composed of oxide materials having a composition that deviates from the stoichiometric composition.

[0054] The oxide semiconductor layer 112 has a structure in which a first region 112-1 and a second region 112-2 are stacked from the substrate 102 side. The first region 112-1 is arranged on the first surface of the oxide semiconductor layer 112 that faces the substrate 102 side, and the second region is arranged on the second surface that is opposite to the first surface. In the oxide semiconductor layer 112, the thickness of the first region 112-1 is greater than the thickness of the second region 112-2. The thickness of the first region 112-1 of the oxide semiconductor layer 112 is preferably 30 nm to 100 nm. The thickness of the second region 112-2 of the oxide semiconductor layer 112 is preferably 2 nm to 10 nm. However, this is not limiting, and the thickness of the oxide semiconductor layer 112 including the first region 112-1 and the second region 112-2 can be 20 nm to 100 nm, for example, 30 nm to 60 nm.

[0055] In the oxide semiconductor layer 112, the first region 112-1 and the second region 112-2 have different carrier concentrations (majority carrier concentrations). The carrier concentration of the second region 112-2 is smaller than that of the first region 112-1. The carrier concentration of the first region 112-1 is preferably 1×10 15 / cm 3 ~5×10 18 / cm 3 The carrier concentration of the second region 112-2 is preferably 1×10 11 / cm 3 ~1×10 15 / cm 3 Accordingly, the conductivity of the first region 112-1 of the oxide semiconductor layer 112 is ideally 1×10 -5 S / cm to 10 S / cm. The conductivity of the second region 112-2 of the oxide semiconductor layer 112 is preferably 1×10 -10 S / cm~1×10 -5 Furthermore, the carrier mobility of the second region 112 - 2 of the oxide semiconductor layer 112 is preferably lower than the carrier mobility of the first region 112 - 1 of the oxide semiconductor layer 112 .

[0056] In addition, the oxide semiconductor layer 112 may have different crystallinity in the first region 112-1 and the second region 112-2. The crystallinity of the second region 112-2 of the oxide semiconductor layer 112 is preferably higher than that of the first region 112-1. The first region 112-1 of the oxide semiconductor layer 112 may be in an amorphous form or in a mixed phase of an amorphous and nanocrystalline phase. The second region 112-2 of the oxide semiconductor layer 112 may be in a nanocrystalline form or in a mixed phase of an amorphous and nanocrystalline phase. In this case, the mixing ratio of the microcrystalline phase in the second region 112-2 is higher than that in the first region 112-1, and the second region 112-2 may be in a mixed phase of a polycrystalline phase.

[0057] The oxide semiconductor layer 112 can be produced by sputtering. The first region 112-1 and the second region 112-2 can be produced by changing the sputtering conditions. For example, the first region 112-1 of the oxide semiconductor layer 112 is formed using a rare gas such as Ar as a sputtering gas, and the second region 112-2 is formed using a rare gas such as Ar and oxygen as a sputtering gas. By making the oxygen partial pressure during film formation of the second region 112-2 higher than that of the first region 112-1, the donor defects of the second region 112-2 can be reduced and the crystallization rate can be increased. As a result, the carrier concentration of the second region 112-2 can be reduced compared to the first region 112-1, thereby reducing the conductivity accordingly. In addition, by adding oxygen to the sputtering gas (by increasing the oxygen partial pressure) when forming the second region 112-2, a denser film (a film with a higher density) than the first region 112-1 can be formed.

[0058] The oxide semiconductor layer 112 can have the same composition as the first region 112-1 and the second region 112-2, but can be combined in such a way that the crystallinity differs. Alternatively, the oxide semiconductor layer 112 can use the same metal oxide in the first region 112-1 and the second region 112-2, but can be combined in such a way that the composition differs. Furthermore, metal oxides having different compositions can be combined in the first region 112-1 and the second region 112-2. By applying such a combination to the first region 112-1 and the second region 112-2, it is possible to achieve different carrier concentrations and different electrical conductivity.

[0059] Figure 2AAn example of an energy band diagram for the oxide semiconductor layer 112 when the first region 112-1 and the second region 112-2 have different crystallinity ratios is shown. For example, the oxide semiconductor layer 112 is formed of an In2O3-Ga2O3-ZnO-based oxide material. The first region 112-1 can be an amorphous region or a mixed region of amorphous and nanocrystals. The second region 112-2 can be a nanocrystal region or a mixed region of amorphous and nanocrystals. In this case, the nanocrystal component is preferably greater than that of the first region 112-1.

[0060] Even if the oxide semiconductor layer 112 has a single composition, the band gaps of the first region 112-1 and the second region 112-2 differ due to their different crystal structures. The band gap of the first region 112-1 is 2.8 eV to 3.0 eV, while the band gap of the second region 112-2 is 3.0 eV to 3.2 eV, with the band gap of the first region 112-1 being smaller than the band gap of the second region. Furthermore, as the crystallization rate differs, the work function of the first region 112-1 is greater than that of the second region 112-2. Therefore, in the energy band diagram of the bonded state of the first region 112-1 and the second region 112-2, the energy (Ec) at the bottom of the conduction band in the second region 112-2 is higher than that in the first region 112-1.

[0061] With reference to the structure of transistor 100a, the following is achieved: a second region 112-2 is provided between the first insulating layer 114 and the first region 112-1 to form an energy barrier for electrons in the conduction band. This structure enables transistor 100a to form a channel region at a location away from the interface between the first insulating layer 114 and the oxide semiconductor layer 112. By forming a buried channel in the oxide semiconductor layer 112 and making it operable, transistor 100a can prevent carriers (electrons) from being trapped at the interface between the first insulating layer 114 and the oxide semiconductor layer 112.

[0062] Figure 2B An example of an energy band diagram when the first region 112-1 and the second region 112-2 use oxide materials of different compositions is shown. For example, the first region 112-1 can be composed of In2O3-Ga2O3-SnO2-ZnO series oxide materials, In2O3-Ga2O3-SnO2 series oxide materials, and In2O3-Ga2O3-ZnO series oxide materials, and the second region 112-2 can be composed of Ga2O3 series oxide materials, GaSnO x Oxide materials, GaSiO xThe gallium oxide material is a wide bandgap material and can form a bandgap of 4 eV or more. For example, the bandgap of the In2O3-Ga2O3-SnO2 oxide material forming the first region 112-1 is 2.8 eV to 3.0 eV. In contrast, the bandgap of α-Ga2O3, an oxide material forming the second region 112-2, is 4.3 eV, and that of α-GaSnO is 4.8 eV. x The band gap of α-GaSiO is 4.0eV. x The band gap of the first region 112 - 1 is 4.5 eV or more, which can be increased by 1.0 eV or more compared with the first region 112 - 1 .

[0063] The oxide material constituting the first region 112-1 may further contain 2 to 5 atm% of silicon (Si). Including silicon in the oxide material constituting the first region 112-1 can increase the field-effect mobility of the transistor 100a and control the threshold voltage by improving heat resistance.

[0064] like Figure 2B As shown, the band gaps of the first region 112-1 and the second region 112-2, which are made of oxide semiconductor materials of different compositions, are different. The band gap of the first region 112-1 is smaller than the band gap of the second region 112-2, and the work function of the first region 112-1 is larger than the work function of the second region 112-2. Figure 2A Similarly, in the energy band diagram of the bonded state between the first region 112-1 and the second region 112-2, the energy (Ec) at the bottom of the conduction band in the second region 112-2 is higher than that in the first region 112-1. This structure allows the transistor 100a to form a channel region away from the interface between the first insulating layer 114 and the oxide semiconductor layer 112. In other words, the transistor 100a can prevent carriers (electrons) from being trapped at the interface between the first insulating layer 114 and the oxide semiconductor layer 112.

[0065] When the first region 112-1 and the second region 112-2 are formed of oxide semiconductor layers containing different elements, the band gap of the Ga oxide material forming the second region 112-2 only needs to be larger than that of the oxide material forming the first region 112-1 by at least 1 eV. For example, the first region 112-1 of the oxide semiconductor layer 112 may be formed of an In2O3-Ga2O3-ZnO-based oxide material, and the second region 112-2 may be formed of a Ga2O3-based oxide material.

[0066] When forming an oxide semiconductor layer by sputtering, the ion sheath annihilates at the stage of terminating the glow discharge. However, the sputtered particles that remain in the gas phase subsequently settle and form low-density regions, which may affect transistor characteristics. The transistor 100a according to this embodiment overcomes this problem by forming the first region 112-1 and the second region 112-2 in the oxide semiconductor layer 112.

[0067] In the transistor 100a, the oxide semiconductor layer 112 has a lower conductivity in the second region 112-2 than in the first region 112-1, thereby reducing carrier concentration and making it difficult for carriers to flow across the interface between the first insulating layer 114 and the oxide semiconductor layer 112. Furthermore, by making the crystallinity of the second region 112-2 higher than that of the first region 112-1, a dense film is formed. Furthermore, by making the band gap of the energy band of the second region 112-2 wider than that of the first region 112-1, a channel region is formed within the oxide semiconductor layer 112 (i.e., a buried-channel transistor is formed).

[0068] By having such a structure, the transistor 100a reduces the charge trapped at the interface between the first insulating layer 114 and the oxide semiconductor layer 112, prevents the threshold voltage from drifting, and realizes a normally-off transistor. In addition, by becoming a buried channel type, the transistor 100a can suppress the leakage current flowing through the interface between the first insulating layer 114 and the oxide semiconductor layer 112, thereby reducing the off current. In addition, as Figure 1 As shown, the first oxide conductive layer 108a and the second oxide conductive layer 108b forming the source region and the drain region are in contact with the first region 112-1 having high conductivity, thereby increasing the on-current. 9 to 1×10 12 The ratio of the on-current to the off-current (on-off ratio) is about 100%.

[0069] Furthermore, an intermediate region of the oxide semiconductor in which the carrier concentration changes stepwise or continuously may exist between the first region 112-1 and the second region 112-2. Furthermore, the intermediate region of the oxide semiconductor may be formed in the same oxide semiconductor layer as the first region 112-1 and the second region 112-2, or may be formed separately as a different oxide semiconductor layer.

[0070] 1-3. Oxide conductive layer

[0071] The first oxide conductive layer 108a and the second oxide conductive layer 108b are made of a conductive metal oxide material, a metal nitride material, or a metal oxynitride material. Examples of metal oxide materials include indium tin oxide (In2O3·SnO2: ITO), indium tin zinc oxide (In2O3·SnO2·ZnO: ITZO), indium tin silicon oxide (In2O3·SnO2·SiO2: ITSO), tin oxide (SnO2), aluminum zinc tin oxide (Al2O3·ZnO·SnO2: AZTO), gallium zinc tin oxide (Ga2O3·ZnO·SnO2: GZTO), zinc tin oxide (ZnO·SnO2: ZTO), and gallium tin oxide (Ga2O3·SnO2: GTO). These metal oxide materials can form a good ohmic contact with the first region 112-1 of the oxide semiconductor layer 112.

[0072] In addition, as the metal oxide material for the first oxide conductive layer 108a and the second oxide conductive layer 108b, titanium oxide (TiO x ) etc.; As metal nitride materials, titanium nitride (TiN x ), zirconium nitride (ZrN x ) etc.; As metal nitride oxide materials, titanium oxynitride (TiO x N y ), tantalum oxynitride (TaO x N y ), zirconium oxynitride (ZrO x N y ), Hafnium Oxynitride (HfO x N y ) etc. In addition, a trace amount of metal elements that improve conductivity can be added to these metal oxide materials, metal nitride materials, and metal oxynitride materials. For example, niobium-doped titanium oxide (TiOx: Nb) can also be used. TiSiO x High-melting-point metal silicon oxides such as silicon oxides. By using such metal oxide materials, metal nitride materials, or metal oxynitride materials exhibiting n-type conductivity, stability can be ensured even when in contact with the first wiring 110a and the second wiring 110b. Specifically, by using such metal oxide materials, metal nitride materials, or metal oxynitride materials, redox reactions (localized battery reactions) with aluminum (Al), which has a low potential, can be prevented.

[0073] 1-4. Insulation layer

[0074] The second insulating layer 106 and the first insulating layer 114 are formed using an inorganic insulating material. As the inorganic insulating material, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc. can be applied. The second insulating layer 106 and the first insulating layer 114 have a single-layer film structure composed of these inorganic insulating materials or a structure in which a multilayer film is stacked. For example, as the second insulating layer 106, a structure in which a silicon nitride film and a silicon oxide film are stacked from the substrate 102 side can be applied. In addition, the first insulating layer 114 can apply a structure in which a silicon oxide film and a silicon nitride film are stacked from the oxide semiconductor layer 112 side. By stacking multiple inorganic insulating films in this way, the second insulating layer 106 and the first insulating layer 114 can alleviate the effect of internal stress and improve the barrier properties against water vapor, etc.

[0075] Furthermore, the surfaces of the second insulating layer 106 and the first insulating layer 114 that are in contact with the oxide semiconductor layer 112 are preferably formed of a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. Providing an insulating layer comprising an inorganic insulating material of an oxide in contact with the oxide semiconductor layer 112 (in other words, not providing an insulating layer comprising an inorganic insulating material of a nitride in contact with the oxide semiconductor layer 112) can reduce the diffusion of impurities such as hydrogen, which can generate donors, into the oxide semiconductor layer 112. Furthermore, providing an insulating film of an oxide in contact with the oxide semiconductor layer 112 can prevent the generation of defects (donors) caused by oxygen vacancies in the oxide semiconductor layer 112.

[0076] In addition, the silicon-based material of the silicon oxide film in contact with the oxide semiconductor layer 112 in the second insulating layer 106 and the first insulating layer 114 is Si. α -X β In the case where X is represented by , preferably, X contains at least one of: -OC≡N, i.e., cyanate group, -N=C=O, i.e., isocyanate group, -C≡N, i.e., cyanate group, =N2, i.e., diazo group, -N3, i.e., azido group, -NO, i.e., nitroso group, and -NO2, i.e., nitro group, α is 1 to 3, and β is 1 to 8. For example, it is preferred to use any of the following materials: tetracyanatosilane represented by structural formula (1), tetraisocyanatosilane represented by structural formula (2), tetracyanosilane represented by structural formula (3), 1,1,1,1-isocyanatocyanatocyanonitrosilane represented by structural formula (4), 1,1-diisocyanato 1,1-dicyanatosilane represented by structural formula (5), hexaisocyanatosilane represented by structural formula (6), and octaisocyanatosilane represented by structural formula (7). In addition, in the film formation method of the silicon oxide film, the oxidizing gas is preferably at least one of O2, O3, NO, NO2, N2O, N2O3, N2O4, N2O5, CO, and CO2.

[0077]

[0078]

[0079] By using a silicon-based material that does not contain hydrogen for the silicon oxide film in contact with the oxide semiconductor layer 112 in the second insulating layer 106 and the first insulating layer 114 , diffusion of impurities such as hydrogen that generate donors into the oxide semiconductor layer 112 can be further reduced.

[0080] For example, the silicon oxide film in contact with the oxide semiconductor layer 112 of the second insulating layer 106 and the first insulating layer 114 can be formed using a tetraisocyanatosilane-based material and a gas containing oxygen, such as oxygen (O2) or nitrous oxide (N2O). When a parallel plate plasma CVD apparatus is used to form the silicon oxide film, the film is preferably formed at a reaction gas pressure of 13 Pa to 666 Pa and a substrate temperature of 200° C. to 350° C. When an ICP-CVD apparatus is used, the film is preferably formed at a reaction gas pressure of 1.3 Pa to 66 Pa and a substrate temperature of 200° C. to 300° C.

[0081] Furthermore, the second insulating layer 106 and the first insulating layer 114 preferably have a structure in which a silicon nitride film is stacked on the side of the silicon oxide film that is in contact with the oxide semiconductor layer 112, opposite to the oxide semiconductor layer 112. Silicon tetrafluoride gas (SiF4) is preferably used as the silicon-based material for the silicon nitride film. Furthermore, in the method for forming the silicon nitride film, nitrogen gas (N2) is preferably used as a nitrogen atom supply source.

[0082] By using a silicon-based material that does not contain hydrogen for the second insulating layer 106 and the silicon nitride film in contact with the silicon oxide film of the first insulating layer 114, it is possible to further reduce the adverse effects of hydrogen, such as reducing the oxide semiconductor layer 112 to make it a conductor, or generating oxygen vacancies to increase the carrier concentration. For example, the formation of the silicon nitride film in contact with the silicon oxide film of the second insulating layer 106 and the first insulating layer 114 can also use an inductively coupled plasma chemical vapor deposition (ICP-CVD) device to form a fluorine-containing silicon nitride (P-SiN) film using SiF4 gas and N2 gas. x :F) membrane.

[0083] The second insulating layer 106 and the first insulating layer 114 formed from a raw material containing no hydrogen atoms can suppress the hydrogen content to 10 18 / cm 3 ~10 20 / cm 3 The transistor involved in this embodiment is formed by applying a silicon oxide film made of a tetraisocyanate silane-based material and a fluorine-containing silicon nitride (SiN) made of a SiF4-based material to the second insulating layer 106 and the first insulating layer 114. x:F) The structure in which the films are stacked can suppress an increase in the carrier concentration of the oxide semiconductor layer 112 and suppress a variation in the threshold voltage of the transistor.

[0084] 1-5. Gate electrode

[0085] The first gate electrode 116 is made of a metal material such as aluminum (Al), molybdenum (Mo), tungsten (W), or zirconium (Zr). For example, the first gate electrode 116 is made of a film of aluminum (Al), a molybdenum-tungsten (MoW) alloy, or the like. In addition, the first gate electrode 116 can also be made of an aluminum alloy, a copper alloy, or a silver alloy. As aluminum alloys, aluminum-neodymium alloy (Al-Nd), aluminum-neodymium-nickel alloy (Al-Nd-Ni), aluminum-carbon-nickel alloy (Al-C-Ni), copper-nickel alloy (Cu-Ni), or the like can be used. Furthermore, the first gate electrode 116 can also be formed of a transparent conductive film of indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). In addition, electrodes with a three-layer stacked structure such as Mo / Al / Mo or Mo / Cu / Mo are also effective. That is, a three-layer stacked structure in which the above-mentioned metal materials are sandwiched between oxidation-resistant layers containing molybdenum (Mo), zirconium (Zr), titanium (Ti), or alloys thereof may be applied.

[0086] 1-6. Wiring

[0087] The first wiring 110a and the second wiring 110b are made of metal materials with high electrical conductivity, such as aluminum (Al) and copper (Cu). For example, the first wiring 110a and the second wiring 110b are made of aluminum alloy, copper alloy, or silver alloy. As aluminum alloys, aluminum-neodymium alloy (Al-Nd), aluminum-titanium alloy (Al-Ti), aluminum-silicon alloy (Al-Si), aluminum-neodymium-nickel alloy (Al-Nd-Ni), aluminum-carbon-nickel alloy (Al-C-Ni), copper-nickel alloy (Cu-Ni), etc. can be used. If such metal materials are used, heat resistance can be achieved and wiring resistance can be reduced. In addition, electrodes with three-layer stacked structures such as Mo / Al / Mo and Mo / Cu / Mo are also effective. In other words, a three-layer stacked structure formed by sandwiching the above-mentioned metal materials with anti-oxidation layers containing molybdenum (Mo), zirconium (Zr), titanium (Ti), or their alloys can also be used.

[0088] 1-7. Description of Transistor Operation and Function

[0089] The transistor 100a has a first gate electrode 116 disposed on one surface side of the oxide semiconductor layer 112 (the side opposite to the substrate 102). A channel is formed in the region where the oxide semiconductor layer 112 and the first gate electrode 116 overlap. The second region 112-2 constituting the oxide semiconductor layer 112 has a lower carrier concentration than the first region 112-1. Therefore, a channel is formed in the first region 112-1 of the oxide semiconductor layer 112 in the transistor 100a. By allowing current to flow through the second region 112-2 side (the first gate electrode 116 side) of the first region 112-1 of the oxide semiconductor layer 112, the field-effect mobility of the transistor 100a can be improved.

[0090] In the transistor 100a according to this embodiment, the second region 112-2 of the oxide semiconductor layer 112 is formed using a mixed gas of a rare gas and oxygen (O2). The oxygen partial pressure during the formation of the second region 112-2 of the oxide semiconductor layer 112 is higher than the oxygen partial pressure during the formation of the first region 112-1. Figure 3 1 shows the electrical characteristics (Vg-Id characteristics) of the transistor when the oxygen partial pressure is changed when the second region 112-2 of the oxide semiconductor layer 112 is formed. Figure 3 As shown, by changing the oxygen partial pressure during the formation of the second region 112-2 of the oxide semiconductor layer 112 to 5%, 10%, 15%, 20%, and 50%, the threshold voltage of the transistor can be adjusted. The threshold voltage of the transistor involved in this embodiment is preferably in the range of 0V to 5V, and more preferably in the range of 0.5V to 3V. By not using a reducing gas to form the first insulating film 114, the substrate temperature during film formation can be increased to approximately 250°C to 350°C. As a result, after the transistor 100a is completed, a high-temperature, long-term annealing process is not required, which can improve reliability. In addition, when the second region 112-2 of the oxide semiconductor layer 112 is formed at an oxygen partial pressure within the range of 15% to 20%, the change in threshold voltage caused by stress such as heat is reduced, and even after the transistor 100a is completed, even if multiple annealing processes at 220°C to 250°C are performed to form the color filter, stable transistor characteristics can be maintained.

[0091] The transistor 100a includes a first oxide conductive layer 108a and a second oxide conductive layer 108b on one surface side (the substrate 102 side) of the oxide semiconductor layer 112. Therefore, the first oxide conductive layer 108a and the second oxide conductive layer 108b are in contact with the first region 112-1 of the oxide semiconductor layer 112. In the oxide semiconductor layer 112, the conductivity of the first region 112-1 is higher than the conductivity of the second region 112-2. Therefore, the contact resistance between the first oxide conductive layer 108a and the first region 112-1 of the oxide semiconductor layer 112, and the contact resistance between the second oxide conductive layer 108b and the first region 112-1 of the oxide semiconductor layer 112, can be reduced. In other words, by making the first oxide conductive layer 108a and the second oxide conductive layer 108b contact the surface of the oxide semiconductor layer 112 on the substrate 102 side, the contact resistance can be reduced.

[0092] 1-8. Manufacturing Method

[0093] Next, a manufacturing process of the transistor 100a will be described. Figure 4A 1 shows a stage in which a second insulating layer 106, a second conductive film 107, and a third conductive film 109 are formed on the substrate 102. A first oxide conductive layer 108a and a second oxide conductive layer 108b are formed from the second conductive film 107, and a first wiring 110a and a second wiring 110b are formed from the third conductive film 109.

[0094] A transparent insulating substrate, for example, is used as the substrate 102. Examples of the transparent insulating substrate include an alkali-free glass substrate such as aluminosilicate glass or aluminoborosilicate glass, and a quartz substrate. Among transparent insulating substrates, a flexible transparent insulating substrate having flexibility such as transparent polyimide or transparent polyamide can be used.

[0095] The second insulating layer 106 is formed of an inorganic insulating film. For example, one or more films selected from a silicon oxide film, a silicon nitride film, or a silicon oxynitride film are formed as the second insulating layer 106 by plasma CVD (Chemical Vapor Deposition). Alternatively, when forming an aluminum oxide film as the second insulating layer 106, the film is formed by sputtering using an aluminum oxide sputtering target.

[0096] The second conductive film 107 forming the first oxide conductive layer 108a and the second oxide conductive layer 108b is formed by forming a coating of a conductive metal oxide material, a metal nitride material, a metal oxynitride material, or a high-melting-point metal silicon oxide material using a sputtering method. For example, the second conductive film 107 forming the first oxide conductive layer 108a and the second oxide conductive layer 108b is formed from a conductive metal oxide material having a thickness of 30 nm to 200 nm. Furthermore, the third conductive film 109 forming the first wiring 110a and the second wiring 110b is formed from a metal material or an alloy material using a sputtering method. To reduce resistance, the third conductive film 109 forming the first wiring 110a and the second wiring 110b is formed from a metal film having a thickness of 200 nm to 2000 nm.

[0097] Figure 4B The photolithography process for forming the first wiring 110a, the second wiring 110b, the first oxide conductive layer 108a, and the second oxide conductive layer 108b is shown. Here, a multi-step exposure method (half-tone exposure method) is used to form the pattern of the first wiring 110a, the second wiring 110b, the first oxide conductive layer 108a, and the second oxide conductive layer 108b using a single photomask.

[0098] A positive-type photoresist film 205 is formed on the third conductive film 109. A multi-level photomask 201 is used for exposure of the photoresist film 205. Known multi-level photomasks 201 include gray-tone masks, which use slits smaller than the exposure machine's resolution as a multi-level mask pattern. These slits partially block light to achieve intermediate exposure, and halftone masks, which use a semi-transparent film to achieve intermediate exposure. In this embodiment, both types of multi-level photomasks 201 can be used. Exposure is performed through the light-transmitting region, semi-transmitting region 202, and non-transmitting region 203 of the multi-level photomask 201, resulting in three types of regions on the photoresist film 205: exposed portions, intermediate exposed portions, and unexposed portions.

[0099] Thereafter, the photoresist film 205 is developed, thereby Figure 5A As shown in FIG. 2 , a photoresist mask 207a having regions with different thicknesses is formed. Figure 5A , the following form is shown: the photoresist mask 207a is formed so that the film thickness of the portion corresponding to the region where the first wiring 110a and the second wiring 110b are formed becomes thicker, and the film thickness of the portion corresponding to the region where the first oxide conductive layer 108a and the second oxide conductive layer 108b are formed becomes relatively thinner.

[0100] The third conductive film 109 and the second conductive film 107 are etched using the photoresist mask 207a. Etching conditions are not limited. For example, the third conductive film 109 formed of a metal material is wet etched using a mixed acid etchant, while the second conductive film 107 formed of a metal oxide material is dry etched using a chlorine-based gas or wet etched using an oxalic acid-based etchant. At this stage, the first oxide conductive layer 108a and the second oxide conductive layer 108b are formed. Following this etching, an ashing process is performed to remove the thin regions of the photoresist mask 207a, exposing the surface of the third conductive film 109. Figure 5B FIG. 2 shows the photoresist mask 207 b after the ashing process. The photoresist mask 207 b remains on the third conductive film 109 .

[0101] Next, the exposed third conductive film 109 is etched. This etching is performed, for example, by wet etching using a mixed acid etchant. If the second conductive film 107, formed of a metal oxide or the like, contains 10 atm% or more of tin (Sn), it is less susceptible to etching by the mixed acid etchant, resulting in a relatively high selectivity. This allows the shapes of the underlying first oxide conductive layer 108a and second oxide conductive layer 108b to be maintained. Figure 6A The third conductive film 109 is etched to form the first wiring 110a and the second wiring 110b. After the third conductive film 109 is etched, the photoresist mask 207b is removed using a photoresist stripping solution or ashing.

[0102] The surfaces of the already formed first oxide conductive layer 108a and second oxide conductive layer 108b are exposed to oxygen plasma through a photoresist stripping solution or ashing process. However, even when the titanium (Ti), tantalum (Ta), hafnium (Hf), and zirconium (Zr) components of the first oxide conductive layer 108a and second oxide conductive layer 108b are converted into oxides, they do not generate defects that trap carriers (electrons) and do not act as carrier (electron) killers, but instead become n-type oxide semiconductors. Therefore, even when exposed to oxygen plasma, they can form good contact with the oxide semiconductor layer 112 formed in subsequent steps.

[0103] Figure 6B This figure shows the stage of forming the oxide semiconductor layer 112. The oxide semiconductor layer 112 is formed on substantially the entire surface of the transistor 100a, covering the first oxide conductive layer 108a, the second oxide conductive layer 108b, the first wiring 110a, and the second wiring 110b. The oxide semiconductor layer 112 is formed using a sputtering method. A sputtering target made by sintering an oxide semiconductor material is used. The oxide semiconductor layer 112 is formed to a thickness of 20 nm to 100 nm, for example, 30 nm to 60 nm.

[0104] The oxide semiconductor layer 112 can be fabricated using, for example, a sputtering target corresponding to a quaternary oxide material, a ternary oxide material, a binary oxide material, or a monolithic oxide material. The first region 112-1 of the oxide semiconductor layer 112 can be fabricated using a rare gas such as argon (Ar) or xenon (Xe) as a sputtering gas. The second region 112-2 of the oxide semiconductor layer 112 can be fabricated using a mixed gas of a rare gas and oxygen (O2). The oxygen partial pressure when fabricating the second region 112-2 of the oxide semiconductor layer 112 can be adjusted to be greater than the oxygen partial pressure when fabricating the first region 112-1. The oxygen partial pressure when fabricating the second region 112-2 of the oxide semiconductor layer 112 is preferably, for example, 10% to 50%. The oxygen partial pressure when fabricating the second region 112-2 of the oxide semiconductor layer 112 is more preferably 15% to 30%. Alternatively, a mixed gas of nitrogen (N2) or nitrous oxide (N2O) added to a rare gas (Ar) and oxygen (O2) can be used. Specifically, at the completion of film formation in the first region 112-1, the glow discharge state is maintained while oxygen is introduced into the film formation chamber in addition to the rare gas (argon). At this point, the exhaust rate can be increased to reduce the pressure within the film formation chamber, thereby slowing the film formation rate. This control can increase the density of the second region 112-2.

[0105] The first region 112-1 and the second region 112-2 of the oxide semiconductor layer 112 according to this embodiment can be continuously fabricated by controlling the oxygen partial pressure in this manner, thereby improving productivity. By increasing the oxygen partial pressure during the formation of the second region 112-2 of the oxide semiconductor layer 112, the crystallinity of the second region 112-2 can be increased, thereby making it less susceptible to reduction even when exposed to plasma during the formation of the first insulating layer 114 using plasma CVD. Consequently, the substrate temperature during the formation of the first insulating layer 114 can be increased to above 250°C, enabling the formation of a high-quality SiO2 film. This can improve the reliability of the transistor.

[0106] Regarding the method for fabricating the first region 112-1 and the second region 112-2 of the oxide semiconductor layer 112 involved in this embodiment, a method of continuously fabricating the oxide semiconductor layer 112 by using the same sputtering target and controlling the oxygen partial pressure of the sputtering gas is described as an example. However, this is not limiting. For example, the entire oxide semiconductor layer 112 can be fabricated under the same conditions as the first region 112-1, and the second region 112-2 can be formed by performing a water vapor treatment or an N2O plasma oxidation treatment. The water vapor treatment can be performed, for example, at 350°C to 500°C in a nitrogen atmosphere with a water vapor partial pressure of 10% to 50%. In addition, not only can the oxide semiconductor layer 112 be formed by varying the oxygen partial pressure, but the second region 112-2 can also be fabricated by performing a fluorine doping treatment using NF3 or SiF4 gas, or by doping with Sn, Si, or W. The second region 112-2 fabricated in this manner can also have a lower carrier concentration than the first region 112-1. Alternatively, for example, the first region 112-1 may be made of an In-Ga-Sn-O-based oxide material, and the second region 112-2 may be made of a Ga2O3-based oxide material, thereby forming two regions containing different elements. By using this manufacturing method for the first region 112-1 and the second region 112-2 of the oxide semiconductor layer 112 according to this embodiment, the second region 112-2 can have a lower carrier concentration than the first region 112-1.

[0107] Thereafter, the oxide semiconductor layer 112 having the first region 112-1 and the second region 112-2 is patterned by etching. Figure 6B As shown, the end of the first region 112-1 of the oxide semiconductor layer 112 is exposed. However, this is not limiting. In the oxide semiconductor layer 112 of this embodiment, for example, when the first region 112-1 is formed and patterned to form the second region 112-2, the end of the first region 112-1 may be covered by the second region 112-2. This structure can further improve the physical properties of the oxide semiconductor layer 112.

[0108] Figure 7A 1 shows the stage of forming the first insulating layer 114 and the fourth conductive film 115 on the oxide semiconductor layer 112. The first insulating layer 114 is made in the same manner as the second insulating layer 106. The fourth conductive film 115 is made in the same manner as the first conductive film 103. Thereafter, the fourth conductive film 115 is etched to form the first gate electrode 116. Thus, the first gate electrode 116 is made. Figure 7B Transistor 100a is shown.

[0109] According to the method for manufacturing the transistor 100a of this embodiment, the use of a multi-stage photomask can reduce the number of photomasks required for manufacturing. Furthermore, the use of a multi-stage photomask allows multiple patterns (the first oxide conductive layer 108a and the second oxide conductive layer 108b, and the first wiring 110a and the second wiring 110b) to be formed in a single exposure. This improves the productivity of integrated circuit devices including the transistor 100a and reduces manufacturing costs.

[0110] like Figure 7A and Figure 7B As shown, the first wiring 110a and the second wiring 110b are arranged so as not to overlap with the first gate electrode 116. By arranging the first wiring 110a and the second wiring 110b as far away as possible from the channel region of the transistor 100a (the region where the first gate electrode 116 and the oxide semiconductor layer 112 overlap), contamination by metal elements can be prevented. For example, copper (Cu) used as a wiring material acts as a killer impurity (an impurity that degrades and eliminates the characteristics of the oxide semiconductor) for the oxide semiconductor, which is also an n-type semiconductor. In contrast, by arranging the first wiring 110a and the second wiring 110b away from the channel region of the transistor 100a as in this embodiment, even if the first wiring 110a and the second wiring 110b contain copper (Cu), contamination of the oxide semiconductor layer 112 by copper (Cu) can be reduced.

[0111] According to the method for manufacturing the transistor 100a according to this embodiment, the first region 112-1 and the second region 112-2 of the oxide semiconductor layer 112 can be continuously formed by using the same sputtering target and controlling the oxygen partial pressure of the sputtering gas, thereby improving productivity.

[0112] Second embodiment:

[0113] This embodiment shows an example of a display device including transistors having the same structure as the transistors shown in the first embodiment. Figure 8 As shown, the display device 120 includes a display area 121 including a plurality of pixels 122 , a scan line driving circuit 123 , and a data line driving circuit 125 . Figure 8 Although not shown in the figure, the plurality of pixels 122 are provided with organic EL elements as display elements and transistors for driving the organic EL elements.

[0114] 2-1. Equivalent circuit

[0115] Figure 9FIG. 1 shows an equivalent circuit of a pixel 122 of a display device according to this embodiment. The pixel 122 includes a selection transistor 124, a drive transistor 126, a capacitor 128, and an organic EL element 130. The selection transistor 124 and the drive transistor 126 have the same structure as the transistor 100a shown in the first embodiment. That is, Figure 9 The transistors are shown as having a top-gate structure. The selection transistor 124 has a first gate electrode 116 b , and the drive transistor 126 has a first gate electrode 116 a .

[0116] In this embodiment, the selection transistor 124 and the drive transistor 126 are n-channel transistors. The first gate electrode 116b of the selection transistor 124 is connected to the gate signal line 132a. One of the input / output terminals (source and drain) of the selection transistor 124 is connected to the data signal line 134, and the other terminal is connected to the first gate electrode 116a of the drive transistor 126. The first gate electrode 116a of the drive transistor 126 is connected to the other of the input / output terminals of the selection transistor 124. The drain of the drive transistor 126 is connected to the organic EL element 130, and the source is connected to the second common wiring 136b. One terminal of the capacitor 128 is connected to the other of the input / output terminals (source and drain) of the selection transistor 124, and the other terminal is connected to the first common wiring 136a. The first common wiring 136a and the second common wiring 136b are supplied with, for example, a ground potential.

[0117] One terminal of the organic EL element 130 is connected to the drain of the driving transistor 126, and the other terminal is connected to a power supply line 138. A power supply potential VDD is supplied to the power supply line 138, which is higher than the potential of the common wiring 136. In this embodiment, the terminal of the organic EL element 130 connected to the drain of the driving transistor 126 serves as a cathode, and the terminal connected to the power supply line 138 serves as an anode.

[0118] 2-2. Pixel Structure

[0119] will with Figure 9 An example of a planar structure of a pixel 122a corresponding to the equivalent circuit shown is shown in FIG. Figure 10 In addition, Figure 10 The cross-sectional structures corresponding to the lines A1-A2 and B1-B2 are shown in FIG. Figure 11A and Figure 11B Shown in. Figure 11A 1 shows the cross-sectional structure of the driving transistor 126 and the organic EL element 130. Figure 11B 1 and 2 show the cross-sectional structures of the selection transistor 124 and the capacitor 128. In the following description, reference is made to Figure 10 、 Figure 11A and Figure 11B In addition, Figure 10 In the top view of the pixel 122 a shown, the structure of the organic EL element 130 is omitted.

[0120] 2-2-1. Driver transistor

[0121] The driver transistor 126 has the same configuration as the transistor 100a described in Embodiment 1. Specifically, the driver transistor 126 has a stacked structure comprising the second insulating layer 106, the first oxide semiconductor layer 112a (the first region 112-1 and the second region 112-2), the first insulating layer 114, and a first gate electrode 116a. The first gate electrode 116a is provided on the upper layer of the first insulating layer 114 (on the surface opposite to the substrate 102).

[0122] The first oxide conductive layer 108a and the second oxide conductive layer 108b are provided between the second insulating layer 106 and the first oxide semiconductor layer 112a. The first oxide conductive layer 108a and the second oxide conductive layer 108b are provided in contact with the first region 112-1 of the first oxide semiconductor layer 112a.

[0123] The first oxide conductive layer 108a and the second oxide conductive layer 108b have regions overlapping with the first gate electrode 116a and are arranged to sandwich the first gate electrode 116a from both sides in a plan view. The second oxide conductive layer 108b has a U-shaped pattern in a plan view, at least in the region overlapping with the first gate electrode 116a. The first oxide conductive layer 108a has a linear pattern extending inside the U-shaped pattern of the second oxide conductive layer 108b. Figure 1 The cross-sectional view of the transistor shown in FIG. 1 shows a unit structure of the first oxide conductive layer 108 a to the second oxide conductive layer 108 b. Figure 10 In the cross-sectional view of the driving transistor 126 in the second direction (D2 direction), Figure 1 The cross-sectional view shows a repeating structure.

[0124] The width of the linear pattern of the first oxide conductive layer 108a is preferably in the range of 1.0 μm to 5 μm, more preferably in the range of 1.5 μm to 3 μm. The shortest distance between the first oxide conductive layer 108a and the second oxide conductive layer 108b in the region overlapping the first gate electrode 116a is preferably in the range of 1.5 μm to 10 μm, more preferably in the range of 2 μm to 5 μm. By employing a structure in which the shortest distance between the first oxide conductive layer 108a and the second oxide conductive layer 108b is equal to or greater than the width of the linear pattern of the first oxide conductive layer 108a, an increase in leakage current when the drive transistor 126 is off can be suppressed. By having such a structure of the first oxide conductive layer 108a and the second oxide conductive layer 108b, even if there is a misalignment between the first gate electrode 116a and the first and second oxide conductive layers 108a and 108b, fluctuations in gate-drain capacitance can be suppressed, thereby suppressing display unevenness and improving yield.

[0125] In the driving transistor 126, the first oxide conductive layer 108a or the region where the first oxide conductive layer 108a and the first oxide semiconductor layer 112a are in contact becomes a drain region, and the second oxide conductive layer 108b or the region where the first oxide semiconductor layer 112a and the second oxide conductive layer 108b are in contact becomes a source region.

[0126] The second oxide conductive layer 108b of the driver transistor 126 is electrically connected to a first common wiring 136a and a second common wiring 136b, along with the first oxide semiconductor layer 112a. The second common wiring 136b is provided in the same layer structure as the wiring layer 110 provided between the oxide conductive layer 108 and the oxide semiconductor layer 112. The first common wiring 136a and the second oxide conductive layer 108b are electrically connected via a first contact hole 117a provided in the second insulating layer 106. The second common wiring 136b is directly in contact with the upper surface of the second oxide conductive layer 108b.

[0127] The second insulating layer 106 has, for example, a structure in which a first silicon nitride film 141a and a first silicon oxide film 140a are stacked from the substrate 102 side. The first insulating layer 114 has a structure in which a second silicon oxide film 140b and a second silicon nitride film 141b are stacked from the first oxide semiconductor layer 112a side.

[0128] The driver transistor 126 forms a channel in the region where the first oxide semiconductor layer 112a and the first gate electrode 116a overlap. Therefore, the first oxide semiconductor layer 112a is disposed in contact with the first silicon oxide films 140a and 140b in the region where the channel is formed. By disposing the first oxide semiconductor layer 112a in contact with an insulating oxide film, the generation of oxygen vacancies is suppressed. Ideally, the first silicon oxide films 140a and 140b should be free of oxygen vacancies to prevent oxygen from being deprived of the first oxide semiconductor layer 112a. They should preferably contain an excess of oxygen. This is because the first silicon oxide films 140a and 140b containing an excess of oxygen can serve as an oxygen source for the first oxide semiconductor layer 112a. Here, a silicon oxide film containing an excess of oxygen includes a silicon oxide film containing more oxygen than the stoichiometric composition, and may also contain oxygen within the crystal lattice. Alternatively, the second insulating layer 106 and the first insulating layer 114 may be formed of a silicon oxynitride film or an aluminum oxide film instead of a silicon oxide film.

[0129] The driver transistor 126 is covered with a planarization layer 142. Planarization layer 142 is formed from an organic resin material, such as an acrylic resin, polyimide resin, epoxy resin, or polyamide resin. During the manufacturing process, when a composition containing a precursor of the organic resin material is applied, the surface of planarization layer 142 is flattened by the leveling effect of the coating film.

[0130] Openings 144 are provided in the planarization layer 142 and the first insulating layer 114. A first electrode 146, which serves as a cathode of the organic EL element 130, is arranged to overlap the openings 144. The organic EL element 130 is formed by stacking multiple layers at least in the region of the openings 144.

[0131] In this embodiment, the driving transistor 126 is as shown in FIG. Figure 1 As described above, the oxide semiconductor layer 112 is composed of a first region 112-1 and a second region 112-2. Furthermore, the carrier concentration in the second region 112-2 is lower than that in the first region 112-1. Consequently, the drive transistor 126 has a structure in which a channel is formed in the first region 112-1, which is away from the first insulating layer 114, in the oxide semiconductor layer 112. In order to create a normally-off (enhancement-mode) TFT, a buried channel can be formed in one embodiment of the present invention.

[0132] If a region corresponding to the second region 112-2 is not provided in the oxide semiconductor layer 112, a region with poor film quality (low density and many defects) formed in the final stage of film formation of the oxide semiconductor layer 112 is directly in contact with the first insulating layer 114. In this structure, since the channel region is formed including the region with poor film quality in the oxide semiconductor layer 112, the field-effect mobility is reduced, and since it is easily reduced during the formation of the first insulating layer 114, it becomes a factor causing a large fluctuation in the threshold voltage.

[0133] In contrast, the driver transistor 126 according to this embodiment can improve field-effect mobility by providing the second region 112-2 between the first region 112-1 of the oxide semiconductor layer 112 and the first insulating layer 114. Furthermore, fluctuations in the threshold voltage of the driver transistor 126 can be suppressed, and reliability can be improved through stable electrical characteristics.

[0134] 2-2-2. Selecting transistors

[0135] The selection transistor 124 has the same configuration as the transistor 100a described in Embodiment 1. Specifically, the selection transistor 124 has a stacked structure comprising the second insulating layer 106, the second oxide semiconductor layer 112b (the first region 112-1 and the second region 112-2), the first insulating layer 114, and the first gate electrode 116b. The channel of the selection transistor 124 is formed in the region where the second oxide semiconductor layer 112b and the first gate electrode 116b overlap.

[0136] A third oxide conductive layer 108c and a fourth oxide conductive layer 108d are provided between the second insulating layer 106 and the second oxide semiconductor layer 112b. The third oxide conductive layer 108c and the fourth oxide conductive layer 108d are provided in contact with the first region 112-1 of the second oxide semiconductor layer 112b, thereby functioning as source and drain regions.

[0137] The third oxide conductive layer 108c and the fourth oxide conductive layer 108d have regions overlapping with the first gate electrode 116b and are arranged to sandwich the first gate electrode 116b from both sides in a plan view. The third oxide conductive layer 108c has a U-shaped pattern in a plan view, at least in the region overlapping with the first gate electrode 116b. The fourth oxide conductive layer 108d has a linear pattern extending inside the U-shaped pattern of the third oxide conductive layer 108c. Figure 1 The cross-sectional view of the transistor shown in FIG. 1 shows a unit structure of the first oxide conductive layer 108 a to the second oxide conductive layer 108 b. Figure 10 In the cross-sectional view of the selection transistor 124 in the second direction (D2 direction) Figure 1 The cross-sectional view shows a repeating structure.

[0138] The width of the linear pattern of the fourth oxide conductive layer 108d is preferably in the range of 1.0 μm to 5 μm, more preferably in the range of 1.5 μm to 3 μm. The shortest distance between the third oxide conductive layer 108c and the fourth oxide conductive layer 108d in the region overlapping the first gate electrode 116b is preferably in the range of 1.5 μm to 10 μm, more preferably in the range of 2 μm to 5 μm. By employing a structure in which the shortest distance between the third oxide conductive layer 108c and the fourth oxide conductive layer 108d is equal to or greater than the width of the linear pattern of the fourth oxide conductive layer 108d, an increase in leakage current when the select transistor 124 is off can be suppressed. By having such a structure of the third oxide conductive layer 108c and the fourth oxide conductive layer 108d, even if there is a misalignment between the first gate electrode 116b and the third oxide conductive layer 108c and the fourth oxide conductive layer 108d, fluctuations in gate-drain capacitance can be suppressed, thereby suppressing display unevenness and improving productivity.

[0139] The third oxide conductive layer 108c is electrically connected to the data signal line 134. The data signal line 134 is provided with the same layer structure as the wiring layer 110 provided between the oxide conductive layer 108 and the oxide semiconductor layer 112. The data signal line 134 is directly in contact with the upper surface of the third oxide conductive layer 108c. In addition, the second oxide semiconductor layer 112b extends to the area where the data signal line 134 is provided and is provided so as to cover the data signal line 134. By directly contacting the data signal line 134 with the third oxide conductive layer 108c, the contact area is increased compared to the case of connection through a contact hole, thereby reducing the contact resistance. In addition, the data signal line 134 is covered by the second oxide semiconductor layer 112b on the upper surface and side surfaces, so that it is not exposed to oxidizing atmospheres and reducing atmospheres during the manufacturing process. Therefore, the data signal line 134 can suppress the increase in surface resistance.

[0140] 2-2-3. Capacitor elements

[0141] The capacitor element 128 has a stacked structure comprising a first capacitor electrode 160a, a second insulating layer 106, a fourth oxide conductive layer 108d, and a second capacitor electrode 160b. The second capacitor electrode 160b has the same layer structure as the data signal line 134. Since the fourth oxide conductive layer 108d is electrically connected to the second capacitor electrode 160b, it essentially functions as the other electrode of the capacitor element 128.

[0142] The second oxide semiconductor layer 112b and the first insulating layer 114 are provided above the second capacitor electrode 160b. The second capacitor electrode 160b is electrically connected to the first gate electrode 116a via a second contact hole 117b penetrating the first insulating layer 114 and the second oxide semiconductor layer 112b.

[0143] 2-2-4. Organic EL elements

[0144] The organic EL element 130 has a structure in which, from the substrate 102 side, a first electrode 146 corresponding to a cathode, a first oxide semiconductor layer 112a (first region 112-1 and second region 112-2), an electron transport layer 148, an electron injection layer 150, a light-emitting layer 152, a hole transport layer 154, a hole injection layer 156, and a second electrode 158 corresponding to an anode are stacked. In the organic EL element 130, a structure in which the hole transport layer, the light-emitting layer, the electron transport layer, and the cathode are stacked in this order from the anode side closer to the substrate 102 is referred to as a forward stacking structure. The organic EL element 130 according to this embodiment has a structure in which the electron transport layer, the light-emitting layer, the hole transport layer, and the cathode are stacked in this order from the cathode side closer to the substrate 102, and is therefore also referred to as a reverse stacking structure.

[0145] In this embodiment, by adopting a structure in which the energy level decreases in the order of the electron transport layer 148, the second region 112-2 of the first oxide semiconductor layer 112a, the first region 112-1 of the first oxide semiconductor layer 112a, and the first electrode 146, the energy level difference can be reduced, the electron injection efficiency can be improved, and the luminous efficiency of the organic EL element 130 can be improved. In addition, in this embodiment, since the driving transistor 126 is an n-channel type, the source and the anode are connected when the organic EL element is a forward stacking structure. At this time, there is a problem that the drain current of the driving transistor changes due to changes in the characteristics of the organic EL element. However, if the organic EL element is set to a reverse stacking structure as in this embodiment, then in the n-channel driving transistor, the drain and the cathode of the organic EL element are connected, so that a circuit structure in which the drain current is not easily affected by changes in the characteristics of the organic EL element can be made.

[0146] An electron transport layer 148, an electron injection layer 150, a light-emitting layer 152, a hole transport layer 154, a hole injection layer 156, and a second electrode 158 serving as an anode are stacked on the upper surface of the planarization layer 142 and in the opening 144 provided in the planarization layer 142 and the first insulating layer 114. The region where this stack overlaps with the first electrode 146, which serves as a cathode, forms the light-emitting region of the organic EL element 130.

[0147] The organic EL element 130 according to this embodiment is a so-called bottom emission type that emits light toward the substrate 102. Hereinafter, each layer constituting the organic EL element 130 will be described in detail.

[0148] 2-2-4-1. Cathode

[0149] Materials such as aluminum-lithium alloy (AlLi) and magnesium-silver alloy (MgAg) have been used as cathode materials for organic EL devices. However, these materials are susceptible to degradation by atmospheric oxygen and moisture, making them difficult to process. Furthermore, these cathode materials are metallic and therefore unsuitable for bottom-emission organic EL devices with an inverted stack structure.

[0150] The organic EL element 130 involved in this embodiment realizes a bottom emission type structure by forming the first electrode 146 as a cathode from a transparent conductive film. Specifically, by expanding the first oxide conductive layer 108a of the driving transistor 126 to the region of the organic EL element 130, a layer that functions as a cathode, i.e., the first electrode 146, is provided. By adopting this structure, the structure for electrically connecting the driving transistor 126 and the organic EL element 130 is simplified. For example, if an interlayer insulating layer is interposed between the driving transistor and the organic EL element, a contact hole needs to be provided to connect the two. However, according to the structure of the pixel 122a involved in this embodiment, a contact hole is not required.

[0151] The first electrode 146, serving as a cathode, is formed from the same conductive film as the first oxide conductive layer 108a. The first oxide conductive layer 108a is formed from a conductive metal oxide material, metal nitride material, or metal oxynitride material. Conductive films formed from these materials have a band gap of 2.8 eV or greater, preferably 3.0 eV or greater, and thus transmit nearly all light in the visible light band. Therefore, it can be used as an electrode on the light-emitting surface side of the organic EL element 130.

[0152] A first oxide semiconductor layer 112a extending from the driving transistor 126 may also be provided on the upper layer of the first electrode 146 corresponding to the cathode. The first oxide semiconductor layer 112a has a band gap of 3 eV or more and is therefore translucent to visible light. In addition, as described below, in this embodiment, the electron transport layer 148 is formed of a metal oxide. Therefore, by interposing the first oxide semiconductor layer 112a, which is the same material as or of the same type as the electron transport layer 148, between the first electrode 146 corresponding to the cathode, it is possible to avoid forming an electron injection barrier. In other words, the first oxide semiconductor layer 112a extending from the channel region of the driving transistor 126 can be used as a part of the electron transport layer 148 connected to the first electrode 146 corresponding to the cathode.

[0153] 2-2-4-2. Electron transport layer

[0154] The electron transport layer 148 is formed using a metal oxide material. As the metal oxide material, the same ternary oxide material, binary oxide material, and unary oxide material as the materials described in the first embodiment are applied. These metal oxide materials can be in an amorphous form, a crystalline form, or a mixed phase of an amorphous and crystalline phase. For example, the electron transport layer 148 is composed of one or more selected from indium oxide, zinc oxide, gallium (Ga) oxide, and tin (Sn) oxide. These metal oxide materials must not absorb visible light but be transparent, so the band gap is required to be 3.0 eV or more. Furthermore, the electron transport layer 148 can prevent the short circuit of the cathode and the anode by increasing the film thickness as much as possible. As a result, the yield of the organic EL panel can be greatly improved. As a representative electron transport layer, there are ZnSiO x By doping ZnO with SiO2 at approximately 10 to 15 atm%, a band gap of 3.5 eV and a work function of 3.5 eV suitable for an electron transport layer can be obtained. X Similar physical properties can be achieved with an oxide semiconductor containing 20 atm% Mg and 80 atm% Zn. This electron transport layer 148 can be formed by sputtering, vacuum evaporation, coating, or other methods. Using these film-forming methods, the electron transport layer 148 can be formed to a thickness of 50 nm to 1000 nm.

[0155] In addition, the carrier concentration of the electron transport layer 148 is preferably less than 1 / 10, preferably less than 1 / 100, of the average carrier concentration of the first oxide semiconductor layer 112a. In other words, the average carrier concentration of the first oxide semiconductor layer 112a is preferably 10 times or more, preferably 100 times or more, relative to the carrier concentration of the electron transport layer 148. Specifically, the carrier concentration of the electron transport layer 148 is 10 13 / cm 3 ~10 17 / cm 3 In contrast, the carrier concentration in the first region 112-1 of the first oxide semiconductor layer 112a is 1×10 15 / cm 3 ~1×10 19 / cm 3 The difference in carrier concentration between the two sides is a single digit or more, preferably a double digit or more, as described above. By making the first region 112-1 of the first oxide semiconductor layer 112a have 10 15 / cm 3 ~10 19 / cm3 The carrier concentration of the electron transport layer 148 is 10, which can reduce the resistance loss in the electrical connection between the driving transistor 126 and the organic EL element 130 and suppress the increase in the driving voltage. 20 / cm 3 On the other hand, if the carrier concentration of the electron transport layer 148 is 10 13 / cm 3 If the carriers supplied to the light-emitting layer 152 decrease, sufficient brightness cannot be achieved. By stacking and contacting the first oxide conductive layer 108a and the first oxide semiconductor layer 112a extending from the driving transistor 126 with the electron transport layer 148 in this manner, and making the carrier concentrations of the three layers different, it is possible to prevent the driving voltage from increasing, improve the electron injection efficiency, and enhance the luminous efficiency of the organic EL element 130.

[0156] 2-2-4-3. Electron injection layer

[0157] In organic EL devices, an electron injection layer is used to reduce the energy barrier for injecting electrons from the cathode into the electron transport material. In this embodiment, electron injection layer 150 is used to facilitate electron injection from electron transport layer 148, which is formed of an oxide semiconductor, into light-emitting layer 152. Specifically, electron injection layer 150 is provided between electron transport layer 148 and light-emitting layer 152.

[0158] The electron injection layer 150 is preferably made of a material with a low work function in order to inject electrons into the light-emitting layer 152 formed of an organic material. The electron injection layer 150 is composed of calcium (Ca) oxide and aluminum (Al) oxide. For example, a C12A7 (12CaO·7Al2O3) electron salt is preferably used as the electron injection layer 150. The C12A7 electron salt has semiconductor properties and can be controlled between high and low resistance. Its work function is also comparable to that of alkali metals, ranging from 2.4 eV to 3.2 eV, making it suitable for use as the electron injection layer 150.

[0159] The electron injection layer 150, formed of a C12A7 electron salt, is formed by sputtering using a polycrystal of a C12A7 electron compound as a target. Because the C12A7 electron salt exhibits semiconductor properties, the thickness of the electron injection layer 150 can be set within a range of 1 nm to 100 nm. Furthermore, the C12A7 electron salt preferably has a Ca:Al molar ratio within a range of 13:13 to 11:16. Since the C12A7 electron salt is formed by sputtering, it is preferably amorphous, but may also be crystalline.

[0160] Because C12A7 electron salts are stable in the atmosphere, they offer the advantage of being easier to handle than alkali metal compounds such as lithium fluoride (LiF), lithium oxide (Li2O), sodium chloride (NaCl), and potassium chloride (KCl), which have been used in electron injection layers. This eliminates the need for working in dry air or inert gas during the organic EL device manufacturing process, easing the constraints on manufacturing conditions.

[0161] In addition, since the C12A7 electron salt has a large ionization potential, it can be used as a hole blocking layer by being arranged on the opposite side of the hole transport layer 154 with the light emitting layer 152 sandwiched therebetween. That is, by providing the electron injection layer 150 formed of the C12A7 electron salt between the electron transport layer 148 and the light emitting layer 152, it is possible to suppress the holes injected into the light emitting layer 152 from penetrating to the first electrode 146 side as the cathode, thereby improving the light emission efficiency. MgZnO can also be used. x (Mg: 30 atm %, Zn: 70 atm %) was used as an electron injection layer.

[0162] 2-2-4-4. Luminescent layer

[0163] Various materials can be used for the light-emitting layer 152. For example, a fluorescent compound that emits fluorescence or a phosphorescent compound that emits phosphorescence can be used.

[0164] For example, as a blue-based light-emitting material, N,N'-bis[4-(9H-carbazol-9-yl)phenyl]-N,N'-diphenylstilbene-4,4'-diamine (YGA2S), 4-(9H-carbazol-9-yl)-4'-(10-phenyl-9-anthryl)triphenylamine (YGAPA), etc. can be used. As a green-based light-emitting material, N-(9,10-diphenyl-2-anthryl)-N,9-diphenyl-9H-carbazol-3-amine (2PCAPA), N-[9,10-bis(1,1'-biphenyl-2-yl)-2-anthryl]-N,9-diphenyl-9H-carbazol-3-amine (2PCABPhA), N-(9,10-diphenyl-2-anthryl)-N,N',N'-triphenyl-1,4-phenylenediamine (2PCAPA) can be used. Examples of red emitting materials include N,N,N',N'-tetrakis(4-methylphenyl)naphthacene-5,11-diamine (p-mPhTD) and 7,13-diphenyl-N,N,N',N'-tetrakis(4-methylphenyl)acenaphtho[1,2-a]fluoranthene-3,10-diamine (p-mPhAFD). Alternatively, bis[2-(2'-benzo[4,5-α]thienyl)pyridine-N,C 3 '] Phosphorescent materials such as iridium (III) acetylacetonate (Ir(btp)2(acac)).

[0165] Various known materials can be used for the light-emitting layer 152. The light-emitting layer 152 can be formed by vapor deposition, transfer, spin coating, spray coating, gravure printing, etc. The thickness of the light-emitting layer 152 can be appropriately selected, for example, within a range of 10 nm to 100 nm.

[0166] 2-2-4-5. Hole transport layer

[0167] The hole transport layer 154 is formed using a material having a hole transport property. For example, the hole transport layer 154 may be an arylamine compound, an amine compound containing a carbazole group, or an amine compound containing a fluorene derivative. The hole transport layer 154 can use organic materials such as 4,4'-bis[N-(naphthyl)-N-phenyl-amino]biphenyl (α-NPD), N,N'-bis(3-methylphenyl)-(1,1'-biphenyl)-4,4'-diamine (TPD), 2-TNATA, 4,4',4"-tris(N-(3-methylphenyl)N-phenylamino)triphenylamine (MTDATA), 4,4'-N,N'-dicarbazolebiphenyl (CBP), 4,4'-bis[N-(9,9-dimethylfluoren-2-yl)-N-phenylamino]biphenyl (DFLDPBi), 4,4'-bis[N-(spiro-9,9'-bifluoren-2-yl)-N-phenylamino]biphenyl (BSPB), spiro-NPD, spiro-TPD, spiro-TAD, TNB, etc.

[0168] The hole transport layer 154 is formed by a common film forming method such as vacuum deposition or coating. The hole transport layer 154 is formed to a thickness of 10 nm to 500 nm by such a film forming method. Alternatively, the hole transport layer 154 may be omitted.

[0169] 2-2-4-6. Hole injection layer

[0170] The hole injection layer 156 contains a substance having a higher hole injection property than the organic layer. As a substance having a high hole injection property, metal oxides such as molybdenum oxide, vanadium oxide, ruthenium oxide, tungsten oxide, and manganese oxide can be used. In addition, phthalocyanine (H2Pc), copper (II) phthalocyanine (abbreviated as: CuPc), vanadyl phthalocyanine (VOPc), 4,4',4"-tris(N,N-diphenylamino)triphenylamine (TDATA), 4,4',4"-tris[N-(3-methylphenyl)-N-phenylamino]triphenylamine (MTDATA), 4,4'-bis[N-(4-diphenylaminophenyl)-N-phenylamino]biphenyl (DPAB), 4,4'-bis(N-{4-[N'-(3-methylphenyl)-N'-phenylamino]phenyl}-N-phenylamino)biphenyl (DNTPD), 1,3,5-tris[ Organic compounds such as N-(4-diphenylaminophenyl)-N-phenylamino]benzene (DPA3B), 3-[N-(9-phenylcarbazole-3-yl)-N-phenylamino]-9-phenylcarbazole (PCzPCA1), 3,6-bis[N-(9-phenylcarbazole-3-yl)-N-phenylamino]-9-phenylcarbazole (PCzPCA2), 3-[N-(1-naphthyl)-N-(9-phenylcarbazole-3-yl)amino]-9-phenylcarbazole (PCzPCN1), and 2,3,6,7,10,11-hexacyano-1,4,5,8,9,12-hexaazatriphenylene (HAT-CN).

[0171] The hole injection layer 156 is formed by a common film forming method such as vacuum deposition or coating, and is formed to a thickness of 1 nm to 100 nm by such a film forming method.

[0172] 2-2-4-7. Anode

[0173] The second electrode 158 corresponding to the anode is made of a metal, alloy, or conductive compound with a large work function (specifically, 4.0 eV or more). The second electrode 158 corresponding to the anode uses, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide containing tungsten oxide and zinc oxide (IWZO), etc. The second electrode 158 corresponding to the anode using these conductive metal oxide materials is produced by vacuum evaporation or sputtering. In this embodiment, the organic EL element 130 is a bottom emission type, so the second electrode 158 corresponding to the anode is preferably light reflective or has a light reflecting surface. Since the coating of conductive metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO) is light-transmitting, a metal film such as aluminum (Al) or silver (Ag) can also be stacked on the surface opposite to the hole injection layer 156. Furthermore, a passivation layer that blocks the permeation of oxygen (O2) and water (H2O) may be provided on the upper layer of the second electrode 158 corresponding to the anode over substantially the entire surface of the display region 121. Figure 10 、 Figure 11A and Figure 11B is omitted.

[0174] As described above, according to this embodiment, a pixel 122a in which an n-channel conductive driving transistor 126 and an organic EL element 130 are electrically connected can be realized. In this case, the organic EL element 130 can adopt a reverse stacking structure in which an electron transport layer 148, an electron injection layer 150, a light-emitting layer 152, a hole transport layer 154, a hole injection layer 156, etc. are appropriately stacked from the side of the first electrode 146 serving as a cathode. The first electrode 146 serving as a cathode does not need to use an alkali metal material, thereby improving the reliability of the display device. Furthermore, by forming the electron transport layer and the electron injection layer arranged on the lower side from an inorganic insulating material, even if an organic layer is formed thereon, it is possible to suppress the degradation of the characteristics caused by deterioration, etc., thereby stabilizing the characteristics of the organic EL element 130.

[0175] 2-3. Transistor Structure

[0176] like Figure 11A and Figure 11B As shown, the structure of the pixel 122a according to this embodiment is a structure in which the second electrode 158 covers the entire surface of the drive transistor 126 and the select transistor 124. Furthermore, the drive transistor 126 and the select transistor 124 have a bottom-contact top-gate structure, in which the first oxide conductive layer 108a and the second oxide conductive layer 108b are arranged in contact with the lower layer of the oxide semiconductor layer 112 forming the channel, and the first gate electrode 116 is arranged on the upper layer side of the oxide semiconductor layer 112.

[0177] on the other hand, Figure 12AA bottom-contact bottom-gate type transistor 300 is shown, which has a cross-sectional structure in which a gate electrode 304, a second insulating layer 306, a first oxide conductive layer 308a, a second oxide conductive layer 308b, a first wiring 310a, a second wiring 310b, an oxide semiconductor layer 312, a first insulating layer 314, a planarization layer 342, and an anode 358 are stacked on a substrate 302. Figure 12B A top-contact bottom-gate transistor 400 is shown, having a cross-sectional structure in which a gate electrode 404, a second insulating layer 406, an oxide semiconductor layer 412, a first oxide conductive layer 408a, a second oxide conductive layer 408b, a first wiring 410a, a second wiring 410b, a first insulating layer 414, a planarization layer 442, and an anode 458 are stacked in this order on a substrate 402. In these bottom-gate transistors 300 and 400, current flows through the region (dashed line) on the first gate electrode 304 and 404 side of the first region 312-1 and 412-1 of the oxide semiconductor layers 312 and 412. Furthermore, in the bottom-gate transistors 300 and 400, the back channel side (the anode side of the oxide semiconductor layers 312 and 412) is easily affected by the anode. Specifically, the potential of the anode 358, 458 is positive, and the distance between the interface (back channel interface) between the oxide semiconductor layer 312, 412 and the first insulating layer 314, 414 and the anode 358, 458 is approximately 3 μm to 5 μm. Therefore, positive charge is easily accumulated at the interface between the back channel side of the oxide semiconductor layer 312, 412 and the first insulating layer 314, 414. If positive charge accumulates at the interface between the back channel side and the first insulating layer 314, 414, there is a problem that the threshold voltage of the transistor shifts to the negative side (becoming normally off).

[0178] To solve this problem, it is preferable to adopt a configuration in which a gate electrode is provided on the upper side of the oxide semiconductor layer 112 as shown in this embodiment. In this case, the first gate electrode 116 is grounded to a constant potential, thereby stabilizing the potential on the back channel side.

[0179] Figure 13 Figure 1 shows the bottom-contact, top-gate structure of transistor 100a according to this embodiment. The first oxide conductive layer 108a and the second oxide conductive layer 108b are arranged in contact with the lower layer of oxide semiconductor layer 112, and the first gate electrode 116 is arranged on the upper layer side of oxide semiconductor layer 112. By having the first oxide conductive layer 108a and the second oxide conductive layer 108b in contact with the first region 112-1 of the oxide semiconductor layer 112, which has a higher carrier concentration than the second region 112-2, contact resistance can be reduced. As a result, transistor 100a according to this embodiment can improve admittance and drain current.

[0180] Figure 13 , as one embodiment of the transistor 100a, shows a structure in which a first gate electrode 116 on the upper side of the oxide semiconductor layer 112 and a first oxide conductive layer 108a and a second oxide conductive layer 108b corresponding to source / drain electrodes overlap. The width W of the first gate electrode 116 in the channel length direction is top The overlap width W between the first oxide conductive layer 108a and the second oxide conductive layer 108b is ov By overlapping the first gate electrode 116 with a portion of the first oxide conductive layer 108a and the second oxide conductive layer 108b in this manner, the channel region of the oxide semiconductor layer 112 is substantially shielded from the influence of the electric field of the second electrode 158. Thus, even if the second electrode 158 is arranged to cover the entire surface of the transistor 100a, the transistor 100a is not affected by the electric field from the second electrode 158. Furthermore, the threshold voltage of the transistor 100a can be prevented from fluctuating over time.

[0181] 2-4. Method for Manufacturing Display Device

[0182] An example of a method for manufacturing the display device 120 according to one embodiment of the present invention will be described. In the following description, portions overlapping with the description of the method for manufacturing the transistor 100a described in the first embodiment will be omitted as appropriate, and only the different portions will be described.

[0183] Figure 14 and Figure 15A and Figure 15B 1 shows a stage of forming the first capacitor electrode 160a and the first common wiring 136a on the substrate 102, and a stage of forming the second insulating layer 106. Figure 14 12 is a top view of a region corresponding to pixel 122a. Figure 15A represents a cross-sectional view corresponding to line A1-A2, Figure 15B A cross-sectional view corresponding to line B1-B2 is shown.

[0184] like Figure 14 、 Figure 15A and Figure 15B As shown, the first common wiring 136a and the first capacitor electrode 160a are formed of the same conductive film. Therefore, the first common wiring 136a and the first capacitor electrode 160a are formed as one continuous pattern using the conductive film formed in the same layer.

[0185] The second insulating layer 106 is formed on the upper side of the first common wiring 136a and the first capacitor electrode 160a. For example, the second insulating layer 106 is formed by stacking a first silicon nitride film 141a and a first silicon oxide film 140a from the substrate 102 side. The first silicon nitride film 141a is formed by ICP-CVD using gases such as SiF4 and N2 as raw materials. The first silicon oxide film 140a is similarly formed by plasma CVD using tetraisocyanatosilane materials, N2O, etc. as appropriate. This second insulating layer 106 is formed over substantially the entire surface of the substrate 102.

[0186] Figure 16A and Figure 16B The figure shows the stage where the second conductive film 107 and the third conductive film 109 are formed on the upper layer of the second insulating layer 106, and a photoresist mask 207 is formed thereon using a multi-level photomask 201. By exposing the light through the light-transmitting region 203, the semi-transmitting region 202, and the non-transmitting region 203 of the multi-level photomask 201, three types of portions, namely, exposed portions, intermediate exposed portions, and unexposed portions, are formed on the photoresist film 205. The second common wiring 136b ( Figure 16A ), data signal line 134 ( Figure 16B The second conductive film 107 is formed of a transparent conductive material, and the third conductive film 109 is formed of a metal material. Figure 16A As shown, a first contact hole 117 a for exposing the first common wiring 136 a is formed in advance in the second insulating layer 106 .

[0187] Figure 17 、 Figure 18A and Figure 18B The third conductive film 109 and the second conductive film 107 are shown in a state where they are etched using the photoresist masks 207a, 207b, 207c, and 207d. Figure 17 A top view of a region corresponding to pixel 122a at this stage is shown. Figure 18A represents a cross-sectional view corresponding to line A1-A2, Figure 18B A cross-sectional view corresponding to line B1-B2 is shown.

[0188] The first oxide conductive layer 108a, the second oxide conductive layer 108b, the third oxide conductive layer 108c, and the fourth oxide conductive layer 108d are formed from the second conductive film 107. The first oxide conductive layer 108a, the second oxide conductive layer 108b, the third oxide conductive layer 108c, and the fourth oxide conductive layer 108d are formed on the second insulating layer 106. The second common wiring 136b, the second capacitor electrode 160b, and the data signal line 134 are formed from the third conductive film 109. The second common wiring 136b is formed on the second oxide conductive layer 108b. The second common wiring 136b is formed in contact with the upper surface of the second oxide conductive layer 108b. In this manner, the first common wiring 136a, the second oxide conductive layer 108b, and the second common wiring 136b are electrically connected.

[0189] The second capacitor electrode 160b is formed in contact with the upper surface of the fourth oxide conductive layer 108d. The second capacitor electrode 160b is arranged so that at least a portion of the second capacitor electrode 160b overlaps with the first capacitor electrode 160a via the fourth oxide conductive layer 108d and the second insulating layer 106. The capacitor element 128 is formed in the region where the first capacitor electrode 160a and the second capacitor electrode 160b overlap via the second insulating layer 106.

[0190] The data signal line 134 is formed in contact with the upper surface of the third oxide conductive layer 108c. This ensures electrical connection between the third oxide conductive layer 108c and the data signal line 134. The third oxide conductive layer 108c, formed along the data signal line 134, ensures reliable electrical connection.

[0191] Furthermore, the end of the second common wiring 136b is positioned inward of the end of the second oxide conductive layer 108b. This ensures that even when the second oxide conductive layer 108b and the second common wiring 136b are stacked, a stepped portion is formed, thereby improving coverage of the step difference with the oxide semiconductor layer 112 and the first insulating layer 114 formed in subsequent steps. Similarly, the end of the data signal line 134 is positioned inward of the end of the third oxide conductive layer 108c, and the end of the second capacitor electrode 160b is positioned inward of the end of the fourth oxide conductive layer 108d. This improves coverage of the step difference with the oxide semiconductor layer 112 and the first insulating layer 114 formed on the upper side.

[0192] Figure 19 、 Figure 20A and Figure 20B This shows a stage in which the oxide semiconductor layer 112 , the first insulating layer 114 , and the fourth conductive film 115 are formed. Figure 19 A top view of a region corresponding to pixel 122a at this stage is shown. Figure 20A represents a cross-sectional view corresponding to line A1-A2, Figure 20B A cross-sectional view corresponding to line B1-B2 is shown.

[0193] The first oxide semiconductor layer 112a is formed to cover substantially the entire surface of the first oxide conductive layer 108a and the second oxide conductive layer 108b. Furthermore, the second oxide semiconductor layer 112b is formed to cover substantially the entire surface of the third oxide conductive layer 108c and the fourth oxide conductive layer 108d. Furthermore, the first oxide semiconductor layer 112a and the second oxide semiconductor layer 112b each have a stacked structure including a first region 112-1 and a second region 112-2. The first oxide semiconductor layer 112a and the second oxide semiconductor layer 112b are formed sequentially by sputtering using an oxide semiconductor as a target, and then photolithography is performed to form the predetermined shapes described above. The first region 112-1 of the first oxide semiconductor layer 112a is formed in contact with the first oxide conductive layer 108a and the second oxide conductive layer 108b, and the first region 112-1 of the second oxide semiconductor layer 112b is formed in contact with the third oxide conductive layer 108c and the fourth oxide conductive layer 108d, thereby achieving an electrical connection.

[0194] A first insulating layer 114 is formed on the first oxide semiconductor layer 112a and the second oxide semiconductor layer 112b. The first insulating layer 114 is formed, for example, by stacking a second silicon oxide film 140b and a second silicon nitride film 141b from the oxide semiconductor layer 112 side. Thus, the first silicon oxide film 140a is formed on the lower side of the oxide semiconductor layer 112, and the second silicon oxide film 140b is formed on the upper side. The oxide semiconductor layer 112 is sandwiched between the oxide-based insulating films, thereby suppressing the generation of defects (donor levels) caused by oxygen vacancies.

[0195] Furthermore, the first silicon oxide films 140a and 140b ideally have no oxygen vacancies to prevent oxygen from being deprived from the first oxide semiconductor layer 112a, and preferably contain an excessive amount of oxygen. After forming the first insulating layer 114, a heat treatment at 250°C to 400°C is performed to diffuse oxygen from the first and second silicon oxide films 140a and 140b into the first and second oxide semiconductor layers 112a and 112b. This heat treatment allows oxygen vacancies to be compensated by oxygen diffused from the silicon oxide film 140, even if they are present in the oxide semiconductor layer 112. This annihilates defects that would otherwise become donor levels, thereby improving resistance.

[0196] A second contact hole 117b is formed in the first insulating layer 114 in a region overlapping with the second capacitor electrode 160b. Thereafter, the fourth conductive film 115 is formed. The fourth conductive film 115 is formed in the same manner as the first conductive film 103.

[0197] Figure 21 、 Figure 22A and Figure 22B This shows the stage of forming the first gate electrode 116 . Figure 21 A top view of a region corresponding to pixel 122a at this stage is shown. Figure 22A represents a cross-sectional view corresponding to line A1-A2, Figure 22B A cross-sectional view corresponding to line B1-B2 is shown.

[0198] The first gate electrode 116 is formed by etching the fourth conductive film through a photolithography process. The first gate electrode 116a is formed to include a region where the first oxide conductive layer 108a and one end of the second oxide conductive layer 108b overlap, via the first insulating layer 114. Furthermore, the first gate electrode 116b is formed to include a region where the third oxide conductive layer 108c and one end of the fourth oxide conductive layer 108d overlap, via the first insulating layer 114. This forms the drive transistor 126 and the select transistor 124. Furthermore, the capacitor 128 is electrically connected to the first gate electrode 116a via the second contact hole 117b.

[0199] like Figure 23A and Figure 23B As shown, a planarization layer 142 is formed so as to bury the selection transistor 124, the drive transistor 126, and the capacitor 128. The planarization layer 142 is formed of an organic resin material such as an acrylic resin, a polyimide resin, an epoxy resin, or a polyamide resin. In the planarization layer 142, an opening 144 is formed in a region overlapping with the first electrode 146 serving as a cathode, exposing the first oxide semiconductor layer 112a. When the planarization layer 142 is formed of a photosensitive resin material, the opening 144 is formed by performing an exposure process using a photomask. In addition, before forming the planarization layer 142, an opening is formed in advance in the first insulating layer 114 in a region corresponding to the opening 144. Alternatively, an opening exposing the first oxide semiconductor layer 112a may be formed in the first insulating layer 114 at the stage of forming the opening 144 in the planarization layer 142. The opening 144 of the planarization layer 142 is preferably formed so that the inner wall surface becomes a trapezoidal shape in order to form the organic EL element 130 .

[0200] Figure 24A and Figure 24BIndicates the stage of forming the electron transport layer 148 and the electron injection layer 150. The electron transport layer 148 is formed using a metal oxide material. As the metal oxide material, a sputtering target of a ternary oxide material, a binary oxide material, or a unary oxide material, which is the same as the material described in the first embodiment, is used and produced by sputtering. The electron injection layer 150 is made of C12A7 electron salt. The electron injection layer 150 can also be produced by sputtering using a sputtering target of C12A7 electron salt. In this case, the sputtering method can be implemented using at least one gas species selected from the group consisting of He (helium), Ne (neon), N2 (nitrogen), Ar (argon), NO (nitrogen monoxide), Kr (krypton), and Xe (xenon). The electron transport layer 148 and the electron injection layer 150 are layers commonly used between multiple pixels, and are therefore formed on substantially the entire surface of the area where the pixel 122a is configured.

[0201] Thereafter, a light emitting layer 152, a hole transport layer 154, a hole injection layer 156, and a second electrode 158 as an anode are formed, thereby forming Figure 11A and Figure 11B The pixel shown. The light-emitting layer 152 is formed using different light-emitting materials corresponding to the red pixel, the green pixel, and the blue pixel. When the light emitted from the light-emitting layer 152 has a white light emission spectrum, it can be formed as a layer common to all pixels on substantially the entire surface of the display area 121. The hole transport layer 154 and the hole injection layer 156 are formed as layers common to all pixels on substantially the entire surface of the area where the pixel 122a is configured. In addition, the second electrode 158, which serves as an anode, is formed on substantially the entire surface of the area where the pixel 122a is configured because it serves as a common electrode between pixels.

[0202] According to the method for manufacturing the display device 120 according to this embodiment, by using the multi-stage photomask 201 , the number of photomasks required for manufacturing can be reduced. Figures 25A to 25C 2 shows patterns near the capacitor 128 and the selection transistor 124 of a photomask used for manufacturing the display device 120 according to this embodiment. Figure 25AThis is a multi-stage photomask 201 used to form the third oxide conductive layer 108c, the fourth oxide conductive layer 108d, the data signal line 134, and the second capacitor electrode 160b. The non-transparent region 203 of the multi-stage photomask 201 corresponds to the region where the data signal line 134 and the second capacitor electrode 160b are formed. The semi-transparent region 202 corresponds to the region where the third oxide conductive layer 108c and the fourth oxide conductive layer 108d are formed. By using this multi-stage photomask 201, multiple patterns (such as the first oxide conductive layer 108a, the second oxide conductive layer 108b, the third oxide conductive layer 108c, and the fourth oxide conductive layer 108d, as well as the data signal line 134, the second common wiring 136b, and the second capacitor electrode 160b) can be produced with a single exposure. Figure 25B This is a photomask for forming the second oxide semiconductor layer 112 b . By using such a photomask, a plurality of patterns (the first oxide semiconductor layer 112 a and the second oxide semiconductor layer 112 b ) can be formed by a single exposure. Figure 25C This is a photomask for forming the first gate electrode 116. By using this photomask, multiple patterns (the first gate electrode 116a and the first gate electrode 116b) can be produced by a single exposure. This can improve the productivity of the display device 120 and reduce manufacturing costs. In this embodiment, although the selection transistor 124 is discussed as a thin film transistor for an organic EL element, it can also be applied to a liquid crystal display element. It can also be improved. Figures 25A to 25C A selection transistor for a liquid crystal display element is manufactured using the photomask group described above.

[0203] In addition, in this embodiment, the selection transistor 124 and the driving transistor 126 are both shown to have a top-gate structure, but the present invention is not limited thereto. For example, the selection transistor 124 and the driving transistor 126 may also use a double-gate transistor in which a bottom gate is arranged in a region overlapping with the first gate electrode 116 as described below. Figure 9 The circuit shown as an example may also be applied to a pixel circuit having three or more transistors per pixel by using the transistor and the organic EL element according to this embodiment.

[0204] 3rd embodiment:

[0205] In the third embodiment, a transistor having a different configuration from the first embodiment is described. The third embodiment differs from the first embodiment in that a second gate electrode 104 is disposed on one surface side (the substrate 102 side) of the oxide semiconductor layer 112. The same reference numerals as in the first embodiment are used to designate the same components as those described above, and duplicate descriptions are omitted.

[0206] 3-1. Transistor Structure

[0207] Figure 26 The structure of a transistor 100b according to one embodiment of the present invention is shown in a cross-sectional view. The transistor 100b includes a second gate electrode 104, a second insulating layer 106, an oxide semiconductor layer 112, a first insulating layer 114, and a first gate electrode 116, which are provided on a substrate 102 having an insulating surface. The oxide semiconductor layer 112 includes a first region 112-1 and a second region 112-2, as viewed from the substrate 102 side.

[0208] The second gate electrode 104 is arranged on one surface side of the oxide semiconductor layer 112 (on the substrate 102 side). The second insulating layer 106 is arranged between the oxide semiconductor layer 112 and the second gate electrode 104. The first gate electrode 116 is arranged on the other surface side of the oxide semiconductor layer 112 (on the side opposite to the substrate 102). The first insulating layer 114 is arranged between the oxide semiconductor layer 112 and the first gate electrode 116. The second gate electrode 104 and the first gate electrode 116 are arranged so as to include a region where the oxide semiconductor layer 112 and the first insulating layer 114 overlap, with the second insulating layer 106 interposed therebetween. The transistor 100b forms a channel in the region where the oxide semiconductor layer 112, the second gate electrode 104, and the first gate electrode 116 overlap. The second insulating layer 106 functions as a gate insulating film in the region where the oxide semiconductor layer 112 and the second gate electrode 104 overlap. The first insulating layer 114 functions as a gate insulating film in the region where the oxide semiconductor layer 112 and the first gate electrode 116 overlap.

[0209] The second insulating layer 106 is arranged between the oxide semiconductor layer 112 and the second gate electrode 104. The first oxide conductive layer 108a and the second oxide conductive layer 108b are arranged between the oxide semiconductor layer 112 and the second insulating layer 106. The first oxide conductive layer 108a and the second oxide conductive layer 108b are provided in contact with the oxide semiconductor layer 112. One end of the first oxide conductive layer 108a and one end of the second oxide conductive layer 108b are arranged to overlap with the second gate electrode 104 and the first gate electrode 116. One of the first oxide conductive layer 108a and the second oxide conductive layer 108b functions as a source region, and the other functions as a drain region. Figure 26 In the structure shown, by configuring one end of the first oxide conductive layer 108a and the second oxide conductive layer 108b to overlap with the second gate electrode 104 and the first gate electrode 116, an offset region (region with high resistance) is not formed in the oxide semiconductor layer 112, thereby further improving the on-current.

[0210] A first wiring 110a is provided in contact with the first oxide conductive layer 108a, and a second wiring 110b is provided in contact with the second oxide conductive layer 108b. The first wiring 110a is arranged between the first oxide conductive layer 108a and the oxide semiconductor layer 112, and the second wiring 110b is arranged between the second oxide conductive layer 108b and the oxide semiconductor layer 112. Providing the first wiring 110a and the second wiring 110b in contact with the first oxide conductive layer 108a and the second oxide conductive layer 108b, respectively, can reduce the number of photolithography steps.

[0211] 3-2. Description of Transistor Operation and Function

[0212] The transistor 100b has a second gate electrode 104 on one surface side (the substrate 102 side) of the oxide semiconductor layer 112, and a first gate electrode 116 on the other surface side (the side opposite to the substrate 102). A channel is formed in the region where the oxide semiconductor layer 112, the second gate electrode 104, and the first gate electrode 116 overlap. The carrier concentration of the second region 112-2 constituting the oxide semiconductor layer 112 is lower than that of the first region 112-1. Therefore, the transistor 100b has a channel formed in the first region 112-1 of the oxide semiconductor layer 112. By allowing current to flow through both the second region 112-2 side (the first gate electrode 116 side) of the first region 112-1 of the oxide semiconductor layer 112 and the second insulating layer 106 side of the first region 112-1 (the upper and lower interfaces of the first region 112-1), the field-effect mobility of the transistor 100b can be improved. Furthermore, fluctuations in the threshold voltage of the transistor 100 b can be suppressed, and reliability can be improved due to stable electrical characteristics.

[0213] By applying a certain potential (fixed potential) to one of the second gate electrode 104 and the first gate electrode 116, it can be used as a back gate. In the case of an n-channel transistor 100b, for example, by applying a potential lower than the source potential to one of the second gate electrode 104 and the first gate electrode 116, it can function as a back gate electrode. This can suppress fluctuations in the threshold voltage of the transistor 100b. In addition, by applying the same gate voltage to the second gate electrode 104 and the first gate electrode 116, the transistor 100b can operate as a dual-gate transistor. As a result, the transistor 100b can achieve an increase in on-current and an improvement in frequency characteristics.

[0214] The transistor 100b is provided with a first oxide conductive layer 108a and a second oxide conductive layer 108b on one surface side (substrate 102 side) of the oxide semiconductor layer 112. The first oxide conductive layer 108a and the second oxide conductive layer 108b are in contact with the first region 112-1 of the oxide semiconductor layer 112. In the oxide semiconductor layer 112, the conductivity of the first region 112-1 is higher than the conductivity of the second region 112-2. Therefore, the contact resistance between the first oxide conductive layer 108a and the first region 112-1 of the oxide semiconductor layer 112, and the contact resistance between the second oxide conductive layer 108b and the first region 112-1 of the oxide semiconductor layer 112 can be reduced. In other words, by making the first oxide conductive layer 108a and the second oxide conductive layer 108b contact the surface of the oxide semiconductor layer 112 on the substrate 102 side, the contact resistance can be reduced. The carrier concentration of the oxide conductive layer 108 is preferably 10 20 / cm 3 More than 10 21 / cm 3 The conductivity of the oxide conductive layer 108 is preferably 1×10 2 S / cm or more, more preferably 1×10 3 S / cm or more. The first region 112-1 of the oxide semiconductor layer 112 in contact with the oxide conductive layer 108 has both a carrier concentration and a conductivity that are lower by at least two digits compared to the oxide conductive layer 108. The second region 112-2 of the oxide semiconductor layer 112 in contact with the first region 112-1 of the oxide semiconductor layer 112 has both a carrier concentration and a conductivity that are lower by at least two digits compared to the first region 112-1. The carrier mobility of the second region 112-2 of the oxide semiconductor layer 112 is also lower than the carrier mobility of the first region 112-1 of the oxide semiconductor layer 112.

[0215] 3-3. Manufacturing method

[0216] The manufacturing process of the transistor 100b is the same as the manufacturing method of the transistor according to the first embodiment, except that a second gate electrode 104 is formed on one surface of the substrate 102, and a second insulating layer 106, a second conductive film 107, and a third conductive film 109 are formed on the second gate electrode 104. Therefore, only the stage of forming the second gate electrode 104 on the substrate 102 will be described here. The second gate electrode 104 can be made of the same metal material as the first gate electrode 116.

[0217] First, a first conductive film is formed on one surface of the substrate 102. Thereafter, a photoresist mask is formed on the first conductive film by a photolithography process, and the second gate electrode 104 is formed by etching. The thickness of the first conductive film is not limited, and it is, for example, made to have a thickness of about 100 nm to 2000 nm. The second gate electrode 104 preferably has a trapezoidal end face when observed in a cross section. By making the end face of the second gate electrode 104 have a trapezoidal shape, it can be reliably covered by the second insulating layer 106. Therefore, in the etching process for forming the second gate electrode 104, it is preferred to perform so-called trapezoidal etching, which can perform etching according to the photoresist mask while anisotropically etching the first conductive film. The photoresist mask remaining after the second gate electrode 104 is formed is removed by treatment with a stripping solution and ashing.

[0218] As in the first embodiment, according to the manufacturing method of the transistor 100b involved in this embodiment, by using the same sputtering target and controlling the oxygen partial pressure of the sputtering gas, the first region 112-1 and the second region 112-2 of the oxide semiconductor layer 112 can be continuously manufactured, thereby improving productivity.

[0219] Fourth embodiment:

[0220] This embodiment shows an example of a display device including transistors having the same structure as the transistors described in Embodiment 3. Components identical to those in Embodiment 2 are denoted by the same reference numerals as those described above, and redundant descriptions are omitted.

[0221] 4-1. Equivalent circuit

[0222] Figure 27 FIG. 1 shows an equivalent circuit of a pixel 122b of a display device according to this embodiment. The pixel 122b includes a selection transistor 124b, a driving transistor 126b, a capacitor 128, and an organic EL element 130. The selection transistor 124b and the driving transistor 126b have the same structure as the transistor 100b shown in the third embodiment. That is, Figure 27 The transistors have a dual-gate structure. The selection transistor 124b includes a second gate electrode 104b and a first gate electrode 116b, and the driving transistor 126b includes a second gate electrode 104a and a first gate electrode 116a.

[0223] In this embodiment, the selection transistor 124b and the driver transistor 126b are n-channel transistors. The gate of the selection transistor 124b (the second gate electrode 104b and the first gate electrode 116b) is connected to the gate signal line 132a. One terminal of the input / output terminal (source and drain) of the selection transistor 124b is connected to the data signal line 134, and the other terminal is connected to the gate (the second gate electrode 104a and the first gate electrode 116a) of the driver transistor 126b. The gate (the second gate electrode 104a and the first gate electrode 116a) of the driver transistor 126b is connected to the other terminal of the input / output terminal of the selection transistor 124b. The drain of the driver transistor 126b is connected to the organic EL element 130, and the source is connected to the second common wiring 136b. One terminal of the capacitor 128 is connected to the other terminal of the input / output terminal (source and drain) of the selection transistor 124b, and the other terminal is connected to the first common wiring 136a. For example, a ground potential is supplied to the first common wiring 136 a and the second common wiring 136 b .

[0224] One terminal of the organic EL element 130 is connected to the drain of the driving transistor 126 b, and the other terminal is connected to the power supply line 138. A power supply potential VDD is supplied to the power supply line 138, which is higher than the potential of the common wiring 136. In this embodiment, the terminal of the organic EL element 130 connected to the drain of the driving transistor 126 b serves as a cathode, and the terminal connected to the power supply line 138 serves as an anode.

[0225] 4-2. Pixel Structure

[0226] Will and Figure 27 An example of a planar structure of a pixel 122b corresponding to the equivalent circuit shown is shown in FIG. Figure 28 In addition, Figure 28 The cross-sectional structures corresponding to the lines A1-A2 and B1-B2 are shown in FIG. Figure 29A and Figure 29B Shown. Figure 29A 1 shows the cross-sectional structure of the driving transistor 126b and the organic EL element 130. Figure 29B 1 shows a cross-sectional structure of the selection transistor 124b and the capacitor 128. In the following description, reference is made to Figure 28 、 Figure 29A and Figure 29B In addition, Figure 28 In the top view of the pixel 122 b shown, the structure of the organic EL element 130 is omitted.

[0227] 4-2-1. Driver transistor

[0228] The driver transistor 126b has the same configuration as the transistor 100b described in Embodiment 3. Specifically, the driver transistor 126b has a stacked structure comprising a second gate electrode 104a, a second insulating layer 106, a first oxide semiconductor layer 112a, a first insulating layer 114, and a first gate electrode 116a. The second gate electrode 104a is provided between the substrate 102 and the second insulating layer 106. The first gate electrode 116a is provided on the upper layer of the first insulating layer 114 (on the side opposite to the substrate 102).

[0229] The first oxide conductive layer 108a and the second oxide conductive layer 108b are provided between the second insulating layer 106 and the first oxide semiconductor layer 112a. The first oxide conductive layer 108a and the second oxide conductive layer 108b are provided in contact with the first oxide semiconductor layer 112, thereby functioning as source and drain regions.

[0230] The first oxide conductive layer 108a and the second oxide conductive layer 108b have regions overlapping with the second gate electrode 104a and the first gate electrode 116a, and are provided so as to sandwich the second gate electrode 104a and the first gate electrode 116a from both sides in a plan view. The second oxide conductive layer 108b has a U-shaped pattern in a plan view, at least in the region overlapping with the second gate electrode 104a and the first gate electrode 116a. The first oxide conductive layer 108a has a linear pattern extending inside the U-shaped pattern of the second oxide conductive layer 108b. Figure 26 The cross-sectional view of the transistor shown in FIG. 1 shows a unit structure of the first oxide conductive layer 108 a to the second oxide conductive layer 108 b. Figure 28 In the cross-sectional view of the driving transistor 126b in the second direction (D2 direction), Figure 26 The second gate electrode 104a is provided in the same layer structure as the first common wiring 136a.

[0231] In this embodiment, the driving transistor 126b includes the oxide semiconductor layer 112 formed of a first region 112-1 and a second region 112-2. Furthermore, the carrier concentration of the second region 112-2 is lower than that of the first region 112-1. Consequently, the driving transistor 126 has a structure in which a channel is formed in the first region 112-1, which is away from the first insulating layer 114, in the oxide semiconductor layer 112. The driving transistor 126b of this embodiment can improve field-effect mobility by providing the second region 112-2 between the first region 112-1 and the first insulating layer 114 of the oxide semiconductor layer 112. Furthermore, fluctuations in the threshold voltage of the driving transistor 126b can be suppressed, and reliability can be improved through stable electrical characteristics. Furthermore, the driving transistor 126b has a dual-gate structure, which improves current drive capability. Therefore, when driving the organic EL element 130, sufficient current can be supplied even when the voltage of the second electrode 158, which serves as the anode, is reduced. Even if the operating point of the organic EL element fluctuates, constant current driving can be performed in accordance with the fluctuation of the operating point. By adopting a dual-gate structure for the driving transistor 126b, power consumption can be reduced, thereby solving the problem of heat generation that becomes prominent when the organic EL display device is enlarged, and effectively extending the life of the organic EL element.

[0232] 4-2-2. Selecting transistors

[0233] The selection transistor 124b has the same configuration as the transistor 100b described in Embodiment 3. Specifically, the selection transistor 124b has a stacked structure comprising a second gate electrode 104b, a second insulating layer 106, a second oxide semiconductor layer 112b, a first insulating layer 114, and a first gate electrode 116b. The channel of the selection transistor 124b is formed in the region where the second oxide semiconductor layer 112b, the second gate electrode 104b, and the first gate electrode 116b overlap.

[0234] The third oxide conductive layer 108c and the fourth oxide conductive layer 108d are provided between the second insulating layer 106 and the second oxide semiconductor layer 112b. The third oxide conductive layer 108c and the fourth oxide conductive layer 108d are provided in contact with the second oxide semiconductor layer 112b, thereby functioning as source and drain regions.

[0235] The third oxide conductive layer 108c and the fourth oxide conductive layer 108d have regions overlapping with the second gate electrode 104b and the first gate electrode 116b, and are provided so as to sandwich the second gate electrode 104b and the first gate electrode 116b from both sides in a plan view. The third oxide conductive layer 108c has a U-shaped pattern in a plan view, at least in the region overlapping with the second gate electrode 104b and the first gate electrode 116b. The fourth oxide conductive layer 108d has a linear pattern extending inside the U-shaped pattern of the third oxide conductive layer 108c. Figure 26 The cross-sectional view of the transistor shown in FIG. 1 shows a unit structure of the first oxide conductive layer 108 a to the second oxide conductive layer 108 b. Figure 28 In the cross-sectional view of the selection transistor 124b in the second direction (D2 direction) Figure 26 The second gate electrode 104b is provided in the same layer structure as the first capacitor electrode 160a.

[0236] 4-3. Transistor Structure

[0237] like Figure 29A and Figure 29B As shown, the structure of pixel 122b according to this embodiment is a structure in which the second electrode 158 covers the entire surface of the drive transistor 126b and the select transistor 124b. Furthermore, the drive transistor 126b and the select transistor 124b have a bottom-contact dual-gate structure, in which the first oxide conductive layer 108a and the second oxide conductive layer 108b are arranged in contact with the lower layer of the oxide semiconductor layer 112 forming the channel, the second gate electrode 104 is arranged on the lower layer side of the oxide semiconductor layer 112, and the first gate electrode 116 is arranged on the upper layer side of the oxide semiconductor layer 112.

[0238] Figure 30A and Figure 30BFigure 1 shows the bottom-contact dual-gate structure of the transistor 100b according to this embodiment, in which the first oxide conductive layer 108a and the second oxide conductive layer 108b are arranged in contact with the lower layer of the oxide semiconductor layer 112, the first gate electrode 116 is arranged on the upper side of the oxide semiconductor layer 112, and the second gate electrode 104 is arranged on the lower side of the oxide semiconductor layer 112. Since the oxide semiconductor layer 112 has a first region 112-1 having a higher carrier concentration than the second region 112-2, the transistor 100b according to this embodiment allows current to flow through the region of the oxide semiconductor layer 112 on the second region 112-2 side (the first gate electrode 116 side) of the first region 112-1, thereby improving field-effect mobility. In addition, by bringing the first oxide conductive layer 108a and the second oxide conductive layer 108b into contact with the first region 112-1 of the oxide semiconductor layer 112 having high conductivity, the contact resistance between the first oxide conductive layer 108a and the first region 112-1 of the oxide semiconductor layer 112 and the contact resistance between the second oxide conductive layer 108b and the first region 112-1 of the oxide semiconductor layer 112 can be reduced.

[0239] By adopting a configuration in which gate electrodes are provided on the lower and upper sides of the oxide semiconductor layer 112 as shown in this embodiment, it is possible to suppress the accumulation of positive charge on the back channel side of the oxide semiconductor layer 112. In this case, the second gate electrode 104 can be grounded to a constant potential or supplied with the same voltage as the first gate electrode 116, thereby stabilizing the potential on the back channel side.

[0240] Figure 30A , as one embodiment of the transistor 100b, shows a structure in which the second gate electrode 104 on the lower side of the oxide semiconductor layer 112 and the first gate electrode 116 on the upper side overlap with the first oxide conductive layer 108a and the second oxide conductive layer 108b corresponding to the source and drain electrodes. The width W of the second gate electrode 104 in the channel length direction is bottom The overlap width W between the first oxide conductive layer 108a and the second oxide conductive layer 108b is ov1 The width W of the first gate electrode 116 in the channel length direction is top The overlap width W between the first oxide conductive layer 108a and the second oxide conductive layer 108b is ov2By overlapping the second gate electrode 104 with the first gate electrode 116 and portions of the first oxide conductive layer 108a and the second oxide conductive layer 108b, the channel region of the oxide semiconductor layer 112 is substantially shielded from the influence of the external electric field. Consequently, even if the second electrode 158 is arranged to cover the entire surface of the transistor 100b, it is not affected by the electric field from the second electrode 158. Furthermore, the threshold voltage of the transistor 100b can be prevented from fluctuating over time.

[0241] Figure 30B , as one embodiment of the transistor 100b, shows a structure in which the upper first gate electrode 116 overlaps with both the first oxide conductive layer 108a and the second oxide conductive layer 108b, which correspond to the source and drain electrodes, and the second gate electrode 104 does not overlap with the first oxide conductive layer 108a and the second oxide conductive layer 108b. The width W of the first gate electrode 116 in the channel length direction is top The overlap width W between the first oxide conductive layer 108a and the second oxide conductive layer 108b is ov2 On the other hand, the width W of the second gate electrode 104 in the channel length direction is bottom The distance between the first oxide conductive layer 108a and the second oxide conductive layer 108b is narrower and offset by a width W. off . By making the first gate electrode 116 overlap with at least a portion of the first oxide conductive layer 108a and the second oxide conductive layer 108b in this way, the channel region of the oxide semiconductor layer 112 is substantially shielded from the influence of the electric field of the second electrode 158. Therefore, it is possible to prevent the threshold voltage of the transistor 100b from changing over time. That is, the area where the first gate electrode and the oxide semiconductor layer overlap is larger than the area where the second gate electrode and the oxide semiconductor layer overlap, thereby shielding the influence of the charge that may accumulate on the back channel side. In other words, by arranging the second gate electrode 104 and the first gate electrode 116 to overlap in a plan view, and providing the first gate electrode 116 in a manner that covers the second gate electrode 104, it is possible to shield the influence of the charge that may accumulate on the back channel side.

[0242] Furthermore, considering the alignment accuracy of the photomask in the photolithography process, it is preferable to set the width W of the first gate electrode to top Greater than the width W of the second gate electrode 104 bottom (W top >W bottom That is, by making the width of the upper first gate electrode 116 larger than the lower second gate electrode 104, it is possible to provide a margin for the alignment accuracy of the photomask in the photolithography process, so that the channel region formed in the oxide semiconductor layer 112 can be reliably covered by the first gate electrode 116.

[0243] 4-4. Method for Manufacturing Display Device

[0244] Regarding the manufacturing process of the display device 120 involved in one embodiment of the present invention, a second gate electrode 104 is formed on one surface of the substrate 102, and a second insulating layer 106, a second conductive film 107, and a third conductive film 109 are formed on the upper layer of the second gate electrode 104. Other than this, the manufacturing method of the display device is the same as that involved in the first embodiment. Therefore, here, only the stage of forming the second gate electrode 104 on the substrate 102 is described.

[0245] The second gate electrodes 104a and 104b, the first capacitor electrode 160a, and the first common wiring 136a are formed on the substrate 102. The first common wiring 136a and the first capacitor electrode 160a are formed from the same conductive film as the second gate electrodes 104a and 104b. Therefore, the second gate electrode 104a and the gate signal line 132a are formed as a continuous pattern using the conductive film formed in the same layer. Similarly, the first common wiring 136a and the first capacitor electrode 160a are formed as a continuous pattern using the conductive film formed in the same layer.

[0246] As in the first embodiment, according to the method for manufacturing the display device 120 of this embodiment, the number of photomasks required for manufacturing can be reduced by using the multi-stage photomask 201. Figure 31A and Figure 31B 3 shows the vicinity of the capacitor 128 and the selection transistor 124 of an additional photomask used in manufacturing the display device 120 according to this embodiment. Figure 31A This is a photomask used to form the second gate electrode 104b, the first capacitor electrode 160a, and the first common wiring 136a. By using this photomask, multiple patterns (the second gate electrodes 104a and 104b, the first capacitor electrode 160a, and the first common wiring 136a) can be formed in a single exposure. Figure 31B This is a photomask for forming the third contact hole 117c connecting the second gate electrode 104b and the first gate electrode 116. By adding and using the additional photomask used in the method for manufacturing the display device 120 according to the first embodiment, the reliability of the display device 120 can be improved and power consumption can be reduced.

[0247] As in the first embodiment, according to the manufacturing method of the transistor 100b involved in this embodiment, by using the same sputtering target and controlling the oxygen partial pressure of the sputtering gas, the first region 112-1 and the second region 112-2 of the oxide semiconductor layer 112 can be continuously manufactured, which can improve productivity.

[0248] In addition, in this embodiment, the selection transistor 124b and the driving transistor 126b are both dual-gate structures, but the present invention is not limited thereto. For example, the selection transistor 124b or the driving transistor 126b may also be a top-gate transistor in which the second gate electrode 104b is omitted. Figure 27 The circuit shown as an example may also be applied to a pixel circuit having three or more transistors per pixel by using the transistor and the organic EL element according to this embodiment.

[0249] 5th embodiment:

[0250] In the fifth embodiment, a transistor having a different configuration from that in the first embodiment is described. The fifth embodiment differs from the first embodiment in that the first wiring 110 a is disposed between the first oxide conductive layer 108 a and the second insulating layer 106 , and the second wiring 110 b is disposed between the second oxide conductive layer 108 b and the second insulating layer 106 . Components identical to those in the first embodiment are denoted by the same reference numerals as described above, and duplicate descriptions are omitted.

[0251] 5-1. Transistor Structure

[0252] Figure 32 The structure of a transistor 100c according to one embodiment of the present invention is shown in a cross-sectional view. The transistor 100c includes a second insulating layer 106, an oxide semiconductor layer 112, a first insulating layer 114, and a first gate electrode 116, which are provided on a substrate 102 having an insulating surface.

[0253] The first gate electrode 116 is disposed on one surface side of the oxide semiconductor layer 112 (the side opposite to the substrate 102). The first insulating layer 114 is disposed between the oxide semiconductor layer 112 and the first gate electrode 116. The first gate electrode 116 and the oxide semiconductor layer 112 are disposed so as to include an overlapping region with the first insulating layer 114 interposed therebetween. The transistor 100c forms a channel in the region where the oxide semiconductor layer 112 and the first gate electrode 116 overlap. The first insulating layer 114 functions as a gate insulating film in the region where the oxide semiconductor layer 112 and the first gate electrode 116 overlap.

[0254] A second insulating layer 106 is disposed between the oxide semiconductor layer 112 and the substrate 102. A first oxide conductive layer 108a and a second oxide conductive layer 108b are disposed between the oxide semiconductor layer 112 and the second insulating layer 106. The first oxide conductive layer 108a and the second oxide conductive layer 108b are disposed in contact with the oxide semiconductor layer 112. One end of the first oxide conductive layer 108a and one end of the second oxide conductive layer 108b are disposed so as to overlap with the first gate electrode 116. One of the first oxide conductive layer 108a and the second oxide conductive layer 108b functions as a source region, and the other functions as a drain region. Figure 32 In the structure shown, one end of the first oxide conductive layer 108 a and the second oxide conductive layer 108 b is arranged to overlap with the first gate electrode 116 , thereby preventing an offset region (region with high resistance) from being formed in the oxide semiconductor layer 112 , thereby increasing the on-current.

[0255] A first wiring 110a is provided in contact with the first oxide conductive layer 108a, and a second wiring 110b is provided in contact with the second oxide conductive layer 108b. The first wiring 110a is arranged between the first oxide conductive layer 108a and the second insulating layer 106, and the second wiring 110b is arranged between the second oxide conductive layer 108b and the second insulating layer 106. In the transistor 100c according to this embodiment, the oxide semiconductor layer 112 is not in direct contact with the first wiring 110a and the second wiring 110b, thereby preventing contamination by the metal used as the wiring material.

[0256] 6th embodiment:

[0257] In the sixth embodiment, a transistor having a different configuration from that in the fifth embodiment is described. The sixth embodiment differs from the fifth embodiment in that a second gate electrode 104 is provided on one surface side (the substrate 102 side) of the oxide semiconductor layer 112. The same components as in the first to fifth embodiments are denoted by the same reference numerals as described above, and duplicate descriptions are omitted.

[0258] 6-1. Transistor Structure

[0259] Figure 33 The structure of a transistor 100d according to one embodiment of the present invention is shown in a cross-sectional view. The transistor 100d includes a second gate electrode 104, a second insulating layer 106, an oxide semiconductor layer 112, a first insulating layer 114, and a first gate electrode 116, which are provided on a substrate 102 having an insulating surface.

[0260] The second gate electrode 104 is arranged on one surface side of the oxide semiconductor layer 112 (on the substrate 102 side). The second insulating layer 106 is arranged between the oxide semiconductor layer 112 and the second gate electrode 104. The first gate electrode 116 is arranged on the other surface side of the oxide semiconductor layer 112 (on the side opposite to the substrate 102). The first insulating layer 114 is arranged between the oxide semiconductor layer 112 and the first gate electrode 116. The second gate electrode 104 and the first gate electrode 116 are arranged so as to include a region where the oxide semiconductor layer 112 and the first insulating layer 114 overlap, with the second insulating layer 106 interposed therebetween. The transistor 100d forms a channel in the region where the oxide semiconductor layer 112, the second gate electrode 104, and the first gate electrode 116 overlap. The second insulating layer 106 functions as a gate insulating film in the region where the oxide semiconductor layer 112 and the second gate electrode 104 overlap. The first insulating layer 114 functions as a gate insulating film in the region where the oxide semiconductor layer 112 and the first gate electrode 116 overlap.

[0261] The second insulating layer 106 is arranged between the oxide semiconductor layer 112 and the second gate electrode 104. The first oxide conductive layer 108a and the second oxide conductive layer 108b are arranged between the oxide semiconductor layer 112 and the second insulating layer 106. The first oxide conductive layer 108a and the second oxide conductive layer 108b are provided in contact with the oxide semiconductor layer 112. One end of the first oxide conductive layer 108a and one end of the second oxide conductive layer 108b are arranged to overlap with the second gate electrode 104 and the first gate electrode 116. One of the first oxide conductive layer 108a and the second oxide conductive layer 108b functions as a source region, and the other functions as a drain region. Figure 33 In the structure shown, by configuring one end of the first oxide conductive layer 108a and the second oxide conductive layer 108b to overlap with the second gate electrode 104 and the first gate electrode 116, an offset region (region with high resistance) is not formed in the oxide semiconductor layer 112, thereby increasing the on-current.

[0262] A first wiring 110a is provided in contact with the first oxide conductive layer 108a, and a second wiring 110b is provided in contact with the second oxide conductive layer 108b. The first wiring 110a is arranged between the first oxide conductive layer 108a and the second insulating layer 106, and the second wiring 110b is arranged between the second oxide conductive layer 108b and the second insulating layer 106. In the transistor 100d according to this embodiment, the oxide semiconductor layer 112 is not in direct contact with the first wiring 110a and the second wiring 110b, thereby preventing contamination by the metal used as the wiring material.

[0263] The present invention is not limited to the above-described embodiment, and can be modified appropriately within the scope of the gist of the invention.

Claims

1. A transistor comprising: an oxide semiconductor layer disposed on the substrate and including a first region and a second region; a first gate electrode having a region overlapping with the oxide semiconductor layer and arranged on a surface of the oxide semiconductor layer opposite to the substrate side; a first insulating layer located between the first gate electrode and the oxide semiconductor layer; as well as a first oxide conductive layer and a second oxide conductive layer, each of which is disposed between the oxide semiconductor layer and the substrate and includes a region in contact with the oxide semiconductor layer; The first region and the second region have an overlapping area, the first region is arranged on the substrate side, and the second region is arranged on the side opposite to the substrate; an energy level of a bottom portion of a conduction band of the second region of the oxide semiconductor layer being higher than an energy level of a bottom portion of a conduction band of the first region of the oxide semiconductor layer; The band gap of the second region of the oxide semiconductor layer is larger than the band gap of the first region of the oxide semiconductor layer; and In the oxide semiconductor layer, carrier mobility in the first region is greater than carrier mobility in the second region.

2. The transistor according to claim 1, wherein The first oxide conductive layer and the second oxide conductive layer are in contact with the first region of the oxide semiconductor layer.

3. The transistor according to claim 1, further comprising: a second insulating layer located between the substrate and the oxide semiconductor layer; and The second gate electrode has a region overlapping with the oxide semiconductor layer and the first gate electrode, and is arranged between the second insulating layer and the substrate.

4. The transistor according to claim 3, wherein The width of the first gate electrode in the channel length direction is greater than the width of the second gate electrode in the channel length direction.

5. The transistor according to claim 1, wherein One end of the first oxide conductive layer and the second oxide conductive layer overlaps with the first gate electrode. The transistor according to claim 1 , wherein: In the oxide semiconductor layer, the electrical conductivity of the first region is higher than the electrical conductivity of the second region.

7. The transistor according to claim 1, wherein In the oxide semiconductor layer, a work function of the first region is greater than a work function of the second region.

8. The transistor according to claim 1, wherein In the oxide semiconductor layer, a crystallinity of the first region is lower than a crystallinity of the second region.

9. The transistor according to claim 1, wherein In the oxide semiconductor layer, the first region has a thickness greater than that of the second region.

10. The transistor according to claim 1, wherein The first insulating layer includes a silicon oxide film in contact with the oxide semiconductor layer and a silicon nitride film in contact with the silicon oxide film.

11. The transistor according to claim 1, wherein The material of the first insulating layer is a silicon-based material that does not contain hydrogen.

12. The transistor according to claim 1, wherein A material of the first region of the oxide semiconductor layer is an oxide material including at least two elements selected from In, Ga, and Sn.

13. The transistor according to claim 1, wherein The first oxide conductive layer and the second oxide conductive layer have regions overlapping with the first gate electrode. The second oxide conductive layer has a U-shaped pattern in a plan view at least in a region overlapping with the first gate electrode, and The first oxide conductive layer has a linear pattern extending inside the U-shaped bent pattern in a plan view.

14. A transistor comprising: an oxide semiconductor layer disposed on a substrate and including a first surface on the substrate side and a second surface on the opposite side to the substrate side; a first gate electrode having a region overlapping with the oxide semiconductor layer and arranged on a surface of the oxide semiconductor layer opposite to the substrate side; a first insulating layer located between the first gate electrode and the oxide semiconductor layer; and a first oxide conductive layer and a second oxide conductive layer, each of which is disposed between the oxide semiconductor layer and the substrate and includes a region in contact with the oxide semiconductor layer; an energy level of a bottom portion of a conduction band of the second surface of the oxide semiconductor layer being higher than an energy level of a bottom portion of a conduction band of the first surface of the oxide semiconductor layer; The band gap of the second surface of the oxide semiconductor layer is larger than the band gap of the first surface of the oxide semiconductor layer; and In the oxide semiconductor layer, the carrier mobility of the first surface is greater than the carrier mobility of the second surface.

15. The transistor according to claim 14, wherein In the oxide semiconductor layer, the crystallinity of the first surface is lower than the crystallinity of the second surface.

16. A method for manufacturing a transistor, comprising: forming a first oxide conductive layer and a second oxide conductive layer on a substrate; forming an oxide semiconductor layer, the oxide semiconductor layer including a first region in contact with the first oxide conductive layer and the second oxide conductive layer, and a second region in contact with a surface of the first region opposite to the substrate side; forming a first insulating layer so as to cover the oxide semiconductor layer; and forming a first gate electrode, the first gate electrode being disposed on the first insulating layer and having a region overlapping with the oxide semiconductor layer; an energy level of a bottom portion of a conduction band of the second region of the oxide semiconductor layer being higher than an energy level of a bottom portion of a conduction band of the first region of the oxide semiconductor layer; The band gap of the second region of the oxide semiconductor layer is larger than the band gap of the first region of the oxide semiconductor layer; and In the oxide semiconductor layer, carrier mobility in the first region is greater than carrier mobility in the second region.

17. The method for manufacturing a transistor according to claim 16, wherein: forming the first region of the oxide semiconductor layer by a sputtering method using a rare gas as a sputtering gas; and The second region of the oxide semiconductor layer is formed by a sputtering method using a rare gas and oxygen as sputtering gases.

18. The method for manufacturing a transistor according to claim 17, wherein: The oxygen partial pressure when the second region is formed is higher than the oxygen partial pressure when the first region is formed.

19. The method for manufacturing a transistor according to claim 17, wherein: The film formation by the sputtering method is performed using a target of an oxide material containing at least two elements selected from In, Ga, and Sn.

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