Fourth-order all-pass two-port network and its construction method

Abstract

The present invention discloses a fourth-order full-pass two-port network and a construction method thereof. The fourth-order full-pass two-port network is distributed in a mirror-symmetrical manner and comprises: an inductive element L d , electrically connected between the first port and the second port; capacitive element C c and C x , two sets of capacitive elements C are connected in series c and C x are electrically connected between the first port and the first node, and between the second port and the first node respectively; the inductive element L c , two inductive elements L c Symmetrically electrically connected between the first node and the second node; the inductive element L a And capacitive component C b , two sets of inductive elements L are connected in series a And capacitive component C b Symmetrically electrically connected between the first node and the second node; the inductive element L b And capacitive component C y , inductive element L b And capacitive component C y After being connected in parallel, they are electrically connected to two sets of capacitive elements C c and C x The fourth-order all-pass two-port network of the present invention can obtain better matching bandwidth, frequency and delay performance; and the construction method is simple and easy to implement.

Description

Technical Field

[0001] The present invention belongs to the technical field of network communications, and in particular relates to a fourth-order all-pass two-port network and a construction method thereof. Background Art

[0002] The all-pass two-port network is mainly used in analog and RF circuit systems, and its main function is to adjust the delay characteristics of the signal. In particular, in the field of broadband phased array antennas, due to the wide signal bandwidth, the traditional phased unit using phase shifters will cause the signals in each channel to produce a delay that varies with the frequency, making it impossible to achieve accurate beamforming. Therefore, the all-pass two-port network is widely used in phased array antenna systems with high bandwidth requirements.

[0003] Traditional all-pass networks can be realized using transmission lines. Ideal transmission lines are all-pass for signals, that is, the amplitude is not attenuated by frequency changes, and only a delay effect is produced on the signal. However, the transmission lines are huge in size and have poor economic efficiency. Another type of traditional delay circuit network generally adopts the form of artificial transmission lines composed of lumped components. Its matching characteristics change with frequency, and the matching frequency range is inversely proportional to the value of the basic network unit components that constitute the artificial transmission line. It cannot be applied to ultra-wideband and high-delay application scenarios.

[0004] The delay circuit network using the all-pass two-port network as the basic unit can ideally obtain an infinite matching frequency range, and its group delay characteristic with a second-order response form can obtain a wider flat delay frequency range. However, the second-order all-pass two-port network has the following disadvantages:

[0005] The transmission line type occupies a large area, has high process requirements and high cost;

[0006] The artificial transmission line form of lumped components is often used, which has limited matching bandwidth and cannot expand the application bandwidth;

[0007] In the form of a second-order all-pass network, the signal delay generated by the unit cell is limited, and the efficiency of signal delay generation is low.

[0008] Therefore, in view of the above technical problems, it is necessary to provide a fourth-order all-pass two-port network and a construction method thereof. Summary of the invention

[0009] The object of the present invention is to provide a fourth-order all-pass two-port network and a construction method thereof, so as to solve the problems of signal delay and the like in the prior art.

[0010] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0011] A fourth-order all-pass two-port network, wherein the fourth-order all-pass two-port network is distributed in a mirror-symmetrical manner, and comprises:

[0012] Inductive element L d , electrically connected between the first port and the second port;

[0013] Capacitive component C c and C x , two sets of capacitive elements C are connected in series c and C x Respectively electrically connected between the first port and the first node, and between the second port and the first node;

[0014] Inductive element L c , two inductive elements L c symmetrically electrically connected between the first node and the second node;

[0015] Inductive element L a And capacitive component C b , two sets of inductive elements L are connected in series a And capacitive component C b symmetrically electrically connected between the first node and the second node;

[0016] Inductive element L b And capacitive component C y , inductive element L b And capacitive component C y After being connected in parallel, they are electrically connected to two sets of capacitive elements C c and C x between.

[0017] In one embodiment, the semi-structured circuit of the fourth-order all-pass two-port network in odd mode and even mode includes:

[0018] In the even mode, it includes an inductive element L1 and a capacitive element C2 connected in series, an inductive element L3 connected in parallel with L1 and C2, and a capacitive element C4 connected in series with L1, C2, and L3;

[0019] In odd mode, it includes a capacitive element C1 and an inductive element L2 arranged in parallel, a capacitive element C3 arranged in series with C1 and L2, and an inductive element L4 arranged in parallel with C1, L2, and C3;

[0020] Among them, the reactance value of the inductive component and the susceptance value of the capacitive component satisfy L a =L1,L b =2L2,L c =L3,L d =2L4,C b =C2,C c =C3,

[0021] In one embodiment, in the fourth-order all-pass two-port network, the reactance value of the inductive element and the susceptance value of the capacitive element satisfy:

[0022]

[0023] Among them, L n is the reactance value of the inductive element, C n is the susceptance value of the capacitive element, and Z0 is the port matching impedance.

[0024] In one embodiment, the input impedance Z of the fourth-order all-pass two-port network in the odd mode and the even mode is in,e , Y in,o They are:

[0025]

[0026]

[0027] Input impedance Z in,e , Y in,o satisfy

[0028] Among them, X1=ωL1, X2=ωL2, X3=ωL3, X4=ωL4, B1=ωC1, B2=ωC2, B3=ωC3, B4=ωC4, ω is the angular frequency, and Z0 is the port matching impedance.

[0029] In one embodiment, the second node is connected to GND.

[0030] In one embodiment, the inductive element includes an inductor, and the capacitive element includes a capacitor.

[0031] Another embodiment of the present invention provides a technical solution as follows:

[0032] A method for constructing a fourth-order all-pass two-port network, the method comprising:

[0033] S1. Determine the semi-structured circuits of the fourth-order all-pass two-port network in odd and even modes;

[0034] S2. A fourth-order all-pass two-port network is obtained based on the semi-structured circuit synthesis in odd-even mode.

[0035] In one embodiment, the semi-structured circuit of the fourth-order all-pass two-port network in the step S1 in the odd mode and the even mode includes:

[0036] In the even mode, it includes an inductive element L1 and a capacitive element C2 connected in series, an inductive element L3 connected in parallel with L1 and C2, and a capacitive element C4 connected in series with L1, C2, and L3;

[0037] In the odd mode, it includes a capacitive element C1 and an inductive element L2 connected in parallel, a capacitive element C3 connected in series with C1 and L2, and an inductive element L4 connected in parallel with C1, L2, and C3.

[0038] In one embodiment, the fourth-order all-pass two-port network in step S2 includes:

[0039] Inductive element L d , electrically connected between the first port and the second port;

[0040] Capacitive component C c and C x , two sets of capacitive elements C are connected in series c and C x Respectively electrically connected between the first port and the first node, and between the second port and the first node;

[0041] Inductive element L c , two inductive elements L c symmetrically electrically connected between the first node and the second node;

[0042] Inductive element L a And capacitive component C b , two sets of inductive elements L are connected in series a And capacitive component C b symmetrically electrically connected between the first node and the second node;

[0043] Inductive element L b And capacitive component C y , inductive element L b And capacitive component C y After being connected in parallel, they are electrically connected to two sets of capacitive elements C c and C x between;

[0044] Among them, the reactance value of the inductive component and the susceptance value of the capacitive component satisfy L a =L1,L b =2L2,L c =L3,L d =2L4,C b =C2,C c =C3,

[0045] In one embodiment, the construction method further comprises:

[0046] According to the formula n=1,2,3,4 determines the reactance value of the inductive element and the susceptance value of the capacitive element in the fourth-order all-pass two-port network;

[0047] Among them, Ln is the reactance value of the inductive element, C n is the susceptance value of the capacitive element, and Z0 is the port matching impedance.

[0048] Compared with the prior art, the present invention has the following advantages:

[0049] The fourth-order all-pass two-port network can achieve better matching bandwidth, frequency and delay performance;

[0050] The construction method of the fourth-order all-pass two-port network is simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0052] Figure 1a , 1b They are schematic diagrams of a two-port network and its semi-structure respectively;

[0053] Figure 2a , 2b They are the circuit structures of a second-order all-pass two-port network and its semi-structure respectively;

[0054] Figure 3a , 3b They are the equivalent circuit diagrams of the half structures of the second-order all-pass two-port network in odd mode and even mode respectively;

[0055] Figure 4 A circuit diagram of a fourth-order all-pass two-port network in a specific embodiment of the present invention;

[0056] Figure 5a , 5b They are respectively semi-structural equivalent circuit diagrams of a fourth-order all-pass two-port network in an odd mode and an even mode in a specific embodiment of the present invention;

[0057] Figure 6 This is a comparison of the time delay-frequency characteristic curves of a fourth-order all-pass two-port network and a second-order all-pass two-port network. DETAILED DESCRIPTION

[0058] The present invention will be described in detail below in conjunction with the various embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0059] The present invention discloses a fourth-order all-pass two-port network, which is distributed in a mirror-symmetrical manner and comprises:

[0060] Inductive element L d , electrically connected between the first port and the second port;

[0061] Capacitive component C c and C x , two sets of capacitive elements C are connected in series c and C x Respectively electrically connected between the first port and the first node, and between the second port and the first node;

[0062] Inductive element L c , two inductive elements L c symmetrically electrically connected between the first node and the second node;

[0063] Inductive element L a And capacitive component C b , two sets of inductive elements L are connected in series a And capacitive component C b symmetrically electrically connected between the first node and the second node;

[0064] Inductive element L b And capacitive component C y , inductive element L b And capacitive component C y After being connected in parallel, they are electrically connected to two sets of capacitive elements C c and C x between.

[0065] The present invention also discloses a method for constructing a fourth-order all-pass two-port network, comprising:

[0066] S1. Determine the semi-structured circuits of the fourth-order all-pass two-port network in odd and even modes;

[0067] S2. A fourth-order all-pass two-port network is obtained based on the semi-structured circuit synthesis in odd-even mode.

[0068] In order to ensure the reciprocity of two ports of the all-pass network, the present invention discusses an all-pass network structure with a symmetrical structure.

[0069] The all-pass two-port network synthesis method of the present invention is based on the odd-even mode theory. Figure 1a The symmetrical two-port network shown in Figure 2 only needs to be analyzed Figure 1b The electrical characteristics of the entire two-port network can be obtained by analyzing the half structure of the two-port network.

[0070] For example Figure 2a A complete second-order all-pass two-port network is shown. Figure 2bThe circuit structure of the half structure after the symmetry plane is divided in the odd-even mode is:

[0071] In odd mode, the symmetric plane is grounded, and its equivalent circuit is Figure 3a As shown;

[0072] In the even mode, the symmetry plane is suspended, and its equivalent circuit is: Figure 3b shown.

[0073] The present invention is further described below in conjunction with specific embodiments.

[0074] Ginseng Figure 4 The circuit diagram of a fourth-order all-pass two-port network in a specific embodiment of the present invention is shown. The network is distributed in a mirror-symmetrical manner, and the two ports (the first port 1 and the second port 2) are symmetrical and reciprocal. The fourth-order all-pass two-port network specifically includes:

[0075] Inductive element L d , electrically connected between the first port 1 and the second port 2;

[0076] Capacitive component C c and C x , two sets of capacitive elements C are connected in series c and C x Electrically connected between the first port 1 and the first node M, and between the second port 2 and the first node M, respectively;

[0077] Inductive element L c , two inductive elements L c Symmetrically electrically connected between the first node M and the second node N;

[0078] Inductive element L a And capacitive component C b , two sets of inductive elements L are connected in series a And capacitive component C b Symmetrically electrically connected between the first node M and the second node N;

[0079] Inductive element L b And capacitive component C y , inductive element L b And capacitive component C y After being connected in parallel, they are electrically connected to two sets of capacitive elements C c and C x between.

[0080] Preferably, the second node in this embodiment is connected to GND.

[0081] In this embodiment, the semi-structured circuit of the fourth-order all-pass two-port network in odd mode and even mode includes:

[0082] Ginseng Figure 5a As shown, in the even mode, the half-structure circuit includes an inductive element L1 and a capacitive element C2 arranged in series, an inductive element L3 arranged in parallel with L1 and C2, and a capacitive element C4 arranged in series with L1, C2, and L3;

[0083] Ginseng Figure 5b As shown, in the odd mode, the half-structure circuit includes a capacitive element C1 and an inductive element L2 arranged in parallel, a capacitive element C3 arranged in series with C1 and L2, and an inductive element L4 arranged in parallel with C1, L2, and C3.

[0084] In this embodiment, the reactance value of the inductive element and the susceptance value of the capacitive element between the fourth-order all-pass two-port network and the half-structure circuit in the odd-even mode meet the following conditions:

[0085] L a =L1,L b =2L2,L c =L3,L d =2L4 (1)

[0086]

[0087] In addition, in the fourth-order all-pass two-port network, the reactance value of the inductive element and the susceptance value of the capacitive element also satisfy:

[0088]

[0089] Among them, L n is the reactance value of the inductive element, C n is the susceptance value of the capacitive element, and Z0 is the port matching impedance.

[0090] Therefore, the input impedance Z of the semi-structure of the fourth-order all-pass two-port network in the odd mode and the even mode in this embodiment is in,e , Y in,o They are:

[0091]

[0092]

[0093] From equation (4) and equation (5), we can get:

[0094]

[0095] Among them, X1=ωL1, X2=ωL2, X3=ωL3, X4=ωL4, B1=ωC1, B2=ωC2, B3=ωC3, B4=ωC4, ω is the angular frequency, and Z0 is the port matching impedance.

[0096] Equation (6) is the relationship that the input impedance of the two-port network needs to satisfy, so, Figure 4 The two-port network disclosed in is an all-pass network.

[0097] In this embodiment, L represents an inductive element, and C represents a capacitive element. The inductive element includes an inductor, etc., and the capacitive element includes a capacitor, etc.

[0098] The present invention also discloses a method for constructing a fourth-order all-pass two-port network, which specifically comprises the following steps:

[0099] 1. Determine the semi-structured circuits of a fourth-order all-pass two-port network in odd and even modes.

[0100] The semi-structured circuits of the fourth-order all-pass two-port network in odd mode and even mode are as follows: Figure 5a , 5b As shown, no further description is given here.

[0101] 2. Based on the semi-structured circuit synthesis in odd-even mode, a fourth-order all-pass two-port network is obtained.

[0102] A fourth-order all-pass two-port network is Figure 4 As shown, no further description is given here.

[0103] 3. Determine the reactance value of the inductive element and the susceptance value of the capacitive element in the fourth-order full-pass two-port network according to formula (3).

[0104] According to formula (3), we can determine Figure 5a , 5b In the semi-structure of n and C n The value of can be obtained according to formula (1) and formula (2): Figure 4 The values ​​of each component in the network.

[0105] Ginseng Figure 6 The figure shows a comparison of the delay-frequency characteristic curves of the fourth-order all-pass two-port network and the second-order all-pass two-port network in this embodiment. It can be seen that under the same delay setting, the flat delay frequency range obtained by the fourth-order network is obviously much greater than that of the second-order network.

[0106] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0107] The fourth-order all-pass two-port network can achieve better matching bandwidth, frequency and delay performance;

[0108] The construction method of the fourth-order all-pass two-port network is simple and easy to implement.

[0109] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0110] In addition, it should be understood that although the present specification is described according to embodiments, not every embodiment contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation methods that those skilled in the art can understand.

Claims

1. A fourth-order all-pass two-port network, characterized in that: The fourth-order all-pass two-port network is distributed in a mirror-symmetrical manner and includes: Inductive element L d , electrically connected between the first port and the second port; Capacitive component C c and C x , two sets of capacitive elements C are connected in series c and C x Respectively electrically connected between the first port and the first node, and between the second port and the first node; Inductive element L c , two inductive elements L c symmetrically electrically connected between the first node and the second node; Inductive element L a And capacitive component C b , two sets of inductive elements L are connected in series a And capacitive component C b symmetrically electrically connected between the first node and the second node; Inductive element L b And capacitive component C y , inductive element L b And capacitive component C y After being connected in parallel, they are electrically connected to two sets of capacitive elements C c and C x between; The semi-structured circuit of the fourth-order all-pass two-port network in odd mode and even mode includes: In the even mode, it includes an inductive element L1 and a capacitive element C2 connected in series, an inductive element L3 connected in parallel with L1 and C2, and a capacitive element C4 connected in series with L1, C2, and L3; In odd mode, it includes a capacitive element C1 and an inductive element L2 arranged in parallel, a capacitive element C3 arranged in series with C1 and L2, and an inductive element L4 arranged in parallel with C1, L2, and C3; Wherein, the inductive element includes an inductor, the capacitive element includes a capacitor, and the reactance value of the inductive element and the susceptance value of the capacitive element satisfy L a =L1,L b =2L2,L c =L3,L d =2L4,C b =C2,C c =C3, The input impedance Z of the fourth-order all-pass two-port network in the odd mode and even mode is in,e , Y in,o They are: Input impedance Z in,e , Y in,o satisfy Among them, X1=ωL1, X2=ωL2, X3=ωL3, X4=ωL4, B1=ωC1, B2=ωC2, B3=ωC3, B4=ωC4, ω is the angular frequency, and Z0 is the port matching impedance.

2. The fourth-order all-pass two-port network according to claim 1, characterized in that: In the fourth-order full-pass two-port network, the reactance value of the inductive element and the susceptance value of the capacitive element satisfy: Among them, L n is the reactance value of the inductive element, C n is the susceptance value of the capacitive element, and Z0 is the port matching impedance.

3. The fourth-order all-pass two-port network according to claim 1, characterized in that: The second node is connected to GND.

4. A method for constructing a fourth-order all-pass two-port network, characterized in that: The construction method comprises: S1. Determine the semi-structured circuits of the fourth-order all-pass two-port network in odd and even modes; S2, a fourth-order all-pass two-port network is obtained based on the semi-structured circuit synthesis in odd-even mode; The semi-structured circuit of the fourth-order all-pass two-port network in the odd mode and the even mode in step S1 includes: In the even mode, it includes an inductive element L1 and a capacitive element C2 connected in series, an inductive element L3 connected in parallel with L1 and C2, and a capacitive element C4 connected in series with L1, C2, and L3; In odd mode, it includes a capacitive element C1 and an inductive element L2 arranged in parallel, a capacitive element C3 arranged in series with C1 and L2, and an inductive element L4 arranged in parallel with C1, L2, and C3; The fourth-order all-pass two-port network in step S2 includes: Inductive element L d , electrically connected between the first port and the second port; Capacitive component C c and C x , two sets of capacitive elements C are connected in series c and C x Respectively electrically connected between the first port and the first node, and between the second port and the first node; Inductive element L c , two inductive elements L c symmetrically electrically connected between the first node and the second node; Inductive element L a And capacitive component C b , two sets of inductive elements L are connected in series a And capacitive component C b symmetrically electrically connected between the first node and the second node; Inductive element L b And capacitive component C y , inductive element L b And capacitive component C y After being connected in parallel, they are electrically connected to two sets of capacitive elements C c and C x between; Among them, the inductive element includes inductance, the capacitive element includes capacitance, and the reactance value of the inductive element and the susceptance value of the capacitive element satisfy L a =L1,L b =2L2,L c =L3,L d =2L4,C b =C2,C c =C3, 5. The construction method according to claim 4, characterized in that: The construction method also includes: According to the formula n=1,2,3,4 determines the reactance value of the inductive element and the susceptance value of the capacitive element in the fourth-order all-pass two-port network; Among them, L n is the reactance value of the inductive element, C n is the susceptance value of the capacitive element, and Z0 is the port matching impedance.

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