Display device

Abstract

An exemplary embodiment of the present disclosure provides a display device, including a substrate, a semiconductor layer, a first transistor, a light-emitting diode, and a first layer, wherein the semiconductor layer is arranged on the substrate; the first transistor includes a first gate electrode arranged on the semiconductor layer; the light-emitting diode is connected to the first transistor; and the first layer is arranged between the substrate and the semiconductor layer, wherein the semiconductor layer includes a first electrode, a second electrode, and a channel arranged between the first electrode and the second electrode, the channel includes impurities, and the first layer overlaps with the first transistor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0115868, filed on September 28, 2018, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] A display device is a device that displays an image, and a light emitting diode display has recently attracted attention as a self-luminous display device.

[0005] Unlike liquid crystal display (LCD) devices, light emitting diode displays have self-luminous properties and do not require a separate light source, and can therefore be made thinner and lighter. Furthermore, light emitting diode displays have high-quality properties such as low power consumption, high brightness, and high response speed.

[0006] Generally, a light emitting diode display includes a substrate, a plurality of thin film transistors positioned on the substrate, a plurality of insulating layers arranged between wirings constituting the thin film transistors, and light emitting elements connected to the thin film transistors.

[0007] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the Invention

[0008] The present disclosure has been made in an effort to improve afterimage characteristics and display characteristics.

[0009] An exemplary embodiment of the present disclosure provides a display device, including a substrate, a semiconductor layer, a first transistor, a light-emitting diode, and a first layer, wherein the semiconductor layer is arranged on the substrate; the first transistor includes a first gate electrode arranged on the semiconductor layer; the light-emitting diode is connected to the first transistor; and the first layer is arranged between the substrate and the semiconductor layer, wherein the semiconductor layer includes a first electrode, a second electrode, and a channel arranged between the first electrode and the second electrode, the channel includes impurities, and the first layer overlaps with the first transistor.

[0010] The first layer may be connected to one of the first electrode and the second electrode.

[0011] The display device may further include an insulating layer and a data connection member, the insulating layer being disposed on the first transistor, and the data connection member being disposed on the insulating layer, and the first electrode and the first layer may be connected through the data connection member.

[0012] The impurity may include one of boron, aluminum, indium, and gallium.

[0013] The first layer may include one of a metal having conductive properties and a semiconductor material having conductive properties similar to those of the metal.

[0014] The semiconductor layer may include a protrusion.

[0015] The channel may include a depletion region and a carrier transport region, the depletion region may be disposed at a lower end of the channel, and the carrier transport region may be disposed at an upper end of the channel.

[0016] Cross-sections of the depletion region and the carrier transport region may have a shape inclined with respect to the substrate.

[0017] An exemplary embodiment of the present disclosure provides a display device, including a substrate, a semiconductor layer, a first transistor, a light-emitting diode, and a first layer, wherein the semiconductor layer is arranged on the substrate; the first transistor includes a first gate electrode arranged on the semiconductor layer; the light-emitting diode is connected to the first transistor; and the first layer is arranged between the substrate and the semiconductor layer, wherein the semiconductor layer includes a first electrode, a second electrode, and a channel arranged between the first electrode and the second electrode, the channel includes impurities, and the first layer receives a constant voltage.

[0018] The first layer can receive a driving voltage.

[0019] The display device may further include a storage line overlapping the first gate electrode, and the storage line and the first layer may be connected.

[0020] The storage line may receive a driving voltage.

[0021] The display device may further include a gate insulating layer disposed between the storage line and the first gate electrode, and the storage line and the first gate electrode may constitute a storage capacitor.

[0022] The display device may further include an insulating layer disposed on the storage line and a driving voltage line disposed on the passivation layer, and the driving voltage line may be connected to the storage line through the contact hole.

[0023] The display device may further include a second transistor and a third transistor connected to the first transistor, and the first layer may overlap the third transistor.

[0024] According to the exemplary embodiments, afterimage and display characteristics of a display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A circuit diagram of a pixel of a display device according to an exemplary embodiment is shown.

[0026] Figure 2A top view schematically illustrates an area of a display device according to an exemplary embodiment.

[0027] Figure 3 Shown along Figure 2 A cross-sectional view taken along line III-III'.

[0028] Figure 4 Shown Figure 3 An enlarged schematic cross-sectional view of some constituent elements.

[0029] Figure 5 Cross-sectional views showing steps of a manufacturing process of a display device according to an example are shown.

[0030] Figure 6 Cross-sectional views showing steps of a manufacturing process of a display device according to a comparative example are shown.

[0031] Figure 7 A circuit diagram of a pixel of a display device according to an exemplary embodiment is shown.

[0032] Figure 8 A top view schematically illustrates an area of a display device according to an exemplary embodiment.

[0033] Figure 9 Shown along Figure 8 A cross-sectional view taken along line IX-IX'.

[0034] Figure 10 Graphs showing hysteresis characteristics of the comparative example and the example are shown.

[0035] Figure 11 Graphs showing afterimage characteristics of the comparative example and the example are shown.

[0036] Figure 12 A graph showing the S factors of the comparative example and the example is shown. DETAILED DESCRIPTION

[0037] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings which illustrate exemplary embodiments of the present invention. It will be appreciated by those skilled in the art that the described embodiments may be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0038] In order to clearly describe the present disclosure, parts irrelevant to the description are omitted, and the same reference numerals denote the same or similar constituent elements throughout the specification.

[0039] In addition, since the sizes and thicknesses of the constituent elements shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0040] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, the terms "above" or "on" mean positioned above or below an object portion and do not necessarily mean positioned on the upper side of the object portion based on the direction of gravity.

[0041] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0042] Furthermore, in the specification, the phrase “in a plan view” means when the subject portion is viewed from above, and the phrase “in a cross-sectional view” means when a cross section obtained by vertically cutting the subject portion is viewed from the side.

[0043] In the following, reference will now be made to Figure 1 Describes the driving of pixels. Figure 1 A circuit diagram of a pixel of a display device according to an exemplary embodiment is shown.

[0044] Reference Figure 1 According to the present exemplary embodiment, a pixel PX of the display device may include a plurality of signal lines 151, 152, 153, 154, 171, and 172, a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected thereto, a storage capacitor Cst, and a light emitting diode LED. In the present exemplary embodiment, an example in which one pixel PX includes one light emitting diode LED will be mainly described.

[0045] The signal lines 151 , 152 , 153 , 154 , 171 , and 172 may include a plurality of scan lines 151 , 152 , and 154 , a control line 153 , a data line 171 , and a driving voltage line 172 .

[0046] Scan lines 151, 152, and 154 may carry scan signals GWn, GIn, and GI(n+1), respectively. The scan signals GWn, GIn, and GI(n+1) may transmit gate-on and gate-off voltages that may turn on or off transistors T2, T3, T4, and T7 included in the pixel PX.

[0047] The scan lines 151, 152, and 154 connected to the pixels PX may include a first scan line 151, a second scan line 152, and a third scan line 154. The scan signal GWn can be transmitted through the first scan line 151, the scan signal GIn having a gate-on voltage can be transmitted through the second scan line 152 at a time different from the time of the first scan line 151, and the scan signal GI(n+1) can be transmitted through the third scan line 154. The second scan line 152 can transmit the gate-on voltage at an earlier time than the first scan line 151. For example, when the scan signal GWn is the nth scan signal Sn (n is a natural number equal to or greater than 1) among the scan signals applied during one frame, the scan signal GIn may be a previous scan signal, such as the (n-1)th scan signal Sn-1, and the scan signal GI(n+1) may be the nth scan signal Sn. However, the present exemplary embodiment is not limited thereto, and the scan signal GI(n+1) may be a scan signal different from the nth scan signal Sn.

[0048] The control line 153 may transmit a light emitting control signal EM, and particularly, may transmit a light emitting control signal EM capable of controlling light emission of a light emitting diode LED included in the pixel PX.

[0049] The data line 171 may transmit a data signal Dm, and the driving voltage line 172 may transmit a driving voltage ELVDD. The data signal Dm may have different voltage levels depending on an image signal input into the display device, and the driving voltage ELVDD may have a substantially constant level.

[0050] The transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 included in one pixel PX may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor T7 .

[0051] The first scan line 151 can transmit the scan signal GWn to the second transistor T2 and the third transistor T3, and the second scan line 152 can transmit the scan signal GIn to the fourth transistor T4. The third scan line 154 can transmit the scan signal GI(n+1) to the seventh transistor T7, and the control line 153 can transmit the emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0052] The gate electrode G1 of the first transistor T1 is connected to the first end of the storage capacitor Cst via the driving gate node GN, and the first electrode S1 of the first transistor T1 is connected to the driving voltage line 172 via the fifth transistor T5. The second electrode D1 of the first transistor T1 is connected to the anode electrode of the light emitting diode LED via the sixth transistor T6. According to an exemplary embodiment, the first electrode S1 of the first transistor T1 may also be connected to the first layer 31 to be described below. The first transistor T1 may receive a data signal Dm transmitted by the data line 171 according to the switching operation of the second transistor T2 to supply a driving current I to the light emitting diode LED. led .

[0053] A gate electrode G2 of the second transistor T2 is connected to the first scan line 151, and a first electrode S2 of the second transistor T2 is connected to the data line 171. A second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the first transistor T1 and is connected to the driving voltage line 172 via the fifth transistor T5. Depending on the scan signal GWn received through the first scan line 151, the second transistor T2 can be turned on to transmit the data signal Dm transmitted from the data line 171 to the first electrode S1 of the first transistor T1.

[0054] The gate electrode G3 of the third transistor T3 is connected to the first scan line 151, and the first electrode S3 of the third transistor T3 is connected to the second electrode D1 of the first transistor T1 and, via the sixth transistor T6, to the anode electrode of the light-emitting diode LED. The second electrode D3 of the third transistor T3 is connected to the second electrode D4 of the fourth transistor T4, the first end of the storage capacitor Cst, and the gate electrode G1 of the first transistor T1. Depending on the scan signal GWn transmitted via the first scan line 151, the third transistor T3 can be turned on to connect the gate electrode G1 and the second electrode D1 of the first transistor T1 to each other, thereby enabling the first transistor T1 to be diode-connected.

[0055] A gate electrode G4 of the fourth transistor T4 is connected to the second scan line 152, and a first electrode S4 of the fourth transistor T4 is connected to a terminal for an initialization voltage Vint. A second electrode D4 of the fourth transistor T4 is connected to the second electrode D3 of the third transistor T3, a first end of the storage capacitor Cst, and the gate electrode G1 of the first transistor T1. The fourth transistor T4 is turned on in response to a scan signal GIn received via the second scan line 152 to transmit the initialization voltage Vint to the gate electrode G1 of the first transistor T1, thereby performing an initialization operation for initializing the voltage of the gate electrode G1 of the first transistor T1.

[0056] A gate electrode G5 of the fifth transistor T5 is connected to the control line 153, and a first electrode S5 of the fifth transistor T5 is connected to the driving voltage line 172. A second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the first transistor T1 and the second electrode D2 of the second transistor T2.

[0057] A gate electrode G6 of the sixth transistor T6 is connected to the control line 153, and a first electrode S6 of the sixth transistor T6 is connected to the first electrode S1 of the first transistor T1 and the first electrode S3 of the third transistor T3. A second electrode D6 of the sixth transistor T6 is electrically connected to the anode electrode of the light-emitting diode LED. The fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on in response to the emission control signal EM received via the control line 153, so that the driving voltage ELVDD is compensated by the diode-connected first transistor T1 and transmitted to the light-emitting diode LED.

[0058] A gate electrode G7 of the seventh transistor T7 is connected to the third scan line 154, a first electrode S7 of the seventh transistor T7 is connected to the second electrode D6 of the sixth transistor T6 and the anode electrode of the light emitting diode LED, and a second electrode D7 of the seventh transistor T7 is connected to the terminal of the initialization voltage Vint and the first electrode S4 of the fourth transistor T4.

[0059] The transistors T1, T2, T3, T4, T5, T6, and T7 may be p-type channel transistors such as PMOS transistors, but the present disclosure is not limited thereto, and at least one of the transistors T1, T2, T3, T4, T5, T6, and T7 may be an n-type channel transistor. In addition, the first electrode and the second electrode described above are used to distinguish two electrodes arranged at opposite sides of the channel, and these terms may be interchangeable.

[0060] As described above, the second storage electrode E2 of the storage capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the first storage electrode E1 is connected to the driving voltage line 172. The cathode electrode of the light emitting diode LED is connected to the common voltage ELVSS terminal transmitting the common voltage ELVSS.

[0061] The structure of the pixel PX according to the exemplary embodiment is not limited to Figure 1 , and the numbers of transistors and capacitors included in one pixel PX and the connection relationships thereof may be variously modified.

[0062] The pixel PX of the display device according to the exemplary embodiment further includes a first layer 31 that overlaps at least one of the transistors T1, T2, T3, T4, T5, T6, and T7 in a plan view. For example, the first layer 31 may overlap the first transistor T1. In particular, the first layer 31 may overlap the channel of the first transistor T1.

[0063] Figure 1 A circuit diagram of one pixel PX is shown, and for ease of understanding, the first layer 31 overlapping the first transistor T1 is shown by using a dotted line.

[0064] The first layer 31 can be electrically connected to the first electrode S1 to receive the same voltage as the first electrode S1. The first layer 31 can function not only as a light-blocking layer but also as a bottom gate of a dual-gate structure. The first transistor T1 can have a bottom-gate structure due to the first layer 31, thereby improving transistor reliability, reducing leakage current, and enhancing driving capability, thereby reducing power consumption of the display device.

[0065] In the following, reference will be made to Figure 1 Other Figure 2 and Figure 3 A stack structure of a display device according to an exemplary embodiment is described. Figure 2 schematically shows a top view of a region of a display device according to an exemplary embodiment, and Figure 3 Shown along Figure 2 A cross-sectional view taken along line III-III'.

[0066] Reference Figure 2 as well as Figure 1 The display device according to the present exemplary embodiment includes a first scan line 151 extending along a first direction d1 to transmit an nth scan signal Sn, a second scan line 152 for transmitting an (n-1)th scan signal Sn-1, a light emitting control line 153 for transmitting a light emitting control signal EM, and an initialization voltage line 127 for transmitting an initialization voltage Vint. A bypass signal GB is transmitted through the second scan line 152.

[0067] The display device includes a data line 171 extending in a second direction d2 orthogonal to the first direction d1 to transmit a data signal Dm and a driving voltage line 172 for transmitting a driving voltage ELVDD.

[0068] The display device includes a first transistor T1 as a driving transistor, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and a light emitting diode LED.

[0069] The semiconductor layer 130 may include channels C1, C2, C3, C4, C5, C6, and C7 of a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The channels C1, C2, C3, C4, C5, C6, and C7 may be regions of the semiconductor layer 130. The channels C1, C2, C3, C4, C5, C6, and C7 may indicate regions between the first electrodes S1, S2, S3, S4, S5, S6, and S7 and the second electrodes D1, D2, D3, D4, D5, D6, and D7 in the semiconductor layer 130, respectively.

[0070] The first electrodes S1, S2, S3, S4, S5, S6, and S7 and the second electrodes D1, D2, D3, D4, D5, D6, and D7 of the transistors T1, T2, T3, T4, T5, T6, and T7 are also arranged in the semiconductor layer 130. The first electrodes S1, S2, S3, S4, S5, S6, and S7 and the second electrodes D1, D2, D3, D4, D5, D6, and D7 may indicate some areas of the semiconductor layer 130. The first electrodes S1, S2, S3, S4, S5, S6, and S7 and the second electrodes D1, D2, D3, D4, D5, D6, and D7 may be arranged at opposite sides of the above-mentioned channels C1, C2, C3, C4, C5, C6, and C7.

[0071] Specifically, channels C1, C2, C3, C4, C5, C6, and C7 include region C1 of the semiconductor layer 130 (wherein the semiconductor layer 130 and the first gate electrode 155 overlap with each other), and may include region C2 and region C3 (wherein the semiconductor layer 130 and the first scan line 151 overlap with each other), region C4 and region C7 (wherein the semiconductor layer 130 and the second scan line 152 overlap with each other), and region C5 and region C6 (wherein the semiconductor layer 130 and the light emitting control line 153 overlap with each other).

[0072] Semiconductor layer 130 (in Figure 2 The semiconductor layer 130 may include an oxide semiconductor or a polycrystalline semiconductor made of polycrystalline silicon.

[0073] The semiconductor layer 130 may include channels C1, C2, C3, C4, C5, C6, and C7 doped with n-type or p-type impurities, and first and second doped regions disposed on opposite sides of the channels C1, C2, C3, C4, C5, C6, and C7, each having a higher doping concentration than the impurities doped in the channels C1, C2, C3, C4, C5, C6, and C7. The first and second doped regions correspond to first electrodes S1, S2, S3, S4, S5, S6, and S7 and second electrodes D1, D2, D3, D4, D5, D6, and D7 of transistors T1, T2, T3, T4, T5, T6, and T7, respectively. When one of the first and second doped regions is a source region, the other doped region is a drain region. Furthermore, regions between the first and second electrodes of different transistors may be doped in the semiconductor layer 130 so that the transistors can be electrically connected to each other.

[0074] For example, impurities doped into channels C1, C2, C3, C4, C5, C6, and C7 may include phosphorus (P), arsenic (As), or antimony (Sb), or boron (B), aluminum (Al), indium (In), or gallium (Ga). When the impurities include phosphorus, arsenic, antimony, etc., the transistor may be an n-type thin film transistor (TFT) in which electrons are carriers. When the impurities include boron, aluminum, indium, or gallium, the transistor may be a p-type thin film transistor (TFT) in which holes are carriers.

[0075] Each channel of the transistors T1, T2, T3, T4, T5, T6, and T7 overlaps with each gate electrode of the transistors T1, T2, T3, T4, T5, T6, and T7, and is arranged between the first electrodes S1, S2, S3, S4, S5, S6, and S7 and the second electrodes D1, D2, D3, D4, D5, D6, and D7 of the transistors T1, T2, T3, T4, T5, T6, and T7, respectively. The transistors T1, T2, T3, T4, T5, T6, and T7 may have substantially the same stacked structure. Hereinafter, the first transistor T1 as the driving transistor will be described in detail, and the remaining transistors T2, T3, T4, T5, T6, and T7 will be briefly described.

[0076] The first transistor T1 as a driving transistor includes a first gate electrode 155, a first electrode S1, a second electrode D1, and a channel C1 arranged between the first electrode S1 and the second electrode D1. In a plan view, the channel C1 of the first transistor T1 is arranged between the first electrode S1 and the second electrode D1 to overlap with the first gate electrode 155. The channel C1 is bent to increase the length of the channel C1 in a limited area. As the length of the channel C1 becomes longer, the driving range of the gate voltage Vg applied to the first gate electrode 155 of the first transistor T1 becomes wider, and depending on the gate voltage Vg, the driving current I ledConstantly increases. As a result, the grayscale of the light emitted from the light emitting diode LED can be more finely controlled, and the display quality of the light emitting diode display can be improved by adjusting the magnitude of the gate voltage Vg. In addition, since the channel extends in various directions rather than in one direction, there is an advantage in that the influence of orientation is offset in the manufacturing process, thereby reducing the influence of process scattering. Accordingly, image quality degradation such as stain defects that may occur due to process scattering resulting in changes in the characteristics of the first transistor T1 depending on the area of the display device (for example, even when the same data signal Dm is applied, brightness differences occur depending on the pixel PX) can be prevented. The shape of this channel can be modified in various ways and is not limited to the form shown.

[0077] In a plan view, the first gate electrode 155 overlaps the channel C1 of the first transistor T1. The first electrode S1 and the second electrode D1 are arranged on opposite sides of the channel C1, respectively. The insulated extension of the storage line 126 is arranged on the first gate electrode 155. In a plan view, the extension of the storage line 126 overlaps the first gate electrode 155 with the second gate insulating layer 142 interposed therebetween to form a storage capacitor Cst. The extension of the storage line 126 serves as the first storage electrode E1 of the storage capacitor Cst (see Figure 1 ), and the first gate electrode 155 serves as the second storage electrode E2 (see Figure 1 ). The extension of the storage line 126 has an opening 56 so that the first gate electrode 155 can be connected to the first data link 71. In the opening 56, the upper surface of the first gate electrode 155 and the first data link 71 are electrically connected to each other through the contact hole 61. The first data link 71 is connected to the second electrode D3 of the third transistor T3 to connect the first gate electrode 155 of the first transistor T1 to the second electrode D3 of the third transistor T3. The first layer 31, which will be described later, may overlap with the first transistor T1.

[0078] The gate electrode of the second transistor T2 may be part of the first scan line 151. The data line 171 is connected to the first electrode S2 of the second transistor T2 through the contact hole 62. The first electrode S2 and the second electrode D2 may be part of the semiconductor layer 130. The channel C2 of the second transistor T2 may be arranged between the first electrode S2 and the second electrode D2 in the semiconductor layer 130.

[0079] The third transistor T3 may be formed to include two transistors adjacent to each other. A channel C3 is shown on the left and lower sides of the bent portion relative to the semiconductor layer 130. These two portions each serve as the channel C3 of the third transistor T3. The first electrode S3 of the first third transistor T3 is connected to the second electrode D3 of the second third transistor T3. The gate electrodes of the two third transistors T3 may be part of the first scan line 151 or portions protruding upward from the first scan line 151. This structure may be referred to as a dual-gate structure and can prevent leakage current from flowing. The first electrode S3 of the third transistor T3 is connected to the first electrode S6 of the sixth transistor T6 and the second electrode D1 of the first transistor T1. The second electrode D3 of the third transistor T3 is connected to the first data connection member 71 through the contact hole 63.

[0080] The fourth transistor T4 is formed to include two fourth transistors T4, and the two fourth transistors T4 are formed at the portion where the second scan line 152 and the semiconductor layer 130 meet. The gate electrode of the fourth transistor T4 may be part of the second scan line 152. The first electrode S4 of the first fourth transistor T4 is connected to the second electrode D4 of the second fourth transistor T4. This structure may be referred to as a dual-gate structure and can prevent leakage current from flowing. The second data link 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65, and the first data link 71 is connected to the second electrode D2 of the fourth transistor T4 through the contact hole 63.

[0081] Thus, the third transistor T3 and the fourth transistor T4 may use a double-gate structure to effectively prevent leakage current from occurring by blocking the electron movement path of the channel in the off state.

[0082] The gate electrode of the fifth transistor T5 may be part of the light emission control line 153. The driving voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through the contact hole 67, and the second electrode D5 is connected to the first electrode S1 of the first transistor T1 through the semiconductor layer 130.

[0083] The gate electrode of the sixth transistor T6 may be part of the light emission control line 153. The third data link 73 is connected to the second electrode D6 of the sixth transistor T6 through the contact hole 69, and the first electrode S6 is connected to the second electrode D1 of the first transistor T1 through the semiconductor layer 130.

[0084] A gate electrode of the seventh transistor T7 may be a portion of the second scan line 152. A first electrode S7 of the seventh transistor T7 is connected to the second electrode D6 of the sixth transistor T6, and a second electrode D7 is connected to the first electrode S4 of the fourth transistor T4.

[0085] The storage capacitor Cst includes a first storage electrode E1 and a second storage electrode E2 that overlap with each other, with a second gate insulating layer 142 interposed therebetween. The second storage electrode E2 may correspond to the first gate electrode 155 of the first transistor T1, and the first storage electrode E1 may be an extension of the storage line 126. Here, the second gate insulating layer 142 serves as a dielectric material, and the capacitance is determined by the voltage charged in the storage capacitor Cst and the voltage between the first storage electrode E1 and the second storage electrode E2. By using the first gate electrode 155 as the second storage electrode E2, space for the storage capacitor Cst can be secured within the narrowed space within the pixel PX due to the large area occupied by the channel of the first transistor T1.

[0086] The driving voltage line 172 is connected to the first storage electrode E1 or the storage line 126 through the contact hole 68. Accordingly, the storage capacitor Cst stores charges corresponding to the difference between the driving voltage ELVDD transferred to the first storage electrode E1 through the driving voltage line 172 and the gate voltage Vg of the first gate electrode 155.

[0087] The second data link 72 is connected to the initialization voltage line 127 through the contact hole 64. A pixel electrode, which will be described later, may be connected to the third data link 73 through the contact hole 81.

[0088] A parasitic capacitor control pattern 79 may be arranged between the dual gate electrodes of the third transistor T3. A parasitic capacitor exists in the pixel PX, and when the voltage applied to the parasitic capacitor changes, its image quality characteristics may change. The driving voltage line 172 is connected to the parasitic capacitor control pattern 79 through the contact hole 66. As a result, the image quality characteristics can be prevented from changing by applying a driving voltage ELVDD having a constant DC voltage to the parasitic capacitor. The parasitic capacitor control pattern 79 may be arranged in a region different from the illustrated position, and a voltage other than the driving voltage ELVDD may be applied thereto.

[0089] A first end of the first data link 71 is connected to the first gate electrode 155 through the contact hole 61 , and a second end thereof is connected to the second electrode D3 of the third transistor T3 and the second electrode D4 of the fourth transistor T4 through the contact hole 63 .

[0090] A first end of the second data link 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65 , and a second end thereof is connected to the initialization voltage line 127 through the contact hole 64 .

[0091] The third data link 73 is connected to the second electrode D6 of the sixth transistor T6 through the contact hole 69 .

[0092] The fourth data link 74 may be connected to the semiconductor layer 130 extending from the first electrode S1 of the first transistor T1 through the contact hole A, and may be connected to the first electrode S1 through the contact hole B.

[0093] In the following, reference will be made to Figure 3 as well as Figure 2 , a cross-sectional structure of a display device according to an exemplary embodiment is described depending on its stacking order. Figure 2 Descriptions of contents identical to those described in will be omitted.

[0094] The display device according to the present exemplary embodiment includes a substrate 110. The substrate 110 may include a plastic layer and a barrier layer. The plastic layer and the barrier layer may be alternately stacked.

[0095] The plastic layer can be made of a material selected from the group consisting of polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), poly(arylene ether sulfone) and their combinations.

[0096] The barrier layer may include at least one of silicon oxide, silicon nitride, and aluminum oxide, and may include any inorganic material without limitation.

[0097] The first buffer layer 111 is disposed on the substrate 110. The first buffer layer 111 may include an inorganic insulating material such as silicon oxide, silicon nitride, or aluminum oxide, or an organic insulating material such as polyimide or polyacrylic.

[0098] The first buffer layer 111 may prevent impurities from flowing into the transistor and planarize one surface of the substrate 110. According to example embodiments, the first buffer layer 111 may be omitted.

[0099] The first layer 31 is disposed on the first buffer layer 111. The first layer 31 can be conductive. The first layer 31 may include a conductive metal or a semiconductor material having similar conductive properties. The metal may include, for example, molybdenum, chromium, tantalum, titanium, copper, or alloys thereof. The first layer 31 may be a single layer or multiple layers.

[0100] According to an exemplary embodiment, the first layer 31 may overlap the first transistor T1, particularly, the channel C1 of the first transistor T1. The first layer 31 may overlap not only the channel C1 of the first transistor T1 but also the first electrode S1 and the second electrode D1 disposed at opposite sides of the channel C1.

[0101] In a plan view, the first layer 31 may completely overlap the first gate electrode 155 and may have a region protruding to be connected to another layer. The first layer 31 may have any form overlapping the first transistor T1 and is not limited to the above.

[0102] The first layer 31 prevents light from reaching the first transistor T1, thereby preventing degradation of the transistor's channel characteristics, such as leakage current. The first layer 31 may also function as a bottom gate of the first transistor T1 by receiving a predetermined voltage. A bottom gate structure formed by the first layer 31 improves transistor reliability, thereby reducing leakage current and enhancing driving capability, thereby reducing power consumption of the display device.

[0103] The second buffer layer 112 is disposed on the substrate 110. The second buffer layer 112 may include an inorganic insulating material such as silicon oxide, silicon nitride, or aluminum oxide, or an organic insulating material such as polyimide or polyacrylic acid.

[0104] A semiconductor layer 130 including channels C1, C2, C3, C4, C5, C6, and C7 of transistors T1, T2, T3, T4, T5, T6, and T7, first electrodes S1, S2, S3, S4, S5, S6, and S7, and second electrodes D1, D2, D3, D4, D5, D6, and D7 is disposed on the second buffer layer 112. Details are the same as above and will thus be omitted.

[0105] A portion of the semiconductor layer 130 may be connected to the first layer 31. For example, the first electrode S1 of the first transistor T1 includes a region extending in the first direction d1, and the region and the first layer 31 may be electrically connected. The region extending from the first electrode S1 of the first transistor T1 may receive the same voltage as the first electrode S1.

[0106] A first gate insulating layer 141 covering the semiconductor layer 130 is disposed on the semiconductor layer 130. A first gate conductor including a first gate electrode 155, a first scan line 151, a second scan line 152, and a light emitting control line 153 is disposed on the first gate insulating layer 141.

[0107] A second gate insulating layer 142 covering the first gate conductor is disposed on the first gate conductor. The first gate insulating layer 141 and the second gate insulating layer 142 may include an inorganic insulating material such as silicon nitride, silicon oxide, and aluminum oxide.

[0108] A second gate conductor including a storage line 126 having an opening 56 , an initialization voltage line 127 , and a parasitic capacitor control pattern 79 is disposed on the second gate insulating layer 142 .

[0109] A first insulating layer 160 covering the second gate conductor is disposed on the second gate conductor. The first insulating layer 160 may include an inorganic insulating material such as silicon nitride, silicon oxide, and aluminum oxide, or an organic insulating material.

[0110] A data conductor including a data line 171 , a driving voltage line 172 , a first data link 71 , a second data link 72 , a third data link 73 , and a fourth data link 74 is disposed on the first insulating layer 160 .

[0111] According to an exemplary embodiment, the fourth data link 74 may be connected to a portion of the semiconductor layer 130 through the contact hole A. In particular, referring to Figure 2 , the fourth data link 74 may be connected to the semiconductor layer 130 extending from one end of the first electrode S1 of the first transistor T1 in the first direction d1.

[0112] The fourth data link 74 may also be connected to the first layer 31 through the contact hole B. The first layer 31 and the semiconductor layer 130 may be connected to each other through the fourth data link 74 .

[0113] The first layer 31 may receive a voltage applied to the semiconductor layer 130 , for example, a voltage applied to the first electrode S1 through the fourth data link 74 .

[0114] A second insulating layer 180 covering the data conductor is disposed on the data conductor. The second insulating layer 180 may be a planarization layer and may include an organic insulating material or an inorganic insulating material.

[0115] The pixel electrode 191 is disposed on the second insulating layer 180. Figure 2 As shown in FIG, the pixel electrode 191 is connected to the third data link 73 through the contact hole 81.

[0116] A partition wall 360 is disposed on the second insulating layer 180 and the pixel electrode 191. The partition wall 360 has an opening 361 that overlaps with the pixel electrode 191. An emission layer 370 is disposed in the opening 361. A common electrode 270 that overlaps with the front surface of the substrate 110 is disposed on the emission layer 370 and the partition wall 360. The pixel electrode 191, the emission layer 370, and the common electrode 270 constitute a light emitting diode (LED).

[0117] According to another exemplary embodiment, the pixel electrode may be an anode electrode serving as a hole injection electrode, and the common electrode may be a cathode electrode serving as an electron injection electrode. Conversely, the pixel electrode may be a cathode electrode, and the common electrode may be an anode electrode. When holes and electrons are injected from the pixel electrode and the common electrode into the emissive layer, excitons formed by combining the injected holes and electrons are emitted when they transition from an excited state to a ground state.

[0118] An encapsulation layer 400 for protecting the light emitting diode LED is disposed on the common electrode 270. As shown, the encapsulation layer 400 may contact the common electrode 270, and according to an exemplary embodiment, the encapsulation layer 400 may be spaced apart from the common electrode 270.

[0119] The encapsulation layer 400 may be a thin film encapsulation layer stacking an organic film and an inorganic layer, and may include three layers including an inorganic film, an organic layer, and an inorganic layer. According to an exemplary embodiment, a capping layer and a functional layer may be disposed between the common electrode 270 and the encapsulation layer 400 .

[0120] In the following, reference will be made to Figure 4 The semiconductor layer 130 according to example embodiments is described in more detail. Figure 4 Shown Figure 3 An enlarged schematic cross-sectional view of some constituent elements.

[0121] Reference Figure 4 The channel C1 of the semiconductor layer 130 overlapping the first layer 31 may include a depletion region R1 and a carrier transport region R2. The depletion region R1 may be disposed at a lower end of the semiconductor layer 130, and the carrier transport region R2 may be disposed at an upper end of the semiconductor layer 130.

[0122] The depletion region R1 is a region where carrier transport is not relatively performed, and the carrier transport region R2 may be referred to as a region where carrier transport is actively performed.

[0123] The cross-sections of the depletion region R1 and the carrier transport region R2 may have a shape that is inclined toward the substrate 110. The thickness of the depletion region R1 may vary. For example, the depletion region R1 near the first electrode S1 may be thin, and the depletion region R1 near the second electrode D1 may be thick. The thickness of the carrier transport region R2 may vary. For example, the carrier transport region R2 near the first electrode S1 may be thick, and the carrier transport region R2 near the second electrode D1 may be thin.

[0124] As the area occupied by the depletion region R1 in the semiconductor layer 130 increases, the area in which carriers can move in the channel C1 of the semiconductor layer 130 decreases. In this case, the number of carriers trapped in the channel C1 decreases, and the number of carriers per unit area moving from the first electrode S1 to the second electrode D1 can increase. In other words, the carrier transport effect can be improved.

[0125] When a predetermined voltage is applied to the first layer 31 , the first layer 31 forms an electric field with the first and second electrodes S1 and D1 of the semiconductor layer 130 , thereby reducing leakage current.

[0126] In the following, reference will be made to Figure 5 and Figure 6A method of manufacturing a semiconductor layer according to an exemplary embodiment is described. Figure 5 sectional views showing steps of a manufacturing process of a display device according to an example are shown, and Figure 6 Cross-sectional views showing steps of a manufacturing process of a display device according to a comparative example are shown.

[0127] Reference Figure 5 , an amorphous silicon layer a-Si is formed on the second buffer layer 112 .

[0128] The channel according to an example may include impurities, and thus an impurity doping process may be performed on the amorphous silicon layer a-Si.

[0129] Examples of impurities doped into the amorphous silicon layer a-Si may include phosphorus (P), arsenic (As), antimony (Sb), boron (B), aluminum (Al), indium (In), etc. When the impurities include phosphorus, arsenic, antimony, etc., the transistor may be an n-type thin film transistor (TFT) in which electrons are the charge carriers. When the impurities include boron, aluminum, indium, or gallium, the transistor may be a p-type thin film transistor (TFT) in which holes are the charge carriers.

[0130] Afterwards, the impurity-doped amorphous silicon layer (a-Si) is irradiated with laser light to perform a crystallization process. One type of laser light may be an excimer laser. An excimer laser is a gas laser that uses molecules called excimers (such as ArF, KrF, XeCl, etc.) that may have a single wavelength and high power.

[0131] During impurity doping, the first side of the amorphous silicon layer (a-Si) may be damaged. However, by performing a laser crystallization process after impurity doping, defects in the semiconductor layer can be repaired through the crystallization process. In addition, since the crystallization process is performed while the impurities are stably implanted into the semiconductor layer, the carrier concentration in the semiconductor layer can be increased, thereby improving the characteristics of the semiconductor layer.

[0132] Referring to the comparative example Figure 6 After forming an amorphous silicon layer, a laser crystallization process is performed to form a polycrystalline silicon layer (p-Si). Thereafter, an impurity doping process is performed on the polycrystalline silicon layer (p-Si). This impurity doping process may cause surface damage to the semiconductor layer, which may degrade the reliability of the semiconductor layer.

[0133] In the following, reference will be made to Figure 7 The driving of pixels is described. Figure 7 A circuit diagram of a pixel of a display device according to an exemplary embodiment is shown. Description of constituent elements that are the same as those described above will be omitted.

[0134] The first layer 31 according to the present exemplary embodiment may receive a constant voltage, for example, a driving voltage ELVDD.

[0135] The first layer 31 may provide a light-blocking function for the channel of at least one of the overlapping transistors T1, T2, T3, T4, T5, T6, and T7, thereby preventing leakage current and degradation of the characteristics of the transistors T1, T2, T3, T4, T5, T6, and T7. For example, when the driving voltage ELVDD is constantly applied to the first layer 31, the potential of the first layer 31 can be constantly maintained, thereby preventing it from affecting surrounding electrodes. When the first layer 31 overlaps with the first transistor T1, the first transistor T1 can have a high data range, thereby reducing variations in the gate-source voltage Vgs and output depending on characteristic deviations, thereby improving the display characteristics of the display device.

[0136] Now refer to Figure 8 and Figure 9 A display device according to an exemplary embodiment is described. Figure 8 schematically shows a top view of a region of a display device according to an exemplary embodiment, and Figure 9 Shown along Figure 8 A cross-sectional view taken along line IX-IX'. Figure 8 and Figure 9 In the exemplary embodiment, descriptions of constituent elements that are the same as those described above will be omitted.

[0137] Reference Figure 8 According to the present exemplary embodiment, the first layer 31 may overlap with the first transistor T1. Specifically, the first layer 31 may overlap with the channel C1, the first electrode S1, and the second electrode D1 of the first transistor T1.

[0138] According to an exemplary embodiment, the first layer 31 may also overlap with the third transistor T3. In particular, the first layer 31 may overlap with the channel C3 of the third transistor T3. However, the first layer 31 may have a form that overlaps only with the first transistor T1, such as Figure 2 The present invention is as in the exemplary embodiment of the present invention, but is not limited to this exemplary embodiment.

[0139] The first layer 31 may be connected to the extension of the storage line 126 through the contact hole A. The driving voltage line 172 is connected to the storage line 126 through the contact hole 68. The driving voltage ELVDD may be applied to the storage line 126. The driving voltage ELVDD may be applied to the first layer 31 through the storage line 126.

[0140] When the driving voltage ELVDD is constantly applied to the first layer 31, the potential of the first layer 31 can be constantly maintained, thereby preventing it from affecting the surrounding electrodes. According to exemplary embodiments, when the first layer 31 overlaps with the first transistor T1, the first transistor T1 can have a high data range, so that the deviation in the gate-source voltage Vgs and the variation in the output according to the characteristic deviation can be reduced, thereby improving the display characteristics of the display device.

[0141] In the following, reference will be made to Figures 10 to 12 Characteristics according to examples and comparative examples are described. Figure 10 Graphs showing hysteresis characteristics of the comparative example and the example are shown, Figure 11 Graphs showing afterimage characteristics of the comparative example and the example are shown, and Figure 12 A graph showing the S factors of the comparative example and the example is shown.

[0142] exist Figures 10 to 12 , Example 1 is a display device having a structure including a first layer and a channel having impurities, and Comparative Example 1 is a display device having a structure including neither the first layer nor the channel having impurities. Comparative Example 2 is a display device having a structure including a channel having impurities, and Comparative Example 3 is a display device having a structure including the first layer.

[0143] First, refer to Figure 10 , Comparative Example 1 had a value of about 0.22, Comparative Example 2 had a value of about 0.19, Comparative Example 3 had a value of about 0.19, and Example 1 had a value of about 0.16. The hysteresis characteristics of Example 1 were improved by reducing 0.06 compared to Comparative Example 1, and Example 1 had a low level of hysteresis characteristics compared to Comparative Examples 2 and 3.

[0144] For measuring the time of afterimage Figure 11 As shown in FIG, Comparative Example 1 displays about 7.66 s, Comparative Example 2 displays about 6.52 s, Comparative Example 3 displays about 5.64 s, and Example 1 displays about 3.75 s. It can be seen that the instantaneous afterimage effect according to the examples is the best.

[0145] Reference Figure 10 and Figure 11 It is desirable to provide a display device including a first layer and a channel having impurities so as to improve instantaneous afterimage while improving hysteresis characteristics. The hysteresis characteristics indicate that the smaller the value, the easier the current control.

[0146] In addition, the instantaneous afterimage and threshold voltage according to the doping concentration of the impurity doped into the channel will be described with reference to Table 1. Condition 1 is the case where the channel is not doped with impurities, and Condition 2 is the case where the impurity is doped at a concentration of 5*10 11In the case of concentration doping, condition 3 is that the impurity concentration is 7.5*10 11 In the case of concentration doping, condition 4 is that the impurity is 1*10 12 In the case of concentration doping, condition 5 is that the impurity concentration is 1.5*10 12 The concentration of doping is 2*10 12 Concentration doping situation.

[0147] In this case, when the time for observing the afterimage is less than 6 seconds and the threshold voltage value required for the display device is satisfied, conditions 4 and 5 are satisfied. Exclusively, based on the following conditions, the impurity concentration doped into the channel according to the exemplary embodiment is within the range of 7.5*10 11 and 2*10 12 within the range between.

[0148] (Table 1)

[0149] Momentary afterimage(s) Vth(V) Condition 1 7.5 -3.30 Condition 2 8.0 -3.83 Condition 3 6.4 -3.45 Condition 4 5.7 -3.30 Condition 5 4.7 -2.80 Condition 6 6.4 -2.6

[0150] Refer to the S factor shown Figure 12 , Example 1 has a value of about 0.60, Comparative Example 1 has a value of about 0.57, Comparative Example 2 has a value of about 0.56, and Comparative Example 1 has a value of about 0.61. It may be advantageous for the drive transistor to have a relatively large S factor in order to reduce the brightness deviation caused by the scattering of the gate voltage. In this article, the term "S factor" represents the current-voltage characteristic of the transistor, which indicates the gate voltage required to increase the drain current tenfold when a gate voltage equal to or lower than the threshold voltage is applied. The S factor is often referred to as the "subthreshold slope."

[0151] It can be seen that when the first layer and the channel doped with impurities are included according to Example 1, the S factor is superior to the depletion region of the channel and the increase of the carrier concentration.

[0152] While the invention has been described in connection with what are presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0153] Description of Reference Signs

[0154] 110: substrate

[0155] 130: Semiconductor layer

[0156] LED: Light Emitting Diode

[0157] 31: First floor

Claims

1. A display device comprising: substrate; a semiconductor layer disposed on the substrate; a first transistor comprising a first gate electrode disposed on the semiconductor layer; a light emitting diode connected to the first transistor; as well as a first layer, the first layer being arranged between the substrate and the semiconductor layer, The semiconductor layer includes a first electrode, a second electrode, and a channel arranged between the first electrode and the second electrode. The channel includes impurities, the first layer overlaps the first transistor, The concentration of the impurities is greater than 7.5×10 11 and less than 2×10 12 ,as well as After the amorphous silicon layer is doped with the impurities, the semiconductor layer is formed by a laser crystallization process.

2. The display device according to claim 1, wherein The first layer is connected to one of the first electrode and the second electrode.

3. The display device according to claim 1 , further comprising: an insulating layer disposed on the first transistor; as well as a data connection element, the data connection element being arranged on the insulating layer, The first electrode and the first layer are connected to each other through the data connection member.

4. The display device according to claim 1, wherein The impurity includes one of boron, aluminum, indium and gallium.

5. The display device according to claim 1, wherein The first layer includes one of a metal having conductive properties and a semiconductor material having conductive properties similar to those of the metal. The display device according to claim 1 , wherein: The semiconductor layer includes a protrusion.

7. The display device according to claim 1, wherein: The channel includes a depletion region and a carrier transport region, and The depletion region is disposed at a lower end of the channel, and the carrier transport region is disposed at an upper end of the channel.

8. The display device according to claim 7, wherein: Cross-sections of the depletion region and the carrier transport region have a shape inclined with respect to the substrate.

9. The display device according to claim 1, wherein: The first layer receives a driving voltage.

10. The display device according to claim 1, further comprising: a storage line overlapping the first gate electrode, and The storage line and the first layer are connected to each other.

Images