A crystal oscillator circuit with fast startup

Abstract

The present invention discloses a crystal oscillator circuit with fast startup, which includes a crystal oscillator basic circuit, a ring oscillator, a comparator, a logic counting circuit, a third switch to an N1th switch, where N1 is a positive integer and N1≥3; the input end of the ring oscillator receives a power-on enable signal, the output end is connected to the input end of the third switch, the third switch to the N1th switch are connected in series in sequence, and the output end of the N1th switch is connected to the input end of the crystal oscillator basic circuit; the input end and the output end of the crystal oscillator basic circuit are connected to the two input ends of the comparator; the output end of the comparator outputs a clock signal and outputs the clock signal to an input end of the logic counting circuit; the other input end of the logic counting circuit receives a power-on reset signal, and the output end outputs a third switch control signal to an N1th switch control signal respectively to control the third switch to the N1th switch to be closed or opened; the present invention outputs an excitation signal to the crystal oscillator basic circuit through the ring oscillator to accelerate the startup time.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a crystal oscillator circuit with fast startup. Background Art

[0002] Crystal oscillators have good frequency accuracy and stability, and are small in size and low in power consumption. They are often used as time-frequency references and are widely applied in systems such as communication, radar, navigation, and guidance. Crystal oscillators can provide high-precision clock signals for various electronic systems. In some application environments, it is required that the startup time of the crystal oscillator be as short as possible. For example, in the Internet of Things system, it is necessary to continuously switch between sleep and activation. To achieve a shorter switching time, a shorter startup time of the crystal oscillator is required. At the same time, more and more electronic products require shortening the startup time, which also needs to be achieved by shortening the startup time of the crystal oscillator. How to achieve the fast startup of the crystal oscillator has become a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0003] The purpose of the present invention is to provide a crystal oscillator circuit with fast startup to achieve fast startup.

[0004] To achieve the purpose of the present invention, a technical solution adopted by the present invention is as follows:

[0005] A crystal oscillator circuit with fast startup includes a basic crystal oscillator circuit. The crystal oscillator circuit with fast startup further includes a ring oscillator, a comparator, a logic counting circuit, a first switch, a second switch, a third switch... an N1th switch, where N1 is a positive integer and N1≥3; the input end of the first switch is connected to the power supply, and the output end is connected to the power supply end of the basic crystal oscillator circuit; the input end of the second switch is connected to the power supply, and the output end is connected to the power supply end of the ring oscillator; the input end of the ring oscillator receives a power-on enable signal, and the output end is connected to the input end of the third switch. The third switch to the N1th switch are connected in series in sequence, and the output end of the N1th switch is connected to the input end of the basic crystal oscillator circuit; the input end and the output end of the basic crystal oscillator circuit are respectively connected to the two input ends of the comparator; the output end of the comparator outputs a clock signal and outputs the clock signal to an input end of the logic counting circuit; the other input end of the logic counting circuit receives a power-on reset signal, and the output end outputs a second switch control signal, a third switch control signal... an N1th switch control signal to control the second switch, the third switch... the N1th switch to be closed or opened; the power-on reset signal controls the first switch to be closed or opened.

[0006] To achieve the purpose of the present invention, another technical solution adopted by the present invention is as follows:

[0007] A crystal oscillator circuit with fast startup, including a basic crystal oscillator circuit. The crystal oscillator circuit with fast startup further includes a ring oscillator, a comparator, a logic counting circuit, a third switch to an N1th switch, where N1 is a positive integer and N1 ≥ 3. The power supply terminal of the ring oscillator and the power supply terminal of the basic crystal oscillator circuit are connected to a power supply. The input terminal of the ring oscillator receives a power-on enable signal, and the output terminal is connected to the input terminal of the third switch. The third switch to the N1th switch are connected in series in sequence, and the output terminal of the N1th switch is connected to the input terminal of the basic crystal oscillator circuit. The input terminal and the output terminal of the basic crystal oscillator circuit are respectively connected to the two input terminals of the comparator. The output terminal of the comparator outputs a clock signal and outputs the clock signal to an input terminal of the logic counting circuit. The other input terminal of the logic counting circuit receives a power-on reset signal, and the output terminal outputs a third switch control signal to an N1th switch control signal to control the third switch to the N1th switch to close or open.

[0008] As a specific implementation manner, the logic counting circuit includes an AND gate, a first D flip-flop, a second D flip-flop, a first NOT gate, a second NOT gate, and (N1 - 1) or (N1 - 2) output NOT gates. One input terminal of the AND gate receives the clock signal output by the comparator, and the other input terminal receives the power-on reset signal. The output terminal is connected to the clock signal input terminal of the first D flip-flop. The D port of the first D flip-flop is connected to the output terminal of the first NOT gate, and the Q port is connected to the input terminal of the first NOT gate and the input terminal of the second NOT gate. The output terminal of the second NOT gate is connected to the clock signal input terminal of the second D flip-flop. The D port of the second D flip-flop is connected to the Reset port, and the Q port is respectively connected to the input terminals of (N1 - 1) or (N1 - 2) output NOT gates.

[0009] Alternatively, the logic counting circuit includes an AND gate, a first D flip-flop, a second D flip-flop... an N3th D flip-flop, a first NOT gate, a second NOT gate... an N3th NOT gate, and (N1 - 1) or (N1 - 2) output NOT gates, where N3 is a positive integer and N3 ≥ 3. One input terminal of the AND gate receives the clock signal output by the comparator, and the other input terminal receives the power-on reset signal. The output terminal is connected to the clock signal input terminal of the first D flip-flop. The D port of the nth D flip-flop is connected to the output terminal of the nth NOT gate, and the Q port is connected to the input terminal of the nth NOT gate and the clock signal input terminal of the (n + 1)th D flip-flop, where n = 1 to (N3 - 2). The D port of the (N3 - 1)th D flip-flop is connected to the output terminal of the (N3 - 1)th NOT gate, and the Q port is connected to the input terminal of the (N3 - 1)th NOT gate and the input terminal of the N3th NOT gate. The output terminal of the N3th NOT gate is connected to the clock signal input terminal of the N3th D flip-flop. The D port of the N3th D flip-flop is connected to the Reset port, and the Q port is respectively connected to the input terminals of (N1 - 1) or (N1 - 2) output NOT gates;

[0010] The output terminals of the (N1 - 1) or (N1 - 2) output NOT gates respectively output switch control signals for controlling the second switch, the third switch... the N1th switch or the third switch to the N1th switch; the Reset terminals of the first D flip-flop, the second D flip-flop... the N3th D flip-flop all receive the power-on reset signal.

[0011] As a specific implementation, the ring oscillator includes NAND gates, a first NOT gate, a second NOT gate, a third NOT gate... an N2th NOT gate, where N2 = 3, 7, 9, 11...; One input terminal of the NAND gate receives the power-on reset signal, and the output terminal is connected to the input terminal of the first NOT gate. The first NOT gate, the second NOT gate, the third NOT gate... the N2th NOT gate are connected in series. The output terminal of the (N2 - 1)th NOT gate is connected to the other input terminal of the first NOT gate. The output terminal of the N2th NOT gate outputs an oscillation clock.

[0012] Further, the fast-start crystal oscillator circuit further includes a first buffer and / or a second buffer; The first buffer is connected between the ring oscillator and the third switch, with the input terminal connected to the output terminal of the ring oscillator and the output terminal connected to the input terminal of the third switch; The input terminal of the second buffer is connected to the output terminal of the comparator, and the output terminal outputs a clock signal.

[0013] Further, the fast-start crystal oscillator circuit further includes a first resistor; The first resistor is connected between the N1th switch and the basic crystal oscillator circuit, with one end connected to the output terminal of the N1th switch and the other end connected to the input terminal of the basic crystal oscillator circuit.

[0014] As a specific implementation manner, the ring oscillator includes a NAND gate, a first NOT gate, a second NOT gate, a third NOT gate... a N2th NOT gate, where N2 = 3, 7, 9, 11...; one input terminal of the NAND gate receives a power-on reset signal, and the output terminal is connected to the input terminal of the first NOT gate. The first NOT gate, the second NOT gate, the third NOT gate... the N2th NOT gate are connected in series. The output terminal of the (N2 - 1)th NOT gate is connected to the other input terminal of the first NOT gate, and the output terminal of the N2th NOT gate outputs an oscillation clock.

[0015] Further, the crystal oscillator circuit with fast startup further includes a first buffer and / or a second buffer; the first buffer is connected between the ring oscillator and the third switch, the input terminal is connected to the output terminal of the ring oscillator, and the output terminal is connected to the input terminal of the third switch; the input terminal of the second buffer is connected to the output terminal of the comparator, and the output terminal outputs a clock signal.

[0016] Further, the crystal oscillator circuit with fast startup further includes a first resistor; the first resistor is connected between the N1th switch and the basic crystal oscillator circuit, one end is connected to the output terminal of the N1th switch, and the other end is connected to the input terminal of the basic crystal oscillator circuit.

[0017] As a specific implementation manner, the basic crystal oscillator circuit includes an inverting amplifier, a feedback resistor, a crystal oscillator, a first capacitor, and a second capacitor; the input terminal of the inverting amplifier INV is connected to the output terminal of the N1th switch, one input terminal of the comparator, one end of the feedback resistor, one end of the crystal oscillator, and one end of the first capacitor; the output terminal of the inverting amplifier is connected to the other input terminal of the comparator, the other end of the feedback resistor, the other end of the crystal oscillator, and one end of the second capacitor; the power supply terminal of the inverting amplifier is connected to the other end of the first switch or directly connected to the power supply; the ground terminal of the inverting amplifier, the other end of the first capacitor, and the other end of the second capacitor are grounded.

[0018] Advantages of the present invention:

[0019] As can be seen from the above technical solutions, the present invention outputs an excitation signal from a ring oscillator to the input end of a crystal oscillator basic circuit to accelerate the start-up time of the basic crystal oscillator circuit, and counts the clock signal output by the basic crystal oscillator circuit through a logic counting circuit to control the ring oscillator to stop outputting excitation to the basic crystal oscillator circuit after the basic crystal oscillator circuit starts up stably. At the same time, after the crystal oscillator basic circuit starts up stably, the present invention disconnects the connection between the power supply and the ring oscillator through a second switch to stop the ring oscillator from oscillating and reduce power consumption. After the crystal oscillator basic circuit starts up stably, the third switch to the N1th switch disconnect the connection between the ring oscillator and the crystal oscillator basic circuit to prevent the oscillating clock output by the ring oscillator from affecting the normal operation of the crystal oscillator basic circuit, and reduce the interference of capacitive coupling on the crystal oscillator basic circuit. Further, the present invention increases the clock driving ability through a first buffer and a second buffer, so that the clock signal has good rising and falling edges. Further, the present invention reduces the probability that the working state deviation of the crystal oscillator basic circuit is too large due to the too strong driving ability of the excitation signal output to the crystal oscillator basic circuit, and the ring oscillator needs to re-establish the bias voltage after stopping outputting the excitation signal to the crystal oscillator basic circuit, thereby resulting in a longer start-up time of the crystal oscillator basic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. The drawings described below are only the embodiments in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1 is a structural block diagram of a crystal oscillator circuit with fast start-up provided in Embodiment 1 of the present invention;

[0022] Figure 2 is a circuit schematic diagram of a ring oscillator provided in Embodiment 1 of the present invention;

[0023] Figure 3 is a circuit schematic diagram of a logic counting circuit provided in Embodiment 1 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The present invention will be described in detail below with reference to the drawings.

[0025] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Embodiment 1

[0026] As Figure 1As shown, a crystal oscillator circuit with fast startup includes a basic crystal oscillator circuit, a ring oscillator, a first buffer BUF1, a second buffer BUF2, a comparator CMP, a logic counting circuit, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4; the basic crystal oscillator circuit includes an inverting amplifier INV, a feedback resistor RF, a crystal oscillator XTAL, a first capacitor C1, and a second capacitor C2; the input end of the first switch S1 is connected to the power supply VDD, and the output end is connected to the power supply end of the inverting amplifier INV; the input end of the second switch S2 is connected to the power supply VDD, and the output end is connected to the power supply end of the ring oscillator; the input end of the ring oscillator receives the power-on enable signal EN, and the output end is connected to the input end of the first buffer BUF1; the output end of the first buffer BUF1 is connected to the input end of the third switch S3, the output end of the third switch S3 is connected to the input end of the fourth switch S4, and the output end of the fourth switch S4 is connected to one end of a first resistor R1; the other end of the first resistor R1 is connected to the input end of the inverting amplifier INV, the inverting input end of the comparator CMP, one end of the feedback resistor RF, one end of the crystal oscillator XTAL, and one end of the first capacitor C1; the output end of the inverting amplifier INV is connected to the non-inverting input end of the comparator CMP, the other end of the feedback resistor RF, the other end of the crystal oscillator XTAL, and one end of the second capacitor C2; the ground end of the inverting amplifier INV, the other end of the first capacitor C1, and the other end of the second capacitor C2 are grounded to GND; the output end of the comparator CMP is connected to the input end of the second buffer BUF2 and one input end of the logic counting circuit; the output end of the second buffer BUF2 outputs a clock signal CLKO; the other input end of the logic counting circuit receives the power-on reset signal EN, and the output end outputs a second switch control signal SW2, a third switch control signal SW3, and a fourth switch control signal SW4 to the second switch S2, the third switch S3, and the fourth switch S4 respectively, to control the second switch S2, the third switch S3, and the fourth switch S4 to close or open; the power-on reset signal EN is output to the first switch S1 to control the first switch S1 to close or open.

[0027] In this embodiment, the power-on reset signal EN is a signal that maintains a low level before the power supply is turned on and becomes high after the power supply is turned on; the ring oscillator outputs an oscillation clock CLKring that is the same as or close to the operating frequency of the crystal oscillator; after the oscillation clock CLKring is started by the power-on reset signal EN (i.e., the power-on reset signal changes from low level to high level), it is injected into the input end of the crystal oscillator basic circuit through the first buffer BUF1, the third switch S3, the fourth switch S4, and the first resistor R1. The comparator CMP converts the sine wave oscillation output by the crystal oscillator basic circuit into a clock signal CLK, and the clock signal CLK is a square wave signal; the logic counting circuit counts the clock signal CLK output by the comparator CMP; before the power-on reset signal EN is started, the second switch control signal SW2, the third switch control signal SW3, and the fourth switch control signal SW4 output by the logic counting circuit control the second switch S2, the third switch S3, and the fourth switch S4 to be disconnected; after the power-on reset signal EN is started and before the count value of the logic counting circuit reaches the required value, that is, when the crystal oscillator basic circuit starts to oscillate but is not yet stable, the second switch control signal SW2, the third switch control signal SW3, and the fourth switch control signal SW4 output by the logic counting circuit control the second switch S2, the third switch S3, and the fourth switch S4 to be closed; after the power-on reset signal EN is started and when the count value reaches the required value, that is, after the crystal oscillator basic circuit starts to oscillate stably, the second switch control signal SW2, the third switch control signal SW3, and the fourth switch control signal SW4 output by the logic counting circuit control the second switch S2, the third switch S3, and the fourth switch S4 to be disconnected.

[0028] In this embodiment, after the crystal oscillator basic circuit starts to oscillate stably, the second switch S2 disconnects the connection between the power supply VDD and the ring oscillator, so that the ring oscillator stops oscillating and the power consumption is reduced; the third switch S3 and the fourth switch S4 connected between the ring oscillator and the first resistor R1 are used to disconnect the connection between the ring oscillator and the crystal oscillator basic circuit after the crystal oscillator basic circuit starts to oscillate stably, prevent the oscillation clock CLKring output by the ring oscillator from affecting the normal operation of the crystal oscillator basic circuit, and reduce the interference of capacitive coupling to the crystal oscillator basic circuit; both the first buffer BUF1 and the second buffer BUF2 include two inverters connected in series, which are used to increase the clock driving ability so that the clock signal has good rising and falling edges; the first resistor R1 is used to reduce the probability that the working state deviation of the crystal oscillator basic circuit is too large due to the too strong driving ability of the excitation signal output to the crystal oscillator basic circuit, and the ring oscillator stops outputting the excitation signal to the crystal oscillator basic circuit and then needs to re-establish the bias voltage, resulting in a longer start-up time of the crystal oscillator basic circuit.

[0029] In this embodiment, two switches are connected between the ring oscillator and the first resistor R1, and the isolation degree is better than that when only one switch is connected.

[0030] In this embodiment, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are all transmission gate switches; the power-on reset signal EN is output to the C terminal of the first switch S1, and the inverted power-on reset signal EN is output to the C-bar terminal of the first switch S1; before power-on, the power-on reset signal EN is at a low level, and the first switch S1 is open; after power-on, the power-on reset signal EN is at a high level, and the first switch S1 is closed, and the power supply VDD supplies power to the inverter INV; the second switch control signal SW2, the third switch control signal SW3, and the fourth switch control signal SW4 are respectively output to the C terminal of the second switch S2, the C terminal of the third switch S3, and the C terminal of the fourth switch S4, and the inverted second switch control signal SW2, the inverted third switch control signal SW3, and the inverted fourth switch control signal SW4 are respectively output to the C-bar terminal of the second switch S2, the C-bar terminal of the third switch S3, and the C-bar terminal of the fourth switch S4; before power-on, the power-on reset signal EN is at a low level, and the second switch control signal SW2, the third switch control signal SW3, and the fourth switch control signal SW4 are all at a low level, and the second switch S2, the third switch S3, and the fourth switch S4 are open; after power-on, the power-on reset signal EN becomes high, and before the count value of the logic counting circuit reaches the required value, the second switch control signal SW2, the third switch control signal SW3, and the fourth switch control signal SW4 become high to control the second switch S2, the third switch S3, and the fourth switch S4 to close; after power-on, the power-on reset signal EN becomes high, and after the count value of the logic counting circuit reaches the required value, the second switch control signal SW2, the third switch control signal SW3, and the fourth switch control signal SW4 become low to control the second switch S2, the third switch S3, and the fourth switch S4 to open.

[0031] As Figure 2 shown, in this embodiment, the ring oscillator includes a NAND gate NAND, a first NOT gate NOT1, a second NOT gate NOT2, a third NOT gate NOT3, a fourth NOT gate NOT4, and a fifth NOT gate NOT5; the power supply terminals of the NAND gate NAND, the first NOT gate NOT1, the second NOT gate NOT2, the third NOT gate NOT3, the fourth NOT gate NOT4, and the fifth NOT gate NOT5 are connected to the output terminal of the second switch S2, one input terminal of the NAND gate NAND receives the power-on reset signal EN, and the output terminal is connected to the input terminal of the first NOT gate NOT1, the output terminal of the first NOT gate NOT1 is connected to the input terminal of the second NOT gate NOT2, the output terminal of the second NOT gate NOT2 is connected to the input terminal of the third NOT gate NOT3, the output terminal of the fourth NOT gate NOT4 is connected to the input terminal of the fifth NOT gate NOT5 and the other input terminal of the NAND gate NAND; the output terminal of the fifth NOT gate NOT5 outputs the oscillation clock CLKring.

[0032] In this embodiment, the ring oscillator outputs the oscillating clock CLKring only when the power-on reset signal EN becomes high and the second switch S2 is closed to connect to the power supply VDD.

[0033] As Figure 3 shown, in this embodiment, the logic counting circuit includes an AND gate AND, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a sixth D flip-flop D6, a first NOT gate NOT_D1, a second NOT gate NOT_D2, a third NOT gate NOT_D3, a fourth NOT gate NOT_D4, a fifth NOT gate NOT_D5, a sixth NOT gate NOT_D6, and three output NOT gates NOT; one input terminal of the AND gate AND is connected to the clock signal CLK output by the comparator CMP, the other input terminal receives the power-on reset signal EN, and the output terminal is connected to the clock signal input terminal Clk of the first D flip-flop D1; the D port of the first D flip-flop D1 is connected to the output terminal of the first NOT gate NOT_D1, and the Q port is connected to the input terminal of the first NOT gate NOT_D1 and the clock signal input terminal Clk of the second D flip-flop D2; the D port of the second D flip-flop D2 is connected to the output terminal of the second NOT gate NOT_D2, and the Q port is connected to the input terminal of the second NOT gate NOT_D2 and the clock signal input terminal Clk of the third D flip-flop D3; the D port of the third D flip-flop D3 is connected to the output terminal of the third NOT gate NOT_D3, and the Q port is connected to the input terminal of the third NOT gate NOT_D3 and the clock signal input terminal Clk of the fourth D flip-flop D4; the D port of the fourth D flip-flop D4 is connected to the output terminal of the fourth NOT gate NOT_D4, and the Q port is connected to the input terminal of the fourth NOT gate NOT_D4 and the clock signal input terminal Clk of the fifth D flip-flop D5; the D port of the fifth D flip-flop D5 is connected to the output terminal of the fifth NOT gate NOT_D5, and the Q port is connected to the input terminal of the fifth NOT gate NOT_D5 and the input terminal of the sixth NOT gate NOT_D6, and the output terminal of the sixth NOT gate NOT_D6 is connected to the clock signal input terminal Clk of the sixth D flip-flop D6; the D port of the sixth D flip-flop D6 is connected to the Reset port, and the Q port is respectively connected to the input terminals of the three NOT gates NOT. The output terminals of the three NOT gates NOT respectively output the second switch control signal SW2, the third switch control signal SW3, and the fourth switch control signal SW4; the Reset terminals of the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3, the fourth D flip-flop D4, the fifth D flip-flop D5, and the sixth D flip-flop D6 are all connected to the power-on reset signal EN.

[0034] In this embodiment, the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3, the fourth D flip-flop D4, the fifth D flip-flop D5, and the sixth D flip-flop D6 are all rising-edge flip-flops; the signal output from the Q port of the sixth D flip-flop D6 changes from low level to high level at the 2 （6-1） i.e., 2 5 rising edges (i.e., when the count value of the logic counting circuit is 2 5 ), and the second switch control signal SW2, the third switch control signal SW3, and the fourth switch control signal SW4 output by the corresponding three output NOT gates change from high level to low level, controlling the second switch S2, the third switch S3, and the fourth switch S4 to change from closed to open. Embodiment 2

[0035] The difference between this embodiment and Embodiment 1 is that: the fourth switch S4 is not included; the other end of the third switch S3 is directly connected to one end of the first resistor R1; the logic counting circuit only includes two output NOT gates, and the two output NOT gates output the second switch control signal SW2 and the third switch control signal SW3 to the second switch S2 and the third switch S3, controlling the second switch S2 and the third switch S3 to be closed or open. Embodiment 3

[0036] The difference between this embodiment and Embodiment 1 or Embodiment 2 is that: it includes the first switch S1, the second switch S2, the third switch S3... the N1th switch SN1, where N1 is a positive integer and N1≥3; after the third switch S3 to the N1th switch SN1 are connected in series, they are connected between the output end of the ring oscillator and one end of the first resistor R1; the logic counting circuit includes (N1 - 1) output NOT gates, and the (N1 - 1) output NOT gates respectively output the second switch control signal SW2, the third switch control signal SW3... the N1th switch control signal SWN1 to the second switch S2, the third switch S3... the N1th switch SN1, controlling the second switch S2, the third switch S3... the N1th switch SN1 to be closed or open. Embodiment 4

[0037] The difference between this embodiment and Embodiment 1 or Embodiment 2 or Embodiment 3 is that: the first switch S1 and the second switch S2 are not included; the power supply VDD is directly connected to the power supply terminal of the ring oscillator and the power supply terminal of the inverting amplifier INV.

[0038] In this embodiment, the logic counting circuit includes (N1 - 2) output NOT gates NOT. The (N1 - 2) output NOT gates NOT respectively output the third switch control signal SW3 to the N1th switch control signal SWN1 to the third switch S3 to the N1th switch SN1, controlling the third switch S3 to the N1th switch SN1 to close or open. Embodiment Five

[0039] The difference between this embodiment and Embodiment One or Embodiment Two or Embodiment Three or Embodiment Four is that: the ring oscillator does not include the fourth NOT gate NOT4 and the fifth NOT gate NOT5; the first NOT gate NOT1, the second NOT gate NOT2, and the third NOT gate NOT3 are connected in series. The input end of the first NOT gate NOT1 is connected to the output end of the NAND gate NAND, and the output end of the second NOT gate NOT2 is connected to the other input end of the NAND gate NAND; the output end of the third NOT gate NOT3 outputs the oscillation clock CLKring. Embodiment Six

[0040] The difference between this embodiment and Embodiment One or Embodiment Two or Embodiment Three or Embodiment Four or Embodiment Five is that: the ring oscillator includes a NAND gate NAND, a first NOT gate NOT1, a second NOT gate NOT2, a third NOT gate NOT3... an N2th NOT gate NOTN2, where N2 = 3, 5, 7, 9, 11..., that is, N2 takes odd numbers greater than or equal to 3; one input end of the NAND gate NAND is connected to the power-on reset signal EN, and the output end is connected to the input end of the first NOT gate NOT1. The first NOT gate NOT1, the second NOT gate NOT2, the third NOT gate NOT3... the N2th NOT gate NOTN2 are connected in series. The output end of the (N2 - 1)th NOT gate NOT(N2 - 1) is connected to the other input end of the first NOT gate NOT1, and the output end of the N2th NOT gate NOTN2 outputs the oscillation clock CLKring. Embodiment Seven

[0041] The difference between this embodiment and Embodiment 1, Embodiment 2, Embodiment 3, Embodiment 4, Embodiment 5, or Embodiment 6 is as follows: The logic counting circuit includes an AND gate AND, a first D flip-flop D1, a second D flip-flop D2, a first NOT gate NOT_D1, a second NOT gate NOT_D2, and an output NOT gate NOT; One input terminal of the AND gate AND is connected to the clock signal CLK output by the comparator CMP, the other input terminal receives the power-on reset signal EN, and the output terminal is connected to the clock signal input terminal Clk of the first D flip-flop D1; The D port of the first D flip-flop D1 is connected to the output terminal of the first NOT gate NOT_D1, the Q port is connected to the input terminal of the first NOT gate NOT_D1 and the input terminal of the second NOT gate NOT_D2, and the output terminal of the second NOT gate NOT_D2 is connected to the clock signal input terminal Clk of the second D flip-flop D2; The D port of the second D flip-flop D2 is connected to the Reset port, and the Q port is respectively connected to the input terminals of the corresponding output NOT gate NOT.

[0042] In this embodiment, the signal output from the Q port of the second D flip-flop D2 changes from low level to high level at the 2 rising edges of the clock signal CLK (i.e., the logic counting circuit count value is two), and the switch control signal output by the corresponding output NOT gate NOT changes from high level to low level, controlling the switch to change from closed to open. Embodiment 8

[0043] The difference between this embodiment and Embodiment 1 or Embodiment 2 or Embodiment 3 or Embodiment 4 or Embodiment 5 or Embodiment 6 or Embodiment 7 is that: the logic counting circuit includes an AND gate AND, a first D flip-flop D1, a second D flip-flop D2... an N3th D flip-flop DN3, a first NOT gate NOT_D1, a second NOT gate NOT_D2... an N3th NOT gate NOT_DN3, and an output NOT gate NOT, where N3 is a positive integer and N3≥3; one input terminal of the AND gate AND is connected to the clock signal CLK output by the comparator CMP, the other input terminal receives the power-on reset signal EN, and the output terminal is connected to the clock signal input terminal Clk of the first D flip-flop D1; the D port of the nth D flip-flop Dn is connected to the output terminal of the nth NOT gate NOT_Dn, and the Q port is connected to the input terminal of the nth NOT gate NOT_Dn and the clock signal input terminal Clk of the (n + 1)th D flip-flop D(n + 1), where n = 1 to (N3 - 2); the D port of the (N3 - 1)th D flip-flop D5 is connected to the output terminal of the (N3 - 1)th NOT gate NOT_D5(N3 - 1), the Q port is connected to the input terminal of the (N3 - 1)th NOT gate NOT_D(N3 - 1) and the input terminal of the N3th NOT gate NOT_DN3, and the output terminal of the N3th NOT gate NOT_DN3 is connected to the clock signal input terminal Clk of the N3th D flip-flop DN3; the D port of the N3th D flip-flop DN3 is connected to the Reset port, and the Q port is respectively connected to the input terminals of the corresponding output NOT gate NOT.

[0044] In this embodiment, the signal output from the Q port of the N3th D flip-flop DN3 changes from low level to high level at the 2 （N3-1） rising edges of the clock signal CLK (i.e., when the count value of the logic counting circuit is 2 （N3-1） ), and the switch control signal output by the corresponding NOT gate NOT changes from high level to low level, controlling the switch to change from closed to open.

[0045] The above are only the preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments. Any technical solutions falling within the concept of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A crystal oscillator circuit with fast startup, including a basic crystal oscillator circuit, where the basic crystal oscillator circuit includes an inverting amplifier, a feedback resistor, a crystal oscillator, a first capacitor, and a second capacitor; the inverting amplifier, the feedback resistor, and the crystal oscillator are connected in parallel, and one end is grounded through the first capacitor and the other end is grounded through the second capacitor; It is characterized in that: It further includes a ring oscillator, a comparator, a logic counting circuit, a third switch to an N1th switch, where N1 is a positive integer and N1≥3; the power supply terminal of the ring oscillator and the power supply terminal of the basic crystal oscillator circuit are connected to the power supply; the input terminal of the ring oscillator receives a power-on enable signal, and the output terminal is connected to the input terminal of the third switch. The third switch to the N1th switch are connected in series in sequence, and the output terminal of the N1th switch is connected to the input terminal of the basic crystal oscillator circuit; the input terminal and the output terminal of the basic crystal oscillator circuit are respectively connected to the two input terminals of the comparator; the output terminal of the comparator outputs a clock signal and outputs the clock signal to an input terminal of the logic counting circuit; the other input terminal of the logic counting circuit receives a power-on reset signal, and the output terminal outputs a third switch control signal to an N1th switch control signal to control the third switch to the N1th switch to close or open.

2. The crystal oscillator circuit with fast start-up oscillation according to claim 1, characterized in that: It further includes a first switch and a second switch; the first switch is connected between the power supply and the basic crystal oscillator circuit, with the input terminal connected to the power supply and the output terminal connected to the power supply terminal of the basic crystal oscillator circuit; the second switch is connected between the power supply and the ring oscillator, with the input terminal connected to the power supply and the output terminal connected to the power supply terminal of the ring oscillator; the output terminal of the logic counting circuit outputs a second switch control signal to control the second switch to close or open; the power-on reset signal controls the first switch to close or open.

3. The crystal oscillator circuit with rapid oscillation startup according to any one of claims 1 or 2, characterized in that: The logic counting circuit includes an AND gate, a first D flip-flop, a second D flip-flop, a first NOT gate, a second NOT gate, and (N1 - 1) or (N1 - 2) output NOT gates. One input terminal of the AND gate receives the clock signal output by the comparator, and the other input terminal receives the power-on reset signal. The output terminal is connected to the clock signal input terminal of the first D flip-flop. The D port of the first D flip-flop is connected to the output terminal of the first NOT gate, and the Q port is connected to the input terminal of the first NOT gate and the input terminal of the second NOT gate. The output terminal of the second NOT gate is connected to the clock signal input terminal of the second D flip-flop. The D port of the second D flip-flop is connected to the Reset port, and the Q port is respectively connected to the input terminals of (N1 - 1) or (N1 - 2) output NOT gates. Alternatively, the logic counting circuit includes an AND gate, a first D flip-flop, a second D flip-flop, …, an N3th D flip-flop, a first NOT gate, a second NOT gate, …, an N3th NOT gate, and (N1 - 1) or (N1 - 2) output NOT gates, where N3 is a positive integer and N3 ≥ 3. One input terminal of the AND gate receives the clock signal output by the comparator, and the other input terminal receives the power-on reset signal. The output terminal of the AND gate is connected to the clock signal input terminal of the first D flip-flop. The D port of the nth D flip-flop is connected to the output terminal of the nth NOT gate, and the Q port is connected to the input terminal of the nth NOT gate and the clock signal input terminal of the (n + 1)th D flip-flop, where n ranges from 1 to (N3 - 2). The D port of the (N3 - 1)th D flip-flop is connected to the output terminal of the (N3 - 1)th NOT gate, and the Q port is connected to the input terminal of the (N3 - 1)th NOT gate and the input terminal of the N3th NOT gate. The output terminal of the N3th NOT gate is connected to the clock signal input terminal of the N3th D flip-flop. The D port of the N3th D flip-flop is connected to the Reset port, and the Q port is respectively connected to the input terminals of (N1 - 1) or (N1 - 2) output NOT gates; The output terminals of the (N1 - 1) or (N1 - 2) output NOT gates respectively output switch control signals for controlling the second switch, the third switch, …, the N1th switch or the third switch to the N1th switch; the Reset terminals of the first D flip-flop, the second D flip-flop, …, the N3th D flip-flop all receive the power-on reset signal.

4. The crystal oscillator circuit with fast start-up oscillation according to claim 3, characterized in that: The ring oscillator includes NAND gates, a first NOT gate, a second NOT gate, a third NOT gate, …, an N2th NOT gate, where N2 = 3, 7, 9, 11, …; one input terminal of the NAND gate receives the power-on reset signal, and the output terminal is connected to the input terminal of the first NOT gate. The first NOT gate, the second NOT gate, the third NOT gate, …, the N2th NOT gate are connected in series. The output terminal of the (N2 - 1)th NOT gate is connected to the other input terminal of the first NOT gate. The output terminal of the N2th NOT gate outputs an oscillation clock.

5. The crystal oscillator circuit with fast oscillation startup according to claim 3, wherein: It further includes a first buffer and / or a second buffer; the first buffer is connected between the ring oscillator and the third switch, with the input terminal connected to the output terminal of the ring oscillator and the output terminal connected to the input terminal of the third switch; the input terminal of the second buffer is connected to the output terminal of the comparator, and the output terminal outputs a clock signal.

6. The crystal oscillator circuit with fast startup according to claim 4, characterized in that: It further includes a first resistor; the first resistor is connected between the N1th switch and the basic crystal oscillator circuit, with one end connected to the output terminal of the N1th switch and the other end connected to the input terminal of the basic crystal oscillator circuit.

7. The crystal oscillator circuit with fast oscillation startup according to any one of claims 1 or 2, characterized in that: The ring oscillator includes NAND gates, a first NOT gate, a second NOT gate, a third NOT gate, …, an N2th NOT gate, where N2 = 3, 7, 9, 11, …; one input terminal of the NAND gate receives the power-on reset signal, and the output terminal is connected to the input terminal of the first NOT gate. The first NOT gate, the second NOT gate, the third NOT gate, …, the N2th NOT gate are connected in series. The output terminal of the (N2 - 1)th NOT gate is connected to the other input terminal of the first NOT gate. The output terminal of the N2th NOT gate outputs an oscillation clock.

8. The crystal oscillator circuit with rapid oscillation startup according to any one of claims 1 or 2, characterized in that: It further includes a first buffer and / or a second buffer; the first buffer is connected between the ring oscillator and the third switch, with its input terminal connected to the output terminal of the ring oscillator and its output terminal connected to the input terminal of the third switch; the input terminal of the second buffer is connected to the output terminal of the comparator, and the output terminal outputs a clock signal.

9. The crystal oscillator circuit with quick start-up oscillation according to claim 8, wherein: It further includes a first resistor; the first resistor is connected between the N1 switch and the basic crystal oscillator circuit, with one end connected to the output terminal of the N1 switch and the other end connected to the input terminal of the basic crystal oscillator circuit.

10. The crystal oscillator circuit with fast oscillation startup according to any one of claims 1 or 2, characterized in that: The input terminal of the inverting amplifier is connected to the output terminal of the N1 switch, one input terminal of the comparator, one end of the feedback resistor, one end of the crystal oscillator, and one end of the first capacitor; the output terminal of the inverting amplifier is connected to the other input terminal of the comparator, the other end of the feedback resistor, the other end of the crystal oscillator, and one end of the second capacitor; the power supply terminal of the inverting amplifier is connected to the other end of the first switch or directly connected to the power supply; the grounding terminal of the inverting amplifier, the other end of the first capacitor, and the other end of the second capacitor are grounded.

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