Fingerprint sensor and display device including the same

Abstract

A fingerprint sensor and a display device including the fingerprint sensor are provided. The display device may include: a first substrate including a pixel area; a circuit element layer disposed on a first surface of the first substrate and including at least one conductive layer; a light emitting element layer disposed on the circuit element layer; pixels each including a circuit element disposed on the circuit element layer and a light emitting element on the light emitting element layer in a corresponding pixel area in the pixel area; a first light-transmitting hole array layer including first light-transmitting holes distributed in the circuit element layer; and a light sensor array layer disposed on a second surface of the first substrate and configured to overlap with the first light-transmitting hole array layer, the light sensor array layer including a light sensor. The first light-transmitting hole may include an opening distributed in the at least one conductive layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0117795, filed on October 2, 2018, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention generally relate to a fingerprint sensor and a display device including the fingerprint sensor. Background Art

[0003] Recently, as display devices such as smartphones and tablet PCs are used in various ways, biometric information authentication methods using a user's fingerprint, etc. have been widely used. Therefore, it has been necessary to install various sensors including a fingerprint sensor in the display device.

[0004] For example, the fingerprint sensor may be configured as a light sensing type sensor. The light sensing type fingerprint sensor may include a light source, an optical system including a lens, and a light sensor array. When the fingerprint sensor is implemented in a display device, the thickness of the display device is increased and the production cost of the display device may be increased.

[0005] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0006] Devices constructed according to exemplary embodiments of the invention relate to a light sensing type fingerprint sensor and a display device including the light sensing type fingerprint sensor, which can reduce the thickness of a module and provide improved reliability.

[0007] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0008] According to one or more further embodiments of the invention, a display device includes: a first substrate including a plurality of pixel areas; a circuit element layer disposed on a first surface of the first substrate, the circuit element layer including at least one conductive layer; a light-emitting element layer disposed on the circuit element layer; a plurality of pixels each including a circuit element disposed on the circuit element layer and a light-emitting element on the light-emitting element layer in a corresponding pixel area among the plurality of pixel areas; a first light-transmitting hole array layer including a plurality of first light-transmitting holes distributed in the circuit element layer; and a light sensor array layer disposed on a second surface of the first substrate and superimposed on the first light-transmitting hole array layer, the light sensor array layer including a plurality of light sensors, wherein the plurality of first light-transmitting holes may include openings distributed in the at least one conductive layer.

[0009] The plurality of first light transmission holes may be provided in at least one of the plurality of pixels.

[0010] The plurality of pixels may include: first pixels, each including at least one first light-transmitting hole; and second pixels, disposed near the first pixels, each of the second pixels including a region having a structure different from the structure of a corresponding region of each of the first pixels in which the first light-transmitting hole is formed.

[0011] Each of the plurality of first light-transmitting holes may include: a first opening formed in a first conductive layer disposed on a first substrate; a second opening formed in a second conductive layer disposed on the first conductive layer, the second opening overlapping the first opening; and at least one insulating layer disposed between the first conductive layer and the second conductive layer.

[0012] At least one of the first conductive layer and the second conductive layer may include a light-blocking metal pattern.

[0013] Each of the plurality of pixels may include at least one capacitor. The capacitor of at least one pixel among the plurality of pixels may include: a first capacitor electrode disposed in the first conductive layer and surrounding a first opening of one of the plurality of first light-transmitting holes; and a second capacitor electrode disposed in the second conductive layer, overlapping the first capacitor electrode and surrounding a second opening of the one first light-transmitting hole.

[0014] The first opening and the second opening may have the same width in one direction.

[0015] The second opening may have a width in one direction greater than a width of the first opening.

[0016] Each of the plurality of pixels may include at least one transistor. The at least one transistor may include: an active pattern disposed in a semiconductor layer on a first substrate; a gate electrode disposed in a first conductive layer, the first conductive layer disposed on the semiconductor layer, and at least one insulating layer interposed between the first conductive layer and the semiconductor layer, the gate electrode overlapping the active pattern; and a source electrode and a drain electrode coupled to respective opposite ends of the active pattern.

[0017] The display device may further include at least one of the following elements: a second conductive layer disposed on the first conductive layer, with at least one insulating layer disposed between the first conductive layer and the second conductive layer, the second conductive layer including at least one capacitor electrode; and a third conductive layer disposed on the second conductive layer, with at least one insulating layer disposed between the second conductive layer and the third conductive layer, the third conductive layer including at least one line.

[0018] Each of the plurality of first light-transmitting holes may include a plurality of openings formed in at least two of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer, the plurality of openings overlapping each other.

[0019] The light emitting element may include: a first electrode and a second electrode provided in each of the plurality of pixel regions of the light emitting element layer, the first electrode and the second electrode overlapping each other; and an emission layer provided between the first electrode and the second electrode.

[0020] At least one of the plurality of first light-transmitting holes may be formed in one pixel among the plurality of pixels and disposed in a non-emission region of the one pixel, and the at least one first light-transmitting hole does not overlap with a first electrode of a light-emitting element of the one pixel.

[0021] The display device may further include a second light transmission hole array layer disposed between the first substrate and the circuit element layer and overlapping the first light transmission hole array layer, the second light transmission hole array layer including a plurality of second light transmission holes overlapping the plurality of first light transmission holes.

[0022] The plurality of first light transmission holes and the plurality of second light transmission holes may have different widths.

[0023] The display device may further include: a second substrate, disposed between the first substrate and the light sensor array layer; and a third light-transmitting hole array layer, disposed between the first substrate and the second substrate and configured to overlap with the first light-transmitting hole array layer, the third light-transmitting hole array layer including a plurality of third light-transmitting holes overlapping with the plurality of first light-transmitting holes.

[0024] The display device may include a sensing region including at least a portion of a display region in which the plurality of pixels are disposed, wherein the first light-transmitting hole array layer and the light sensor array layer may be disposed in the sensing region.

[0025] The plurality of first light transmission holes may be distributed in the sensing area at a resolution lower than a resolution of the plurality of pixels.

[0026] The light sensors may be distributed in the sensing area with a resolution higher than a resolution of the plurality of first light-transmitting holes.

[0027] According to one or more embodiments of the invention, a fingerprint sensor includes: a first substrate; a circuit element layer, which is disposed on a first surface of the first substrate and includes at least one conductive layer; a light-emitting element layer, which is disposed on the circuit element layer and includes a plurality of light-emitting elements; a first light-transmitting hole array layer, which includes a plurality of first light-transmitting holes distributed in the circuit element layer; and a light sensor array layer, which is disposed on a second surface of the first substrate and overlaps with the first light-transmitting hole array layer, the light sensor array layer including a plurality of light sensors. The plurality of first light-transmitting holes may include openings distributed in the at least one conductive layer.

[0028] The circuit element layer may include: a first conductive layer disposed on the first substrate; a second conductive layer disposed on the first conductive layer; and at least one insulating layer disposed between the first conductive layer and the second conductive layer.

[0029] Each of the plurality of first light-transmitting holes may include: a first opening formed in the first conductive layer; and a second opening formed in the second conductive layer and overlapping the first opening.

[0030] At least one of the first conductive layer and the second conductive layer may include a light-blocking metal pattern.

[0031] The circuit element layer may include at least one capacitor. The capacitor may include: a first capacitor electrode disposed in the first conductive layer and surrounding a first opening of any one of the plurality of first light-transmitting holes; and a second capacitor electrode disposed in the second conductive layer, overlapping the first capacitor electrode and surrounding a second opening of any one of the first light-transmitting holes.

[0032] The circuit element layer may include at least one transistor, the at least one transistor including an active pattern, a gate electrode, a source electrode, and a drain electrode. Each of the plurality of first light-transmitting holes may include at least one opening formed in at least one of a semiconductor layer in which the active pattern is disposed, a first conductive layer in which the gate electrode is disposed, and a second conductive layer disposed on the first conductive layer, and at least one insulating layer is disposed between the semiconductor layer, the first conductive layer, and the second conductive layer.

[0033] Each of the plurality of light emitting elements may include: a first electrode and a second electrode disposed in each emission region of the light emitting element layer, the first electrode and the second electrode overlapping each other; and an emission layer disposed between the first electrode and the second electrode.

[0034] The plurality of first light-transmitting holes may be distributed in a non-emitting region of the light-emitting element layer, and the plurality of first light-transmitting holes do not overlap with the first electrodes of the plurality of light-emitting elements.

[0035] The fingerprint sensor may further include a second light-transmitting hole array layer disposed between the first substrate and the circuit element layer and overlapping the first light-transmitting hole array layer, the second light-transmitting hole array layer including a plurality of second light-transmitting holes overlapping the plurality of first light-transmitting holes.

[0036] The fingerprint sensor may further include: a second substrate, disposed between the first substrate and the light sensor array layer; and a third light-transmitting hole array layer, disposed between the first substrate and the second substrate and configured to overlap with the first light-transmitting hole array layer, the third light-transmitting hole array layer including a plurality of third light-transmitting holes overlapping with the plurality of first light-transmitting holes.

[0037] The light sensor may be disposed on the second surface of the first substrate with a resolution higher than a resolution of the plurality of first light transmission holes.

[0038] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept, wherein the accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0040] Figure 1 and Figure 2 Each is a plan view showing a fingerprint sensor and a display device including the fingerprint sensor according to an exemplary embodiment of the present disclosure.

[0041] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E Each is a plan view showing an arrangement structure of pixels and light sensors according to an exemplary embodiment of the present disclosure.

[0042] Figure 4 is a plan view showing a pinhole array layer according to an exemplary embodiment of the present disclosure.

[0043] Figure 5A , Figure 5B , Figure 5C and Figure 5D Each is a plan view showing an arrangement structure of a pixel, a pinhole, and a light sensor according to an exemplary embodiment of the present disclosure.

[0044] Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 9 , Fig.10 , Fig.11 and Fig.12 Each is a cross-sectional view showing a fingerprint sensor and a display device including the fingerprint sensor according to an exemplary embodiment of the present disclosure.

[0045] Fig.13 : is a cross-sectional view comparatively showing required sizes of opening areas according to positions of a pinhole array layer for various exemplary embodiments.

[0046] Fig.14 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present disclosure.

[0047] Fig.15 It is shown Fig.14 0 is a plan view of an exemplary embodiment of a layout of pixels shown in FIG.

[0048] Fig.16A and Fig. 16B are along Fig.15 Cross-sectional views taken along the lines II-I' and II-II'.

[0049] Fig.17 is a plan view illustrating an example of a layout of a first pixel according to an exemplary embodiment of the present disclosure.

[0050] Fig.18 is along Fig.17 A cross-sectional view taken along line III-III'.

[0051] Fig.19 is a plan view illustrating an example of a layout of a first pixel according to an exemplary embodiment of the present disclosure.

[0052] Fig. 20 is along Fig.19 A cross-sectional view taken along section line IV-IV'.

[0053] Fig.21 is a plan view illustrating an example of a layout of a first pixel according to an exemplary embodiment of the present disclosure.

[0054] Fig.22A and Fig. 22B are along Fig.21 Cross-sectional view taken along sections V-V' and VI-VI'.

[0055] Fig.23 is a plan view illustrating an example of a layout of first pixels and second pixels according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] In the following description, for the purpose of illustration, many specific details are set forth to provide a comprehensive understanding of various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable words for non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, in order to avoid making various exemplary embodiments unnecessarily obscure, known structures and devices are shown in block diagram form. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, construction and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0057] Unless otherwise specified, the illustrated exemplary embodiments will be understood as providing exemplary features of various details of some ways in which the inventive concept can actually be implemented. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0058] The use of cross hatching and / or shading is usually provided in the drawings to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence and absence of cross hatching or shading do not express or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0059] When an element or layer is referred to as "on" another element or layer, "connected to" or "bonded to" another element or layer, the element or layer may be directly on, directly connected to or directly bonded to the other element or layer, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as "directly on" another element or layer, "directly connected to" or "directly bonded to" another element or layer, there is no intermediate element or intermediate layer. For this reason, the term "connection" may represent a physical connection, electrical connection and / or fluid connection with or without an intermediate element. For the purpose of this disclosure, "at least one (kind / person) of X, Y and Z" and "at least one (kind / person) selected from the group consisting of X, Y and Z" may be interpreted as any combination of only X, only Y, only Z or two (kind / person) or more (kind / person) of X, Y and Z, such as taking XYZ, XYY, YZ and ZZ as an example. As used herein, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items.

[0060] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the disclosed teachings, the first element discussed below may be named as the second element.

[0061] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another (additional) element as shown in the accompanying drawings. Spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features will subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "under" can include both above and below orientations. In addition, the device can be positioned otherwise (e.g., rotated 90 degrees or at other orientations), so the spatially relative descriptors used herein are interpreted accordingly.

[0062] The terms used herein are for the purpose of describing specific embodiments, and are not intended to be limited. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprising" and / or "including" are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, elements, components and / or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than as terms of degree, so that they are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0063] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded illustrations as schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations, such as those caused by manufacturing techniques and / or tolerances, are expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as being limited to the shapes of the specifically illustrated regions, but will include deviations in shapes caused by, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, no limitation is necessarily intended.

[0064] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an ideal or overly formal sense unless explicitly defined as such herein.

[0065] Figure 1 and Figure 2 1 and 2 are plan views each showing a fingerprint sensor and a display device including the fingerprint sensor according to an exemplary embodiment of the present disclosure. In more detail, Figure 1 and Figure 2 A display panel 110 provided in a display device according to an exemplary embodiment and a photo sensor PHS provided in the display device are schematically shown such that the photo sensor PHS overlaps at least a portion of the display panel 110. The photo sensor PHS may form a light sensing type fingerprint sensor.

[0066] Reference Figure 1 and Figure 2, a display device according to an exemplary embodiment of the present disclosure may include a display panel 110 having a display area DA and a non-display area NDA. In an exemplary embodiment, a portion of the display panel 110 may be set as a sensing area SA where a user's fingerprint or the like may be sensed.

[0067] A plurality of pixels PXL are disposed in the display area DA. In an exemplary embodiment, each pixel PXL may include at least one light emitting element. In an exemplary embodiment, the light emitting element may be a light emitting unit including an organic light emitting diode or an inorganic light emitting diode each having a size in the micrometer or nanometer range, but the light emitting element is not limited thereto. The display device may drive the pixels PXL in response to image data input thereto, thereby displaying an image in the display area DA.

[0068] In an exemplary embodiment, the display area DA may include the sensing area SA. In other words, the display area DA and the sensing area SA may overlap each other, and at least a portion of the display area DA may also be the sensing area SA.

[0069] For example, Figure 1 As shown in , only a portion of the display area DA may be set as the sensing area SA. Figure 2 As shown in , the entire display area DA may be set as the sensing area SA. As another alternative, in an exemplary embodiment, the display area DA and the sensing area SA may be disposed adjacent to each other in such a manner that only respective portions of the display area DA and the sensing area SA overlap each other.

[0070] In other words, in an exemplary embodiment, at least a portion of the display area DA may be set as the sensing area SA. In the sensing area SA, a plurality of photosensors PHS may be disposed together with a plurality of pixels PXL.

[0071] In an exemplary embodiment, the light sensor PHS may be provided on both the image display surface (e.g., the front surface) and the other surface (e.g., the rear surface) opposite to the front surface of the display panel 110. Each light sensor PHS may employ a light emitting element provided in at least one pixel PXL provided in the sensing area SA or provided near the sensing area SA as a light source required for sensing fingerprints or the like. To this end, the light sensor PHS may overlap at least some of the pixels PXL provided in the sensing area SA, or may be provided near the pixels PXL.

[0072] The light sensor PHS together with the pixel PXL of the sensing area SA (specifically, together with the light emitting element provided in the pixel PXL) can form a light sensing type fingerprint sensor. In the present disclosure, the fingerprint sensor is not limited to being dedicated to the fingerprint sensing function only, and the fingerprint sensor can be used for other purposes besides the fingerprint sensing function. For example, the fingerprint sensor can also be used as a touch sensor, a scanner, etc. In other words, the fingerprint sensor according to the present disclosure can construct various light sensing type sensors including a touch sensor or a scanner, and is not limited to a sensor used only for the fingerprint sensing function.

[0073] In addition, the display device according to the exemplary embodiment of the present disclosure may further include an optical system that constructs a light sensing type fingerprint sensor together with the optical sensor PHS. In an exemplary embodiment, at least a portion of the optical system may be provided integrally with the display panel 110. For example, the display panel 110 may be an optical system integrated display panel including a pinhole array layer formed on a circuit element layer.

[0074] The non-display area NDA may be an area disposed near the display area DA and indicates a remaining area other than the display area DA. In an exemplary embodiment, the non-display area NDA may include a line area, a pad area, a driving circuit mounting area, and / or various dummy areas.

[0075] The display device according to the above embodiment may sense a shape, pattern, etc. of an object placed on the display panel 110 using the photosensor PHS disposed in the sensing area SA overlapping the display area DA. For example, the display device may sense a fingerprint of a user.

[0076] In addition, in an exemplary embodiment of the present disclosure, the display device can sense the fingerprint of the user using the light emitted from the pixel PXL. In this way, when the fingerprint sensor embedded in the display device is configured to use the pixel PXL as a light source without using a separate external light source, the thickness of the module including the light sensing type fingerprint sensor and the display device using the light sensing type fingerprint sensor can be reduced or minimized, and the production cost can also be reduced.

[0077] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E 1 and 2 are plan views showing an arrangement structure of a pixel PXL and a light sensor PHS according to an exemplary embodiment of the present disclosure. In detail, Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E Shows the settings for Figure 1 and Figure 2 Different embodiments of the relative size, resolution and / or arrangement relationship of the pixels PXL and the light sensors PHS in the sensing area SA. Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E The exemplary embodiments shown in FIG. 1 may change the shape, configuration, relative size, number, resolution and / or mutual arrangement relationship of the pixels PXL and / or the photosensors PHS disposed in the sensing area SA in various ways.

[0078] Reference Figure 3A , the light sensors PHS may be provided at least in the sensing area SA with the same resolution (or the same density) as that of the pixels PXL. For example, the same number of light sensors PHS as the number of pixels PXL may be provided in the sensing area SA such that the light sensors PHS are paired one-to-one with the pixels PXL. In an exemplary embodiment, the pixels PXL and the light sensors PHS may be provided in a 1:1 ratio and arranged alternately such that the pixels PXL and the light sensors PHS do not overlap each other.

[0079] In an exemplary embodiment, at least a portion of each light sensor PHS may overlap with at least one pixel PXL. For example, each light sensor PHS may have a size smaller than that of each pixel PXL and may be disposed in a pixel region in which any one pixel PXL is formed. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, the pixels PXL and the light sensors PHS may be alternately arranged without overlapping each other, regardless of the relative sizes and / or numbers of the pixels PXL and the light sensors PHS.

[0080] Reference Figure 3B , the number of light sensors PHS included in the sensing area SA may be greater than the number of pixels PXL included in the sensing area SA. For example, each light sensor PHS may have a size smaller than that of each pixel PXL. The light sensors PHS may be densely distributed in the sensing area SA with a resolution higher than that of the pixels PXL. In an exemplary embodiment, at least some of the light sensors PHS may be disposed to overlap with the pixels PXL.

[0081] Reference Figure 3C and Figure 3D , the number of light sensors PHS included in the sensing area SA may be smaller than the number of pixels PXL included in the sensing area SA. For example, each light sensor PHS may have a size smaller than that of each pixel PXL. The light sensors PHS may be distributed in the sensing area SA with a resolution lower than that of the pixels PXL.

[0082] For example, Figure 3C As shown in , the light sensor PHS may be arranged to overlap only some of the pixels PXL in the sensing area SA. Figure 3D As shown in , the light sensor PHS may be disposed in a space between the pixels PXL so that the light sensor PHS does not overlap with the pixels PXL in the sensing area SA. Figure 3C and Figure 3D An embodiment is shown in which one photosensor PHS is disposed for every four pixels PXL in the sensing area SA, but the present disclosure is not limited thereto. In other words, the relative size, number, pitch, and / or resolution of the photosensors PHS and pixels PXL disposed in the sensing area SA may be changed in various ways.

[0083] Reference Figure 3E , the size of each photosensor PHS and / or the pitch at which the photosensors PHS are arranged in the sensing area SA may be within a range that allows each photosensor PHS to overlap with a plurality of pixels PXL disposed in the sensing area SA. In an exemplary embodiment, each photosensor PHS may be disposed between a plurality of pixels PXL adjacent to each other such that the photosensor PHS partially overlaps with the pixels PXL.

[0084] For example, in an exemplary embodiment, each photosensor PHS may have a size capable of covering at least one pixel PXL and may be arranged to overlap with the at least one pixel PXL. As another alternative, in an exemplary embodiment, the size of each photosensor PHS and / or the pitch at which the photosensors PHS are arranged in the sensing area SA may be independent of the mutual arrangement relationship between the photosensors PHS and the pixels PXL or whether the photosensors PHS overlap with the pixels PXL.

[0085] As described above, the size, number, resolution, and position of the optical sensors PHS disposed in the sensing area SA and / or the arrangement structure of the optical sensors PHS and the pixels PXL may be changed in various ways. For example, the size, number, resolution, and position of the optical sensors PHS disposed in the sensing area SA and / or the arrangement structure of the optical sensors PHS and the pixels PXL may be determined in consideration of various factors such as the minimum light reception amount required for fingerprint sensing, resolution, and / or crosstalk.

[0086] In addition, although Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3EAn embodiment is shown in which the light sensors PHS are arranged in a regular array in the sensing area SA, but the present disclosure is not limited thereto. For example, in an exemplary embodiment, the light sensors PHS may be irregularly distributed in the sensing area SA.

[0087] Figure 4 is a plan view showing a pinhole array layer PHL according to an exemplary embodiment of the present disclosure.

[0088] Reference Figure 4 , the pinhole array layer PHL may include a light blocking mask LBM and a plurality of pinholes PIH distributed in the light blocking mask LBM.

[0089] In an exemplary embodiment, the light blocking mask LBM may be formed of a light blocking material and / or a light absorbing material. For example, the light blocking mask LBM may be formed of an opaque metal layer partially opened in a portion where a corresponding pinhole PIH is formed. However, the material of the light blocking mask LBM is not limited to metal, and the light blocking mask LBM may be formed of various materials capable of blocking light transmission. For example, the light blocking mask LBM may be formed of a known black matrix material.

[0090] In an exemplary embodiment, the pinhole PIH may be an opening distributed in the light blocking mask LBM. For example, the pinhole array layer PHL may include a plurality of pinholes PIH having a constant size and uniformly distributed in the light blocking mask LBM at a regular pitch. However, the present disclosure is not limited thereto, and the size, shape, number, resolution and / or arrangement structure of the pinhole PIH may be changed in various ways. For example, in an exemplary embodiment of the present disclosure, the pinhole PIH may be distributed in the light blocking mask LBM in an irregular pattern.

[0091] In an exemplary embodiment, in a light sensing type sensor (eg, referring to Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E In the described light sensor PHS) and the display device including the light sensing type sensor, the pinhole array layer PHL can be arranged between the light emitting element layer in which the light emitting element is arranged and the light sensor array layer in which the light sensor PHS is arranged, so that an optical system for controlling the path of light, etc. can be formed by allowing only some light to selectively pass through the pinhole array layer PHL.

[0092] In an exemplary embodiment of the present disclosure, the pinhole array layer PHL together with the above-mentioned light sensor PHS can form a fingerprint sensor. In addition, in an exemplary embodiment, the pinhole array layer PHL can be integrally provided with the circuit element layer of the display panel 110. In this case, the thickness of the module including the light sensing type fingerprint sensor and the display device including the fingerprint sensor can be reduced or minimized. In addition, the ripple effect that may occur in the light sensing type fingerprint sensor can be reduced or prevented by controlling the size, pitch and / or resolution of the light sensor array layer including the light sensor PHS and the pinhole array layer PHL including the pinholes PIH.

[0093] Figure 5A , Figure 5B , Figure 5C and Figure 5D 1 and 2 are plan views showing an arrangement structure of a pixel PXL, a pinhole PIH, and a light sensor PHS according to an exemplary embodiment of the present disclosure. In detail, Figure 5A , Figure 5B , Figure 5C and Figure 5D Shows the settings for Figures 1 to 3E Different embodiments of the relative size, resolution and / or arrangement relationship of the pixel PXL, the pinhole PIH and the light sensor PHS in the sensing area SA.

[0094] Reference Figure 5A , each of the numbers of the pinholes PIH and the light sensors PHS included in the sensing area SA may be smaller than the number of the pixels PXL included in the sensing area SA. For example, each pinhole PIH and each light sensor PHS may have a size smaller than that of each pixel PXL. The pinholes PIH and the light sensors PHS may be distributed in the sensing area SA with a resolution lower than that of the pixels PXL.

[0095] In an exemplary embodiment, the number and pitch of the pinholes PIH distributed in the sensing area SA may be the same as the number and pitch of the light sensors PHS distributed in the sensing area SA, so that the pinholes PIH and the light sensors PHS correspond one to one to each other. For example, the pinholes PIH and the light sensors PHS may be paired one to one and arranged to overlap each other. In an exemplary embodiment, a pair of pinholes PIH and the light sensors PHS may be arranged to overlap with any one of the pixels PXL arranged in the sensing area SA, but is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the pinholes PIH and the light sensors PHS may be alternately arranged so as not to overlap with each other. For example, the pinholes PIH and / or the light sensors PHS may be arranged so as not to overlap with the pixels PXL.

[0096] In an exemplary embodiment, the pinhole PIH and the light sensor PHS may have the same size or different sizes. In other words, the relative sizes or resolutions of the pinhole PIH and the light sensor PHS are not limited to a specific range.

[0097] Reference Figure 5B , the number of pinholes PIH included in the sensing area SA may be smaller than the number of pixels PXL included in the sensing area SA, and the number of light sensors PHS included in the sensing area SA may be greater than the number of pixels PXL. For example, each pinhole PIH and each light sensor PHS may have a size smaller than that of each pixel PXL. The pinholes PIH may be distributed in the sensing area SA with a resolution lower than that of the pixel PXL. The light sensors PHS may be densely distributed in the sensing area SA with a resolution higher than that of the pixel PXL.

[0098] In an exemplary embodiment, at least some of the light sensors PHS may overlap with any one of the pinholes PIH and / or the pixels PXL, but are not limited thereto. For example, some of the light sensors PHS may be disposed to overlap with the pinholes PIH and / or the pixels PXL, and some of the light sensors PHS may be disposed in a space between the pixels PXL.

[0099] Reference Figure 5C and Figure 5D , each of which has a relatively small size of light sensor PHS can be distributed in the sensing area SA with a relatively high resolution. For example, a plurality of light sensors PHS can be overlapped with each pinhole PIH and / or each pixel PXL. The pinhole PIH can be distributed in the sensing area SA with a resolution equal to or different from the resolution of the pixel PXL. For example, Figure 5C As shown in , the pinholes PIH may be uniformly distributed in the sensing area SA with a resolution equal to that of the pixels PXL. Figure 5D As shown in , the pinholes PIH may be uniformly distributed in the sensing area SA at a resolution lower than that of the pixels PXL.

[0100] As described above, the size, number, resolution and position of the pinhole PIH and / or the photosensor PHS provided in the sensing area SA and / or the arrangement structure of the pinhole PIH and / or the photosensor PHS and the pixel PXL may be changed in various ways. For example, in order to sense the shape of the user's fingerprint using the photosensor PHS in a manner similar to that of a pinhole camera, each pinhole PIH may be formed to have a size (e.g., width or area) corresponding to a range in which light diffraction can be prevented and the shape of the fingerprint can be sensed more clearly. For example, each pinhole PIH may have a width (or a diameter in the case of a circular shape) in the range of about 5 μm to about 15 μm in a first direction (e.g., horizontal direction) and / or a second direction (e.g., vertical direction). Thus, the reliability of the fingerprint sensor may be improved. For example, the width of each pinhole PIH may be in a wider range from about 2 μm to about 20 μm. In an exemplary embodiment, the size of each pinhole PIH may be changed according to various factors such as the wavelength bandwidth of the light used to sense the fingerprint and / or the thickness of each layer of the module.

[0101] In addition, although Figure 5A , Figure 5B , Figure 5C and Figure 5D An embodiment in which the pinholes PIH and the light sensors PHS are arranged in a regular array in the sensing area SA is shown, but the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the pinholes PIH and / or the light sensors PHS may be irregularly distributed in the sensing area SA. For example, the density or arrangement structure of the pinholes PIH and / or the light sensors PHS may be changed by a region or portion of the sensing area SA.

[0102] The arrangement structure of the pixel PXL, the pinhole PIH and the light sensor PHS is not limited to Figure 5A , Figure 5B , Figure 5C and Figure 5D For example, the shape, configuration, relative size, number, resolution and / or mutual arrangement relationship of the pixels PXL, pinholes PIH and / or photosensors PHS disposed in the sensing area SA may be changed in various ways.

[0103] Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 9 , Fig.10 , Fig.11 and Fig.121 and 2 are cross-sectional views each showing a fingerprint sensor and a display device 100 including the fingerprint sensor according to an exemplary embodiment of the present disclosure. In more detail, Figures 6 to 12 Different embodiments of the display device 100 are shown. The display device 100 includes a display panel 110 and Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 5A , Figure 5B , Figure 5C and Figure 5D The light sensor PHS and the light-transmitting hole array layer LTHL shown in the figure have at least one layer structure including a pinhole array layer PHL disposed between the light-emitting element layer and the light sensor PHS. In an exemplary embodiment, the light-transmitting hole array layer LTHL having at least one layer structure may be disposed in the sensing area SA and form an optical system of the fingerprint sensor.

[0104] Reference Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 4 , Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 6 , the display device 100 according to an exemplary embodiment of the present disclosure may include at least a display panel 110 and a light sensor array layer PSL disposed on one surface of the display panel 110. In an exemplary embodiment, the display device 100 may include: a first substrate SUB1; a circuit element layer BPL, a light emitting element layer LDL, a first passivation layer PTL1, a first adhesive layer ADL1, and a window WIN, which are sequentially disposed on a first surface (e.g., an upper surface) of the first substrate SUB1; and a second passivation layer PTL2, a second adhesive layer ADL2, and a light sensor array layer PSL, which are sequentially disposed on a second surface (e.g., a lower surface) of the first substrate SUB1. In an exemplary embodiment, the first substrate SUB1, the circuit element layer BPL, the light emitting element layer LDL, and the first passivation layer PTL1 and / or the second passivation layer PTL2 may form the display panel 110.

[0105] The display device 100 may further include a pinhole array layer PHL disposed between the light emitting element layer LDL and the light sensor array layer PSL. In an exemplary embodiment, the light sensor array layer PSL and the pinhole array layer PHL may be disposed to overlap each other in the sensing area SA.

[0106] In addition, in an exemplary embodiment, although not shown, the display device 100 may further include, for example, a polarizing plate and / or a touch sensor layer (touch electrode layer). For example, the display device 100 may further include a polarizing plate and / or a touch sensor layer disposed between the first passivation layer PTL1 and the window WIN.

[0107] The first substrate SUB1 may be a base substrate of the display panel 110 and may be formed of a substantially transparent light-transmitting substrate. In an exemplary embodiment, the first substrate SUB1 may be formed of a rigid substrate including glass or tempered glass or a flexible substrate made of plastic. However, the material of the first substrate SUB1 is not limited thereto, and the first substrate SUB1 may be formed of various materials.

[0108] In an exemplary embodiment, if Figure 1 and Figure 2 As shown in FIG. 1 , the first substrate SUB1 may include a display area DA and a non-display area NDA. The display area DA may include a plurality of pixel areas PXA in which respective pixels PXL are disposed and / or formed.

[0109] The circuit element layer BPL may be disposed on the first surface of the first substrate SUB1 and may include at least one conductive layer. For example, the circuit element layer BPL may include a plurality of circuit elements and lines configured to supply various power supply voltages and signals for driving the pixels PXL, each of the plurality of circuit elements being formed in a corresponding pixel region PXA in the pixel region PXA to form a pixel circuit of the corresponding pixel PXL. In this case, the circuit element layer BPL may include various circuit elements such as transistors and capacitors and a plurality of conductive layers configured to form lines to be connected to the various circuit elements.

[0110] The light emitting element layer LDL may be disposed on the first surface of the first substrate SUB1, and the circuit element layer BPL is disposed between the light emitting element layer LDL and the first surface of the first substrate SUB1. In an exemplary embodiment, the light emitting element layer LDL may include a plurality of light emitting elements LD coupled to circuit elements and / or lines of the circuit element layer BPL through contact holes, etc. For example, the light emitting element layer LDL may include a plurality of light emitting elements LD, at least one of which is disposed in each pixel region PXA.

[0111] In other words, in an exemplary embodiment, each pixel PXL may include a circuit element disposed on the circuit element layer BPL of each pixel area PXA and at least one light emitting element LD disposed on the light emitting element layer LDL above the circuit element layer BPL. The structure of the pixel PXL will be described in detail later.

[0112] The first passivation layer PTL1 may be disposed on the light emitting element layer LDL to cover at least the display area DA. In an exemplary embodiment, the first passivation layer PTL1 may include a sealing member such as a thin film encapsulation (TFE) layer or an encapsulation substrate, and may include a passivation film or the like in addition to the sealing member.

[0113] The first adhesive layer ADL1 may be disposed between the first passivation layer PTL1 and the window WIN to combine the first passivation layer PTL1 with the window WIN. In an exemplary embodiment, the first adhesive layer ADL1 may include a transparent adhesive such as an optically clear adhesive (OCA), and may include various adhesive materials other than the transparent adhesive.

[0114] The window WIN may be a protective member disposed on the uppermost surface of a module including the display device 100 having the display panel 110, and may be a substantially transparent light-transmitting substrate. The window WIN may include a rigid or flexible substrate, and a constituent material of the window WIN is not limited to a specific material.

[0115] The second passivation layer PTL2 may be disposed on the second surface of the first substrate SUB1. In exemplary embodiments, the second passivation layer PTL2 may include at least one film layer such as a passivation film layer.

[0116] The second adhesive layer ADL2 may be disposed between the second passivation layer PTL2 and the photo sensor array layer PSL to combine the second passivation layer PTL2 with the photo sensor array layer PSL. In an exemplary embodiment, the second adhesive layer ADL2 may include a transparent adhesive such as OCA, and may include various adhesive materials other than the transparent adhesive.

[0117] The light sensor array layer PSL may be attached to the rear surface of the display panel 110 such that the light sensor array layer PSL overlaps at least a portion of the display panel 110. For example, the light sensor array layer PSL may be disposed to overlap the display panel 110 at least in the sensing area SA. The light sensor array layer PSL may include a plurality of light sensors PHS distributed at a predetermined resolution and / or pitch.

[0118] The pinhole array layer PHL may be disposed between the light emitting element layer LDL and the light sensor array layer PSL in the sensing area SA. For example, the pinhole array layer PHL may be disposed on the first surface of the first substrate SUB1 such that the pinhole array layer PHL is located between the first substrate SUB1 and the circuit element layer BPL. The pinhole array layer PHL may selectively transmit light (referred to as "reflected light") reflected by an object (e.g., a user's fingerprint) placed on a module including the display device 100.

[0119] The pinhole PIH may also be an optical hole, and each pinhole PIH may be a light-transmitting hole. For example, on the path along which light passes vertically or obliquely through the display panel 110 and enters the reflective optical sensor PHS, light-transmitting holes having the smallest size (area) among light-transmitting holes formed in various layers of the display device 100 so that the light-transmitting holes overlap each other may form each pinhole PIH.

[0120] In an exemplary embodiment, the display panel 110 may be transparent in an area of ​​the display panel 110 where the pinhole PIH is disposed, to allow reflected light reflected by a fingerprint area of ​​a finger, etc., to pass through the corresponding pinhole PIH. In addition, in order to reduce the loss of reflected light required for fingerprint sensing, the display panel 110 may be configured to allow light satisfying a field of view (FOV, also referred to as "viewing angle") within a predetermined angle range to pass through the corresponding pinhole PIH.

[0121] For example, the display panel 110 may be transparent in a region of the display panel 110, each of which is formed centered on a corresponding pinhole PIH, has an area larger than that of the pinhole PIH, and overlaps with the pinhole PIH. Hereinafter, a region that is transparent to allow light to pass therethrough will be referred to as an "optical opening area (OPA)".

[0122] For example, when θ represents the angle of FOV having a desired range based on the center of each pinhole PIH, q represents the thickness of the circuit element layer BPL, and 2p represents the width of the optical opening area OPA to be formed in the interface between the circuit element layer BPL and the light emitting element layer LDL, the equation 2p=2*(q*tanθ) may be satisfied. In an exemplary embodiment, the angle of FOV may be approximately in the range of 30° to 60°, for example, 45°, but is not limited thereto.

[0123] In addition, each pinhole PIH may have a predetermined width w, for example, a width w in the range of 4 μm to 15 μm. Considering the width w of the pinhole PIH, the width of the optical opening area OPA to be formed in the interface between the first passivation layer PTL1 and the light emitting element layer LDL may be 2p+w. In this way, the width of the optical opening area OPA to be formed in each layer of the display device 100 may be gradually increased in a direction away from the pinhole array layer PHL (ie, upward and downward from the pinhole array layer PHL).

[0124] The width (or diameter) w of each pinhole PIH can be set to about 10 times or more (for example, to about 4 μm or 5 μm or more) the wavelength of the reflected light with respect to each direction (for example, each of the horizontal and vertical directions) to prevent light diffraction. In addition, the width w of each pinhole PIH can be set to a size suitable for preventing image blur and more clearly sensing the shape of the fingerprint. For example, the width w of each pinhole PIH can be set to about 15 μm or less. However, the present disclosure is not limited thereto, and the width w of each pinhole PIH can be changed according to the wavelength bandwidth of the reflected light and / or the thickness of each layer of the module.

[0125] For example, the pitch between adjacent pinholes PIH may be determined in consideration of the distance between the pinhole array layer PHL and the light sensor array layer PSL and the wavelength range of the reflected light. For example, when the angle of the FOV of the reflected light intended to be obtained is approximately 45°, the distance between adjacent pinholes PIH may be set to be more than twice the distance between the pinhole array layer PHL and the light sensor array layer PSL, and may be set to be greater than a value obtained by adding a predetermined error range to the distance. In this case, images sensed by the individual light sensors PHS may be prevented from overlapping each other, thereby preventing image blur. For example, the pinholes PIH may be distributed in the sensing area SA at a resolution lower than that of the pixel PXL.

[0126] In addition, the shape of the fingerprint can be detected by synthesizing images obtained from a plurality of light sensors PHS. To this end, the distance between the light sensors PHS can be set to a predetermined value so that the light sensors PHS are dense so that the reflected light reflected from the object (e.g., a specific area of ​​the finger such as the fingerprint area) can be incident on at least two adjacent light sensors PHS. For example, the light sensors PHS may have a width and / or pitch smaller than the width and / or pitch of the pinholes PIH, and may be distributed in the sensing area SA with a resolution higher than the resolution of the pinholes PIH. For example, the light sensors PHS may be distributed in the sensing area SA with a small pitch corresponding to approximately 1 / 10 to 1 / 100 of the pitch of the pinholes PIH, and may be densely arranged in the sensing area SA with a resolution higher than the resolution of the pixels PXL. For example, the light sensors PHS may be arranged at a pitch of 50 μm in each of the horizontal and vertical directions, and the pinholes PIH may be arranged at a pitch of 450 μm in each of the horizontal and vertical directions.

[0127] The display device 100 according to the above-described embodiment may include a fingerprint sensor including a light emitting element layer LDL, a light sensor array layer PSL, and a pinhole array layer PHL. In detail, the fingerprint sensor according to the exemplary embodiment of the present disclosure may include a light emitting element layer LDL, a light sensor array layer PSL, and a pinhole array layer PHL. The light emitting element layer LDL may include a light emitting element LD that may also be used as a light source of a light sensing type sensor. The light sensor array layer PSL may include a light sensor PHS that receives reflected light emitted from the light emitting element layer LDL and reflected from an object (e.g., a fingerprint area of ​​a finger) placed on the display device 100. The pinhole array layer PHL may be disposed between the light emitting element layer LDL and the light sensor array layer PSL, and may include a pinhole PIH formed to selectively transmit the reflected light.

[0128] In an exemplary embodiment, the fingerprint sensor may further include an optical opening area OPA formed in the display panel 110, etc. to prevent the loss of reflected light incident into each pinhole PIH within a predetermined angle range of the FOV. In addition, the fingerprint sensor may selectively include a separate light control layer disposed in the display panel 110 and / or at least one surface of the display panel 110 to more easily control the FOV.

[0129] In an exemplary embodiment, each photosensor PHS may have a size smaller than that of each pixel PXL or each pinhole PIH. The photosensors PHS may be densely distributed in the sensing area SA with a resolution higher than that of the pixels PXL or the pinholes PIH. For example, the photosensors PHS may be distributed in the sensing area SA at a pitch of approximately 50 μm in each of the horizontal and vertical directions, and the pinholes PIH may be distributed in the sensing area SA at a pitch of approximately 450 μm in each of the horizontal and vertical directions. In this case, the photosensors PHS may be densely arranged in the sensing area SA without aligning the photosensors PHS with the pixels PXL and / or the pinholes PIH one-to-one. Therefore, regardless of whether the photosensors PHS are aligned with the pixels PXL and / or the pinholes PIH, the ripple effect may be prevented or minimized.

[0130] In other words, in an exemplary embodiment, the moire effect that may occur in a light sensing type fingerprint sensor can be prevented or reduced by adjusting the resolution of the pinhole array layer PHL and the light sensor array layer PSL, for example, so that there is a large difference in resolution between the pinhole array layer PHL and the light sensor array layer PSL, enough to eliminate the need for alignment. Therefore, the fingerprint information can be prevented from being distorted due to the moire effect, and the reliability of the fingerprint sensor can be improved.

[0131] In the fingerprint sensor and the display device 100 including the fingerprint sensor according to the exemplary embodiment of the present disclosure, the light emitting element LD of the pixel PXL may also be used as the light source of the fingerprint sensor. However, the present disclosure is not limited thereto. For example, in the exemplary embodiment, the fingerprint sensor and the display device including the fingerprint sensor may further include a separate light source for fingerprint sensing.

[0132] A fingerprint sensing method of a fingerprint sensor and a display device 100 including the fingerprint sensor according to an exemplary embodiment of the present disclosure will be briefly described. During a fingerprint sensing period in which the light sensor PHS is activated, a pixel PXL of a sensing area SA (specifically, a light emitting element LD disposed in the pixel PXL) may emit light when a user's finger (e.g., fingerprint area) is in contact with the sensing area SA or is positioned adjacent to the sensing area SA. For example, during the fingerprint sensing period, all pixels PXL of the sensing area SA may emit light simultaneously or sequentially. For example, in an exemplary embodiment, among the pixels PXL of the sensing area SA, only some pixels PXL separated by a predetermined interval or selected some pixels PXL that emit light of a specific color (e.g., short-wavelength light such as blue light) may emit light, thereby serving as a light source for fingerprint sensing.

[0133] Then, some of the light emitted from the pixel PXL may be reflected by the user's finger and may be incident on the light sensor PHS via the pinhole PIH and the optical opening area OPA formed in each layer of the display device 100. Here, the difference in light intensity and / or waveform between the reflected light reflected by the ridges and valleys of the fingerprint may be detected, thereby detecting the user's fingerprint shape (fingerprint pattern).

[0134] Reference Figure 7 , the display panel 110 may further include a second substrate SUB2 disposed on a second surface of the first substrate SUB1. For example, the second substrate SUB2 of the display panel 110 may be disposed between the first substrate SUB1 and the light sensor array layer PSL. The pinhole array layer PHL may be disposed between the first substrate SUB1 and the second substrate SUB2. Figure 7 In the description of the embodiments of the present invention and the remaining drawings, a detailed description of a configuration similar to or the same as that of at least one of the above-described embodiments will be omitted.

[0135] In an exemplary embodiment, the second substrate SUB2 may be made of a material that is the same as or different from that of the first substrate SUB1. For example, each of the first substrate SUB1 and the second substrate SUB2 may be a thin film substrate made of polyimide (PI). In an exemplary embodiment, each of the first substrate SUB1 and the second substrate SUB2 may be a mixed substrate including different materials. The second substrate SUB2 may include at least one of the above-mentioned materials as the constituent materials of the first substrate SUB1. In addition, the second substrate SUB2 may be made of various other materials.

[0136] Reference Fig. 8A , Figure 8B , Figure 8C and Fig.8D The circuit element layer BPL may include a light-transmitting hole array layer LTHL having at least one layer structure and disposed in the sensing area SA. Fig. 8A As shown in , the circuit element layer BPL may include a first light-transmitting hole array layer LTHL1 having a plurality of first light-transmitting holes LTH1 distributed in the circuit element layer BPL. Each first light-transmitting hole LTH1 may form a pinhole PIH of the fingerprint sensor. In other words, in an exemplary embodiment, the first light-transmitting hole array layer LTHL1 of the circuit element layer BPL may form a pinhole array layer PHL of the fingerprint sensor.

[0137] In an exemplary embodiment, the circuit element layer BPL may include a plurality of light-transmitting hole array layers LTHL. Figure 8B , Figure 8C and Fig.8D As shown in , the circuit element layer BPL may include a first light-transmitting hole array layer LTHL1 and a second light-transmitting hole array layer LTHL2 disposed in the circuit element layer BPL and overlapping each other. In an exemplary embodiment, the first light-transmitting hole array layer LTHL1 may include a plurality of first light-transmitting holes LTH1 distributed in a first layer (e.g., a first conductive layer) of the circuit element layer BPL. The second light-transmitting hole array layer LTHL2 may include a plurality of second light-transmitting holes LTH2 distributed in a second layer (e.g., a second conductive layer) of the circuit element layer BPL, such that the second light-transmitting holes LTH2 overlap with the first light-transmitting holes LTH1.

[0138] In an exemplary embodiment, each pair of the first light transmission holes LTH1 and the second light transmission holes LTH2 corresponding to each other may have the same size or different sizes. Figure 8BAs shown in , each pair of first light-transmitting holes LTH1 and second light-transmitting holes LTH2 may have substantially the same width and / or area and may be arranged to overlap each other. In an exemplary embodiment, a pair of first light-transmitting holes LTH1 and second light-transmitting holes LTH2 may form a pinhole PIH having a multi-layer structure. For example, each first light-transmitting hole LTH1 may form a first pinhole PIH1 formed in a first layer of a circuit element layer BPL. Each second light-transmitting hole LTH2 may form a second pinhole PIH2 formed in a second layer of the circuit element layer BPL. Each pair of first light-transmitting holes LTH1 and second light-transmitting holes LTH2 having the same size and overlapping each other may form a single pinhole PIH having a multi-layer structure. In this case, a first light-transmitting hole array layer LTHL1 including a first light-transmitting hole LTH1 and a second light-transmitting hole array layer LTHL2 including a second light-transmitting hole LTH2 may form a pinhole array layer PHL having a multi-layer structure.

[0139] For example, Figure 8C and Fig.8D As shown in , each pair of the first light transmission hole LTH1 and the second light transmission hole LTH2 may have different widths and / or areas, and may be arranged to overlap each other, thereby forming a pinhole unit PIHU. Figure 8C As shown in , each first light-transmitting hole LTH1 may have a width and / or area smaller than that of the corresponding second light-transmitting hole LTH2, and form a pinhole PIH. Each second light-transmitting hole LTH2 may form a light control hole LCH, which controls the path of the light passing through the corresponding first light-transmitting hole LTH1 (for example, limits the FOV of the reflected light to a predetermined angle range). In this case, the first light-transmitting hole array layer LTHL1 may form a pinhole array layer PHL, and the second light-transmitting hole array layer LTHL2 may form a light control layer LBL. For example, as Fig.8D As shown in , each first light-transmitting hole LTH1 may have a width and / or area greater than that of the corresponding second light-transmitting hole LTH2, and form a light control hole LCH. Each second light-transmitting hole LTH2 may form a pinhole PIH. In this case, the first light-transmitting hole array layer LTHL1 may form a light control layer LBL, and the second light-transmitting hole array layer LTHL2 may form a pinhole array layer PHL.

[0140] In an exemplary embodiment, the first light transmission holes LTH1 and the second light transmission holes LTH2 may be uniformly distributed in the sensing area SA with a resolution lower than that of the pixel PXL and the light sensor PHS. In this case, the light sensor PHS may have a width and a pitch smaller than those of the first light transmission holes LTH1 and the second light transmission holes LTH2, and may be distributed in the sensing area SA with a resolution higher than that of the first light transmission holes LTH1 and the second light transmission holes LTH2.

[0141] according to Fig. 8A , Figure 8B , Figure 8C and Fig.8D The display device 100 of each exemplary embodiment may include a fingerprint sensor having a first light-transmitting hole array layer LTHL1 integrated with a circuit element layer BPL. In detail, the fingerprint sensor according to the exemplary embodiments of the present disclosure may include: a first substrate SUB1; a circuit element layer BPL and a light-emitting element layer LDL, which are sequentially disposed on a first surface of the first substrate SUB1; a light sensor array layer PSL, which is disposed on a second surface of the first substrate SUB1; and a light-transmitting hole array layer LTHL (having, for example, at least one layer structure including a first light-transmitting hole array layer LTHL1), which is disposed in the circuit element layer BPL, overlapped with the light sensor array layer PSL, and has a plurality of first light-transmitting holes LTH1 distributed in the circuit element layer BPL.

[0142] In an exemplary embodiment, the light-transmitting hole array layer LTHL having at least one layer structure can be formed integrally with the circuit element layer BPL using an opaque pattern (e.g., an opaque pattern such as a metal electrode or metal line disposed on the first gate layer, the second gate layer, and / or the source-drain layer) as a mask without using a separate mask layer through an additional process, and the opaque pattern is disposed on at least one conductive layer (e.g., a semiconductor layer, a first gate layer, a second gate layer, and / or a source-drain layer) of various circuit elements and / or lines disposed to form the circuit element layer BPL. In this case, no additional process is required to form the light-transmitting hole array layer LTHL. Therefore, the thickness of the display device 100 including the light-sensing fingerprint sensor can be reduced, the production cost of the display device 100 can be reduced, and the process efficiency can be improved.

[0143] Reference Fig. 9, the circuit element layer BPL may include a first light-transmitting hole array layer LTHL1 having a plurality of first light-transmitting holes LTH1. A second light-transmitting hole array layer LTHL2 overlapping the first light-transmitting hole array layer LTHL1 may be disposed between the first substrate SUB1 and the circuit element layer BPL. In an exemplary embodiment, the second light-transmitting hole array layer LTHL2 may have a plurality of second light-transmitting holes LTH2 overlapping the respective first light-transmitting holes LTH1. Each second light-transmitting hole LTH2 may have a width different from that of each first light-transmitting hole LTH1. For example, the width of each second light-transmitting hole LTH2 may be smaller than the width of the corresponding first light-transmitting hole LTH1 overlapping the second light-transmitting hole LTH2. In this case, each pair of the first light-transmitting hole LTH1 and the second light-transmitting hole LTH2 may form a pinhole unit PIHU. In addition, the first light-transmitting hole array layer LTHL1 may form a light control layer LBL, and the second light-transmitting hole array layer LTHL2 may form a pinhole array layer PHL.

[0144] Reference Fig.10 In the circuit element layer BPL, each second light-transmitting hole LTH2 may have a width greater than a width of a corresponding first light-transmitting hole LTH1 overlapped with the second light-transmitting hole LTH2. In this case, the first light-transmitting hole array layer LTHL1 may form a pinhole array layer PHL, and the second light-transmitting hole array layer LTHL2 may form a light-controlling layer LBL.

[0145] Reference Fig.11 , the circuit element layer BPL may include a first light-transmitting hole array layer LTHL1 forming the pinhole array layer PHL. The display device 100 may further include a third light-transmitting hole array layer LTHL3 disposed between the first substrate SUB1 and the second substrate SUB2 and overlapping the first light-transmitting hole array layer LTHL1. The third light-transmitting hole array layer LTHL3 may include a plurality of third light-transmitting holes LTH3 overlapping the respective first light-transmitting holes LTH1.

[0146] For example, each third light-transmitting hole LTH3 may have a size larger than that of each first light-transmitting hole LTH1, and may form a light control hole LCH. In this case, the third light-transmitting hole array layer LTHL3 may form a light control layer LBL. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, each third light-transmitting hole LTH3 may have a size smaller than that of each first light-transmitting hole LTH1, and may form a pinhole PIH. In this case, the third light-transmitting hole array layer LTHL3 may form a pinhole array layer PHL.

[0147] Reference Fig.12, the circuit element layer BPL may include a first light-transmitting hole array layer LTHL1 forming a pinhole array layer PHL. A second light-transmitting hole array layer LTHL2 and a third light-transmitting hole array layer LTHL3 forming a first light control layer LBL1 and a second light control layer LBL2, respectively, may be disposed on respective opposite surfaces of the first substrate SUB1. In this case, each group of the first light-transmitting holes LTH1, the second light-transmitting holes LTH2, and the third light-transmitting holes LTH3 stacked on each other may form a pinhole unit PIHU.

[0148] As described above, the fingerprint sensor and the display device 100 according to the exemplary embodiment of the present disclosure may include a light-transmitting hole array layer LTHL having at least one layer structure including a pinhole array layer PHL. The number, structure and / or position of the light-transmitting hole array layer LTHL may be changed in various ways.

[0149] In an exemplary embodiment, each light sensor PHS may have a smaller size than the size of each pixel PXL, each pinhole PIH, and / or each light control hole LCH. The light sensors PHS may be densely distributed in the sensing area SA at a resolution higher than the resolution of the pixels PXL and the optical system (e.g., the pinholes PIH and the light control holes LCH). For example, the light sensors PHS may be distributed in the sensing area SA at a pitch of approximately 50 μm in each of the horizontal and vertical directions. The pinholes PIH and / or the light control holes LCH may be distributed in the sensing area SA at a pitch of approximately 450 μm in each of the horizontal and vertical directions, and the pitch and / or width of each of the pinholes PIH and / or the light control holes LCH may be greater than the pitch and / or width of each of the light sensors PHS. In this case, the light sensors PHS may be densely arranged in the sensing area SA without aligning the light sensors PHS with the pixels PXL, the pinholes PIH, and / or the light control holes LCH one-to-one. Therefore, regardless of whether the light sensor PHS is aligned with the pixel PXL, the pinhole PIH, and / or the light control hole LCH, the occurrence of the moire effect of the fingerprint sensor can be prevented or minimized.

[0150] In other words, in an exemplary embodiment, the moire effect that may occur in a light sensing type fingerprint sensor can be prevented or reduced by adjusting the resolution of the pinhole array layer PHL, the light control layer LBL, and / or the light sensor array layer PSL that overlaps the pinhole array layer PHL and the light control layer LBL, for example, so that there is a large difference in resolution between them, enough to make alignment unnecessary. Therefore, the fingerprint information can be prevented from being distorted due to the moire effect, and the reliability of the fingerprint sensor can be improved.

[0151] Although Figure 6 , Figure 7, Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 9 , Fig.10 , Fig.11 and Fig.12 It is shown that each pinhole PIH and the like are disposed in a boundary region between two pixel regions PXA, but the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, at least one of the first light transmission holes LTH1 forming a corresponding pinhole PIH or a corresponding light control hole LCH may be disposed in a pixel region PXA of any one pixel PXL disposed in the sensing region SA. Detailed embodiments related thereto will be described later herein.

[0152] In an exemplary embodiment, at least one light-transmitting hole array layer LTHL may be supplied with a predetermined voltage. For example, each light blocking mask LBM forming at least one pinhole array layer PHL and / or light control layer LBL may be formed with a conductive layer. The light blocking mask LBM may be electrically connected to a signal line supplied with a predetermined drive signal (e.g., a data signal, a scan signal, or other control signal), or the light blocking mask LBM may be electrically connected to a power supply line supplied with a driving power supply voltage of a predetermined power supply (e.g., a high potential or low potential pixel power supply, a gate-on or gate-off power supply, a bias power supply, a reference power supply, or a ground power supply). For example, a predetermined voltage may be selectively supplied to at least one light-transmitting hole array layer LTHL so that the characteristics of the circuit elements constituting the pixel PXL may be controlled, or changes in the characteristics of the circuit elements may be reduced or compensated. In this case, at least one light-transmitting hole array layer LTHL may form an optical system of a fingerprint sensor, and may also be used for stable driving of a display device.

[0153] Fig.13 is a cross-sectional view comparatively showing the required size of the optical opening area according to the position of the pinhole array layer for various exemplary embodiments. Fig.13 In the description of the exemplary embodiments of the present invention, the same reference numerals will be used to denote the same Figures 6 to 12 For components similar to or identical to those of the exemplary embodiments, a detailed description thereof will be omitted.

[0154] Reference Fig.13, the size (area) of the optical opening area OPA that needs to be formed in each layer of the display panel 110 can be changed according to the position of the pinhole array layer PHL. For example, when the range of the angle (θ) of the FOV for reflecting light is intended to remain the same, the width (2p1, 2p2, 2p3) (or area) of the optical opening area (OPA1, OPA2, OPA3) based on the center of each pinhole PIH that needs to be fixed in the interface between the circuit element layer BPL and the light emitting element layer LDL (hereinafter referred to as the "first interface") will gradually increase as the distance (q1, q2, q3) from the pinhole array layer PHL to the first interface increases. Here, the first electrode of the light emitting element layer LDL (for example, each anode electrode of the pixel PXL) can be set in the first interface. Therefore, as the width (2p1, 2p2, 2p3) of the optical opening area (OPA1, OPA2, OPA3) increases, the area of ​​the area to be prevented from overlapping with the first electrode will increase. However, as the resolution of the display panel 110 increases, the size of the pixel area PXA used to form each pixel PXL decreases, and thus there may be limitations in the design. Therefore, the closer the pinhole array layer PHL is disposed to the pixel circuit layer BPL, the smaller the width (2p1, 2p2, 2p3) of the optical opening area (OPA1, OPA2, OPA3) that needs to be fixed in the first interface. Therefore, even in a high-resolution display device 100, a fingerprint sensor can be more easily formed. For example, in the case where the pinhole array layer PHL is disposed in the pixel circuit layer BPL, the width 2p1 of the optical opening area OPA1 that needs to be fixed in the first interface can be optimized.

[0155] Therefore, in the present disclosure, an optical system of a fingerprint sensor may be formed by providing at least one first light-transmitting hole array layer LTHL1 in the pixel circuit layer BPL. In an exemplary embodiment, the first light-transmitting hole array layer LTHL1 may be a pinhole array layer PHL. However, the present disclosure is not limited to an exemplary embodiment in which the first light-transmitting hole array layer LTHL1 forms a pinhole array layer PHL. As described in the previous embodiment, the first light-transmitting hole array layer LTHL1 may form a light control layer LBL.

[0156] In addition, in an exemplary embodiment of the present disclosure, the first light-transmitting hole array layer LTHL1 may be formed integrally with at least one conductive layer of the circuit element layer BPL. For example, each first light-transmitting hole LTH1 may include at least one opening formed in the at least one conductive layer, and may be formed integrally with the at least one opening. For example, the first light-transmitting hole LTH1 may include a plurality of openings distributed in at least one conductive layer of the circuit element layer BPL, or may be formed by an opening.

[0157] In this case, the first light transmission hole array layer LTHL1 may be formed in the circuit element layer BPL without forming a separate mask layer. Therefore, the thickness of a module including a light sensing type fingerprint sensor and the display device 100 including the fingerprint sensor may be reduced or minimized.

[0158] Fig.14 is a circuit diagram showing a pixel PXL according to an exemplary embodiment of the present disclosure. For illustration purposes, Fig.14 A pixel PXL coupled to both an i-th scan line Si disposed on an i-th horizontal pixel column and a j-th data line Dj disposed on a j-th vertical pixel column is shown.

[0159] Reference Fig.14 According to an exemplary embodiment of the present disclosure, the pixel PXL may include a light emitting element LD, first to seventh transistors T1 to T7, and a storage capacitor Cst. In an exemplary embodiment, the light emitting element LD may be an organic light emitting diode (OLED), but the present disclosure is not limited thereto.

[0160] The anode electrode of the light emitting element LD may be coupled to the first transistor T1 via the sixth transistor T6, and the cathode electrode of the light emitting element LD may be coupled to the second power source ELVSS. The light emitting element LD may emit light having a predetermined brightness corresponding to the current supplied from the first transistor T1. The voltage of the first power source ELVDD may be set to a value higher than the voltage of the second power source ELVSS to allow current to flow to the light emitting element LD.

[0161] The seventh transistor T7 may be coupled between the initialization power supply Vint and the first electrode (e.g., anode electrode) of the light emitting element LD. The gate electrode of the seventh transistor T7 may be coupled to the (i+1)th scan line Si+1. When a scan signal of a gate-on voltage (e.g., a low-level voltage) is supplied to the (i+1)th scan line Si+1, the seventh transistor T7 is turned on so that the voltage of the initialization power supply Vint may be supplied to the anode electrode of the light emitting element LD. The voltage of the initialization power supply Vint may be set to a voltage lower than the voltage of the data signal. In other words, the voltage of the initialization power supply Vint may be set to the minimum voltage of the data signal or less. Although the case where the anode initialization control line coupled to the gate electrode of the seventh transistor T7 is the (i+1)th scan line Si+1 is described by way of example in the present embodiment, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the gate electrode of the seventh transistor T7 may be coupled to the i-th scan line Si. In this case, when the scan signal of the gate-on voltage is supplied to the i-th scan line Si, the voltage of the initialization power source Vint may be supplied to the anode electrode of the light emitting element LD via the seventh transistor T7.

[0162] The sixth transistor T6 is coupled between the first transistor T1 and the light emitting element LD. The gate electrode of the sixth transistor T6 may be coupled to the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal (e.g., a high level voltage) of a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0163] The fifth transistor T5 may be coupled between the first power source ELVDD and the first transistor T1. A gate electrode of the fifth transistor T5 may be coupled to the i-th emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal of a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0164] A first electrode of the first transistor (T1; driving transistor) may be coupled to the first power source ELVDD via the fifth transistor T5, and a second electrode of the first transistor T1 may be coupled to the anode electrode of the light emitting element LD via the sixth transistor T6. A gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may control a current flowing from the first power source ELVDD to the second power source ELVSS via the light emitting element LD in response to a voltage of the first node N1.

[0165] The third transistor T3 may be coupled between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be coupled to the i-th scan line Si. When a scan signal of a gate-on voltage is supplied to the i-th scan line Si, the third transistor T3 may be turned on to electrically connect the second electrode of the first transistor T1 to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0166] The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be coupled to the (i-1)th scan line Si-1. When the scan signal is supplied to the (i-1)th scan line Si-1, the fourth transistor T4 is turned on so that the voltage of the initialization power supply Vint can be supplied to the first node N1. In the present embodiment, the (i-1)th scan line Si-1 may be used as an initialization control line to initialize the gate node (i.e., the first node N1) of the first transistor T1. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, other control lines (e.g., the (i-2)th scan line Si-2) may be used as initialization control lines to initialize the gate node of the first transistor T1.

[0167] The second transistor T2 may be coupled between the jth data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be coupled to the ith scan line Si. When a scan signal is supplied to the ith scan line Si, the second transistor T2 may be turned on so that the first electrode of the first transistor T1 may be electrically coupled to the jth data line Dj.

[0168] The storage capacitor Cst may be coupled between the first power source ELVDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal and the threshold voltage of the first transistor T1.

[0169] The structure of the pixel PXL is not limited to Fig.14 For example, various pixel circuits having known structures may be applied to the pixel PXL.

[0170] Fig.15 It is shown Fig.14 Detailedly, Fig.15 Details show the settings in Figure 1 and Figure 2 An exemplary embodiment of the layout of any pixel PXL in the display area DA is shown, for example, Fig.14 An exemplary embodiment of a layout of a pixel PXL is shown in FIG. Fig.16A and Fig. 16B Along Fig.15 Cross-sectional views taken along the lines II-I' and II-II'.

[0171] In the right Figures 15 to 16B In the description of the exemplary embodiment, for the sake of explanation, the scan line on the (i-1)th row will be referred to as the "(i-1)th scan line Si-1", the scan line on the i-th row will be referred to as the "i-th scan line Si", the scan line on the (i+1)th row will be referred to as the "(i+1)th scan line Si+1", the emission control line on the i-th row will be referred to as the "emission control line Ei", the data line on the j-th column will be referred to as the "data line Dj", and the power line on the j-th column to which the first power supply ELVDD is applied, for example, will be referred to as the "power line PL".

[0172] Reference Fig.15 , Fig.16A and Fig. 16B as well as Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 4 , Figure 5A , Figure 5B, Figure 5C , Figure 5D , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 , the display device 100 may include a pixel PXL disposed in each pixel area PXA of the display area DA and a line unit configured to supply a driving signal and / or power to the pixel PXL. In an exemplary embodiment, the line unit may include scan lines Si-1, Si and Si+1, a data line Dj, an emission control line Ei, a power line PL, and an initialization power line IPL.

[0173] The scan lines Si-1, Si, and Si+1 may extend in the first direction DR1 in the display area DA. In an exemplary embodiment, the scan lines Si-1, Si, and Si+1 may include an (i-1)th scan line Si-1, an i-th scan line Si, and an (i+1)th scan line Si+1 sequentially arranged in a second direction DR2 crossing the first direction DR1. The scan lines Si-1, Si, and Si+1 may receive scan signals. For example, the (i-1)th scan line Si-1 may receive an (i-1)th scan signal, the i-th scan line Si may receive an i-th scan signal, and the (i+1)th scan line Si+1 may receive an (i+1)th scan signal.

[0174] The emission control line Ei may extend in the first direction DR1 in parallel with the scan lines Si-1, Si, and Si+1 in the display area DA. The emission control line Ei may receive an emission control signal.

[0175] The data line Dj may extend in the second direction DR2 in the display area DA. In other words, the data line Dj may extend in a direction crossing the control lines Si-1, Si, Si+1, and Ei including the scan lines Si-1, Si, Si+1, and the emission control line Ei. The data line Dj may receive a data signal.

[0176] The power line PL may extend in the second direction DR2 in the display area DA, but the present disclosure is not limited thereto. The power line PL may be disposed at a position spaced apart from the data line Dj and may receive a first power source ELVDD.

[0177] The initialization power line IPL may extend in the first direction DR1 in the display area DA, but the present disclosure is not limited thereto. The initialization power line IPL may receive an initialization power Vint.

[0178] In an exemplary embodiment, each pixel PXL may include first to seventh transistors T1 to T7 , a storage capacitor Cst, and a light emitting element LD.

[0179] The first transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source electrode SE1 , a first drain electrode DE1 , and a connection line CNL.

[0180] In an exemplary embodiment, the first gate electrode GE1 may be disposed to overlap the first active pattern ACT1, and at least one insulating layer (e.g., a first insulating layer INS1) is interposed between the first gate electrode GE1 and the first active pattern ACT1. The first gate electrode GE1 may be combined with a third drain electrode (DE3; including DE3a and DE3b) of the third transistor T3 and a fourth source electrode (SE4; including SE4a and SE4b) of the fourth transistor T4.

[0181] In an exemplary embodiment, the connection line CNL may couple the first gate electrode GE1, the third drain electrode DE3, and the fourth source electrode SE4 to each other. A first end of the connection line CNL may couple to the first gate electrode GE1 through a first contact hole CH1. A second end of the connection line CNL may couple to the third drain electrode DE3 and the fourth source electrode SE4 through a second contact hole CH2.

[0182] In an exemplary embodiment of the present disclosure, each of the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be formed of an undoped semiconductor pattern or a semiconductor pattern doped with impurities. For example, each of the first source electrode SE1 and the first drain electrode DE1 may be formed of a semiconductor pattern doped with impurities. The first active pattern ACT1 may be formed of an undoped semiconductor pattern.

[0183] In an exemplary embodiment, the first active pattern ACT1 may have a shape extending in a predetermined direction and the first active pattern ACT1 may be bent several times in a longitudinal direction of the first active pattern ACT1. The first active pattern ACT1 may overlap with the first gate electrode GE1 in a plan view. Because the first active pattern ACT1 is relatively long, the channel region of the first transistor T1 may also be relatively long. Therefore, the driving range of the gate voltage to be applied to the first transistor T1 may be increased. Therefore, the grayscale of the light emitted from the light emitting element LD may be accurately controlled.

[0184] In an exemplary embodiment, the first source electrode SE1 may be coupled to a first end of the first active pattern ACT1. The first source electrode SE1 may be coupled to the second drain electrode DE2 of the second transistor T2 and the fifth drain electrode DE5 of the fifth transistor T5. In an exemplary embodiment, the first drain electrode DE1 may be coupled to a second end of the first active pattern ACT1. The first drain electrode DE1 may be coupled to the third source electrode SE3 of the third transistor T3 and the sixth source electrode SE6 of the sixth transistor T6.

[0185] The second transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0186] In an exemplary embodiment, the second gate electrode GE2 may be disposed to overlap the second active pattern ACT2, and at least one insulating layer (e.g., a first insulating layer INS1) is interposed between the second gate electrode GE2 and the second active pattern ACT2. The second gate electrode GE2 may be coupled to the i-th scan line Si. For example, the second gate electrode GE2 may be disposed as a portion of the i-th scan line Si, or may be formed to have a shape protruding from the i-th scan line Si.

[0187] In an exemplary embodiment, each of the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be formed of an undoped semiconductor pattern or a semiconductor pattern doped with impurities. For example, each of the second source electrode SE2 and the second drain electrode DE2 may be formed of a semiconductor pattern doped with impurities. The second active pattern ACT2 may be formed of an undoped semiconductor pattern. The second active pattern ACT2 may correspond to a portion of the second transistor T2 overlapping the second gate electrode GE2.

[0188] In an exemplary embodiment, a first end of the second source electrode SE2 may be coupled to the second active pattern ACT2. A second end of the second source electrode SE2 may be coupled to the data line Dj through the sixth contact hole CH6. In an exemplary embodiment, a first end of the second drain electrode DE2 may be coupled to the second active pattern ACT2. A second end of the second drain electrode DE2 may be coupled to the first source electrode SE1 of the first transistor T1 and the fifth drain electrode DE5 of the fifth transistor T5.

[0189] The third transistor T3 may have a dual-gate structure to prevent leakage current. In other words, the third transistor T3 may include a 3a transistor T3a and a 3b transistor T3b. The 3a transistor T3a may include a 3a gate electrode GE3a, a 3a active pattern ACT3a, a 3a source electrode SE3a, and a 3a drain electrode DE3a. The 3b transistor T3b may include a 3b gate electrode GE3b, a 3b active pattern ACT3b, a 3b source electrode SE3b, and a 3b drain electrode DE3b. As used below, the 3a gate electrode GE3a and the 3b gate electrode GE3b will be referred to as "third gate electrode GE3". The 3a active pattern ACT3a and the 3b active pattern ACT3b will be referred to as "third active pattern ACT3". The 3a source electrode SE3a and the 3b source electrode SE3b will be referred to as "third source electrode SE3". The 3a drain electrode DE3a and the 3b drain electrode DE3b will be referred to as "third drain electrode DE3".

[0190] In an exemplary embodiment, the third gate electrode GE3 may be disposed to overlap the third active pattern ACT3, and at least one insulating layer (e.g., the first insulating layer INS1) is interposed between the third gate electrode GE3 and the third active pattern ACT3. The third gate electrode GE3 may be coupled to the i-th scan line Si. For example, the third gate electrode GE3 may be disposed as a portion of the i-th scan line Si, or may be formed to have a shape protruding from the i-th scan line Si. For example, the 3b gate electrode GE3b may have a shape protruding from the i-th scan line Si, and the 3a gate electrode GE3a may be formed as a portion of the i-th scan line Si.

[0191] In an exemplary embodiment, each of the third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be formed of an undoped semiconductor pattern or a semiconductor pattern doped with impurities. For example, each of the third source electrode SE3 and the third drain electrode DE3 may be formed of a semiconductor pattern doped with impurities. The third active pattern ACT3 may be formed of an undoped semiconductor pattern. The third active pattern ACT3 may correspond to a portion of the third transistor T3 overlapping the third gate electrode GE3.

[0192] In an exemplary embodiment, a first end of the third source electrode SE3 may be coupled to the third active pattern ACT3. A second end of the third source electrode SE3 may be coupled to the first drain electrode DE1 of the first transistor T1 and the sixth source electrode SE6 of the sixth transistor T6. In an exemplary embodiment, a first end of the third drain electrode DE3 may be coupled to the third active pattern ACT3. A second end of the third drain electrode DE3 may be coupled to the fourth source electrode SE4 of the fourth transistor T4. The third drain electrode DE3 may be coupled to the first gate electrode GE1 of the first transistor T1 through the connection line CNL, the second contact hole CH2, and the first contact hole CH1.

[0193] The fourth transistor T4 may have a dual-gate structure to prevent leakage current. In other words, the fourth transistor T4 may include a 4a transistor T4a and a 4b transistor T4b. The 4a transistor T4a may include a 4a gate electrode GE4a, a 4a active pattern ACT4a, a 4a source electrode SE4a, and a 4a drain electrode DE4a. The 4b transistor T4b may include a 4b gate electrode GE4b, a 4b active pattern ACT4b, a 4b source electrode SE4b, and a 4b drain electrode DE4b. As used below, the 4a gate electrode GE4a and the 4b gate electrode GE4b will be referred to as "fourth gate electrode GE4". The 4a active pattern ACT4a and the 4b active pattern ACT4b will be referred to as "fourth active pattern ACT4". The 4a source electrode SE4a and the 4b source electrode SE4b will be referred to as "fourth source electrode SE4". The 4a drain electrode DE4a and the 4b drain electrode DE4b will be referred to as "fourth drain electrode DE4".

[0194] In an exemplary embodiment, the fourth gate electrode GE4 may be disposed to overlap with the fourth active pattern ACT4, and at least one insulating layer (e.g., a first insulating layer INS1) is disposed between the fourth gate electrode GE4 and the fourth active pattern ACT4. The fourth gate electrode GE4 may be coupled to the (i-1)th scan line Si-1. For example, the fourth gate electrode GE4 may be disposed as a portion of the (i-1)th scan line Si-1, or may be formed to have a shape protruding from the (i-1)th scan line Si-1. For example, the 4a gate electrode GE4a may be disposed as a portion of the (i-1)th scan line Si-1. The 4b gate electrode GE4b may have a shape protruding from the (i-1)th scan line Si-1.

[0195] In an exemplary embodiment, each of the fourth active pattern ACT4, the fourth source electrode SE4, and the fourth drain electrode DE4 may be formed of an undoped semiconductor pattern or a semiconductor pattern doped with impurities. For example, each of the fourth source electrode SE4 and the fourth drain electrode DE4 may be formed of a semiconductor pattern doped with impurities. The fourth active pattern ACT4 may be formed of an undoped semiconductor pattern. The fourth active pattern ACT4 may correspond to a portion of the fourth transistor T4 overlapping the fourth gate electrode GE4.

[0196] In an exemplary embodiment, a first end of the fourth source electrode SE4 may be coupled to the fourth active pattern ACT4. A second end of the fourth source electrode SE4 may be coupled to the third drain electrode DE3 of the third transistor T3. In an exemplary embodiment, a first end of the fourth drain electrode DE4 may be coupled to the fourth active pattern ACT4. A second end of the fourth drain electrode DE4 may be coupled to both the initialization power line IPL of the pixel PXL on the (i-1)th row and the seventh drain electrode DE7 of the seventh transistor T7 of the pixel PXL on the (i-1)th row.

[0197] The fourth source electrode SE4 may be coupled to the first gate electrode GE1 of the first transistor T1 through the connection line CNL, the second contact hole CH2, and the first contact hole CH1. The auxiliary connection line AUX may be disposed between the fourth drain electrode DE4 and the initialization power line IPL. The first end of the auxiliary connection line AUX may be coupled to the fourth drain electrode DE4 through the ninth contact hole CH9. The second end of the auxiliary connection line AUX may be coupled to the initialization power line IPL on the (i-1)th row through the eighth contact hole CH8 of the pixel PXL on the (i-1)th row.

[0198] The fifth transistor T5 may include a fifth gate electrode GE5 , a fifth active pattern ACT5 , a fifth source electrode SE5 , and a fifth drain electrode DE5 .

[0199] In an exemplary embodiment, the fifth gate electrode GE5 may be disposed to overlap the fifth active pattern ACT5, and at least one insulating layer (e.g., a first insulating layer INS1) is interposed between the fifth gate electrode GE5 and the fifth active pattern ACT5. The fifth gate electrode GE5 may be coupled to the emission control line Ei. The fifth gate electrode GE5 may be disposed as a portion of the emission control line Ei, or be formed to have a shape protruding from the emission control line Ei.

[0200] In an exemplary embodiment, each of the fifth active pattern ACT5, the fifth source electrode SE5, and the fifth drain electrode DE5 may be formed of an undoped semiconductor pattern or a semiconductor pattern doped with impurities. For example, each of the fifth source electrode SE5 and the fifth drain electrode DE5 may be formed of a semiconductor pattern doped with impurities. The fifth active pattern ACT5 may be formed of an undoped semiconductor pattern. The fifth active pattern ACT5 may correspond to a portion of the fifth transistor T5 overlapping the fifth gate electrode GE5.

[0201] In an exemplary embodiment, a first end of the fifth source electrode SE5 may be coupled to the fifth active pattern ACT5. A second end of the fifth source electrode SE5 may be coupled to the power line PL through the fifth contact hole CH5. In an exemplary embodiment, a first end of the fifth drain electrode DE5 may be coupled to the fifth active pattern ACT5. A second end of the fifth drain electrode DE5 may be coupled to the first source electrode SE1 of the first transistor T1 and the second drain electrode DE2 of the second transistor T2.

[0202] The sixth transistor T6 may include a sixth gate electrode GE6 , a sixth active pattern ACT6 , a sixth source electrode SE6 , and a sixth drain electrode DE6 .

[0203] In an exemplary embodiment, the sixth gate electrode GE6 may be disposed to overlap the sixth active pattern ACT6, and at least one insulating layer (e.g., a first insulating layer INS1) is interposed between the sixth gate electrode GE6 and the sixth active pattern ACT6. The sixth gate electrode GE6 may be coupled to the emission control line Ei. For example, the sixth gate electrode GE6 may be disposed as a portion of the emission control line Ei, or may be formed to have a shape protruding from the emission control line Ei.

[0204] In an exemplary embodiment, each of the sixth active pattern ACT6, the sixth source electrode SE6, and the sixth drain electrode DE6 may be formed of an undoped semiconductor pattern or a semiconductor pattern doped with impurities. For example, each of the sixth source electrode SE6 and the sixth drain electrode DE6 may be formed of a semiconductor pattern doped with impurities. The sixth active pattern ACT6 may be formed of an undoped semiconductor pattern. The sixth active pattern ACT6 may correspond to a portion of the sixth transistor T6 overlapping the sixth gate electrode GE6.

[0205] In an exemplary embodiment, a first end of the sixth source electrode SE6 may be coupled to the sixth active pattern ACT6. A second end of the sixth source electrode SE6 may be coupled to the first drain electrode DE1 of the first transistor T1 and the third source electrode SE3 of the third transistor T3. In an exemplary embodiment, a first end of the sixth drain electrode DE6 may be coupled to the sixth active pattern ACT6. A second end of the sixth drain electrode DE6 may be coupled to the seventh source electrode SE7 of the seventh transistor T7.

[0206] The seventh transistor T7 may include a seventh gate electrode GE7 , a seventh active pattern ACT7 , a seventh source electrode SE7 , and a seventh drain electrode DE7 .

[0207] In an exemplary embodiment, the seventh gate electrode GE7 may be disposed to overlap the seventh active pattern ACT7, and at least one insulating layer (e.g., a first insulating layer INS1) is interposed between the seventh gate electrode GE7 and the seventh active pattern ACT7. The seventh gate electrode GE7 may be coupled to the (i+1)th scan line Si+1. For example, the seventh gate electrode GE7 may be disposed as a portion of the (i+1)th scan line Si+1, or may be formed to have a shape protruding from the (i+1)th scan line Si+1.

[0208] In an exemplary embodiment, each of the seventh active pattern ACT7, the seventh source electrode SE7, and the seventh drain electrode DE7 may be formed of an undoped semiconductor pattern or a semiconductor pattern doped with impurities. For example, each of the seventh source electrode SE7 and the seventh drain electrode DE7 may be formed of a semiconductor pattern doped with impurities. The seventh active pattern ACT7 may be formed of an undoped semiconductor pattern. The seventh active pattern ACT7 may correspond to a portion of the seventh transistor T7 overlapping the seventh gate electrode GE7.

[0209] In an exemplary embodiment, a first end of the seventh source electrode SE7 may be coupled to the seventh active pattern ACT7. A second end of the seventh source electrode SE7 may be coupled to the sixth drain electrode DE6 of the sixth transistor T6. In an exemplary embodiment, a first end of the seventh drain electrode DE7 may be coupled to the seventh active pattern ACT7. A second end of the seventh drain electrode DE7 may be coupled to the initialization power line IPL.

[0210] The storage capacitor Cst may include a first capacitor electrode LE and a second capacitor electrode UE. In an exemplary embodiment, the first capacitor electrode LE may be a lower electrode of the storage capacitor Cst and may be formed integrally with the first gate electrode GE1 of the first transistor T1. In an exemplary embodiment, the second capacitor electrode UE may be an upper electrode of the storage capacitor Cst and may overlap with the first gate electrode GE1. In a plan view, the second capacitor electrode UE may cover at least a portion of the first capacitor electrode LE. The capacitance of the storage capacitor Cst may be increased by increasing the area of ​​the overlapping portion between the first capacitor electrode LE and the second capacitor electrode UE.

[0211] In an exemplary embodiment, the second capacitor electrode UE may extend in the first direction DR1. In an exemplary embodiment of the present disclosure, a voltage having the same level as that of the first power source ELVDD may be applied to the second capacitor electrode UE. The second capacitor electrode UE may have an opening OPN in a region having a first contact hole CH1 through which the first gate electrode GE1 contacts the connection line CNL.

[0212] The light emitting element LD may include a first electrode (e.g., an anode electrode) AD, a second electrode (e.g., a cathode electrode) CD, and an emission layer EML disposed between the first electrode AD and the second electrode CD. In an exemplary embodiment, the first electrode AD and the second electrode CD may be disposed to overlap each other in an emission region defined in each pixel region PXA of the light emitting element layer LDL. The emission layer EML may be disposed in the emission region. In other words, the emission region of each pixel PXL may be a region where the first electrode AD, the emission layer EML, and the second electrode CD of the light emitting element LD overlap each other.

[0213] The first electrode AD may be disposed in a predetermined emission region corresponding to each pixel PXL of the pixel area PXA. The first electrode AD may be coupled to the seventh source electrode SE7 of the seventh transistor T7 and the sixth drain electrode DE6 of the sixth transistor T6 through the seventh contact hole CH7 and the tenth contact hole CH10. The bridge pattern BRP may be disposed between the seventh contact hole CH7 and the tenth contact hole CH10. The bridge pattern BRP may couple the sixth drain electrode DE6, the seventh source electrode SE7, and the first electrode AD to each other.

[0214] Hereinafter, a stack structure (cross-sectional structure) of a pixel PXL and a display area DA including the pixel PXL according to an exemplary embodiment of the present disclosure will be described.

[0215] The semiconductor layer may be disposed on the first surface of the first substrate SUB1. In exemplary embodiments, a buffer layer BFL may be disposed between the first substrate SUB1 and the semiconductor layer.

[0216] In an exemplary embodiment, active patterns ACT1 to ACT7 (hereinafter, referred to as "ACT") may be provided in a semiconductor layer. In an exemplary embodiment, the active patterns ACT may include first to seventh active patterns ACT1 to ACT7. The first to seventh active patterns ACT1 to ACT7 may be formed of a semiconductor material.

[0217] The first insulating layer INS1 may be disposed on the first substrate SUB1 provided with the first to seventh active patterns ACT1 to ACT7. In an exemplary embodiment, the first insulating layer INS1 may be a gate insulating layer disposed between the active patterns ACT1 to ACT7 of the transistors T1 to T7 disposed in the pixel PXL and the gate electrodes GE1 to GE7. In an exemplary embodiment, the first insulating layer INS1 may include at least one inorganic layer and / or organic layer. For example, the first insulating layer INS1 may be made of a layer including SiO x or SiN x For example, the first insulating layer INS1 may include an inorganic layer such as SiO x 、SiN x , SiON, SiOF or AlO x of an inorganic insulating material or an organic insulating material, and may have a single-layer or multi-layer structure including at least one of the foregoing materials.

[0218] In an exemplary embodiment of the present disclosure, the first insulating layer INS1 may have a thickness defined within a predetermined range to allow the transistors T1 to T7 to be easily driven. For example, the first insulating layer INS1 may have a thickness of to The thickness is within the range of (e.g., approximately ), but the thickness of the first insulating layer INS1 is not limited thereto.

[0219] The first conductive layer may be disposed on the first insulating layer INS1. In an exemplary embodiment, the first conductive layer may be a first gate layer. The control lines Si-1, Si, Si+1, and Ei and the gate electrodes GE1 to GE7 may be disposed in the first conductive layer. In an exemplary embodiment, the electrode (e.g., the first capacitor electrode LE) of the storage capacitor Cst may be disposed in the first conductive layer. In detail, the (i-1)th scan line Si-1, the i-th scan line Si, the (i+1)th scan line Si+1, the emission control line Ei, and the first gate electrode GE1 to the seventh gate electrode GE7 may be disposed in the first conductive layer on the first insulating layer INS1. In an exemplary embodiment, the first gate electrode GE1 may also be used as the first capacitor electrode LE of the storage capacitor Cst. In other words, in an exemplary embodiment, the first gate electrode GE1 and the first capacitor electrode LE may be formed integrally with each other. In an exemplary embodiment, the second gate electrode GE2 and the third gate electrode GE3 may be formed integrally with the i-th scan line Si. In an exemplary embodiment, the fourth gate electrode GE4 may be formed integrally with the (i-1)th scan line Si-1. In an exemplary embodiment, the fifth gate electrode GE5 and the sixth gate electrode GE6 may be integrally formed with the emission control line Ei. In an exemplary embodiment, the seventh gate electrode GE7 may be integrally formed with the (i+1)th scan line Si+1.

[0220] In an exemplary embodiment, the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the lower electrode LE of the storage capacitor Cst disposed in the first conductive layer may be formed of the same material. For example, the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the lower electrode LE of the storage capacitor Cst may be formed of a predetermined first gate metal.

[0221] In an exemplary embodiment, Ti, Cu, Mo, Al, Au, Cr, TiN, Ag, Pt, Pd, Ni, Sn, Co, Rh, Ir, Fe, Ru, Os, Mn, W, Nb, Ta, Bi, Sb, Pb, etc. are representative examples of materials capable of forming the first gate metal. In addition, various other metals can be used. MoTi, AlNiLa, etc. are representative examples of alloys capable of forming the first gate metal. In addition, various other alloys can be used. Ti / Cu, Ti / Au, Mo / Al / Mo, ITO / Ag / ITO, TiN / Ti / Al / Ti, TiN / Ti / Cu / Ti, etc. are representative examples of conductive materials having a multilayer structure capable of forming the first gate metal. In addition, various other conductive materials having a multilayer structure can be used.

[0222] The constituent materials of the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the first capacitor electrode LE provided in the first conductive layer are not limited to metals. In other words, any material can be used as the constituent material of the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the first capacitor electrode LE as long as the material can provide conductivity that is sufficiently stable to drive the pixel PXL.

[0223] For example, the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the first capacitor electrode LE can be formed of a conductive polymer or a conductive metal oxide. Examples of conductive polymers capable of forming the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the first capacitor electrode LE may include polythiophene compounds, polypyrrole compounds, polyaniline compounds, polyacetylene compounds, polyphenylene compounds and mixtures thereof. Specifically, among the polythiophene compounds, PEDOT / PSS compounds can be used. Examples of conductive metal oxides capable of forming the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the first capacitor electrode LE may include ITO, IZO, AZO, ITZO, ZnO, SnO 2 wait.

[0224] The second insulating layer INS2 may be disposed on the first conductive layer. In an exemplary embodiment, the second insulating layer INS2 may be a first interlayer insulating layer disposed between the first capacitor electrode LE and the second capacitor electrode UE. In an exemplary embodiment, the second insulating layer INS2 may have a thickness defined within a predetermined range to ensure sufficient capacity of the storage capacitor Cst in a limited area. In an exemplary embodiment, the second insulating layer INS2 may have a thickness similar to that of the first insulating layer INS1. For example, the second insulating layer INS2 may have to The thickness is within the range of (e.g., approximately ), but the thickness of the second insulating layer INS2 is not limited thereto.

[0225] In an exemplary embodiment, the second insulating layer INS2 may include at least one inorganic layer and / or organic layer. For example, the second insulating layer INS2 may include SiO x or SiN x The second insulating layer INS2 may include an inorganic layer such as SiO x 、SiN x , SiON, SiOF or AlO x of an inorganic insulating material or an organic insulating material, and may have a single-layer or multi-layer structure including at least one of the foregoing materials.

[0226] The second conductive layer may be disposed on the second insulating layer INS2. In an exemplary embodiment, the second conductive layer may be a second gate layer.

[0227] In an exemplary embodiment, the second capacitor electrode UE and the initialization power line IPL may be disposed in the second conductive layer. In an exemplary embodiment, the second capacitor electrode UE may cover the first capacitor electrode LE. The second capacitor electrode UE may overlap the first capacitor electrode LE, thereby forming a storage capacitor Cst together with the first capacitor electrode LE, and the second insulating layer INS2 is disposed between the second capacitor electrode UE and the first capacitor electrode LE.

[0228] In an exemplary embodiment, the second capacitor electrode UE and the initialization power line IPL disposed in the second conductive layer may be formed of the same material. For example, the second capacitor electrode UE and the initialization power line IPL may be formed of a predetermined second gate metal. In an exemplary embodiment, the second gate metal may be any of the metal materials proposed as examples of the first gate metal, but the present disclosure is not limited thereto. In addition, the constituent materials of the second capacitor electrode UE and the initialization power line IPL disposed in the second conductive layer are not limited to metals. In other words, any material may be used as a constituent material of the second capacitor electrode UE and the initialization power line IPL, as long as the material can provide conductivity that is sufficiently stable to drive the pixel PXL. For example, the second capacitor electrode UE and the initialization power line IPL disposed in the second conductive layer may be formed of a conductive polymer or a conductive metal oxide.

[0229] The third insulating layer INS3 may be disposed on the second conductive layer. In an exemplary embodiment, the third insulating layer INS3 may be a second interlayer insulating layer. In an exemplary embodiment, the third insulating layer INS3 may have a thickness greater than that of the first insulating layer INS1 or the second insulating layer INS2. For example, the thickness of the third insulating layer INS3 may be equal to or greater than the sum of the thickness of the first insulating layer INS1 and the thickness of the second insulating layer INS2. For example, the third insulating layer INS3 may have a thickness of approximately The thickness of the third insulating layer INS3 is not limited thereto. Therefore, if the third insulating layer INS3 has a sufficient thickness greater than the sum of the thickness of the first insulating layer INS1 and the thickness of the second insulating layer INS2, electrical stability between components disposed above and below the third insulating layer INS3 can be ensured. Therefore, a short circuit can be effectively prevented from occurring.

[0230] In an exemplary embodiment, the third insulating layer INS3 may include at least one inorganic layer and / or organic layer. For example, the third insulating layer INS3 may include SiO x or SiN x For example, the third insulating layer INS3 may include an inorganic layer such as SiO x 、SiN x , SiON, SiOF or AlO x of an inorganic insulating material or an organic insulating material, and may have a single-layer or multi-layer structure including at least one of the foregoing materials.

[0231] The third conductive layer may be disposed on the third insulating layer INS3. In an exemplary embodiment, the third conductive layer may be a source-drain layer.

[0232] In exemplary embodiments, the data line Dj, the power line PL, the connection line CNL, the auxiliary connection line AUX, and the bridge pattern BRP may be disposed in the third conductive layer.

[0233] In an exemplary embodiment, the data line Dj may be coupled to the second source electrode SE2 through a sixth contact hole CH6 passing through the first, second, and third insulating layers INS1, INS2, and INS3.

[0234] In an exemplary embodiment, the power line PL may be coupled to the second capacitor electrode UE of the storage capacitor Cst through the third contact hole CH3 and the fourth contact hole CH4 passing through the third insulating layer INS3. In addition, the power line PL may be coupled to the fifth source electrode SE5 through the fifth contact hole CH5 passing through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0235] In an exemplary embodiment, the connection line CNL may be coupled to the first gate electrode GE1 through a first contact hole CH1 passing through the second insulating layer INS2 and the third insulating layer INS3. In addition, the connection line CNL may be coupled to the third drain electrode DE3 and the fourth source electrode SE4 through a second contact hole CH2 passing through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0236] In an exemplary embodiment, the auxiliary connection line AUX may be coupled to the initialization power line IPL through an eighth contact hole CH8 passing through the third insulating layer INS3. In addition, the auxiliary connection line AUX may be coupled to the seventh drain electrode DE7 through a ninth contact hole CH9 passing through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0237] In an exemplary embodiment, a bridge pattern BRP may be disposed between the sixth drain electrode DE6 and the first electrode AD and provided as a medium for coupling the sixth drain electrode DE6 and the first electrode AD to each other. The bridge pattern BRP may be coupled to the sixth drain electrode DE6 and the seventh source electrode SE7 through a seventh contact hole CH7 passing through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0238] In an exemplary embodiment, the data line Dj, the power line PL, the connection line CNL, the auxiliary connection line AUX and the bridge pattern BRP disposed in the third conductive layer may be formed of the same material. For example, the data line Dj, the power line PL, the connection line CNL, the auxiliary connection line AUX and / or the bridge pattern BRP may be formed of a predetermined source-drain metal.

[0239] In an exemplary embodiment, the source-drain metal may be any of the metal materials proposed as examples of the first gate metal and / or the second gate metal, but the present disclosure is not limited thereto. In addition, the constituent materials of the data line Dj, the power line PL, the connection line CNL, the auxiliary connection line AUX and / or the bridge pattern BRP disposed in the third conductive layer are not limited to metals. In other words, any material may be used as a constituent material of the data line Dj, the power line PL, the connection line CNL, the auxiliary connection line AUX and / or the bridge pattern BRP, as long as the material can provide conductivity that is sufficiently stable to drive the pixel PXL. For example, the data line Dj, the power line PL, the connection line CNL, the auxiliary connection line AUX and / or the bridge pattern BRP may be formed of a conductive polymer or a conductive metal oxide.

[0240] In an exemplary embodiment, at least two of the first gate metal, the second gate metal, and the source-drain metal may be formed of the same material. For example, although the first gate metal and the second gate metal are disposed on respective different layers, the first gate metal and the second gate metal may be formed of the same material. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, the first gate metal, the second gate metal, and the source-drain metal may be formed of different materials.

[0241] The fourth insulating layer INS4 may be disposed on the third conductive layer. In exemplary embodiments, the fourth insulating layer INS4 may include a passivation layer and / or a planarization layer.

[0242] The light emitting element LD may be disposed on the fourth insulating layer INS4. The light emitting element LD may include a first electrode AD, a second electrode CD, and an emission layer EML disposed between the first electrode AD and the second electrode CD.

[0243] In an exemplary embodiment, the first electrode AD may be disposed on the fourth insulating layer INS4. The first electrode AD may be coupled to the bridge pattern BRP through the tenth contact hole CH10 passing through the fourth insulating layer INS4. Since the bridge pattern BRP is coupled to the sixth drain electrode DE6 and the seventh source electrode SE7 through the seventh contact hole CH7, the first electrode AD may be finally coupled to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0244] In an exemplary embodiment, a pixel defining layer (or bank layer) PDL for defining an emission region of each pixel PXL may be disposed on a first substrate SUB1 on which a first electrode AD, etc., has been formed. The pixel defining layer PDL may expose an upper surface of the first electrode AD and protrude from the first substrate SUB1 along a periphery of each pixel PXL.

[0245] The emission layer EML may be disposed in an emission region of each pixel PXL surrounded by the pixel defining layer PDL. The second electrode CD may be disposed on the emission layer EML. In an exemplary embodiment, a thin film encapsulation layer TFE may be disposed on the second electrode CD to cover the second electrode CD. In an exemplary embodiment, the thin film encapsulation layer TFE may be replaced with another type of encapsulation layer, an encapsulation substrate, at least one passivation layer, etc.

[0246] In an exemplary embodiment, one of the first electrode AD and the second electrode CD may be an anode electrode, and the other may be a cathode electrode. For example, the first electrode AD may be an anode electrode, and the second electrode CD may be a cathode electrode.

[0247] At least one of the first electrode AD and the second electrode CD may be a transmissive electrode. For example, in the case where the light-emitting element LD is a bottom-emitting organic light-emitting display element, the first electrode AD may be a transmissive electrode, and the second electrode CD may be a reflective electrode. In the case where the light-emitting element LD is a top-emitting organic light-emitting display element, the first electrode AD may be a reflective electrode, and the second electrode CD may be a transmissive electrode. In the case where the light-emitting element LD is a double-sided emission organic light-emitting display element, both the first electrode AD and the second electrode CD may be transmissive electrodes. In the present embodiment, an example is shown in which the light-emitting element LD is a top-emitting organic light-emitting display element and the first electrode AD is an anode electrode. In addition, in the present embodiment, although the light-emitting element LD is used as a light source, the present disclosure is not limited thereto. For example, the light-emitting element LD may be replaced with another type of light-emitting element.

[0248] In an exemplary embodiment, the first electrode AD may include a reflective layer (not shown) that may reflect light and a transparent conductive layer (not shown) disposed on or below the reflective layer. At least one of the transparent conductive layer and the reflective layer may be coupled to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0249] In an exemplary embodiment, the reflective layer may include a material capable of reflecting light. For example, the reflective layer may include at least one of aluminum (Al), silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni), and alloys thereof.

[0250] In an exemplary embodiment, the transparent conductive layer may include a transparent conductive oxide. For example, the transparent conductive layer may include at least one transparent conductive oxide of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO).

[0251] In an exemplary embodiment, the pixel defining layer PDL may include an organic insulating material. For example, the pixel defining layer PDL may include at least one of polystyrene, polymethyl methacrylate (PMMA), polyacrylonitrile (PAN), polyamide (PA), polyimide (PI), polyarylether (PAE), heterocyclic polymer, polyparaxylene, epoxy resin, benzocyclobutene (BCB), siloxane-based resin, and silane-based resin.

[0252] The emission layer EML may be disposed on the exposed surface of the first electrode AD. In an exemplary embodiment, the emission layer EML may have a multilayer thin film structure including at least a light generating layer (LGL). For example, the emission layer EML may include: a hole injection layer (HIL) into which holes are injected; a hole transport layer (HTL) having excellent hole transport performance or promoting hole transport and suppressing the movement of electrons that are not combined with holes in the light generating layer, thereby increasing the chance of recombination between holes and electrons; a light generating layer that emits light through recombination between injected electrons and holes; a hole blocking layer (HBL) that suppresses the movement of holes that are not combined with electrons in the light generating layer; an electron transport layer (ETL) that is configured to smoothly transfer electrons to the light generating layer; and / or an electron injection layer (EIL) into which electrons are injected.

[0253] In an exemplary embodiment, the color of the light generated from the light generating layer may be one of red, green, blue and white, but in this embodiment, this is not limited. For example, the color of the light generated from the light generating layer of the emission layer EML may be one of magenta, cyan and yellow.

[0254] In exemplary embodiments, the hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, and the electron injection layer may be a common layer coupled between adjacent emission regions.

[0255] In an exemplary embodiment, the second electrode CD may be a semi-transmissive layer. For example, the second electrode CD may be a thin metal layer having a thickness that allows light emitted from the emission layer EML to pass through the second electrode CD. For example, the second electrode CD may allow some of the light generated from the emission layer EML to pass through the second electrode CD, and may reflect the remaining light generated from the emission layer EML.

[0256] In an exemplary embodiment, the second electrode CD may include a material having a work function lower than that of the transparent conductive layer. For example, the second electrode CD may include at least one of molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and alloys thereof.

[0257] Some of the light emitted from the emission layer EML may not pass through the second electrode CD, and the light reflected by the second electrode CD is reflected by the reflective layer again. That is, the light emitted from the emission layer EML may resonate between the reflective layer and the second electrode CD. The light extraction efficiency of the organic light emitting diode OLED can be improved by the resonance of light.

[0258] In an exemplary embodiment, the thin film encapsulation layer TFE may prevent oxygen or water from penetrating into the light emitting element LD. To this end, the thin film encapsulation layer TFE may include an inorganic layer. The inorganic layer may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide. The thin film encapsulation layer TFE may cover at least the pixel area PXA and extend to the outside of the pixel area PXA.

[0259] In an exemplary embodiment, the circuit elements and lines disposed on the first surface of the first substrate SUB1 from the buffer layer BFL to the fourth insulating layer INS4 may form a circuit element layer BPL of the display device 100 and / or the fingerprint sensor. In addition, the light emitting elements LD disposed in each pixel area PXA from the first electrode AD to the second electrode CD and the pixel defining layer PDL disposed between the light emitting elements LD may form a light emitting element layer LDL of the display device 100 and / or the fingerprint sensor. A thin film encapsulation layer TFE or the like may be formed to at least cover the light emitting element layer LDL, and a first passivation layer PTL1 may be formed.

[0260] Fig.17 is a plan view illustrating an example of a layout of a first pixel PXL1 according to an exemplary embodiment of the present disclosure. Fig.18 is along Fig.17 In an exemplary embodiment, Fig.17 and Fig.18 The first pixel PXL1 shown in FIG. Figures 1 to 3E as well as Figure 5A , Figure 5B , Figure 5C and Figure 5D In other words, in an exemplary embodiment of the present disclosure, at least some of the pixels PXL of the sensing area SA may include the first light-transmitting hole LTH1 formed in a corresponding pixel area (hereinafter, referred to as “first pixel area PXA1”) to communicate with the first light-transmitting hole LTH1. Fig.17 and Fig.18 The optical system of the fingerprint sensor is formed in the same manner as the optical system of the first pixel PXL1 shown in FIG.

[0261] Reference Fig.17 and Fig.18, the first pixel PXL1 according to an exemplary embodiment of the present disclosure may include a first light-transmitting hole LTH1 formed in at least one conductive layer of the circuit element layer BPL. In an exemplary embodiment, the sensing area SA may include a plurality of first pixels PXL1 each including at least one first light-transmitting hole LTH1. In this case, the sensing area SA may include a plurality of first light-transmitting holes LTH1 distributed in at least one conductive layer of the circuit element layer BPL and each of which forms a pinhole PIH or a light control hole LCH. In addition, the first light-transmitting hole LTH1 may include a plurality of openings distributed in at least one conductive layer of the circuit element layer BPL.

[0262] For example, each of the first light-transmitting holes LTH1 may include at least one opening formed in a conductive layer (e.g., a semiconductor layer, a first conductive layer (e.g., a first gate layer), a second conductive layer (e.g., a second gate layer), and / or a third conductive layer (e.g., a source-drain layer)) of the circuit element layer BPL. For example, each of the first light-transmitting holes LTH1 may include at least one opening formed in at least one of the conductive patterns (electrodes and / or lines of the circuit element) of at least one of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer forming the circuit element layer BPL.

[0263] In an exemplary embodiment of the present disclosure, each first light-transmitting hole LTH1 may include a first opening OPN1 formed in a first conductive layer disposed in a first substrate SUB1 and a second opening OPN2 overlapped with the first opening OPN1 and formed in a second conductive layer disposed above the first conductive layer, and at least one insulating layer (e.g., a second insulating layer INS2) is located between the first conductive layer and the second conductive layer. For example, each first light-transmitting hole LTH1 may be formed in a region of any one of the first pixels PXL1 in which a storage capacitor Cst is formed.

[0264] For example, each of the first light-transmitting holes LTH1 may include a first opening OPN1 formed in the first conductive layer and surrounded by the first capacitor electrode LE of the storage capacitor Cst of the first pixel PXL1, and a second opening OPN2 formed in the second conductive layer and surrounded by the second capacitor electrode UE of the storage capacitor Cst. In other words, in an exemplary embodiment, the first opening OPN1 may be formed as an opening formed in the first capacitor electrode LE. The second opening OPN2 may be formed as an opening formed in the second capacitor electrode UE and overlapping the first opening OPN1.

[0265] In an exemplary embodiment, the first capacitor electrode LE and / or the second capacitor electrode UE may be formed of a light-blocking metal. In an exemplary embodiment, at least one of the first conductive layer and the second conductive layer may include a light-blocking metal pattern and may have a first opening OPN1 and / or a second opening OPN2 formed as an opening formed in the light-blocking metal pattern.

[0266] In an exemplary embodiment, when each of the first light-transmitting holes LTH1 is formed by a pair of first openings OPN1 and second openings OPN2 overlapping each other, the pair of first openings OPN1 and second openings OPN2 may have the same width (W) along at least one direction. For example, the pair of first openings OPN1 and second openings OPN2 may have the same width (W) along the first direction DR1. In this case, as Figure 8B As shown in the exemplary embodiment of the present invention, the pair of first openings OPN1 and second openings OPN2 may form a pinhole PIH having a multi-layer structure. For example, in the exemplary embodiment, the pair of first openings OPN1 and second openings OPN2 may form a light control hole LCH having a multi-layer structure.

[0267] In an exemplary embodiment of the present disclosure, at least one first light-transmitting hole LTH1 may be located in any one of the first pixels PXL1 and formed so as not to overlap with at least one opaque electrode (e.g., the first electrode AD of the light-emitting element LD) among the electrodes of the light-emitting element LD forming the first pixel PXL1. For example, although each of the first light-transmitting holes LTH1 is located in the first pixel area PXA1 in which any one of the first pixels PXL1 is formed, the first light-transmitting hole LTH1 may be formed in the non-emission area of ​​the first pixel PXL1 to prevent the first light-transmitting hole LTH1 from overlapping with the first electrode AD of the light-emitting element LD of the first pixel PXL1.

[0268] According to the aforementioned embodiment, the first light-transmitting hole array layer LTHL1 can be formed integrally with the circuit element layer BPL without forming an additional layer in the circuit element layer BPL. Therefore, the thickness of the module including the display device 100 can be reduced. The width of the opening area OPA that needs to be fixed between the circuit element layer BPL and the light-emitting element layer LDL (for example, at the interface between the circuit element layer BPL and the light-emitting element layer LDL in which the first electrode AD of the light-emitting element LD is disposed) can be reduced.

[0269] Fig.19 is a plan view illustrating an example of a layout of a first pixel PXL1 according to an exemplary embodiment of the present disclosure. Fig. 20 is along Fig.19 A sectional view taken along the section line IV-IV'. Fig.19 and Fig. 20In the description of the exemplary embodiments of the present invention, the same reference numerals will be used to denote the same Fig.17 and Fig.18 The components of the exemplary embodiment are similar or identical to those of the exemplary embodiment, and a detailed description thereof will be omitted.

[0270] Reference Fig.19 and Fig. 20 , a pair of first openings OPN1 and second openings OPN2 forming each first light transmission hole LTH1 may have different widths along at least one direction. For example, each first opening OPN1 may have a first width W1 along the first direction DR1, and each second opening OPN2 may have a second width W2 greater than the first width W1 along the first direction DR1. In this case, each first light transmission hole LTH1 may include a first opening OPN1 forming a pinhole PIH and a second opening OPN2 forming a light control hole LCH. Each pair of first openings OPN1 and second openings OPN2 may have different widths along at least one direction. Figure 8C The pinhole unit PIHU is formed in the same manner as the exemplary embodiment shown in FIG.

[0271] Although each first opening OPN1 forms a pinhole PIH and each second opening OPN2 forms a light control hole LCH in the present embodiment, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, each first opening OPN1 may have a width greater than that of a corresponding second opening OPN2 overlapped with the first opening OPN1 and may form a light control hole LCH, and each second opening OPN2 may form a pinhole PIH.

[0272] Fig.21 is a plan view illustrating an example of a layout of a first pixel PXL1 according to an exemplary embodiment of the present disclosure. Fig.22A and Fig. 22B are respectively along the exemplary embodiments according to the present disclosure Fig.21 The sectional view taken along the section lines I-I' and II-II'. Fig.21 , Fig.22A and Fig. 22B In the description of the exemplary embodiments of the present invention, the same reference numerals will be used to refer to components similar to or identical to those of the previous embodiments, and detailed descriptions thereof will be omitted.

[0273] Reference Fig.21 , Fig.22A and Fig. 22B, each first light-transmitting hole LTH1 may include a plurality of openings MLO, which are overlapped with each other and formed in a plurality of conductive layers forming the circuit element layer BPL. For example, each first light-transmitting hole LTH1 may include: a plurality of openings MLO, which are overlapped with each other and formed in at least two layers of the semiconductor layer of the circuit element layer BPL on which the first active pattern ACT1 to the seventh active pattern ACT7 are disposed; a first conductive layer of the circuit element layer BPL, in which the first gate electrode GE1 to the seventh gate electrode GE7 are disposed; a second conductive layer of the circuit element layer BPL, in which the second capacitor electrode UE, etc. are disposed; and a third conductive layer of the circuit element layer BPL, in which the power line PL, etc. are disposed. In the present disclosure, the position and / or structure of the first light-transmitting holes LTH1 distributed in the circuit element layer BPL are not limited and may be changed in various ways.

[0274] Fig.23 is a plan view showing an example of a layout of a first pixel PXL1 and a second pixel PXL2 according to an exemplary embodiment of the present disclosure. In the exemplary embodiment, Fig.23 The first pixel PXL1 and the second pixel PXL2 shown in FIG. 1 may be Figures 1 to 3E as well as Figure 5A , Figure 5B , Figure 5C and Figure 5D Pixels disposed adjacent to each other among the pixels PXL of the sensing area SA shown in FIG.

[0275] Reference Fig.23 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig.22A and Fig. 22B The first light transmission holes LTH1 described in the exemplary embodiment of the present invention may be formed only in some of the pixels PXL of the sensing area SA. For example, the pixels PXL of the sensing area SA may include first pixels PXL1 and second pixels PXL2, each of the first pixels PXL1 including at least one first light transmission hole LTH1, the second pixels PXL2 are disposed near the first pixels PXL1, and each of the pixels PXL2 is configured such that an area thereof corresponding to an area of ​​each first pixel PXL1 in which the first light transmission hole LTH1 is formed has a structure different from that of the first pixel PXL1.

[0276] However, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, all pixels PXL disposed in the sensing area SA may be configured as first pixels PXL1 each including at least one first light-transmitting hole LTH1. At least one pixel PXL disposed in the remaining display area DA other than the sensing area SA may be formed of a second pixel PXL2 configured such that an area thereof corresponding to an area of ​​each first pixel PXL1 in which the first light-transmitting hole LTH1 is formed has a structure different from that of the first pixel PXL1.

[0277] In the light sensing fingerprint sensor according to the exemplary embodiment of the present disclosure, the first light transmission hole array layer of the optical system can be formed integrally with the fingerprint sensor and the circuit element layer of the display device. Therefore, the thickness of the module including the light sensing fingerprint sensor and the display device including the light sensing fingerprint sensor can be reduced or minimized. In addition, in the exemplary embodiment, in the case where the first light transmission hole array layer forms a pinhole array layer, the width of the opening area that needs to be fixed between the circuit element layer and the light emitting element layer can be reduced. Therefore, even if the pixels are set in the display panel with high resolution, the display panel can be easily constructed as a display panel of the integrated optical system.

[0278] In addition, in an exemplary embodiment of the present disclosure, the ripple effect that may occur in a light sensing type fingerprint sensor can be prevented or reduced by adjusting the resolution of the light transmission hole array layer and the light sensor array layer superimposed on the light transmission hole array layer. Therefore, the fingerprint information can be prevented from being distorted by the ripples, and the reliability of the fingerprint sensor can be improved.

[0279] Although specific exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, as will be apparent to one of ordinary skill in the art, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements.

Claims

1. A display device, comprising: A first substrate including a plurality of pixel regions; A circuit element layer is disposed on the first surface of the first substrate, and the circuit element layer includes at least one conductive layer; A light emitting element layer, disposed on the circuit element layer; A plurality of pixels each comprising: a circuit element and a light emitting element, wherein the circuit element and the light emitting element are respectively arranged on the circuit element layer and the light emitting element layer in corresponding pixel regions among the plurality of pixel regions; A first light-transmitting hole array layer, comprising a plurality of first light-transmitting holes distributed in the circuit element layer; and a light sensor array layer, disposed on the second surface of the first substrate and overlapping the first light-transmitting hole array layer, the light sensor array layer comprising a plurality of light sensors, Each of the plurality of first light-transmitting holes comprises a first opening and a second opening distributed in the at least one conductive layer, wherein each of the plurality of pixels comprises at least one capacitor, Wherein, the capacitor of at least one pixel among the plurality of pixels comprises: a first capacitor electrode surrounding the first opening of one of the plurality of first light-transmitting holes; and The second capacitor electrode overlaps with the first capacitor electrode and surrounds the second opening of the one first light-transmitting hole.

2. The display device according to claim 1, wherein: The plurality of first light transmission holes are disposed in at least one of the plurality of pixels.

3. The display device according to claim 2, wherein: The plurality of pixels comprises: The first pixels each include at least one first light-transmitting hole; and Second pixels are disposed near the first pixels, each of the second pixels including a region having a structure different from a structure of a corresponding region of each of the first pixels in which the first light-transmitting hole is formed.

4. The display device according to claim 1, wherein: The first opening is formed in a first conductive layer disposed on the first substrate, The second opening is formed in a second conductive layer disposed on the first conductive layer, the second opening overlaps the first opening, and Each of the plurality of first light-transmitting holes further includes: at least one insulating layer disposed between the first conductive layer and the second conductive layer.

5. The display device according to claim 4, wherein: At least one of the first conductive layer and the second conductive layer includes a light-blocking metal pattern.

6. The display device according to claim 4, wherein: The first capacitor electrode is disposed in the first conductive layer, and The second capacitor electrode is disposed in the second conductive layer.

7. The display device according to claim 4, wherein: The first opening and the second opening have the same width along one direction.

8. The display device according to claim 4, wherein: The second opening has a width in one direction that is greater than a width of the first opening.

9. The display device according to claim 1, in, Each of the plurality of pixels includes at least one transistor, and Wherein, the at least one transistor comprises: an active pattern, arranged in the semiconductor layer on the first substrate; a gate electrode disposed in a first conductive layer, the first conductive layer being disposed on the semiconductor layer, and at least one insulating layer being interposed between the first conductive layer and the semiconductor layer, the gate electrode overlapping the active pattern; and A source electrode and a drain electrode are coupled to respective opposite ends of the active pattern.

10. The display device according to claim 9, further comprising at least one of the following elements: a second conductive layer disposed on the first conductive layer with at least one insulating layer interposed between the first conductive layer and the second conductive layer, and the second conductive layer includes at least one capacitor electrode; and The third conductive layer is disposed on the second conductive layer, and at least one insulating layer is disposed between the second conductive layer and the third conductive layer. The third conductive layer includes at least one line.

11. The display device according to claim 10, wherein: Each of the plurality of first light-transmitting holes includes a plurality of openings formed in at least two of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer, the plurality of openings overlapping each other.

12. The display device according to claim 1, wherein: The light emitting element comprises: A first electrode and a second electrode are provided in each of the plurality of pixel regions of the light emitting element layer, the first electrode and the second electrode overlapping each other; and The emission layer is arranged between the first electrode and the second electrode.

13. The display device according to claim 12, wherein: At least one of the plurality of first light-transmitting holes is formed in one of the plurality of pixels and is disposed in a non-emitting region of the one pixel, and the at least one first light-transmitting hole does not overlap with the first electrode of the light-emitting element of the one pixel.

14. The display device according to claim 1, further comprising a second light-transmitting hole array layer disposed between the first substrate and the circuit element layer and overlapping the first light-transmitting hole array layer, the second light-transmitting hole array layer comprising a plurality of second light-transmitting holes overlapping the plurality of first light-transmitting holes.

15. The display device according to claim 14, wherein: The plurality of first light transmission holes and the plurality of second light transmission holes have different widths.

16. The display device according to claim 1, further comprising: a second substrate, disposed between the first substrate and the light sensor array layer; as well as The third light-transmitting hole array layer is disposed between the first substrate and the second substrate and is configured to overlap with the first light-transmitting hole array layer. The third light-transmitting hole array layer includes a plurality of third light-transmitting holes overlapping with the plurality of first light-transmitting holes.

17. The display device according to claim 1, comprising a sensing area including at least a portion of a display area in which the plurality of pixels are disposed, wherein: The first light-transmitting hole array layer and the light sensor array layer are disposed in the sensing area.

18. The display device according to claim 17, wherein: The plurality of first light transmission holes are distributed in the sensing area at a resolution lower than a resolution of the plurality of pixels.

19. The display device according to claim 17, wherein: The light sensors are distributed in the sensing area with a resolution higher than a resolution of the plurality of first light-transmitting holes.

20. A fingerprint sensor, comprising: first base; a circuit element layer disposed on the first surface of the first substrate and comprising at least one conductive layer and at least one capacitor; a light emitting element layer, disposed on the circuit element layer and comprising a plurality of light emitting elements; A first light-transmitting hole array layer, comprising a plurality of first light-transmitting holes distributed in the circuit element layer; as well as a light sensor array layer, disposed on the second surface of the first substrate and overlapping the first light-transmitting hole array layer, the light sensor array layer comprising a plurality of light sensors, Each of the plurality of first light-transmitting holes comprises a first opening and a second opening distributed in the at least one conductive layer, Wherein, the at least one capacitor comprises: a first capacitor electrode surrounding the first opening of any one of the plurality of first light-transmitting holes; and The second capacitor electrode overlaps with the first capacitor electrode and surrounds the second opening of any one of the first light-transmitting holes.

21. The fingerprint sensor according to claim 20, wherein: The circuit element layer comprises: A first conductive layer, disposed on the first substrate; a second conductive layer, disposed on the first conductive layer; and At least one insulating layer is disposed between the first conductive layer and the second conductive layer.

22. The fingerprint sensor according to claim 21, wherein: The first opening is formed in the first conductive layer, and The second opening is formed in the second conductive layer and overlaps the first opening.

23. The fingerprint sensor according to claim 22, wherein: At least one of the first conductive layer and the second conductive layer includes a light-blocking metal pattern.

24. The fingerprint sensor according to claim 22, wherein: The first capacitor electrode is disposed in the first conductive layer, and The second capacitor electrode is disposed in the second conductive layer.

25. The fingerprint sensor according to claim 20, wherein: The circuit element layer includes at least one transistor, the at least one transistor includes an active pattern, a gate electrode, a source electrode, and a drain electrode, and Wherein, each of the plurality of first light-transmitting holes includes at least one opening, the at least one opening is formed in at least one of a semiconductor layer in which the active pattern is arranged, a first conductive layer in which the gate electrode is arranged, and a second conductive layer arranged on the first conductive layer, and at least one insulating layer is placed between the semiconductor layer, the first conductive layer and the second conductive layer.

26. The fingerprint sensor according to claim 20, wherein: Each of the plurality of light emitting elements comprises: A first electrode and a second electrode are provided in each emission region of the light emitting element layer, the first electrode and the second electrode overlap each other; and The emission layer is arranged between the first electrode and the second electrode.

27. The fingerprint sensor according to claim 26, wherein: The plurality of first light-transmitting holes are distributed in a non-emitting region of the light-emitting element layer, and the plurality of first light-transmitting holes do not overlap with the first electrodes of the plurality of light-emitting elements.

28. The fingerprint sensor according to claim 20, further comprising a second light-transmitting hole array layer disposed between the first substrate and the circuit element layer and overlapping the first light-transmitting hole array layer, the second light-transmitting hole array layer comprising a plurality of second light-transmitting holes overlapping the plurality of first light-transmitting holes.

29. The fingerprint sensor according to claim 20, further comprising: a second substrate, disposed between the first substrate and the light sensor array layer; as well as The third light-transmitting hole array layer is disposed between the first substrate and the second substrate and is configured to overlap with the first light-transmitting hole array layer. The third light-transmitting hole array layer includes a plurality of third light-transmitting holes overlapping with the plurality of first light-transmitting holes.

30. The fingerprint sensor according to claim 20, wherein: The light sensor is disposed on the second surface of the first substrate with a resolution higher than a resolution of the plurality of first light transmission holes.

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