Multi-version library cell disposal and integrated circuit structure fabricated therefrom

Abstract

Describes multi-version library cell disposition and an integrated circuit structure fabricated therefrom. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch being less than the first pitch.

Description

Technical Field

[0001] Embodiments of the present disclosure are in the field of integrated circuit structures and, in particular, in the field of multi-version library cell handling. Background Art

[0002] For the past several decades, the scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling to ever-smaller features has enabled an increase in the density of functional units on the limited real estate of semiconductor chips.

[0003] For example, shrinking the size of transistors allows for an increased number of memory or logic devices to be incorporated on a chip, resulting in products with increased capacity. However, the pursuit of ever-larger capacity is not without problems. The need to optimize the performance of each device has become increasingly important. In the fabrication of integrated circuit devices, as device sizes continue to shrink, multi-gate transistors, such as tri-gate transistors, have become more common. In conventional processes, tri-gate transistors are typically fabricated on a bulk silicon substrate or a silicon-on-insulator substrate. In some cases, the bulk silicon substrate is preferred due to its lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure. However, scaling multi-gate transistors is not without consequences. As the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks fabricated in a given area increases, the constraints on the semiconductor processes used to fabricate these building blocks have become quite onerous.

[0004] Variability in conventional and state-of-the-art fabrication processes may limit the possibility of further scaling them, for example, into the 10 nm or sub-10 nm range. Thus, fabricating the functional components required for future technology nodes may require introducing new methods or integrating new technologies either in or to replace current fabrication processes. New layouts may be introduced to accommodate or enable such future technology nodes. Brief Description of the Drawings

[0005] Figure 1 A first view illustrating a conventional cell layout for a memory cell.

[0006] Figure 2 A first view illustrating a cell layout for a memory cell having an increased Metal 1 pitch density relative to an underlying gate line, in accordance with an embodiment of the present disclosure.

[0007] Figure 3AThe figure shows a top view of increased pin hits of multiple Metal 2 (M2) lines according to an embodiment of the present disclosure, the multiple Metal 2 (M2) lines being in a layout having Metal 1 (M1), the Metal 1 (M1) having an increased density relative to underlying gate lines.

[0008] Figure 3B The figure shows a top view of conventional pin hits of multiple Metal 2 (M2) lines, the multiple Metal 2 (M2) lines being in a layout having Metal 1 (M1), the Metal 1 (M1) having the same density relative to underlying gate lines.

[0009] Figure 4 The figure shows a top view of (a) an inverter cell having an even poly pitch relative to (b) a NAND cell having an odd poly pitch according to an embodiment of the present disclosure.

[0010] Figure 5 The figure shows a top view of (a) an inverter cell having an even poly pitch relative to (b) a NAND cell having an odd poly pitch according to another embodiment of the present disclosure.

[0011] Figure 6 The figure shows a cross-sectional view of two different layouts for the same standard cell according to an embodiment of the present disclosure.

[0012] Figure 7 The figure shows a top view of four different cell arrangements indicating even (E) or odd (O) markings according to an embodiment of the present disclosure.

[0013] Figure 8 The figure shows a top view of a block-level poly grid according to an embodiment of the present disclosure.

[0014] Figure 9 The figure shows an exemplary acceptable (pass) layout based on standard cells having different versions according to an embodiment of the present disclosure.

[0015] Figure 10 The figure shows an exemplary unacceptable (fail) layout based on standard cells having different versions according to an embodiment of the present disclosure.

[0016] Figure 11 The figure shows another exemplary acceptable (pass) layout based on standard cells having different versions according to an embodiment of the present disclosure.

[0017] Figure 12 The figure shows a second view of a conventional cell layout for a memory cell.

[0018] Figure 13A second view of a cell layout for a memory cell having an M1 pitch that is tighter than the gate line pitch, according to an embodiment of the present disclosure.

[0019] Figure 14 A third view of a conventional cell layout for a memory cell.

[0020] Figure 15 A third view of a cell layout for a memory cell having an M1 pitch that is tighter than the gate line pitch, according to an embodiment of the present disclosure.

[0021] Figure 16A A cross-sectional view of a non-planar semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 16B A plan view of a semiconductor device taken along the a-a' axis according to an embodiment of the present disclosure Figure 16A thereof.

[0023] Figure 17 A computing device according to an implementation of an embodiment of the present disclosure.

[0024] Figure 18 is an interposer that implements one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] Describes multi-version library cell handling and integrated circuit structures fabricated therefrom. In the following description, numerous specific details such as specific layouts or material systems are set forth in order to provide a thorough understanding of embodiments of the present disclosure. Those skilled in the art will appreciate that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features such as single or dual damascene processing are not described in detail so as not to unnecessarily obscure embodiments of the present disclosure. Additionally, it will be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations are described as multiple discrete operations in sequence in the manner most helpful for understanding the present disclosure, but the order of the description should not be construed as implying that these operations are necessarily order-dependent. In particular, these operations need not be performed in the order presented.

[0026] In the following description, certain terms may also be used for reference purposes only and are thus not intended to be limiting. For example, terms such as "upper", "lower", "above", "below", "bottom", and "top" refer to the directions in the accompanying drawings to which they are referred. Terms such as "front", "rear", "back", and "side" describe the orientation and / or position of parts of components within a consistent but arbitrary reference system, made clear by reference to the text describing the components in question and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words of similar import.

[0027] The embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL generally encompasses everything up to (but not including) the deposition of the metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any circuitry).

[0028] The embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bond sites for chip-to-package connections. In the BEOL part of the fabrication stage, contacts (pads), interconnect lines, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in BEOL.

[0029] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although FEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to BEOL processing. Similarly, although BEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to FEOL processing.

[0030] One or more embodiments described herein relate to multi-version library cell disposition when parallel interconnect lines (e.g., metal 1 lines) and gate lines are misaligned. Embodiments may relate to technology nodes of 10 nm or less. Embodiments may include or relate to a cell layout that enables higher performance cells in the same or smaller footprint relative to previous technology nodes. In an embodiment, an interconnect line covering a gate line is fabricated to have an increased density relative to the underlying gate line. Such embodiments may achieve an increase in pin hits, increased routing possibilities, or increased access to cell pins. Embodiments may be implemented to provide a block-level density greater than 6%.

[0031] To provide context, the next parallel level of gates and interconnects (commonly referred to as metal 1, where the metal 0 layer extends orthogonally between metal 1 and the gate lines) needs to be aligned at the block level. However, in an embodiment, the pitch of the metal 1 lines is made different from (e.g., less than) the pitch of the gate lines. Two standard cell versions (e.g., two different cell patterns) are made available for each cell to accommodate the pitch difference. The particular version selected is placed following rules adhered to at the block level. If selected improperly, then dirty registration (DR) may occur. According to embodiments of the present disclosure, a higher metal layer (e.g., metal 1 or M1) having an increased pitch density relative to the underlying gate line is implemented. In an embodiment, such methods implement aggressive scaling to provide an improved cost per transistor for, e.g., a 10 nanometer (10 nm) technology node.

[0032] As a comparative example, Figure 1 A first view illustrating a conventional cell layout for a memory cell.

[0033] Reference Figure 1 , an exemplary 14 nanometer (14 nm) layout 100 includes a bit cell 102. The bit cell 102 includes a gate or poly line 104 and a metal 1 (M1) line 106. In the example shown, the poly line 104 has a 1x pitch, and the M1 line 106 has a 1x pitch. In a particular embodiment, the poly line 104 has a 70 nm pitch, and the M1 line 106 has a 70 nm pitch.

[0034] In contrast to Figure 1 compared to Figure 2 A first view illustrating a cell layout for a memory cell having an increased metal 1 pitch density relative to the underlying gate line according to an embodiment of the present disclosure.

[0035] Reference Figure 2, the exemplary 10 nanometer (10 nm) layout 200 includes bit cells 202. The bit cell 202 includes a gate or polysilicon line 204 and a metal 1 (M1) line 206. In the example shown, the polysilicon line 204 has a 1x pitch, and the M1 line 206 has a 0.67x pitch. The result is an overlap line 205, which includes an M1 line directly above the polysilicon line. In a particular embodiment, the polysilicon line 204 has a 54 nm pitch, and the M1 line 206 has a 36 nm pitch.

[0036] Compared to the layout 100, in the layout 200, the M1 pitch is less than the gate pitch, leaving an extra line (205) empty for every three lines (e.g., for every two polysilicon lines, there are three M1 lines). In an embodiment, the contact to the polysilicon is achieved through an active gate on contact (COAG) arrangement.

[0037] More generally referring to Figure 2 , in an embodiment, the integrated circuit structure includes memory bit cells 202 on a substrate. The memory bit cell 202 includes first and second gate lines 204 parallel along a second direction 2 of the substrate. The first and second gate lines 204 have a first pitch along a first direction (1) of the substrate, and the first direction (1) is perpendicular to the second direction (2). First, second, and third interconnect lines 206 are above the first and second gate lines 204. The first, second, and third interconnect lines 206 are parallel along the second direction (2) of the substrate. The first, second, and third interconnect lines 206 have a second pitch along the first direction, where the second pitch is less than the first pitch.

[0038] As applicable throughout this disclosure, the gate line 204 may be referred to as being on a track used to form a grid structure. The interconnect line 206 may also be referred to as being on a track used to form a grid structure. In an embodiment, the term "grid" for the gate line or interconnect line is used herein to refer to a grid structure with a tight pitch. In one such embodiment, the tight pitch cannot be directly achieved by conventional lithography. For example, as is known in the art, a pattern based on conventional lithography may be formed first, but the pitch can be halved by using spacer mask patterning. Even further, the original pitch can be quartered by a second round of spacer mask patterning. Thus, the grid-like patterns described herein may have gate lines or interconnect lines spaced at a constant pitch and having a constant width. The patterns can be made by pitch halving or pitch quartering or other pitch division methods.

[0039] In an embodiment, an increased pin hit is achieved by increasing the density of the first-level interconnect lines relative to the underlying gate lines extending parallel to the interconnect lines. Figure 3AThe figure shows a top view of increased pin hits of multiple Metal 2 (M2) lines according to an embodiment of the present disclosure, the multiple Metal 2 (M2) lines being in a layout having Metal 1 (M1), the Metal 1 (M1) having an increased density relative to underlying gate lines.

[0040] Reference Figure 3A , showing three gate lines 302A (also referred to as poly lines). Four Metal 1 (M1) lines 304A extend parallel to the gate lines 302A. Although not shown, Metal 0 (M0) lines may extend orthogonally between the gate lines 302A and the Metal 1 (M1) lines 304A. The overlying Metal 2 (M2) lines 306A are shown extending orthogonally to the underlying M1 lines 304A. In a particular embodiment, VCC 308A and VSS 310A are shown. Pins are labeled 'a' and 'o'. Five M2 tracks 306A access pin a, and five M2 tracks 306A access pin o.

[0041] Compared with Figure 3A that, Figure 3B The figure shows a top view of conventional pin hits of multiple Metal 2 (M2) lines, the multiple Metal 2 (M2) lines being in a layout having Metal 1 (M1), the Metal 1 (M1) having the same density relative to underlying gate lines.

[0042] Reference Figure 3B , showing two gate lines 302B (also referred to as poly lines). Two Metal 1 (M1) lines 304B extend parallel to the gate lines 302B. Although not illustrated, Metal 0 (M0) lines may extend orthogonally between the gate lines 302B and the Metal 1 (M1) lines 304B. The overlying Metal 2 (M2) lines 306B are shown extending orthogonally to the underlying M1 lines 304B. In a particular embodiment, VCC 308B and VSS 310B are shown. Pins are labeled 'a' and 'o'. Five M2 tracks 306B access pin o, but only three M2 tracks 306B access pin a. At position 350, pin access is blocked due to the presence of a power connection.

[0043] The embodiments described herein provide methods for handling cells in cases where gate lines and Metal 1 lines are misaligned. In an embodiment, two versions of each standard cell with targeted block-level placement are made available for each cell. In an embodiment, there is no restriction on the layout, as a suitable choice between the two versions allows for a scenario where any cell can be placed anywhere.

[0044] As a first standard cell example, Figure 4FIG. (a) shows a plan view of an inverter cell with an even poly pitch relative to a NAND cell with an odd poly pitch according to an embodiment of the present disclosure. Refer to Figure 4 In part (a), cell 400 (dashed box) includes gate lines 402. Metal 1 lines 404 are shown covering the gate lines 402, with one additional M1 line 404 for every three gate lines 402. The M1 lines are on the left and right sides of the cell boundary 400. Refer to Figure 4 In part (b), cell 450 (dashed box) includes gate lines 452. Metal 1 lines 454 are shown covering the gate lines 452, with one additional M1 line 454 for every two gate lines 452. The M1 lines are on the left side of the cell boundary 450, but not on the right side of the cell boundary 450. As a result of this layout, in a scenario where a first inverter is adjacent to NAND cell 450 and the NAND cell 450 is adjacent to a second inverter (as viewed from left to right), dirty registration (DR) occurs between the NAND cell 450 and the second inverter because the metal 1 lines may touch where the NAND cell and the second inverter are adjacent to each other.

[0045] As a second standard cell example, Figure 5 FIG. (a) shows a plan view of an inverter cell with an even poly pitch relative to a NAND cell with an odd poly pitch according to another embodiment of the present disclosure. Refer to Figure 5 In part (a), cell 500 (dashed box) includes gate lines 502. Metal 1 lines 504 are shown covering the gate lines 502, with one additional M1 line 504 for every three gate lines 502. The M1 lines are on the left and right sides of the cell boundary 500. Refer to Figure 5 In part (b), cell 550 (dashed box) includes gate lines 552. Metal 1 lines 554 are shown covering the gate lines 552, with one additional M1 line 554 for every four gate lines 552. The M1 lines are on the right side of the cell boundary 550, but not on the left side of the cell boundary 550. As a result of this layout, in a scenario where a first inverter is adjacent to NAND cell 550 and the NAND cell 550 is adjacent to a second inverter (as viewed from left to right), dirty registration (DR) occurs between the NAND cell 550 and the first inverter because the metal 1 lines may touch where the NAND cell and the first inverter are adjacent to each other.

[0046] Figure 6 FIG. shows a cross-sectional view of two different layouts for the same standard cell according to an embodiment of the present disclosure.

[0047] Refer to Figure 6In part (a), a set of gate lines 604A is disposed over a substrate 602A. A set of metal 1 (M1) interconnects 606A is disposed over the set of gate lines 604A. The set of metal 1 (M1) interconnects 606A has a pitch that is closer than that of the set of gate lines 604A. However, the outermost metal 1 (M1) interconnect 606A is laterally aligned with the outermost gate line 604A. For labeling purposes, as used throughout this disclosure, the Figure 6 alignment arrangement of part (a) is referred to as having an even (E) alignment.

[0048] Compared with part (a), referring to Figure 6 part (b), a set of gate lines 604B is disposed over a substrate 602B. A set of metal 1 (M1) interconnects 606B is disposed over the set of gate lines 604B. The set of metal 1 (M1) interconnects 606B has a pitch that is closer than that of the set of gate lines 604B. The outermost metal 1 (M1) interconnect 606B is not laterally aligned with the outermost gate line 604B. For labeling purposes, as used throughout this disclosure, the Figure 6 misalignment arrangement of part (b) is referred to as having an odd (O) alignment.

[0049] Figure 7 FIG. shows a plan view of four different cell arrangements indicating even (E) or odd (O) labeling in accordance with an embodiment of the present disclosure.

[0050] Referring to Figure 7 part (a), cell 700A has a gate (or poly) line 702A and a metal 1 (M1) line 704A. Cell 700A is labeled as an EE cell because the left side of cell 700A and the right side of cell 700A have aligned gate lines 702A and M1 lines 704A. In contrast, referring to Figure 7 part (b), cell 700B has a gate (or poly) line 702B and a metal 1 (M1) line 704B. Cell 700B is labeled as an OO cell because the left side of cell 700B and the right side of cell 700B have misaligned gate lines 702B and M1 lines 704B.

[0051] Referring to Figure 7 part (c), cell 700C has a gate (or poly) line 702C and a metal 1 (M1) line 704C. Cell 700C is labeled as an EO cell because the left side of cell 700C has aligned gate lines 702C and M1 lines 704C, but the right side of cell 700C has misaligned gate lines 702C and M1 lines 704C. In contrast, referring to Figure 7In part (d), cell 700D has a gate (or poly) line 702D and a metal 1 (M1) line 704D. Cell 700D is labeled as an OE cell because the left side of cell 700D has misaligned gate line 702D and M1 line 704D, but the right side of cell 700D has aligned gate line 702D and M1 line 704D.

[0052] As a basis for choosing the first or second version of a standard cell type for placement, Figure 8 FIG. shows a plan view of a block-level poly grid according to an embodiment of the present disclosure. Refer Figure 8 , the block-level poly grid 800 includes gate lines 802 extending parallel in direction 804. Marked cell layout boundaries 806 and 808 are shown extending in a second orthogonal direction. The gate lines 802 alternate between even (E) and odd (O) markings.

[0053] Figure 9 FIG. shows an exemplary acceptable (pass) layout based on standard cells having different versions according to an embodiment of the present disclosure. Refer Figure 9 , layout 900 includes three cells of type 700C / 700D placed between boundaries 806 and 808 in order from left to right: 700D, an adjacent first 700C, and a separated second 700C. The choice between 700C and 700D is based on the alignment of the E or O markings on the corresponding gate line 802. Layout 900 also includes cells of type 700A / 700B placed below boundary 808 in order from left to right: a first 700A separated from a second 700A. The choice between 700A and 700B is based on the alignment of the E or O markings on the corresponding gate line 802. Layout 900 is a pass layout in the sense that dirty registration (DR) does not occur in layout 900. It will be understood that p marks power, and a, b, c, or o are exemplary pins. In arrangement 900, the power lines p are aligned with each other across boundary 808.

[0054] More generally referring to Figure 9 , according to an embodiment of the present disclosure, an integrated circuit structure includes a plurality of gate lines 802 extending parallel in a first direction of a substrate and having a pitch in a second direction orthogonal to the first direction. A first version 700C of a cell type is above a first portion of the plurality of gate lines 802. The first version 700C of the cell type includes a first plurality of interconnect lines having a second pitch in the second direction, the second pitch being less than the first pitch. A second version 700D of the cell type is laterally adjacent to the first version 700C of the cell type in the second direction above a second portion of the plurality of gate lines 802. The second version 700D of the cell type includes a second plurality of interconnect lines having the second pitch in the second direction. The second version 700D of the cell type is structurally different from the first version 700C of the cell type.

[0055] In an embodiment, each of the first plurality of interconnect lines of the first version 700C of the cell type is aligned with each of the plurality of gate lines 802 in the first direction at a first edge (e.g., left edge) of the first version 700C of the cell type in the second direction but not at a second edge (e.g., right edge) of the first version 700C of the cell type. In one such embodiment, the first version 700C of the cell type is the first version of a NAND cell. Each of the second plurality of interconnect lines of the second version 700D of the cell type is not aligned with each of the plurality of gate lines 802 in the first direction at a first edge (e.g., left edge) of the second version 700D of the cell type in the second direction, but is aligned with each of the plurality of gate lines 802 in the first direction at a second edge (e.g., right edge) of the second version 700D of the cell type. In one such embodiment, the second version 700D of the cell type is the second version of a NAND cell.

[0056] In another embodiment, the first and second versions are selected from cell types 700A and 700B. Each of the first plurality of interconnect lines of the first version 700A of the cell type is aligned with each of the plurality of gate lines 802 in the first direction at both edges of the first version 700A of the cell type in the second direction. In one embodiment, the first version 700A of the cell type is the first version of an inverter cell. It will be appreciated that each of the second plurality of interconnect lines of the second version 700B of the cell type will, conversely, not be aligned with each of the plurality of gate lines 802 in the first direction at both edges of the second version 700B of the cell type in the second direction. In one embodiment, the second version 700B of the cell type is the second version of an inverter cell.

[0057] Figure 10 Illustrated is an exemplary unacceptable (failed) layout based on standard cells having different versions in accordance with embodiments of the present disclosure. Refer to Figure 10, layout 1000 includes three cells of type 700C / 700D as placed between borders 806 and 808 in order from left to right: 700D, the first 700C adjacent, and the second 700C separated. As shown, the appropriate selection between 700C and 700D is based on the alignment of the E or O marks on the corresponding gate line 802. However, layout 1000 also includes cells of type 700A / 700B as placed below border 808 in order from left to right: the first 700A is separated from the second 700A. The difference between layout 1000 and 900 is that the second 700A is moved to the left by one line. Although the selection between 700A and 700B should be based on the alignment of the E or O marks on the corresponding gate line 802, it does not, and the second cell 700A is misaligned, and one consequence of this situation is the misaligned power (p) line. Layout 1000 is a failed cell because dirty registration (DR) appears in layout 1000.

[0058] Figure 11 Another exemplary acceptable (pass) layout based on standard cells with different versions according to an embodiment of the present disclosure is illustrated. Figure 11 , layout 1100 includes three cells of type 700C / 700D placed between borders 806 and 808 in order from left to right: 700D, the first 700C adjacent, and the second 700C separated. The selection between 700C and 700D is based on the alignment of the E or O mark on the corresponding gate line 802. Layout 1100 also includes cells of type 700A / 700B placed below border 808 in order from left to right: 700A is separated from 700B. The position of 700B is the same as the position of 700A in layout 1000, but the selected cell 700B is based on the appropriate alignment of the O mark on the corresponding gate line 802. In the sense that dirty registration (DR) does not appear in layout 1100, layout 1100 is a cell that is passed. It will be understood that p marks power supply, and a, b, c or o are exemplary pins. In arrangement 1100, power line p is aligned with each other across border 808.

[0059] Common Reference Figure 10 and Figure 11, A method of fabricating a layout for an integrated circuit structure includes marking alternating ones of a plurality of gate lines 802 parallel along a first direction as even (E) or odd (O) along a second direction. Then, positions are selected for cell types above the plurality of gate lines 802. The method further includes: depending on the position, selecting between a first version of the cell type and a second version of the cell type, the second version being structurally different from the first version, wherein the selected version of the cell type has an even (E) or odd (O) marking for interconnection at an edge of the cell type along the second direction, and wherein the marking of the edge of the cell type matches the marking of each of the plurality of gate lines under the interconnection.

[0060] In an embodiment, the interconnection has a pitch along the second direction that is smaller than the pitch of the gate lines along the second direction. In an embodiment, each of the interconnections in the first version of the cell type is aligned with each of the plurality of gate lines along the first direction at two edges of the first version of the cell type along the second direction. In one such embodiment, each of the interconnections in the second version of the cell type is not aligned with each of the plurality of gate lines along the first direction at two edges of the second version of the cell type along the second direction. In a particular such embodiment, the cell type is an inverter cell.

[0061] In another embodiment, each of the interconnections in the first version of the cell type is aligned with each of the plurality of gate lines along the first direction at a first edge of the first version of the cell type along the second direction but not at a second edge of the first version of the cell type. In one such embodiment, each of the interconnections in the second version of the cell type is aligned with each of the plurality of gate lines along the first direction at a second edge of the second version of the cell type along the second direction but not at a first edge of the second version of the cell type. In a particular embodiment, the cell type is a NAND cell.

[0062] The cells and cell versions described herein may be included in a cell library. In an embodiment, a library for cell layout design includes a first version of a cell type for placement above a first portion of a plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines. The library also includes a second version of the cell type for placement above a second portion of the plurality of gate lines, the second version of the cell type including a second plurality of interconnect lines, the second version of the cell type being structurally different from the first version of the cell type.

[0063] Continuing with the exemplary applications of memory cells 100 and 200, as a comparative example, Figure 12 A second view of a conventional cell layout 1200 for a memory cell is illustrated.

[0064] Reference Figure 12, showing a 14 nm bit cell 102, which has an N-diffusion 1202 (e.g., a P-type doped active region, such as a boron-doped diffusion region of a lower substrate) and a P-diffusion 1204 (e.g., an N-type doped active region, such as a phosphorus- and / or arsenic-doped diffusion region of a lower substrate), where the M1 lines are removed for clarity. The layout 1200 of the bit cell 102 includes a gate or poly line 104, a trench contact 1206, a gate contact 1208 (specific to the 14 nm node), and a contact via 1210.

[0065] Compared with Figure 12 in comparison, Figure 13 FIG. shows a second view of a cell layout 1300 for a memory cell having a closer M1 pitch than a gate line pitch according to an embodiment of the present disclosure.

[0066] Referring to Figure 13 , showing a 10 nm bit cell 202, which has an N-diffusion 1302 (e.g., a P-type doped active region, such as a boron-doped diffusion region of a lower substrate) and a P-diffusion 1304 (e.g., an N-type doped active region, such as a phosphorus- and / or arsenic-doped diffusion region of a lower substrate), where the M1 lines are removed for clarity. The layout 1300 of the bit cell 202 includes a gate or poly line 204, a trench contact 1306, a gate via 1308 (specific to the 10 nm node), and a trench contact via 1310.

[0067] In comparing the layouts 1200 and 1300, according to an embodiment of the present disclosure, in the 14 nm layout, the internal nodes are connected only through gate contacts (GCN). Due to the poly-to-GCN space constraint, a performance-enhanced layout cannot be created in the same coverage area. In the 10 nm layout, the design allows placing a contact (VCG) on the gate to eliminate the need for poly contacts. In one embodiment, this arrangement uses M1 to achieve the connection of internal nodes, allowing for an additional active region density (e.g., an increased number of fins) within the 14 nm coverage area. In the 10 nm layout, once the contact-on-active-gate (COAG) architecture is used, the spacing between diffusion regions can be made smaller because they are not limited by the spacing between trench contacts and gate contacts. In an embodiment, Figure 12 the layout 1200 of Figure 13 is referred to as a 112 (1 fin pull-up, 1 fin passgate, 2 fin pull-down) arrangement. In contrast, Figure 12within the same coverage area as the 112 layout. In an embodiment, the 122 layout provides improved performance compared to the 112 arrangement.

[0068] As a comparative example, Figure 14 A third view illustrating a conventional cell layout 1400 for a memory cell.

[0069] Reference Figure 14 , showing a 14 nm bit cell 102, which has a metal 0 (M0) line 1402, with the poly lines removed for clarity. Also shown are metal 1 (M1) lines 106, contact vias 1210, and via 0 structures 1404.

[0070] Compared with Figure 14 Figure 15 A third view illustrating a cell layout for a memory cell having an M1 pitch that is closer than the gate line pitch according to an embodiment of the present disclosure.

[0071] Reference Figure 15 , showing a 10 nm bit cell 202, which has a metal 0 (M0) line 1502, with the poly lines removed for clarity. Also shown are metal 1 (M1) lines 206, gate vias 1308, trench contact vias 1310, and via 0 structures 1504. In comparison Figure 14 and Figure 15 , according to an embodiment of the present disclosure, for a 14 nm layout, internal nodes are connected only through gate contacts (GCN), while for a 10 nm layout, free M1 lines are used to connect one of the internal nodes.

[0072] With joint reference to Figure 2 , Figure 13 and Figure 15 , according to an embodiment of the present disclosure, an integrated circuit structure includes a memory bit cell 202 on a substrate. The memory bit cell 202 includes a first active region (top 1302), a second active region (top 1304), a third active region (bottom 1304), and a fourth active region (bottom 1302) parallel along a first direction (1) of the substrate. A first gate line (left 204) and a second gate line (right 204) are above the first, second, third, and fourth active regions 1302 / 1304. The first and second gate lines 204 are parallel along a second direction (2) of the substrate, and the second direction (2) is perpendicular to the first direction (1). A first interconnect line (far left 206), a second interconnect line (near left 206), and a third interconnect line (near right 206) are above the first and second gate lines 204. The first, second, and third interconnect lines 206 are parallel along the second direction (2) of the substrate.

[0073] ​In an embodiment, a first interconnect (far left 206) and a second interconnect (near left 206) are electrically connected to first and second gate lines 204 at positions of the first and second gate lines 204 above one or more of the first, second, third, and fourth active regions 1302 / 1304 (e.g., at so-called “active gate” positions). In one embodiment, the first interconnect (far left 206) and the second interconnect (near left 206) are electrically connected to the first and second gate lines 204 by a plurality of intermediate interconnects 1504 that are perpendicular between the first and second interconnects 206 and the first and second gate lines 204. The plurality of intermediate interconnects 1504 are parallel along a first direction (1) of the substrate.

[0074] In an embodiment, a third interconnect (near right 206) electrically couples a pair of gate electrodes of a memory bit cell 202, the pair of gate electrodes being included in the first and second gate lines 204. In another embodiment, a third interconnect (near right 206) electrically couples a pair of trench contacts of a memory bit cell 202, the pair of trench contacts being included in a plurality of trench contact lines 1306.

[0075] In an embodiment, a first active region (top 1302) is a P-type doped active region (e.g., to provide N-diffusion for an NMOS device), a second active region (top 1304) is an N-type doped active region (e.g., to provide P-diffusion for a PMOS device), a third active region (bottom 1304) is an N-type doped active region (e.g., to provide P-diffusion for a PMOS device), and a fourth active region (bottom 1302) is an N-type doped active region (e.g., to provide N-diffusion for an NMOS device). In an embodiment, the first, second, third, and fourth active regions 1302 / 1304 are in a silicon fin. In an embodiment, a memory bit cell 202 includes a pull-up transistor based on a single silicon fin, a transmission gate transistor based on two silicon fins, and a pull-down transistor based on two silicon fins.

[0076] In an embodiment, the first and second gate lines 204 alternate with each of a plurality of trench contact lines 1306 that are parallel along a second direction (2) of the substrate. The plurality of trench contact lines 1306 include trench contacts of a memory bit cell 202. The first and second gate lines 204 include gate electrodes of a memory bit cell 202.

[0077] In an embodiment, the first and second gate lines 204 have a first pitch along a first direction (1). The first, second, and third interconnect lines 206 have a second pitch along the first direction (1). In one such embodiment, the second pitch is less than the first pitch. In a particular such embodiment, the first pitch ranges from 50 nanometers to 60 nanometers, and the second pitch ranges from 30 nanometers to 40 nanometers. In a particular such embodiment, the first pitch is 54 nanometers, and the second pitch is 36 nanometers.

[0078] In an embodiment, the layout described herein is compatible with uniform plugs and mask patterns including a uniform fin trim mask. The layout can be compatible with non-EUV processes. Additionally, the layout may only require the use of an intermediate fin trim mask. Compared to conventional layouts, the embodiments described herein can achieve increased density in terms of area. Embodiments can be implemented to provide a layout-efficient memory implementation in advanced self-alignment process technologies. Advantages can be achieved in terms of die area and / or memory performance. Circuit technologies can be uniquely implemented by such layout methods.

[0079] One or more embodiments described herein relate to the integration of semiconductor devices, such as metal-oxide-semiconductor (MOS) device integration. As an example, Figure 16A FIG. shows a cross-sectional view of a non-planar semiconductor device according to an embodiment of the present disclosure. Figure 16B FIG. shows according to an embodiment of the present disclosure along Figure 16A a-a' axis of the semiconductor device taken planar view.

[0080] Referring to Figure 16A , the semiconductor structure or device 1600 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 1604 and a sub-fin region 1605) formed from a substrate 1602 and within isolation regions 1606. Gate lines 1608 are disposed over the protruding portions 1604 of the non-planar active region and over a portion of the isolation regions 1606. As shown, the gate lines 1608 include gate electrodes 1650 / 1699 and a gate dielectric layer 1652. In one embodiment, the gate lines 1608 may further include a dielectric capping layer 1654. Also seen from this perspective are gate contacts 1614 and upper-overlying gate contact vias 1616 and upper-overlying metal interconnects 1660, all of which are disposed in an interlayer dielectric stack or layer 1670.

[0081] From Figure 16AAlso seen from the perspective of the angle, in one embodiment, the gate contact 1614 is disposed above the isolation region 1606, but not above the non-planar active region. However, the arrangement of the semiconductor structure or device 1600 places the gate contact above the isolation region. For certain technology nodes, such an arrangement may be considered an inefficient use of layout space in certain applications, or it may be a limitation of the cell design. In another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region to provide a contact-on-active-gate (COAG) architecture.

[0082] It will be understood that for the sake of illustration, the gate line 1608 is shown above three protruding fin portions 1604, but is not limited thereto. For example, the gate line may instead be formed above 1, 2, 4, or even more protruding fin portions. As may be applicable throughout the present disclosure, the protruding fin portions 1604 may be referred to as forming a grid structure. In an embodiment, the term "grid" of the protruding fin portions 1604 is used herein to refer to a closely pitched grid structure. In one such embodiment, the close pitch cannot be directly achieved by conventional lithography. For example, as is known in the art, a pattern based on conventional lithography may first be formed, but the pitch may be halved by using spacer mask patterning. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Thus, the grid-like pattern described herein may have protruding fin portions 1604 that are spaced apart at a constant pitch and have a constant width. The pattern may be fabricated by pitch halving or pitch quartering or other pitch division methods.

[0083] Reference Figure 16B , the gate line 1608 is shown disposed above the protruding fin portions 1604. From this perspective, the source and drain regions 1604A and 1604B of the protruding fin portions 1604 can be seen. In one embodiment, the source and drain regions 1604A and 1604B are doped portions of the original material of the protruding fin portions 1604. In another embodiment, the material of the protruding fin portions 1604 is removed and replaced, for example, by epitaxial deposition with another semiconductor material. In either case, the source and drain regions 1604A and 1604B can extend below the height of the dielectric layer 1606, i.e., into the sub-fin region 1605.

[0084] In an embodiment, the semiconductor structure or device 1600 is a non-planar device such as, but not limited to, a fin-FET or a triple-gate device. In such embodiments, the corresponding semiconductor channel region is composed of or formed in a three-dimensional body. In one such embodiment, the gate electrode and the gate electrode material of the gate line 1608 at least surround the top surface and a pair of sidewalls of the three-dimensional body.

[0085] The substrate 1602 may be composed of a semiconductor material that can withstand the manufacturing process and in which charge can migrate. In an embodiment, the substrate 1602 is a bulk substrate composed of crystalline silicon, silicon / germanium, or a germanium layer, which is doped with charge carriers such as, but not limited to, phosphorus, arsenic, antimony, boron, gallium, or a combination thereof to form the active region 1604. In one embodiment, the concentration of silicon atoms in the bulk substrate 1602 is greater than 97%. In another embodiment, the bulk substrate 1602 is composed of an epitaxial layer grown on top of a different crystalline substrate (e.g., a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate). The bulk substrate 1602 may alternatively be composed of III-V materials. In an embodiment, the bulk substrate 1602 is composed of III-V materials such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, the bulk substrate 1602 is composed of III-V materials, and the charge carrier dopant impurity atoms are atoms such as, but not limited to, magnesium, beryllium, zinc, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0086] The isolation region 1606 may be composed of a material suitable for final electrical isolation or for helping to isolate portions of the permanent gate structure from the underlying bulk substrate, or for isolating active regions (such as fin active regions) formed within the underlying bulk substrate. For example, in one embodiment, the isolation region 1606 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0087] In an embodiment, the gate dielectric layer 1652 is composed of a high-K material. For example, in one embodiment, the gate dielectric layer 1652 is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead niobate zincate, or a combination thereof. Additionally, a portion of the gate dielectric layer may include a native oxide layer formed from the top few layers of the substrate 1602. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 1652 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride.

[0088] In an embodiment, the layer 1650 of the gate electrode 1650 / 1699 is composed of a non-work function setting conductive fill material formed above the work function setting layer 1699. In a particular embodiment, the transistor 1600 is an N-type (NMOS) transistor, and the work function setting layer 1699 has an N-type work function. In another particular embodiment, the transistor 1600 is a P-type (PMOS) transistor, and the work function setting layer 1699 has a P-type work function.

[0089] In one such embodiment, the conductive fill material 1650 comprises a material such as, but not limited to, tungsten (W), aluminum (Al), or copper (Cu). In one embodiment, one or more conductive barrier layers, such as titanium nitride or tantalum nitride, are between layer 1650 and 1699 of the gate electrode. In some implementations, the gate electrode may consist of a "U" - shaped structure that includes a bottom portion generally parallel to the surface of the substrate and two sidewall portions generally perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer generally parallel to the top surface of the substrate and not including sidewall portions generally perpendicular to the top surface of the substrate. In additional implementations of the present disclosure, the gate electrode may consist of a combination of a U - shaped structure and a planar non - U - shaped structure. For example, the gate electrode may consist of one or more U - shaped metal layers formed on top of one or more planar non - U - shaped layers.

[0090] In an embodiment, the dielectric cap layer 1654 and / or dielectric spacer associated with the gate - electrode stack may be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of the permanent gate structure from adjacent or overlying conductive contacts, such as self - aligned contacts. For example, in one embodiment, the dielectric cap layer 1654 and / or dielectric spacer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon - doped silicon nitride.

[0091] The gate contact 1614, overlying gate - contact via 1616, and / or overlying metal interconnect 1660 may be composed of a conductive material. In an embodiment, one or more of the contacts, interconnects, or vias are composed of a metal component. The metal component may be a pure metal such as tungsten, nickel, or cobalt, or may be an alloy such as a metal - metal alloy or a metal - semiconductor alloy (e.g., a silicide material). In a particular embodiment, one or more of the gate contact 1614, overlying gate - contact via 1616, or overlying metal interconnect 1660 includes a barrier layer and a conductive fill material. In one such embodiment, the barrier layer is composed of titanium and / or titanium nitride or tantalum and / or tantalum nitride. In an embodiment, the conductive fill material is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or an alloy thereof. Generally, as used throughout this disclosure, an interconnect line is sometimes also referred to in the art as a trace, a line, a wire, a metal line, or simply an interconnect.

[0092] In an embodiment, the interlayer dielectric stack or layer 1670 consists of or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0093] In an embodiment (although not shown), providing the structure 1600 involves forming a contact pattern that is substantially perfectly aligned with an existing gate pattern while eliminating the use of lithography steps with an overly tight registration budget. In one such embodiment, the method enables the use of a highly selective wet etch (e.g., relative to conventionally implemented dry etch or plasma etch) to generate contact openings. In an embodiment, the contact pattern is formed by leveraging the existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the method enables the elimination of the need for a lithography operation that was originally critical for generating the contact pattern as used in conventional methods. In an embodiment, the trench contact grid is not separately patterned, but rather the trench contact grid is formed between the polycrystalline (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid patterning but before the gate grid cutting.

[0094] In addition, the gate stack structure 1608 can be fabricated by a replacement gate process. In such a scenario, a dummy gate material such as polysilicon or silicon nitride pillar material can be removed and replaced with a permanent gate electrode material. In one such embodiment, contrary to being completed from an earlier process, a permanent gate dielectric layer is also formed in this process. In an embodiment, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gate consists of polysilicon or amorphous silicon, and the dry etch process including the use of SF6 is utilized to remove the dummy gate. In another embodiment, the dummy gate consists of polysilicon or amorphous silicon, and the wet etch process including the use of NH4OH or tetramethylammonium hydroxide dissolved in water is utilized to remove the dummy gate. In one embodiment, the dummy gate consists of silicon nitride, and the wet etch including phosphoric acid dissolved in water is utilized to remove the dummy gate.

[0095] In an embodiment, one or more of the methods described herein generally contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process to achieve structure 1600. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees Celsius, for example, after forming the gate dielectric layer. The annealing is performed prior to forming the permanent contacts.

[0096] In an embodiment, prior to (e.g., in addition to) forming a gate contact structure (such as a via) above an active portion of a gate and in the same layer as a trench contact via, one or more embodiments of the present disclosure include first using a gate-aligned trench contact process. Such a process can be implemented to form trench contact structures for semiconductor structure fabrication (e.g., for integrated circuit fabrication). In an embodiment, the trench contact pattern is formed to be aligned with an existing gate pattern. In contrast, conventional methods typically involve additional lithography processes with tight registration of a lithographic contact pattern with an existing gate pattern in combination with selective contact etching. For example, a conventional process can include patterning of a polycrystalline (gate) grid with separate patterning of contact features.

[0097] In a particular embodiment, each of the trench contacts includes a barrier layer and a conductive fill material. In one such embodiment, the barrier layer consists of titanium and / or titanium nitride or tantalum and / or tantalum nitride. In an embodiment, the conductive fill material consists of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or an alloy thereof.

[0098] It will be appreciated that not all aspects of the processes described above need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, it is not necessary to form a dummy gate prior to fabricating a gate contact above an active portion of a gate stack. The gate stack described above can actually be the permanent gate stack as initially formed. Also, the processes described herein can be used to fabricate one or more semiconductor devices. The semiconductor device can be a transistor or a similar device. For example, in an embodiment, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. And, in an embodiment, the semiconductor device has a three-dimensional architecture such as a triple-gate device, an independently accessed double-gate device, or a FIN-FET. One or more embodiments can be particularly useful for fabricating semiconductor devices at a 10 nanometer (10 nm) or smaller technology node.

[0099] In an embodiment, as also used throughout this description, lithography operations are performed using 193 nm immersion lithography (i193), extreme ultraviolet light (EUV), and / or electron beam direct write (EBDW) lithography or similar methods. Positive or negative photoresists can be used. In one embodiment, the lithography mask is a three-layer mask composed of a topographical mask portion, a layer of an anti-reflection coating (ARC), and a photoresist layer. In a particular such embodiment, the topographical masking portion is a carbon hard mask (CHM) layer, and the layer of the anti-reflection coating is a silicon ARC layer.

[0100] The embodiments disclosed herein can be used to fabricate a variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories can be fabricated. Additionally, the integrated circuits or other microelectronic devices can be used in a variety of electronic devices known in the art. For example, in a computer system (e.g., desktop computer, laptop computer, server), cellular phone, personal electronic product, etc., the integrated circuit can be coupled to a bus and other components in the system. For example, a processor can be coupled to a memory, chipset, etc. via one or more buses. Each of the processor, memory, and chipset can potentially be fabricated using the methods disclosed herein.

[0101] Figure 17 FIG. 1700 illustrates a computing device 1700 in accordance with one implementation of the present disclosure. The computing device 1700 houses a board 1702. The board 1702 can include a plurality of components including, but not limited to, a processor 1704 and at least one communication chip 1706. The processor 1704 is physically and electrically coupled to the board 1702. In some implementations, at least one communication chip 1706 is also physically and electrically coupled to the board 1702. In additional implementations, the communication chip 1706 is part of the processor 1704.

[0102] Depending on its application, the computing device 1700 can include other components that may or may not be physically and electrically coupled to the board 1702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, crypto-processors, chipset, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0103] The communication chip 1706 enables wireless communication to transfer data to and from the computing device 1700. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can transfer data through non-solid media by using modulated electromagnetic radiation. This term does not mean that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 1706 can implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols named 3G, 4G, 5G and above. The computing device 1700 can include multiple communication chips 1706. For example, the first communication chip 1706 can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip 1706 can be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0104] The processor 1704 of the computing device 1700 includes an integrated circuit die encapsulated within the processor 1704. In some implementations of the present disclosure, the integrated circuit die of the processor includes a cell layout with two versions of standard cells, for example provided by a metal line pattern having a pitch tighter than that of the underlying gate line pattern, implemented according to an embodiment of the present disclosure. The term "processor" can refer to any device or part of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0105] The communication chip 1706 also includes an integrated circuit die encapsulated within the communication chip 1706. According to another implementation of an embodiment of the present disclosure, the integrated circuit die of the communication chip includes a cell layout with two versions of standard cells, for example provided by a metal line pattern having a pitch tighter than that of the underlying gate line pattern, implemented according to an embodiment of the present disclosure.

[0106] In additional implementations, another component housed within the computing device 1700 can include an integrated circuit die that includes a cell layout with two versions of standard cells, for example provided by a metal line pattern having a pitch tighter than that of the underlying gate line pattern, implemented according to an embodiment of the present disclosure.

[0107] In various implementations, computing device 1700 can be a laptop computer, netbook, notebook computer, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In additional implementations, computing device 1700 can be any other electronic device that processes data.

[0108] Figure 18 The figures include an interposer 1800 that includes one or more embodiments of the present disclosure. Interposer 1800 is an intermediate substrate for bridging a first substrate 1802 to a second substrate 1804. The first substrate 1802 can be, for example, an integrated circuit die. The second substrate 1804 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 1800 is to extend connections to a wider pitch or to re-route connections to different connections. For example, interposer 1800 can couple an integrated circuit die to a ball grid array (BGA) 1806, which can then be coupled to the second substrate 1804. In some embodiments, the first and second substrates 1802 / 1804 are attached to opposite sides of the interposer 1800. In other embodiments, the first and second substrates 1802 / 1804 are attached to the same side of the interposer 1800. And, in additional embodiments, three or more substrates are interconnected by the interposer 1800.

[0109] Interposer 1800 can be formed of epoxy resin, glass fiber-reinforced epoxy, ceramic material, or a polymeric material such as polyimide. In additional implementations, the interposer can be formed of alternating rigid or flexible materials that can include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials.

[0110] The interposer may include metal interconnects 1808 and vias 1810, including but not limited to through-silicon vias (TSVs) 1812. The interposer 1800 may also include embedded devices 1814, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1800. According to embodiments of the present disclosure, the apparatuses or processes disclosed herein may be used in the fabrication of the interposer 1800. In one such embodiment, one or more of the components of the interposer 1800 include, for example, a cell layout having two versions of a standard cell provided by a metal line pattern having a pitch that is closer than the pitch of the underlying gate line pattern.

[0111] Accordingly, the embodiments described herein include multi-version library cell handling and integrated circuit structures fabricated therefrom.

[0112] The foregoing description of the illustrated implementations of embodiments of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as will be recognized by those skilled in the art.

[0113] Based on the foregoing detailed description, these modifications may be made to the present disclosure. The terms used in the appended claims should not be construed as limiting the present disclosure to the specific implementations disclosed in the specification and claims. Rather, the scope of the present disclosure will be determined entirely by the appended claims, which are to be construed in accordance with established principles of claim interpretation.

[0114] Example Embodiment 1: An integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is above a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch being less than the first pitch. A second version of the cell type is laterally adjacent to the first version of the cell type along the second direction above a second portion of the plurality of gate lines, the second version of the cell type including a second plurality of interconnect lines having the second pitch along the second direction, and the second version of the cell type being structurally different from the first version of the cell type.

[0115] Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein each of the first plurality of interconnect lines of the first version of the cell type is aligned with each of the plurality of gate lines along the first direction at two edges of the first version of the cell type along the second direction.

[0116] Example Embodiment 3: The integrated circuit structure of Example Embodiment 1 or 2, wherein the first version of the cell type is the first version of an inverter cell.

[0117] Example Embodiment 4: The integrated circuit structure of Example Embodiment 1, wherein each of the second plurality of interconnect lines of the second version of the cell type is not aligned with each of the plurality of gate lines along the first direction at two edges of the second version of the cell type along the second direction.

[0118] Example Embodiment 5: The integrated circuit structure of Example Embodiment 1 or 4, wherein the second version of the cell type is the second version of an inverter cell.

[0119] Example Embodiment 6: The integrated circuit structure of Example Embodiment 1, wherein each of the first plurality of interconnect lines of the first version of the cell type is aligned with each of the plurality of gate lines along the first direction at the first edge of the first version of the cell type but not at the second edge of the first version of the cell type along the second direction.

[0120] Example Embodiment 7: The integrated circuit structure of Example Embodiment 1 or 6, wherein the first version of the cell type is the first version of a NAND cell.

[0121] Example Embodiment 8: A method of fabricating a layout for an integrated circuit structure includes marking alternate ones of the plurality of gate lines parallel along the first direction as even (E) or odd (O) along the second direction. Then, positions are selected for the cell type above the plurality of gate lines. The method further includes selecting between the first version of the cell type and the second version of the cell type depending on the position, the second version being structurally different from the first version, wherein the selected version of the cell type has an even (E) or odd (O) marking for interconnection at the edge of the cell type along the second direction, and wherein the marking of the edge of the cell type matches the marking of each of the plurality of gate lines under the interconnection.

[0122] Example Embodiment 9: The method of Example Embodiment 8, wherein the interconnect has a pitch along the second direction that is less than the pitch of the gate lines along the second direction.

[0123] Example Embodiment 10: The method of Example Embodiment 8 or 9, wherein each of the interconnects in the first version of the cell type is aligned with each of the plurality of gate lines along the first direction at two edges of the first version of the cell type along the second direction.

[0124] Example Embodiment 11: The method of Example Embodiment 8, 9, or 10, wherein each of the interconnections in the interconnection of the second version of the cell type is not aligned with each of the gate lines in the plurality of gate lines in the first direction at two edges of the second version of the cell type along the second direction.

[0125] Example Embodiment 12: The method of Example Embodiment 8, 9, 10, or 11, wherein the cell type is an inverter cell.

[0126] Example Embodiment 13: The method of Example Embodiment 8 or 9, wherein each of the interconnections in the interconnection of the first version of the cell type is aligned with each of the gate lines in the plurality of gate lines in the first direction at the first edge of the first version of the cell type along the second direction but not at the second edge of the first version of the cell type.

[0127] Example Embodiment 14: The method of Example Embodiment 8, 9, or 13, wherein each of the interconnections in the interconnection of the second version of the cell type is aligned with each of the gate lines in the plurality of gate lines in the first direction at the second edge of the second version of the cell type along the second direction but not at the first edge of the second version of the cell type.

[0128] Example Embodiment 15: The method of Example Embodiment 8, 9, 13, or 14, wherein the cell type is a NAND cell.

[0129] Example Embodiment 16: A library for cell layout design includes a first version of a cell type for placement above a first portion of a plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines. The library further includes a second version of the cell type for placement above a second portion of the plurality of gate lines, the second version of the cell type including a second plurality of interconnect lines, and the second version of the cell type is structurally different from the first version of the cell type.

[0130] Example Embodiment 17: The library for cell layout design of Example Embodiment 16, wherein each of the first plurality of interconnect lines in the first version of the cell type is aligned with each of the gate lines in the plurality of gate lines in the first direction at two edges of the first version of the cell type along the second direction.

[0131] Example Embodiment 18: The library for cell layout design of Example Embodiment 16 or 17, wherein each of the second plurality of interconnect lines in the second version of the cell type is not aligned with each of the gate lines in the plurality of gate lines in the first direction at two edges of the second version of the cell type along the second direction.

[0132] Example Embodiment 19: A library for cell layout design of Example Embodiment 16, wherein each of the interconnections in the interconnection of the first version of the cell type is aligned with each of the multiple gate lines in the first direction at the first edge of the first version of the cell type but not at the second edge of the first version of the cell type along the second direction.

[0133] Example Embodiment 20: A library for cell layout design of Example Embodiment 16 or 19, wherein each of the interconnections in the interconnection of the second version of the cell type is aligned with each of the multiple gate lines in the first direction at the second edge of the second version of the cell type but not at the first edge of the second version of the cell type along the second direction.

Claims

1. An integrated circuit structure, comprising: A plurality of gate lines, the plurality of gate lines being parallel along a first direction of a substrate and having a first pitch along a second direction orthogonal to the first direction; A first version of a cell type, the first version of the cell type being above a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of metal 1M1 layer interconnects covering the plurality of gate lines, the first plurality of M1 interconnects having a second pitch along the second direction, the second pitch being smaller than the first pitch; and A second version of the cell type, the second version of the cell type being laterally adjacent to the first version of the cell type along the second direction above a second portion of the plurality of gate lines, the second version of the cell type including a second plurality of metal 1M1 layer interconnects covering the plurality of gate lines, the second plurality of M1 interconnects having a second pitch along the second direction, and the second version of the cell type being structurally different from the first version of the cell type, Wherein each of the second plurality of M1 interconnects of the second version of the cell type is not aligned with each of the plurality of gate lines along the first direction at any edge of the second version of the cell type along the second direction.

2. The integrated circuit structure according to claim 1, wherein each of the first plurality of M1 interconnects of the first version of the cell type is aligned with each of the plurality of gate lines along the first direction at two edges of the first version of the cell type along the second direction.

3. The integrated circuit structure according to claim 2, wherein the first version of the cell type is a first version of an inverter cell.

4. The integrated circuit structure according to claim 1, wherein the second version of the cell type is a second version of an inverter cell.

5. The integrated circuit structure according to claim 1, wherein each of the first plurality of M1 interconnects of the first version of the cell type is aligned with each of the plurality of gate lines along the first direction at a first edge of the first version of the cell type along the second direction but not at a second edge of the first version of the cell type along the second direction.

6. The integrated circuit structure according to claim 5, wherein the first version of the cell type is a first version of a NAND cell.

7. A library for cell layout design, the library comprising: A plurality of gate lines, the plurality of gate lines being parallel along a first direction of a substrate and having a first pitch along a second direction orthogonal to the first direction; A first version of a cell type for placement above a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of metal 1M1 layer interconnects covering the plurality of gate lines, the first plurality of M1 interconnects having a second pitch along the second direction, the second pitch being smaller than the first pitch; And A second version of the cell type for placement above the second portion of the plurality of gate lines and laterally adjacent to the first version of the cell type along the second direction, the second version of the cell type including a second plurality of metal 1M1 layer interconnects covering the plurality of gate lines, the second plurality of M1 interconnects having a second pitch along the second direction, and the second version of the cell type being structurally different from the first version of the cell type, wherein each of the second plurality of M1 interconnects of the second version of the cell type is misaligned with each of the plurality of gate lines along the first direction at any edge of the second version of the cell type along the second direction.

8. The library for cell layout design according to claim 7, wherein each of the first plurality of M1 interconnects of the first version of the cell type is aligned with each of the plurality of gate lines along the first direction at two edges of the first version of the cell type along the second direction.

9. The library for cell layout design according to claim 7, wherein each of the interconnects of the first version of the cell type is aligned with each of the plurality of gate lines along the first direction at the first edge of the first version of the cell type along the second direction but not at the second edge of the first version of the cell type.

10. The library for cell layout design according to claim 7, wherein each of the M1 interconnects of the second version of the cell type is aligned with each of the plurality of gate lines along the first direction at the second edge of the second version of the cell type along the second direction but not at the first edge of the second version of the cell type.

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