Display device and method for manufacturing the same

Abstract

A display device and a method for manufacturing the display device are provided. The display device includes: a pixel circuit; a first insulating layer covering the pixel circuit; a first blocking member disposed on the first insulating layer and extending in a first direction; a second blocking member separated from the first blocking member, extending in the first direction and spaced apart from the first blocking member in a second direction substantially perpendicular to the first direction; a first electrode disposed on the first blocking member and electrically connected to the pixel circuit; a second electrode disposed on the second blocking member and separated from the first electrode; a second insulating layer disposed on the first electrode and the second electrode, and a grinding groove disposed in the second insulating layer along the second direction; and a light emitting element aligned along the grinding groove on the second insulating layer and electrically connected to the first electrode and the second electrode.

Description

[0001] This patent application claims the benefit of Korean Patent Application No. 10-2018-0120035, filed on October 8, 2018, which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present disclosure herein relates to a display device having improved reliability and a method of manufacturing the display device. Background Art

[0003] The display device may include a light emitting element. The light emitting element may be electrically connected to an electrode and emit light according to a voltage applied to the electrode. The light emitting element may be formed directly on the electrode, or a light emitting element made separately from the electrode may be connected to the electrode. When the light emitting element is formed separately and then connected to the electrode, a process for aligning the light emitting element on the electrode is necessary. When the light emitting element is not properly aligned on the electrode, the light emitting element will not emit light. Summary of the invention

[0004] The present disclosure provides a display device having improved reliability and a method of manufacturing the display device.

[0005] An exemplary embodiment of the inventive concept provides a display device, which includes: a pixel circuit; a first insulating layer covering the pixel circuit; a first blocking member arranged on the first insulating layer and extending in a first direction; a second blocking member extending in the first direction and spaced apart from the first blocking member in a second direction substantially perpendicular to the first direction; a first electrode arranged on the first blocking member and electrically connected to the pixel circuit; a second electrode arranged on the second blocking member and separated from the first electrode; a second insulating layer arranged on the first electrode and the second electrode, and a grinding groove arranged in the second insulating layer along the second direction; and a light emitting element aligned along the grinding groove on the second insulating layer and electrically connected to the first electrode and the second electrode, and arranged between the first blocking member and the second blocking member.

[0006] In exemplary embodiments, the second insulating layer may be formed of a polyimide-based material.

[0007] In an exemplary embodiment, a width of the light emitting element in the first direction may be less than or equal to a width of the grinding groove in the first direction.

[0008] In exemplary embodiments, a distance between the first barrier and the second barrier in the second direction may be greater than a distance between the first electrode and the second electrode in the second direction.

[0009] In an exemplary embodiment, a distance between the first electrode and the second electrode in the second direction may be smaller than a length of the light emitting element in the second direction.

[0010] In exemplary embodiments, a second insulating layer may be disposed on the first electrode, the first insulating layer, and the second electrode at least between the first barrier and the second barrier.

[0011] The display device may further include: a first connection electrode electrically connecting the first electrode and the light emitting element; and a second connection electrode electrically connecting the second electrode and the light emitting element.

[0012] In an exemplary embodiment, the first electrode may include a first reflective electrode electrically connected to the pixel circuit and including a first reflective material and a first cover electrode covering the first reflective electrode, and the second electrode may include a second reflective electrode configured to receive a power supply voltage and including a reflective material and a second cover electrode covering the second reflective electrode.

[0013] In an exemplary embodiment of the inventive concept, a method for manufacturing a display device is provided, the method comprising the following steps: forming a pixel circuit on a base layer; forming a first insulating layer covering the pixel circuit; forming a first blocking member and a second blocking member extending in a first direction and arranged separately from each other in a second direction on the first insulating layer; forming a first electrode electrically connected to the pixel circuit on the first blocking member and forming a second electrode separated from the first electrode on the second blocking member; forming an insulating material layer on the first insulating layer, the first electrode, and the second electrode; forming a grinding groove on the insulating material layer along the second direction to form a second insulating layer; disposing a light-emitting element on the second insulating layer between the first blocking member and the second blocking member; and aligning the light-emitting element along the grinding groove.

[0014] In an exemplary embodiment, the step of forming the second insulating layer may include: disposing a grinding roller on the insulating material layer with a grinding cloth wound around the grinding roller; and moving the grinding roller in the second direction while rolling the grinding roller to form a grinding groove along the second direction.

[0015] In an exemplary embodiment, the polishing cloth may be provided with a polishing file, and the thickness of the polishing file may be differently set according to the width of the light emitting element in the first direction.

[0016] In an exemplary embodiment, a width of the light emitting element in the first direction may be less than or equal to a width of the grinding groove in the first direction.

[0017] In exemplary embodiments, the insulating material layer may include a polyimide-based material.

[0018] In an exemplary embodiment, the first electrode may include a first reflective electrode including a reflective material and a first cover electrode configured to cover the first reflective electrode, and the second electrode may include a second reflective electrode configured to receive a power supply voltage and including a reflective material and a second cover electrode covering the second reflective electrode.

[0019] In an exemplary embodiment, the steps of forming the first electrode and the second electrode may include: forming a first conductive layer on the first insulating layer, the first barrier and the second barrier; forming a first photoresist pattern on the first conductive layer; removing a portion of the first conductive layer exposed by the first photoresist pattern to form a first reflective electrode and a second reflective electrode; after removing the first photoresist pattern, forming a second conductive layer covering the first reflective electrode and the second reflective electrode; forming a second photoresist pattern on the second conductive layer; and removing a portion of the second conductive layer exposed by the second photoresist pattern to form a first cover electrode and a second cover electrode.

[0020] The manufacturing method may further include: forming a first connection electrode electrically connecting the first electrode and the light emitting element; and forming a second connection electrode electrically connecting the second electrode and the light emitting element.

[0021] The manufacturing method may further include: before forming the first connection electrode, forming a third insulating layer covering the second connection electrode, wherein the first connection electrode is not covered by the third insulating layer.

[0022] The manufacturing method may further include forming a fourth insulating layer covering the first connection electrode and the third insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0024] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the inventive concept;

[0025] Figure 2 is a block diagram of a display device according to an exemplary embodiment of the inventive concept;

[0026] Figure 3 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the inventive concept;

[0027] Figure 4A is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept;

[0028] Figure 4Bis a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept;

[0029] Figure 4C is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept;

[0030] Figure 4D is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept;

[0031] Figure 5 is a cross-sectional view of a display panel according to an exemplary embodiment of the inventive concept;

[0032] Figure 6 is a plan view showing a portion of a display panel according to another exemplary embodiment of the inventive concept;

[0033] Figure 7 is along Figure 6 An example of a cross-sectional view cut along line 1-I' shown in FIG.

[0034] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E , Fig.8F , Figure 8G , Figure 8H , Fig.8I and Figure 8J are diagrams respectively illustrating a portion of a manufacturing process of a display device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0035] It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, directly connected to or directly coupled to the other element, or an intervening third element may be present.

[0036] The same reference numerals in the drawings represent the same elements. In addition, in the drawings, in order to effectively describe the technical contents, the thickness, ratio and size of the elements are exaggerated.

[0037] The term "and / or" includes any and all combinations of one or more associated items.

[0038] Terms such as first, second, etc. can be used to describe various components, but these components should not be limited by the terms. Terms are used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component can be referred to as the second component, or similarly, the second component can be referred to as the first component. Unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "the (the)" are also intended to include plural forms.

[0039] Additionally, terms such as "below," "below," "above," and "on" are used to explain the relationship of items shown in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the example embodiments belong. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0041] It will also be understood that when the terms "include" and / or "comprises" are used in this specification, it indicates the presence of the stated features, integers, steps, operations, elements, components or combinations thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or combinations thereof.

[0042] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0043] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the inventive concept.

[0044] about Figure 1 , the display device DD can display images through the display area DA. Figure 1 It is exemplarily shown that the display area DA is disposed on a surface defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, in a display device according to another exemplary embodiment of the inventive concept, the display area may be disposed on a curved surface.

[0045] The thickness direction of the display device DD is indicated by the third direction DR3. The directions indicated by the first direction to the third directions DR1, DR2 and DR3 are concepts relative to each other and can be changed to other directions. In this specification, the expression "when viewed on a plane" may mean when viewed from the third direction DR3. In addition, the "thickness direction" may mean the third direction DR3.

[0046] exist Figure 1 In the embodiment, the display device DD is exemplarily shown as a TV screen. However, the display device DD can be used not only in large electronic devices such as external billboards, but also in small and medium-sized electronic devices such as personal computers, notebook computers, personal digital assistants, car navigation units, game consoles, smart phones, tablet computers, and cameras. In addition, these are presented only as embodiments, and the display device DD can also be used in other electronic devices without departing from the inventive concept.

[0047] Figure 2 is a block diagram of a display device according to an exemplary embodiment of the inventive concept.

[0048] about Figure 2 , the display device DD may include a display panel DP, a signal controller (or timing controller) TC, a data driver DDV, and a scan driver GDV. Each of the signal controller TC, the data driver DDV, and the scan driver GDV may include a circuit.

[0049] The display panel DP may be an ultra-small light emitting element display panel including ultra-small light emitting elements. For example, the display panel DP may be a micro LED display panel.

[0050] The display panel DP may include a plurality of data lines DL1 to DLm, a plurality of scan lines SL1 to SLn, and a plurality of pixels PX connected to the plurality of data lines DL1 to DLm and the plurality of scan lines SL1 to SLn.

[0051] The data lines DL1 to DLm may extend in a first direction DR1 and be arranged along a second direction DR2 intersecting the first direction DR1. The plurality of scan lines SL1 to SLn may extend in a second direction DR2 and be arranged along the first direction DR1.

[0052] Each of the pixels PX may include a light emitting element and a pixel circuit electrically connected to the light emitting element. The pixel circuit may include a plurality of transistors. A first power supply voltage ELVDD and a second power supply voltage ELVSS may be provided to each of the pixels PX.

[0053] The pixels PX may be arranged in a regular pattern on the plane of the display panel DP. Each of the pixels PX may display one color among the primary colors or one color among the mixed colors. The primary colors may include red, green, and blue, and the mixed colors may include various colors such as yellow, cyan, magenta, and white. However, the colors displayed by the pixels PX are not limited thereto.

[0054] The signal controller TC may receive image data RGB provided from an external device, convert the image data RGB to match the operation of the display panel DP, generate converted image data R'G'B', and output the converted image data R'G'B' to the data driver DDV.

[0055] In addition, the signal controller TC may receive a control signal CS provided from an external device. The control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a main clock signal, a data enable signal, etc. The signal controller TC provides a first control signal CONT1 to the data driver DDV and provides a second control signal CONT2 to the scan driver GDV. The first control signal CONT1 is a signal for controlling the data driver DDV, and the second control signal CONT2 is a signal for controlling the scan driver GDV.

[0056] The data driver DDV may drive the plurality of data lines DL1 to DLm in response to the first control signal CONT1 received from the signal controller TC. The data driver DDV may be implemented as an independent integrated circuit to be electrically connected to one side of the display panel DP, or may be directly mounted on the display panel DP. In addition, the data driver DDV may be implemented as a single chip or include a plurality of chips.

[0057] The scan driver GDV drives the plurality of scan lines SL1 to SLn in response to a second control signal CONT2 from the signal controller TC. The scan driver GDV may be integrated in a designated area of ​​the display panel DP. For example, the scan driver GDV may include a plurality of thin film transistors formed by a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process. In addition, the scan driver GDV may be implemented as an independent integrated circuit chip to be electrically connected to one side of the display panel DP.

[0058] When the gate-on voltage is sequentially applied to one of the plurality of scan lines SL1 to SLn, each transistor in the pixel row connected thereto is turned on. Here, the data driver DDV provides a data drive signal to the data lines DL1 to DLm. The data drive signal provided to the data lines DL1 to DLm is applied to the respective corresponding pixels through the turned-on transistors. The data drive signal may be an analog voltage corresponding to the grayscale value of the image data.

[0059] Figure 3 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the inventive concept. Figure 3 Shows Figure 2 0 is an equivalent circuit diagram of one pixel PX among a plurality of pixels PX shown in FIG.

[0060] Reference Figure 3 , the pixel PX may be connected to a plurality of signal lines. In the present embodiment, among the plurality of signal lines, the scan line SL, the data line DL, the first power line PL1, and the second power line PL2 are exemplarily shown. However, these are exemplarily shown, and the pixel PX according to the exemplary embodiment of the inventive concept may be additionally connected to various signal lines, and is not limited to any one embodiment.

[0061] The pixel PX may include a light emitting element ED, a first electrode E1, a second electrode E2, and a pixel circuit PXC. The pixel circuit PXC may include a first thin film transistor TR1, a capacitor CAP, and a second thin film transistor TR2. This is shown as an example, and the number of thin film transistors and capacitors included in the pixel circuit PXC is not limited to Figure 3 For example, a pixel circuit PXC in another exemplary embodiment of the inventive concept may include seven thin film transistors and one capacitor.

[0062] The first thin film transistor TR1 may be a switching transistor configured to control turning on or off of the pixel PX. The first thin film transistor TR1 may transmit or cut off a data signal provided through the data line DL in response to a scan signal provided through the scan line SL.

[0063] The capacitor CAP is connected to the first thin film transistor TR1 and the first power line PL1. The capacitor CAP is charged with an amount of charge corresponding to a difference between a data signal provided from the first thin film transistor TR1 and a first power source voltage ELVDD applied to the first power line PL.

[0064] The second thin film transistor TR2 is connected to the first thin film transistor TR1, the capacitor CAP and the light emitting element ED. The second thin film transistor TR2 controls the driving current flowing through the light emitting element ED in response to the amount of charge stored in the capacitor CAP. The current flowing through the second thin film transistor TR2 can be determined according to the amount of charge charged in the capacitor CAP.

[0065] Each of the first and second thin film transistors TR1 and TR2 may be an N-type thin film transistor or a P-type thin film transistor. In addition, in another exemplary embodiment of the inventive concept, any one of the first and second thin film transistors TR1 and TR2 may be an N-type thin film transistor, and the other may be a P-type thin film transistor.

[0066] The light emitting element ED may be connected to the second thin film transistor TR2 and the second power line PL2. For example, the light emitting element ED may be electrically connected to a first electrode E1 electrically connected to the second thin film transistor TR2 and a second electrode E2 electrically connected to the second power line PL2. The first electrode E1 may be electrically connected to the pixel circuit PXC, and the second electrode E2 may receive a power supply voltage, for example, a second power supply voltage ELVSS, through the second power line PL2.

[0067] The light emitting element ED may emit light in response to current flowing through the light emitting element ED. For example, electrons and holes are recombined in the light emitting element ED and form excitons to emit light.

[0068] The light emitting element ED may be an ultra-small LED element. The ultra-small LED element may be an LED element having a length ranging from several nanometers to several hundred micrometers. However, the length of the ultra-small LED element is only, for example, the above numerical range and is not limited to the above numerical range.

[0069] Figure 3 Although one light emitting element ED is connected between the second thin film transistor TR2 and the second power line PL2, a plurality of light emitting elements ED may be provided and the plurality of light emitting elements ED may be connected in parallel.

[0070] Figure 4A is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept.

[0071] The light emitting element ED may have various shapes including a cylindrical shape or a polygonal column shape. Figure 4A A cross section of the light emitting element ED is shown.

[0072] about Figure 4A The light emitting element ED may include an n-type semiconductor layer SCN, a p-type semiconductor layer SCP, and an active layer AL. The active layer AL may be disposed between the n-type semiconductor layer SCN and the p-type semiconductor layer SCP.

[0073] The n-type semiconductor layer SCN may be provided with an n-type dopant doped in the semiconductor layer, and the p-type semiconductor layer SCP may be provided with a p-type dopant doped in the semiconductor layer. The semiconductor layer may include a semiconductor material, and the semiconductor material may be, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN or AlInN, but is not limited thereto. The n-type dopant may be silicon (Si), germanium (Ge), tin (Sn), selenium (Se), tellurium (Te) or a combination thereof, but is not limited thereto. The p-type dopant may be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) or a combination thereof, but is not limited thereto.

[0074] The active layer AL may be formed as any one of a single quantum well structure, a multi-quantum well structure, a quantum wire structure, or a quantum dot structure. The active layer AL may be a region where electrons injected through the n-type semiconductor layer SCN and holes injected through the p-type semiconductor layer SCP recombine. The active layer AL is a layer from which light having energy determined by the energy band gap of the material is emitted. The position of the active layer AL may vary depending on the type of diode.

[0075] The n-type semiconductor layer SCN may be connected to the first electrode E1 (refer to Figure 3 ) and the second electrode E2 (reference Figure 3 ) in any one of them, the p-type semiconductor layer SCP can be connected to the other one thereof.

[0076] The length LT of the light emitting element ED may be from several nanometers to hundreds of micrometers. For example, the length LT of the light emitting element ED may be from several nanometers to hundreds of micrometers, and for example, from about 1 micrometer to about 100 micrometers.

[0077] Figure 4B is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept.

[0078] about Figure 4B ,and Figure 4A Compared with the light emitting element ED, the light emitting element EDa may further include a first electrode layer ECL1 and a second electrode layer ECL2.

[0079] The first electrode layer ECL1 may be disposed adjacent to the n-type semiconductor layer SCN, and the second electrode layer ECL2 may be disposed adjacent to the p-type semiconductor layer SCP. For example, the first electrode layer ECL1, the n-type semiconductor layer SCN, the active layer AL, the p-type semiconductor layer SCP, and the second electrode layer ECL2 may be sequentially stacked.

[0080] Each of the first electrode layer ECL1 and the second electrode layer ECL2 may be formed of a metal or an alloy of a metal. For example, each of the first electrode layer ECL1 and the second electrode layer ECL2 may be formed of any one selected from molybdenum (Mo), chromium (Cr), nickel (Ni), gold (Au), aluminum (Al), titanium (Ti), platinum (Pt), vanadium (V), tungsten (W), lead (Pb), copper (Cu), rhodium (Rh), iridium (Ir) or a combination thereof. The first electrode layer ECL1 and the second electrode layer ECL2 may include the same material or materials different from each other.

[0081] Figure 4C is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept.

[0082] about Figure 4C ,and Figure 4ACompared with the light emitting element EDb, the light emitting element EDb may further include an insulating layer IL. For example, the light emitting element EDb may have a core-shell structure.

[0083] The insulating layer IL may cover the n-type semiconductor layer SCN, the p-type semiconductor layer SCP, and the active layer AL and may protect outer surfaces of the n-type semiconductor layer SCN, the p-type semiconductor layer SCP, and the active layer AL. In another exemplary embodiment of the inventive concept, the insulating layer IL may cover only the active layer AL.

[0084] Figure 4D is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept.

[0085] about Figure 4D ,and Figure 4B Compared with the light emitting element EDa, the light emitting element EDc may further include an insulating layer ILa.

[0086] The insulating layer ILa may cover the n-type semiconductor layer SCN, the p-type semiconductor layer SCP, and the active layer AL, but may not cover the first electrode layer ECL1 and the second electrode layer ECL2. However, in another exemplary embodiment of the inventive concept, the insulating layer ILa may cover at least a portion of the first electrode layer ECL1 and the second electrode layer ECL2, or may cover the entirety of the first electrode layer ECL1 and the second electrode layer ECL2.

[0087] Figure 5 is a cross-sectional view of a display panel according to an exemplary embodiment of the inventive concept, and Figure 6 is a plan view of a partial configuration of a display panel according to an exemplary embodiment of the inventive concept. For ease of description, Figure 5 and Figure 6 An area corresponding to one pixel with some components omitted is shown.

[0088] about Figure 5 and Figure 6 , the first base layer BL1 and the second base layer BL2 may face each other. Each of the first base layer BL1 and the second base layer BL2 may have a stacked structure including a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a plurality of insulating layers.

[0089] The buffer layer BFL may be disposed on the first base layer BL1. The first thin film transistor TR1 and the second thin film transistor TR2 may be disposed on the buffer layer BFL.

[0090] The first thin film transistor TR1 may include a first control electrode CE1, a first input electrode IE1, a first output electrode OE1, and a first semiconductor pattern SP1. The second thin film transistor TR2 may include a second control electrode CE2, a second input electrode IE2, a second output electrode OE2, and a second semiconductor pattern SP2.

[0091] The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be disposed on the buffer layer BFL. In this case, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may have a higher adhesion with respect to the buffer layer BFL than in a case where the first semiconductor pattern SP1 and the second semiconductor pattern SP2 are directly formed on the first base layer BL1. Alternatively, the buffer layer BFL may be a barrier layer configured to protect the bottom surface of each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2. In this case, the buffer layer BFL may prevent contaminants, moisture, etc. from the first base layer BL1 from penetrating into the first semiconductor pattern SP1 and the second semiconductor pattern SP2.

[0092] The first insulating layer L1 may be disposed on the buffer layer BFL and cover the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The first insulating layer L1 may include an inorganic material. The inorganic material may be, for example, silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide, but is not limited thereto.

[0093] The first and second control electrodes CE1 and CE2 may be disposed on the first insulating layer L1. The second insulating layer L2 may be disposed on the first insulating layer L1 and cover the first and second control electrodes CE1 and CE2. The second insulating layer L2 may include an inorganic material.

[0094] Capacitor CAP (see Figure 3 ) may include a first cover electrode and a second cover electrode CPa. For example, the first cover electrode may be branched from the second control electrode CE2, and the second cover electrode CPa may be disposed on the second insulating layer L2.

[0095] The third insulating layer L3 is disposed on the second insulating layer L2 and covers the second cover electrode CPa. The first input electrode IE1, the first output electrode OE1, the second input electrode IE2, and the second output electrode OE2 may be disposed on the third insulating layer L3. The first input electrode IE1 and the first output electrode OE1 may be connected to the first semiconductor pattern SP1 via a through hole formed in the first to third insulating layers L1, L2, and L3. The second input electrode IE2 and the second output electrode OE2 may be connected to the second semiconductor pattern SP2 via a through hole formed in the first to third insulating layers L1, L2, and L3. On the third insulating layer L3, not only the first input electrode IE1, the first output electrode OE1, the second input electrode IE2, and the second output electrode OE2 may be disposed, but also at least a portion of the corresponding signal wiring, for example, a scan line or a data line, may be disposed.

[0096] The fourth insulating layer L4 may be disposed on the third insulating layer L3 and cover the first input electrode IE1, the first output electrode OE1, the second input electrode IE2, and the second output electrode OE2. The fourth insulating layer L4 may have a single layer or multiple layers and may include an organic material and / or an inorganic material.

[0097] The connection electrode CNE may be disposed on the fourth insulating layer L4. On the fourth insulating layer L4, not only the connection electrode CNE but also at least other parts of the signal wiring, for example, the scan line or the data line may be disposed. The connection electrode CNE may be connected to the second output electrode OE2.

[0098] The fifth insulating layer L5 may be disposed on the fourth insulating layer L4 and cover the connection electrode CNE. The fifth insulating layer L5 may include an organic material. The fifth insulating layer L5 may cover the pixel circuit PXC disposed thereunder (see Figure 3 ), and provide a flat surface.

[0099] The first barrier BR1 and the second barrier BR2 are disposed on the fifth insulating layer L5. Each of the first barrier BR1 and the second barrier BR2 may extend in the first direction DR1. The second barrier BR2 may be separated from the first barrier BR1 in the second direction DR2 substantially perpendicular to the first direction DR1. The first barrier BR1 and the second barrier BR2 may include the same material. For example, the first barrier BR1 and the second barrier BR2 may include an organic material.

[0100] The first electrode E1 may be disposed on the first barrier BR1, and the second electrode E2 may be disposed on the second barrier BR2. The first electrode E1 may extend in the first direction DR1 and cover the first barrier BR1, and the second electrode E2 may extend in the first direction DR1 and cover the second barrier BR2. In other words, the first barrier BR1 may be disposed between the first electrode E1 and the fifth insulating layer L5, and the second barrier BR2 may be disposed between the second electrode E2 and the fifth insulating layer L5.

[0101] A through hole is provided in the fifth insulating layer L5, and the connection electrode CNE may be exposed through the through hole. The first electrode E1 may be electrically connected to the exposed portion of the connection electrode CNE. Although not shown in the drawings, the second electrode E2 may be electrically connected to the second power line PL2 (see FIG. Figure 3 In other words, the second power supply voltage ELVSS (see Figure 3 ) can be provided to the second electrode E2.

[0102] The first electrode E1 may include a first reflective electrode RFE1 and a first cover electrode CPE1, and the second electrode E2 may include a second reflective electrode RFE2 and a second cover electrode CPE2.

[0103] Each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may include a reflective material. Each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may have a single-layer structure or a multi-layer structure. For example, each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may have a structure in which indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) are sequentially stacked.

[0104] The first cover electrode CPE1 may cover the first reflective electrode RFE1, and the second cover electrode CPE2 may cover the second reflective electrode RFE2. In a plan view, the first cover electrode CPE1 may completely cover the first reflective electrode RFE1, and the second cover electrode CPE2 may completely cover the second reflective electrode RFE2. For example, each of the first cover electrode CPE1 and the second cover electrode CPE2 may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), indium zinc gallium oxide (IGZO), and mixtures / compounds thereof.

[0105] At least between the first barrier BR1 and the second barrier BR2, the sixth insulating layer L6 may be disposed on the first electrode E1, the fifth insulating layer L5, and the second electrode E2. In detail, the sixth insulating layer L6 may be disposed on the fifth insulating layer L5, disposed on the first cover electrode CPE1, and disposed on the second cover electrode CPE2 in a region disposed between the first cover electrode CPE1 and the second cover electrode CPE2. The sixth insulating layer L6 may partially overlap with the first cover electrode CPE1, and partially overlap with the second cover electrode CPE2. For example, the sixth insulating layer L6 may be disposed on the first cover electrode CPE1 to overlap with the first barrier BR1, and disposed on the second cover electrode CPE2 to overlap with the second barrier BR2. However, the structure of the sixth insulating layer L6 is not limited thereto, and the sixth insulating layer L6 may be disposed so as not to overlap with the first barrier BR1 and the second barrier BR2.

[0106] The sixth insulating layer L6 may include an organic material. For example, the sixth insulating layer L6 may be formed of a polyimide-based material. The grinding groove RGV may be provided on the top surface of the sixth insulating layer L6 and extend in the second direction DR2.

[0107] The light emitting element ED is disposed on the sixth insulating layer L6. The light emitting element ED may be disposed in plurality, and the plurality of light emitting elements disposed may be connected in parallel. Each light emitting element ED may be aligned in the second direction DR2 along the grinding groove RGV on the sixth insulating layer L6. Due to the grinding groove RGV, misalignment in which the light emitting element ED is not parallel to the second direction DR2 may be reduced.

[0108] The light emitting element ED may be electrically connected to the first electrode E1 and the second electrode E2. The light emitting element ED may be disposed between the first electrode E1 and the second electrode E2. The light emitting element ED may be disposed such that one end overlaps the first electrode E1 and the other end overlaps the second electrode E2.

[0109] The light emitting element ED may be electrically connected to the first electrode E1 via the first connection electrode CNE1 , and electrically connected to the second electrode E2 through the second connection electrode CNE2 .

[0110] The first connection electrode CNE1 may be disposed on the light emitting element ED, the sixth insulating layer L6, and the first electrode E1. Specifically, the first connection electrode CNE1 may be electrically connected to the first electrode E1 in a portion exposed by the sixth insulating layer L6 on the first cover electrode CPE1.

[0111] The second connection electrode CNE2 may be disposed on the light emitting element ED, the sixth insulating layer L6, and the second electrode E2. Specifically, the second connection electrode CNE2 may be electrically connected to the second electrode E2 in a portion exposed by the sixth insulating layer L6 on the second cover electrode CPE2.

[0112] The seventh insulating layer L7 may be disposed on the second connection electrode CNE2. Although the length of the light emitting element ED is less than several micrometers, the second connection electrode CNE2 and the first connection electrode CNE1 may not be in direct contact through the seventh insulating layer L7. However, this is merely an exemplary embodiment of the inventive concept, and in another exemplary embodiment of the inventive concept, the first connection electrode CNE1 and the second connection electrode CNE2 may be formed substantially simultaneously through the same process. In this embodiment, the seventh insulating layer L7 may be omitted.

[0113] The first connection electrode CNE1 and the second connection electrode CNE2 may include a conductive material. For example, the conductive material may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), indium zinc gallium oxide (IGZO), and mixtures / compounds thereof. However, the inventive concept is not limited thereto. For example, the conductive material may be a metal material, and the metal material may include, for example, molybdenum, silver, titanium, copper, aluminum, or an alloy thereof.

[0114] An eighth insulating layer L8 may be disposed on the first connection electrode CNE1, the light emitting element ED, and the seventh insulating layer L7. The eighth insulating layer L8 may be an encapsulation layer.

[0115] The light shielding layer BM may be disposed on one side of the second base layer BL2 facing the first base layer BL1. An opening portion may be disposed in the light shielding layer BM, and the wavelength conversion portion CL may cover the opening portion. The region exposed by the opening portion may correspond to the pixel light emitting region PXA.

[0116] The wavelength conversion portion CL may include a light emitter. For example, the light emitter may absorb the first light provided from the light emitting element ED, convert the wavelength of the first light, and emit a second light having a different color from the first light. The light emitter may be, for example, a quantum dot. The first light may be blue light, and the second light may be green light or red light. However, this is exemplary, and the inventive concept is not limited thereto. In addition, in another embodiment of the inventive concept, the wavelength conversion portion CL may be replaced with a color filter. The color filter may absorb light of a specific color to achieve a color. In another exemplary embodiment of the inventive concept, the wavelength conversion portion CL may be omitted. In this case, the light emitting element ED may emit blue light, green light, or red light.

[0117] The ninth insulating layer L9 may be disposed between the wavelength conversion portion CL and the eighth insulating layer L8. For example, a pixel circuit PXC (see FIG. 1 ) is disposed thereon. Figure 3) and the first base layer BL1 of the light emitting element ED and the second base layer BL2 on which the wavelength conversion portion CL and the light shielding layer BM are disposed can be combined by the ninth insulating layer L9. For example, the ninth insulating layer L9 can be an optically transparent adhesive film, an optically transparent resin, or a pressure-sensitive adhesive film. However, this is shown as an example, and in another exemplary embodiment of the inventive concept, the ninth insulating layer L9 can be omitted.

[0118] Figure 6 is a plan view showing a portion of a configuration of a display panel according to an exemplary embodiment of the inventive concept, and Figure 7 It is along Figure 6 A cross-sectional view taken along line 1-I'.

[0119] about Figure 6 and Figure 7 The distance DT1 between the first barrier BR1 and the second barrier BR2 in the second direction DR2 is greater than the distance DT2 between the first electrode E1 and the second electrode E2. The distance DT2 between the first electrode E1 and the second electrode E2 in the second direction DR2 is less than the length LT of the light emitting element ED in the second direction DR2.

[0120] In the sixth insulating layer L6, the first upper area URA1 and the second upper area URA2 may be located at a first height H1 from the top surface of the fifth insulating layer L5, the first lower area LRA1 and the second lower area LRA2 may be located at a second height H2 from the top surface of the fifth insulating layer L5, and the central area CA between the first lower area LRA1 and the second lower area LRA2 may be located at a height lower than the first height H1 and the second height H2. The first height H1 is defined as the sum of the thickness of the first barrier BR1 and the thickness of the first electrode E1 or the sum of the thickness of the second barrier BR2 and the thickness of the second electrode E2. The second height H2 may be defined as the thickness of the first electrode E1 or the thickness of the second electrode E2. In the central area CA, the sixth insulating layer L6 is directly formed on the fifth insulating layer L5 at a height lower than the heights of the first lower area LRA1 and the second lower area LRA2.

[0121] The grinding grooves RGV may be disposed in the sixth insulating layer L6 corresponding to the first and second upper areas URA1 and URA2 and the first and second lower areas LRA1 and LRA2.

[0122] The sixth insulating layer L6 has a first slope portion L6-I1 located between the first upper area URA1 and the first lower area LRA1 and a second slope portion L6-I2 located between the second upper area URA2 and the second lower area LRA2. Due to the height difference, the grinding groove RGV may not be formed in the first slope portion L6-I1 and the second slope portion L6-I2. However, the inventive concept is not limited thereto, and the grinding groove RGV may be formed in the first slope portion L6-I1 and the second slope portion L6-I2 according to the grinding process conditions.

[0123] Figure 6 and Figure 7 A structure in which the grinding groove RGV is not formed in the sixth insulating layer L6 located in the central area CA is shown, but the inventive concept is not limited thereto. In the central area CA, the gap GP is provided between the sixth insulating layer L6 and the light emitting element ED. Depending on the grinding process conditions, the grinding groove RGV may also be provided in the top surface of the sixth insulating layer L6 located in the central area CA.

[0124] The grinding groove RGV may be recessed and formed at a specified depth from the top surface of the sixth insulating layer L6. For better understanding, Figure 6 and Figure 7 The grinding groove RGV is shown by dashed lines.

[0125] like Figure 6 As shown in , the grinding groove RGV may extend and be formed in the second direction DR2. A plurality of grinding grooves RGV may be provided in the sixth insulating layer L6, and the plurality of grinding grooves RGV may be arranged in the first direction DR1. A plurality of light emitting elements ED provided on the sixth insulating layer L6 may be aligned along the extension direction of the grinding groove RGV in the second direction DR2, and may be arranged in the first direction DR1.

[0126] The width W1 of the grinding groove RGV in the first direction DR1 may be equal to or greater than the width W2 of the light emitting element ED in the first direction DR1. For example, the width W2 of the light emitting element ED in the first direction DR1 is about 1 micrometer to about 1.5 micrometers, and the length LT of the light emitting element ED in the second direction DR2 may be about 3.5 micrometers. In this case, the width W1 of the grinding groove RGV in the first direction DR1 may be about 1.5 micrometers.

[0127] When viewed on a plane, both ends of the light emitting element ED are disposed in the grinding groove RGV, and may be aligned such that a length direction of the light emitting element ED is parallel to the second direction DR2 .

[0128] As an example of the inventive concept, the length LT of the light emitting element ED may be greater than the distance WT between the first electrode E1 and the second electrode E2. However, the inventive concept is not limited thereto, and the length LT of the light emitting element ED may be set equal to or less than the distance WT between the first electrode E1 and the second electrode E2.

[0129] Although not shown in the drawings, when the length LT of the light emitting element ED is set equal to or less than the distance WT between the first electrode E1 and the second electrode E2 , the light emitting element ED may not overlap the first electrode E1 and the second electrode E2 .

[0130] FIG. 8A to FIG. 8J are diagrams respectively illustrating parts of a manufacturing process of a display device according to an exemplary embodiment of the inventive concept. FIG. 8A to FIG. 8J The manufacturing Figure 5 The process of the display panel shown in FIG. 1 is omitted in the following. Figure 5 Components in the same folder are repeated descriptions.

[0131] about Fig. 8A , prepare a first base layer BL1. Although not separately shown in the drawings, in the manufacturing process, the first base layer BL1 may be disposed on the supporting substrate. After manufacturing the display panel, the supporting substrate may be removed.

[0132] A pixel circuit PXC including a first thin film transistor TR1 and a second thin film transistor TR2 may be formed on the first base layer BL1 (see FIG. Figure 3 ). A connection electrode CNE may be formed on the pixel circuit PXC to cover the pixel circuit PXC. A fifth insulating layer L5 configured to cover the pixel circuit PXC and the connection electrode CNE is formed. The fifth insulating layer L5 may include an organic material. The fifth insulating layer L5 may provide a flat surface on at least a portion thereof. A first blocking member BR1 and a second blocking member BR2 are disposed on the fifth insulating layer L5.

[0133] about Figure 8B A first conductive layer CDL1 configured to cover the first and second barriers BR1 and BR2 is formed on the fifth insulating layer L5. The first conductive layer CDL1 may include a plurality of conductive layers, for example, the first conductive layer CDL1 may be formed by sequentially stacking indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO).

[0134] about Figure 8C , a first photoresist pattern OLP1 is formed on the first conductive layer CDL1. The first photoresist pattern OLP1 may be provided after forming a positive photoresist layer or a negative photoresist layer and then patterning the positive photoresist layer or the negative photoresist layer. For example, the patterning process may include a photolithography process.

[0135] about Figure 8C and Fig.8D , a portion of the first conductive layer CDL1 exposed by the first photoresist pattern OLP1 is removed. For example, the portion of the first conductive layer CDL1 may be wet-etched and removed.

[0136] By removing the portion of the first conductive layer CDL1, the first reflective electrode RFE1 and the second reflective electrode RFE2 are formed. After the first reflective electrode RFE1 and the second reflective electrode RFE2 are formed, the first photoresist pattern OLP1 is removed.

[0137] about Fig. 8E , forming a second conductive layer CDL2 configured to cover the first reflective electrode RFE1 and the second reflective electrode RFE2. The second conductive layer CDL2 may include a conductive material having good selectivity to the first reflective electrode RFE1 and the second reflective electrode RFE2, for example, at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), indium zinc gallium oxide (IGZO) and mixtures / compounds thereof.

[0138] about Fig.8F and Figure 8G , a second photoresist pattern OLP2 is formed on the second conductive layer CDL2. The second photoresist pattern OLP2 may be provided after forming a positive photoresist layer or a negative photoresist layer and then patterning the positive photoresist layer or the negative photoresist layer. For example, the patterning process may include a photolithography process.

[0139] The portion of the second conductive layer CDL2 exposed by the second photoresist pattern OLP2 is removed. For example, the portion of the second conductive layer CDL2 may be wet etched or dry etched and removed. By removing the portion of the second conductive layer CDL2, the first cover electrode CPE1 and the second cover electrode CPE2 are formed.

[0140] about Figure 8H , an insulating material layer L6-B is formed to cover the first electrode E1, the second electrode E2 and the fifth insulating layer L5. The insulating material layer L6-B may include an organic material. For example, the insulating material layer L6-B may be formed of a polyimide-based material.

[0141] about Fig.8I , a grinding roller RR configured to grind the insulating material layer L6-B may be disposed on top of the insulating material layer L6-B. The grinding roller RR rolls and moves in the second direction DR2. According to an exemplary embodiment, the grinding roller RR moves in the second direction DR2, the inventive concept is not limited thereto, and the first base layer BL1 may move in a direction opposite to the second direction DR2.

[0142] The grinding cloth RC may be wound around the grinding roller RR, and the grinding files RF may be arranged at constant intervals on the grinding cloth RC. Figure 6 ) to differently set the thickness of the grinding file RF.

[0143] The grinding groove RGV is formed on the top surface of the insulating material layer L6 -B ground by the grinding roll RR. Since the grinding roll RR moves in the second direction DR2 , the grinding groove RGV may be formed to extend in the second direction DR2 .

[0144] like Figure 8J As shown in , when the grinding process is completed and the grinding groove RGV is formed in the insulating material layer L6-B, a solvent such as ink or slurry including the light emitting element ED is disposed on the insulating material layer L6-B between the first barrier BR1 and the second barrier BR2. The solvent may be a material that can evaporate at room temperature or by heating. An electric field is formed between the first electrode E1 and the second electrode E2 by applying power to the first electrode E1 and the second electrode E2. A dipole is induced to the light emitting element ED by the electric field, and the light emitting element ED can be aligned between the first electrode E1 and the second electrode E2 by the dielectrophoretic force. When the first electrode E1 and the second electrode E2 are short-circuited, the electric field is not properly formed. When the electric field is not properly formed, the light emitting element ED is not properly aligned.

[0145] According to an embodiment of the inventive concept, the light emitting element ED can be more easily aligned between the first electrode E1 and the second electrode E2 through the grinding groove RGV formed on the insulating material layer L6-B, and can be properly aligned in the second direction DR2 along the extension direction of the grinding groove RGV. Therefore, the reliability of the alignment of the light emitting element ED can be improved.

[0146] Although not shown in the drawings, the sixth insulating layer L6 is formed by patterning the insulating material layer L6 -B Then, the second connection electrode CNE2 , the seventh insulating layer L7 , the first connection electrode CNE1 , and the eighth insulating layer L8 may be sequentially formed.

[0147] According to the present disclosure, the grinding groove is formed on the insulating layer disposed at least between the first and second stoppers, and therefore, the light emitting elements disposed between the first and second stoppers can be aligned in the extending direction of the grinding groove. Therefore, the alignment of the light emitting elements can be performed more easily, and as a result, the reliability of the display device can be improved.

[0148] Although the inventive concept has been described with reference to the exemplary embodiments of the inventive concept, it will be apparent to those skilled in the art that various changes and modifications may be made to the described embodiments without departing from the spirit and technical field of the inventive concept as defined in the appended claims and their equivalents. Therefore, the scope of the inventive concept should not be defined or limited by the foregoing description, but should be determined by the broadest permissible interpretation of the claims.

Claims

1. A display device, comprising: Pixel circuit; a first insulating layer, covering the pixel circuit; A first blocking member, disposed on the first insulating layer and extending in a first direction; a second blocking member extending in the first direction and spaced apart from the first blocking member in a second direction perpendicular to the first direction; a first electrode disposed on the first blocking member and electrically connected to the pixel circuit; a second electrode disposed on the second blocking member and separated from the first electrode; A second insulating layer is disposed on the first electrode and the second electrode, and a grinding groove is disposed in the second insulating layer along the second direction; as well as A light emitting element is aligned along the grinding groove on the second insulating layer and electrically connected to the first electrode and the second electrode, and is disposed between the first barrier member and the second barrier member.

2. The display device according to claim 1, wherein: The second insulating layer is formed of a polyimide material.

3. The display device according to claim 1, wherein: A width of the light emitting element in the first direction is smaller than or equal to a width of the grinding groove in the first direction.

4. The display device according to claim 1, wherein: A distance between the first blocking member and the second blocking member in the second direction is greater than a distance between the first electrode and the second electrode in the second direction, and The distance between the first electrode and the second electrode in the second direction is smaller than a length of the light emitting element in the second direction.

5. The display device according to claim 1, further comprising: a first connecting electrode electrically connecting the first electrode and the light emitting element; as well as The second connecting electrode electrically connects the second electrode and the light emitting element.

6. The display device according to claim 1, wherein: The first electrode includes a first reflective electrode electrically connected to the pixel circuit and including a first reflective material and a first cover electrode covering the first reflective electrode, and The second electrode includes a second reflective electrode configured to receive a power supply voltage and including a reflective material, and a second cover electrode covering the second reflective electrode.

7. A method for manufacturing a display device, the method comprising the following steps: forming a pixel circuit on the substrate layer; forming a first insulating layer covering the pixel circuit; forming a first blocking member and a second blocking member extending in a first direction and disposed apart from each other in a second direction on the first insulating layer; forming a first electrode electrically connected to the pixel circuit on the first blocking member and forming a second electrode separated from the first electrode on the second blocking member; forming an insulating material layer on the first insulating layer, the first electrode and the second electrode; forming a grinding groove on the insulating material layer along the second direction to form a second insulating layer; disposing a light emitting element on the second insulating layer between the first blocking member and the second blocking member; as well as The light emitting element is aligned along the grind groove.

8. The manufacturing method according to claim 7, wherein: The step of forming the second insulating layer comprises: placing a grinding roller on the insulating material layer, with a grinding cloth wound around the grinding roller; and The grinding roller is moved in the second direction while rolling the grinding roller to form the grinding grooves along the second direction.

9. The manufacturing method according to claim 8, wherein: The grinding cloth is provided with a grinding file, and The thickness of the grinding file is set differently according to the width of the light emitting element in the first direction.

10. The manufacturing method according to claim 9, wherein: The width of the light emitting element in the first direction is smaller than or equal to the width of the grinding groove in the first direction.

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