Electronic Devices

Abstract

The present disclosure provides an electronic device. The electronic device according to an embodiment of the inventive concept includes a display panel and an input sensing unit, the display panel is divided into a display area in which pixels are arranged and a non-display area arranged adjacent to the display area on a plane, the input sensing unit includes a first pattern and a second pattern, an insulating layer, and a first line and a second line, the first pattern and the second pattern are arranged on the display panel, overlapped with the display area and arranged on the same layer while being spaced apart from each other, the insulating layer is arranged on the encapsulation layer, the first line and the second line overlap with the non-display area, and are arranged on different layers from each other and the insulating layer is located between the first line and the second line, wherein the first line is connected to the first pattern and the second line is connected to the second pattern. The first line overlaps at least a portion of the second line on a plane.

Description

[0001] This patent application claims the benefit of Korean Patent Application No. 10-2018-0118736, filed on October 5, 2018, which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present disclosure relates to an input sensing unit and an electronic device including the same, and more particularly, to an input sensing unit having a reduced inactive area and an electronic device including the same. Background Art

[0003] The electronic device may be activated by receiving an electrical signal. The electronic device may include an electronic panel that detects various types of input applied from the outside (e.g., a touch from a user). The electronic panel may be used alone or may also include a display unit for displaying an image to enhance user convenience.

[0004] The electronic device may include various electrode patterns so as to be activated by an electrical signal, and an area in which the electrode pattern is activated displays information or responds to a touch applied from the outside. Summary of the invention

[0005] The present disclosure provides an input sensing unit having a structure for reducing an inactive area at which an image and an input cannot be detected, and an electronic device including the same.

[0006] An embodiment of the inventive concept provides an electronic device, the electronic device including a display panel and an input sensing unit, the display panel including: a base layer; a pixel layer disposed on the base layer and including a plurality of pixels; and an encapsulation layer covering the pixel layer, the display panel being divided into a display area in which pixels are disposed and a non-display area disposed adjacent to the display area on a plane, the input sensing unit including: a first pattern and a second pattern disposed on the display panel, overlapping the display area, and disposed on the same layer while being spaced apart from each other; an insulating layer disposed on the encapsulation layer; and a first line and a second line overlapping the non-display area and disposed on layers different from each other and the insulating layer being located between the first line and the second line, wherein the first line is connected to the first pattern and the second line is connected to the second pattern. Here, the first line overlaps at least a portion of the second line on a plane.

[0007] In an embodiment, one of the connection between the first pattern and the first line and the connection between the second pattern and the second line may be connected through a contact hole passing through the insulating layer, and the other of the connection between the first pattern and the first line and the connection between the second pattern and the second line may be directly connected on the same layer.

[0008] In an embodiment, the first pattern and the first line may be directly connected on the same layer, and at least a portion of the first line may cover at least a portion of the first pattern.

[0009] In an embodiment, the first pattern and the first line may be directly connected on the same layer, and the first pattern and the first line may have an integral shape.

[0010] In an embodiment, the electronic device may further include: a third pattern disposed on the same layer as the first pattern and spaced apart from the first pattern and the second pattern; and a third line connected to the third pattern.

[0011] In an embodiment, the third pattern may be spaced apart from the first pattern with the second pattern between the third pattern and the first pattern, and the third line may be disposed on the same layer as one of the first line and the second line.

[0012] In an embodiment, the third pattern may be disposed between the first pattern and the second pattern, and the third line may be disposed on the same layer as the first line.

[0013] In an embodiment, the encapsulation layer may include an organic layer and a plurality of inorganic layers covering the organic layer.

[0014] In an embodiment, the electronic device may further include a sealing portion disposed to overlap the non-display area, and the sealing portion may be disposed between the base layer and the encapsulation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0016] Figure 1 is a perspective view showing an electronic device according to an embodiment of the inventive concept;

[0017] FIG. 2A to FIG. 2B is a cross-sectional view showing an electronic device according to an embodiment of the inventive concept;

[0018] Figure 3 is a cross-sectional view showing a pixel according to an embodiment of the inventive concept;

[0019] Figure 4 is a plan view showing an input sensing unit according to an embodiment of the inventive concept;

[0020] Figure 5 It is shown Figure 4 An enlarged view of the area AA';

[0021] Fig. 6A is along Figure 5 A cross-sectional view taken along line II';

[0022] Figure 6B is along Figure 5 A cross-sectional view taken along line II-II';

[0023] Figure 6C is a cross-sectional view illustrating an input sensing unit according to an embodiment of the inventive concept;

[0024] Figure 7 It is shown Figure 4 An enlarged view of region BB';

[0025] Figure 8 is a plan view showing one region of an input sensing unit according to an embodiment of the inventive concept;

[0026] Fig.9A is along Figure 8 A cross-sectional view taken along line III-III';

[0027] Fig. 9B is along Figure 8 A cross-sectional view taken along line IV-IV';

[0028] Fig. 9C is along Figure 8 A cross-sectional view taken along line V-V' of ; and

[0029] Fig.10 is a plan view illustrating one region of an input sensing unit according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0030] In the present specification, it will be understood that when an element such as a region, layer or section is referred to as being “on” another element, the element can be directly on the other element or intervening elements may also be present.

[0031] The same reference numerals always represent the same elements. In addition, in the drawings, the thickness, proportion and size of components are exaggerated for clear explanation.

[0032] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] It will be understood that, although the terms of first and second are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from another component. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in another embodiment. Unless otherwise indicated, terms in the singular may also include plural forms.

[0034] In addition, for ease of description, spatial relative terms such as "below", "lower", "above", and "on" may be used herein to describe the relationship between an element and / or feature as shown in the drawings and another (other) element and / or feature. These terms are relative concepts and are described relative to the directions indicated in the drawings.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art. Terms defined in general dictionaries should be interpreted as having the same meaning as in the context of the relevant technical field, and unless clearly defined in the description, terms should not be interpreted ideally or excessively as having a formal meaning.

[0036] The meaning of "include" or "comprising" refers to including properties, areas, fixed numbers, steps, processes, elements and / or components, but does not exclude other properties, areas, fixed numbers, steps, processes, elements and / or components. In the following, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0037] Figure 1 is a perspective view illustrating an electronic device according to an embodiment of the inventive concept. Figure 2A and Figure 2B is a cross-sectional view illustrating an electronic device according to an embodiment of the inventive concept. Figure 3 is a cross-sectional view illustrating a pixel according to an embodiment of the inventive concept. Figure 4 is a plan view illustrating an input sensing unit according to an embodiment of the inventive concept.

[0038] Reference Figure 1 , the electronic device EA is activated by receiving the electrical signal. On a plane defined by the first direction DR1 and the second direction DR2, the electronic device EA may be divided into an active area AA and a non-active area NAA. Figure 1 , the third direction DR3 is a thickness direction of the electronic device EA and is perpendicular to a plane defined by the first direction DR1 and the second direction DR2.

[0039] When supplied with an electrical signal, the active area AA may be electrically activated. The active area AA may be activated to have various functions according to the purpose of the electronic device EA.

[0040] For example, the active area AA may be a sensing area for detecting an input applied from the outside. According to an embodiment, the electronic device EA may detect an external input TC applied to the active area AA. In this regard, the electronic device EA may function as an input device.

[0041] Although the user's hand is shown as an example of the external input TC, the external input applied from the outside can be provided in various types. For example, the input may include contact generated by a part of the human body such as the user's hand and an external input applied by approaching the electronic device EA or being disposed adjacent to the electronic device EA at a predetermined distance (e.g., hovering). In addition, the external input may have various types such as force, pressure, and light. However, the embodiments of the inventive concept are not limited thereto.

[0042] In addition, the active area AA may be a display area for displaying predetermined information. The electronic device EA may display an image IM in the active area AA, and a user may obtain information through the image. In this regard, the electronic device EA may be used as an output device.

[0043] The non-active area NAA is disposed adjacent to the active area AA. Even when an electrical signal is applied, the non-active area NAA does not provide a function for displaying an image to the outside or detecting an external input.

[0044] The non-active area NAA may be an area in which a signal line for supplying a signal applied from the outside to the active area AA or a driving element for driving the active area AA is disposed.

[0045] In one embodiment, although the non-active area NAA has a frame shape surrounding the active area AA, the inventive concept is not limited thereto. For example, the non-active area NAA may be omitted. The non-active area NAA may have various shapes according to the shape of the active area AA. However, the inventive concept is not limited thereto.

[0046] Figure 1 1 is a view showing a touch screen as an example of the electronic device EA. However, the inventive concept is not limited thereto. For example, the display function of the electronic device EA may be omitted.

[0047] Reference Figure 2A and Figure 3 , the electronic device EA includes a display panel DP and an input sensing unit SU. The display panel DP includes a base layer BF, a circuit layer ML, a light emitting element layer EL, and a thin film encapsulation layer TFE. The display panel DP may include a display area for displaying an image and a non-display area disposed adjacent to the display area. The display area may overlap with the active area AA, and the non-display area may overlap with the non-active area NAA.

[0048] The base layer BF may be a base layer on which other components of the display panel DP are disposed. The base layer BF may include a plastic substrate, a glass substrate, or an organic / inorganic composite substrate. In addition, the base layer BF may be a laminated structure including a plurality of insulating layers.

[0049] The circuit layer ML is disposed on the base layer BF. The circuit layer ML includes a thin film transistor TR and a plurality of insulating layers ILD1, ILD2, and ILD3. The circuit layer ML may include a thin film transistor TR and a capacitor (not shown) electrically connected to the light emitting element layer EL. The circuit layer ML may be electrically connected to the light emitting element layer EL to control light emission of the light emitting element layer EL.

[0050] The light emitting element layer EL is disposed on the circuit layer ML. The light emitting element layer EL includes an organic light emitting element OLD and a pixel defining layer PXL. The light emitting element layer EL realizes an image by displaying light according to an electrical signal transmitted via a capacitor and a thin film transistor TR of the circuit layer ML. Various embodiments of the inventive concept may include a light emitting element layer EL. For example, the light emitting element layer EL may include an electrophoretic element, a liquid crystal capacitor, an electrowetting element, or an organic light emitting element. For ease of description, the light emitting element layer EL is described below as an embodiment including an organic light emitting element.

[0051] The pixel PX for displaying an image is disposed on the base layer BF. The pixel PX includes a thin film transistor TR and an organic light emitting element OLD. The thin film transistor TR may be included in the circuit layer ML. The organic light emitting element OLD may be included in the light emitting element layer EL.

[0052] According to an embodiment of the inventive concept, the active area AA (refer to Figure 1 ) may include a light emitting region PXA and a non-light emitting region NPXA disposed adjacent to the light emitting region PXA. The non-light emitting region NPXA may surround the light emitting region PXA on a plane. The light emitting region PXA may be disposed in plurality in the active area AA. The plurality of light emitting regions PXA may be spaced apart from each other, and the non-light emitting region NPXA may be disposed adjacent to the light emitting region PXA. Figure 3 One light emitting area PXA is shown as an example.

[0053] The thin film transistor TR includes a semiconductor pattern AL, a control electrode GE, an input electrode SE, and an output electrode DE.

[0054] The first insulating layer ILD1 and the semiconductor pattern AL of the thin film transistor TR are disposed on the base layer BF. The first insulating layer ILD1 covers the semiconductor pattern AL.

[0055] The control electrode GE and the second insulating layer ILD2 are disposed on the first insulating layer ILD1. The second insulating layer ILD2 covers the control electrode GE. Each of the first insulating layer ILD1 and the second insulating layer ILD2 includes an organic layer and / or an inorganic layer. Each of the first insulating layer ILD1 and the second insulating layer ILD2 may include a plurality of thin films.

[0056] The input electrode SE, the output electrode DE, and the third insulating layer ILD3 are disposed on the second insulating layer ILD2. The third insulating layer ILD3 covers the input electrode SE and the output electrode DE.

[0057] The input electrode SE and the output electrode DE are connected to the semiconductor pattern AL through first and second through holes CH1 and CH2 defined in the first and second insulating layers ILD1 and ILD2 , respectively.

[0058] The organic light emitting element OLD and the pixel defining layer PXL are disposed on the third insulating layer ILD3. The organic light emitting element OLD includes an anode electrode AE, a light emitting pattern EML, a cathode electrode CE, a hole transport region HCL defined between the anode electrode AE ​​and the light emitting pattern EML, and an electron transport region ECL defined between the cathode electrode CE and the light emitting pattern EML.

[0059] The anode electrode AE ​​is connected to the output electrode DE through a third through hole CH3 defined in the third insulating layer ILD3 .

[0060] The pixel defining layer PXL is disposed on the third insulating layer ILD3. An opening OB for exposing at least a portion of the anode electrode AE ​​may be defined in the pixel defining layer PXL. The region on which the anode electrode AE ​​is disposed may correspond to the light emitting region PXA from which light is emitted from the organic light emitting element OLD. In another embodiment of the inventive concept, the region in which the opening OB is defined may correspond to the light emitting region PXA.

[0061] The hole transport region HCL is disposed on the anode electrode AE ​​to cover the anode electrode AE ​​and the pixel defining layer PXL. The hole transport region HCL may include at least one of a hole injection layer, a hole transport layer, and a single layer having both hole injection and hole transport functions.

[0062] The light emitting pattern EML is disposed on the hole transport region HCL. The light emitting pattern EML may include a fluorescent material, a phosphorescent material, and quantum dots. The light emitting pattern EML may generate light having one color or light having a mixed color of at least two colors. The light emitting region PXA according to an embodiment of the inventive concept may overlap the light emitting pattern EML on a plane.

[0063] The electron transport region ECL is disposed on the light emitting pattern EML to cover the light emitting pattern EML and the hole transport region HCL. The electron transport region ECL may include at least one of an electron transport material and an electron injection material. The electron transport region ECL may be an electron transport layer including an electron transport material or an electron injection / transport single layer including an electron transport material and an electron injection material.

[0064] The cathode electrode CE is disposed on the electron transport region ECL to face the anode electrode AE. The cathode electrode CE may be made of a material having a low work function to easily inject electrons.

[0065] The cathode electrode CE and the anode electrode AE ​​may be made of different materials from each other according to the light emitting method. For example, when the display panel DP according to the embodiment of the inventive concept is a front light emitting type, the cathode electrode CE may be a transmissive electrode, and the anode electrode AE ​​may be a reflective electrode. Alternatively, for example, when the display panel DP according to the embodiment of the inventive concept is a rear light emitting type, the cathode electrode CE may be a reflective electrode, and the anode electrode AE ​​may be a transmissive electrode. The display panel DP according to the embodiment of the inventive concept may include organic light emitting elements having various structures. However, the embodiments of the inventive concept are not limited thereto.

[0066] The thin film encapsulation layer TFE is disposed on the cathode electrode CE. The thin film encapsulation layer TFE covers the entire surface of the cathode electrode CE to seal the organic light emitting element OLD. The thin film encapsulation layer TFE protects the organic light emitting element OLD from moisture and foreign substances. The thin film encapsulation layer TFE may be formed by deposition.

[0067] The thin film encapsulation layer TFE includes an inorganic layer and / or an organic layer. The inorganic layer may include, for example, at least one of aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium oxide, zirconium oxide, and zinc oxide.

[0068] The organic layer may include, for example, at least one of epoxy resin, polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), polyethylene (PE), and polyacrylate. The inorganic layer according to the embodiment may be provided in plurality, and the inorganic layer may be provided so that the organic layer is located between the inorganic layers to cover the organic layer.

[0069] The input sensing unit SU according to an embodiment of the inventive concept may be formed directly on the thin film encapsulation layer TFE. Therefore, the input sensing unit SU may be formed on the thin film encapsulation layer TFE by a continuous process. However, the inventive concept is not limited thereto. For example, an adhesive member (not shown) may be disposed between the thin film encapsulation layer TFE and the input sensing unit SU, and the thin film encapsulation layer TFE and the input sensing unit SU may be bonded to each other by the adhesive member. The adhesive member may be an organic adhesive layer such as an optically transparent adhesive film (OCA), an optically transparent resin (OCR), or a pressure-sensitive adhesive film (PSA). However, the inventive concept is not limited thereto.

[0070] Reference Figure 2B, the electronic device EA-A according to the embodiment includes a display panel DP-A and an input sensing unit SU-A. The display panel DP-A includes a base layer BF-A, a circuit layer ML-A, a light emitting element layer EL-A, a sealing portion LP and an encapsulation substrate EPL. Figure 2A The components of the electronic device EA overlap with the description of the same components.

[0071] The encapsulation substrate EPL according to the embodiment seals the light emitting element layer EL-A. The encapsulation substrate EPL protects the light emitting element layer EL-A from foreign substances such as moisture, oxygen, and dust particles. The encapsulation substrate EPL may be bonded to the base layer BF-A through a sealing portion LP, and the sealing portion LP may be disposed to overlap with a non-display area to be described later. The encapsulation substrate EPL according to the embodiment may be a substrate made of glass or plastic. The sealing portion LP may include glass material. However, the inventive concept is not limited to the material forming the sealing portion LP.

[0072] Despite Figure 2B The input sensing unit SU-A is directly formed on the encapsulation substrate EPL, but the embodiments of the inventive concept are not limited thereto. For example, the input sensing unit SU-A may be separately provided and provided on the encapsulation substrate EPL. In this case, an adhesive member (not shown) may be provided between the encapsulation substrate EPL and the input sensing unit SU-A, and the encapsulation substrate EPL and the input sensing unit SU-A may be combined with each other by the adhesive member.

[0073] Reference Figure 4 , the input sensing unit SU includes a sensing area TA and a peripheral area NTA. The sensing area TA may overlap with the active area AA, and the peripheral area NTA may overlap with the non-active area NAA. The sensing area TA may detect an external input TC. The peripheral area NTA may surround the sensing area TA. The peripheral area NTA may have the same shape as the non-active area NAA.

[0074] Despite Figure 4 Each of the middle sensing area TA and the peripheral area NTA has the same planar shape as each of the active area AA and the non-active area NAA, but the inventive concept is not limited thereto. For example, each of the sensing area TA and the peripheral area NTA may have a different shape from each of the active area AA and the non-active area NAA.

[0075] The input sensing unit SU includes a first electrode SE1, a second electrode SE2, track lines SL1, SL2, and SL3, and a pad PD. The first electrode SE1 and the second electrode SE2 are disposed in the sensing area TA. The track lines SL1, SL2, and SL3 are disposed in the peripheral area NTA.

[0076] The input sensing unit SU according to an embodiment of the inventive concept may be disposed on the base member BSL. Figure 2A Thin film encapsulation layer TFE or Figure 2B However, the inventive concept is not limited thereto. For example, the base member BSL may be different from each of the thin film encapsulation layer TFE and the encapsulation substrate EPL.

[0077] The first electrode SE1 includes driving electrodes, each of which includes a first pattern DSP and a first connection pattern DBP. The second electrode SE2 includes sensing electrodes, each of which includes a second pattern KSP and a second connection pattern KBP. Figure 4 In the figure, two driving electrodes DE1 and DE2 and two sensing electrodes KE1 and KE2 are shown, but in another embodiment to be described later, the driving electrodes DE1 and DE2 and the sensing electrodes KE1 and KE2 may be included in the first electrodes SE1 and

[0078] The driving electrodes and the sensing electrodes in the second electrode SE2 correspond to each other.

[0079] The driving electrodes DE1 and DE2 each extend in the first direction DR1 and are arranged in the second direction DR2. Each of the first pattern DSP and the first connection pattern DBP is provided in plurality. Each first pattern DSP and each first connection pattern DBP are arranged in the first direction to define one driving electrode DE1 or DE2. The first connection pattern DBP is provided between the first patterns DSP provided adjacent to each other. The first patterns DSP are electrically connected through the first connection patterns DBP.

[0080] The sensing electrodes KE1 and KE2 are both extended in the second direction DR2 and arranged in the first direction DR1. Each second pattern KSP and each second connection pattern KBP are provided in plurality. Each second pattern KSP and each second connection pattern KBP are arranged in the second direction DR2 to define one sensing electrode KE1 or KE2. The second connection pattern KBP is provided between the second patterns KSP provided adjacent to each other. The second patterns KSP are electrically connected through the second connection patterns KBP.

[0081] The first track line SL1 is connected to one end of the corresponding driving electrode, the second track line SL2 is connected to the other end of the corresponding driving electrode, and the third track line SL3 is connected to one end of the corresponding sensing electrode.

[0082] Each of the track lines SL1, SL2, and SL3 passes through the peripheral area NTA and is connected to a corresponding pad PD among the pads PD. Each of the first track line SL1 and the second track line SL2 may be connected to one pad corresponding to the driving electrodes DE1 and DE2. Each of the first track line SL1 and the second track line SL2 may transmit an electrical signal provided through a corresponding pad PD among the pads PD to the driving electrodes DE1 and DE2, or transmit an electrical signal provided from the driving electrodes DE1 and DE2 to the outside through the corresponding pad PD. The third track line SL3 may be connected to one pad PD corresponding to the sensing electrodes KE1 and KE2. The third track line SL3 may transmit an electrical signal provided through a corresponding pad PD among the pads PD to the sensing electrodes KE1 and KE2, or transmit an electrical signal provided from the sensing electrodes KE1 and KE2 to the outside through the corresponding pad PD.

[0083] Figure 5 It is shown Figure 4 An enlarged view of area AA'. Fig. 6A is along Figure 5 A cross-sectional view taken along line II'. Figure 6B is along Figure 5 A cross-sectional view taken along line II-II'. Figure 6C is a cross-sectional view showing an input sensing unit according to an embodiment of the inventive concept. Figures 1 to 4 The same components in the drawings will be denoted by the same reference numerals and overlapping descriptions will be omitted. Figure 5 In order to facilitate description, the first sensing pattern SP1, the second sensing pattern SP2, the third sensing pattern SP3 and the fourth sensing pattern SP4 are used to represent the sensing patterns arranged in Figure 4 In addition, the first sensing track line DSL1, the second sensing track line DSL2, the third sensing track line DSL3 and the fourth sensing track line DSL4 (the sensing track lines are also referred to as sensing lines) are represented. Figure 4 The track lines SL1, SL2, and SL3 in FIG. 5 are connected to the first, second, third, and fourth sensing patterns SP1, SP2, SP3, and SP4.

[0084] According to an embodiment of the inventive concept, the first sensing pattern SP1, the second sensing pattern SP2, the third sensing pattern SP3, and the fourth sensing pattern SP4 are respectively connected to the corresponding first sensing track line DSL1, the second sensing track line DSL2, the third sensing track line DSL3, and the fourth sensing track line DSL4. The sensing tracks DSL1, DSL2, DSL3, and DSL4 are arranged in the peripheral area NTA. The peripheral area NTA according to an embodiment of the inventive concept may overlap with the non-active area NAA (refer to Figure 1 ).

[0085] The non-active area NAA may be a portion of the display panel DP (see Figure 2A ) is an area overlapped with the non-display area of ​​the display panel DP and is an area on which driving elements and wirings of each of the display panel DP and the input sensing unit SU are arranged. Therefore, when the non-active area NAA of the electronic device EA is reduced, a narrow frame can be achieved. Therefore, it is necessary to reduce the non-display area of ​​the display panel DP and the peripheral area NTA of the input sensing unit SU.

[0086] According to an embodiment of the inventive concept, corresponding sensing trace lines DSL1, DSL2, DSL3, and DSL4 among the sensing trace lines DSL1, DSL2, DSL3, and DSL4 may overlap each other on a plane. For example, first sensing patterns SP1 and second sensing patterns SP2 spaced apart from each other in a first direction DR1 are connected to first sensing lines DSL1 and second sensing lines DSL2, respectively. The first sensing lines DSL1 and the second sensing lines DSL2 at least partially overlap each other on a plane.

[0087] The third sensing pattern SP3 and the fourth sensing pattern SP4, which are spaced apart from the first sensing pattern SP1 and the second sensing pattern SP2 and spaced apart from each other in the first direction DR1, are connected to the third sensing line DSL3 and the fourth sensing line DSL4, respectively. The third sensing line DSL3 and the fourth sensing line DSL4 at least partially overlap each other on a plane. Each of the third sensing line DSL3 and the fourth sensing line DSL4 is spaced apart from each of the first sensing line DSL1 and the second sensing line DSL2.

[0088] Reference Fig. 6A The first sensing line DSL1 and the first connection pattern DBP are disposed on the thin film encapsulation layer TFE. The first sensing line DSL1 and the first connection pattern DBP are spaced apart from each other by the first insulating layer IL1 and are electrically insulated from each other by the first insulating layer IL1.

[0089] The first insulating layer IL1 is disposed on the first sensing line DSL1 and the first connection pattern DBP. The first insulating layer IL1 includes a sensing contact hole CT and a first contact hole CNT1 each passing through the first insulating layer IL1.

[0090] The first pattern DSP is disposed on the first insulating layer IL1. The first pattern DSP is connected to the first connection pattern DBP through the sensing contact hole CT.

[0091] The second connection pattern KBP and the first sensing pattern SP1 are disposed on the first insulating layer IL1. Each of the second connection pattern KBP and the first sensing pattern SP1 is electrically insulated from the first pattern DSP by the second insulating layer IL2. The second connection pattern KBP and the first sensing pattern SP1 may be disposed on the same layer and connected to each other. The second connection pattern KBP and the first sensing pattern SP1 may substantially have an integral shape. That is, the second connection pattern KBP and the first sensing pattern SP1 may be continuously and integrally formed as a single piece and made of the same material or the same materials. Fig. 6A , for ease of description, the boundary between the second connection pattern KBP and the first sensing pattern SP1 is represented as a dotted line. The second connection pattern KBP and the first sensing pattern SP1 may be formed by a process using one mask in a manufacturing process. The first sensing pattern SP1 is connected to the first sensing line DSL1 through the first contact hole CNT1. Therefore, the second connection pattern KBP, the first sensing pattern SP1, and the first sensing line DSL1 are electrically connected to each other.

[0092] The second sensing line DSL2 is disposed on the first insulating layer IL1. The second sensing line DSL2 is electrically insulated from the first sensing pattern SP1 by the second insulating layer IL2.

[0093] The second insulating layer IL2 is disposed on the first pattern DSP, the second connection pattern KBP, the first sensing pattern SP1, and the second sensing line DSL2. The second insulating layer IL2 may be disposed on the first pattern DSP, the second connection pattern KBP, the first sensing pattern SP1, and the second sensing line DSL2 to provide an input sensing unit SU (refer to Figure 4 ). The first sensing patterns SP1, the second sensing patterns SP2, the third sensing patterns SP3, and the fourth sensing patterns SP4 according to an embodiment of the inventive concept may be disposed on the same layer.

[0094] The insulating layers IL1 and IL2 according to an embodiment of the inventive concept may include a material that insulates components disposed between the insulating layers. However, the inventive concept is not limited thereto.

[0095] Although in Fig. 6A In the embodiment, the first connection pattern DBP is disposed on the thin film encapsulation layer TFE, but the present invention is not limited thereto. For example, the sensing pattern may be disposed on the thin film encapsulation layer TFE with an insulating layer therebetween, and the connection pattern may be disposed on the insulating layer. In addition, although the base layer on which the wiring and the electrode are disposed may include the thin film encapsulation layer TFE, the present invention is not limited thereto. For example, in Figure 2B The above-mentioned encapsulation substrate EPL can be applied as the base layer.

[0096] Reference Figure 6B, the first sensing line DSL1 is disposed on the thin film encapsulation layer TFE. The first insulating layer IL1 is disposed on the first sensing line DSL1.

[0097] The second sensing pattern SP2 and the second sensing line DSL2 are disposed on the first insulating layer IL1. The second sensing pattern SP2 and the second sensing line DSL2 may be disposed on the same layer and connected to each other. The second sensing pattern SP2 and the second sensing line DSL2 may have substantially an integral shape. Figure 6B In FIG. 1 , for convenience of description, a boundary between the second sensing pattern SP2 and the second sensing line DSL2 is represented as a dotted line. A second insulating layer IL2 is disposed on the second sensing pattern SP2 and the second sensing line DSL2.

[0098] According to an embodiment of the inventive concept, the sensing trace lines DSL1 and DSL2 connected to the adjacent sensing patterns SP1 and SP2 may overlap each other on a plane. Fig. 6A and Figure 6B Only the first sensing line DSL1 and the second sensing line DSL2 connected to the first sensing pattern SP1 and the second sensing pattern SP2 are described in Fig. 6A and Figure 6B The structure shown in the figure can be applied to the third sensing line DSL3 and the fourth sensing line DSL4 which are respectively connected to the third sensing pattern SP3 and the fourth sensing pattern SP4 and are spaced apart from the first sensing pattern SP1 and the second sensing pattern SP2 in the first direction DR1. Although not shown in the drawings, the third sensing line DSL3 can be disposed on the same layer as one of the first sensing line DSL1 and the second sensing line DSL2. Therefore, the third sensing line DSL3 and the fourth sensing line DSL4 can partially overlap each other on a plane.

[0099] According to an embodiment of the inventive concept, since the trace lines connected to adjacent sensing patterns partially overlap each other on a plane (for example, a portion of the first sensing line DSL1 and a portion of the second sensing line DSL2 overlap on a plane, and the third sensing line DSL3 and the fourth sensing line DSL4 partially overlap each other on a plane), the space of the peripheral area NTA in which the sensing trace lines DSL1, DSL2, DSL3, and DSL4 are disposed can be reduced. Therefore, the electronic device according to an embodiment of the inventive concept can achieve a narrow frame.

[0100] Reference Figure 6C , different from Figure 6BAccording to the second sensing line DSL2 of the embodiment, the second sensing line DSL2-A may cover a portion of the second sensing pattern SP2. Therefore, the second sensing line DSL2-A and the second sensing pattern SP2 may have independent shapes. The second sensing pattern SP2 and the second sensing line DSL2-A may be formed by different masks from each other during the manufacturing process.

[0101] Figure 7 It is shown Figure 4 The enlarged view of the area BB'. Figures 1 to 4 The same components in the drawings will be denoted by the same reference numerals, and overlapping descriptions will be omitted. Figure 7 In order to facilitate the description, the first drive pattern SP5, the second drive pattern SP6, the third drive pattern SP7 and the fourth drive pattern SP8 are used to represent the drive pattern SP5, the second drive pattern SP6, the third drive pattern SP7 and the fourth drive pattern SP8. Figure 4 In addition, the first driving track line KSL1, the second driving track line KSL2, the third driving track line KSL3 and the fourth driving track line KSL4 (track driving lines may also be referred to as driving lines) are represented. Figure 4 The track lines SL1, SL2 and SL3 in FIG. 1 are connected to the first drive pattern SP5, the second drive pattern SP6, the third drive pattern SP7 and the fourth drive pattern SP8.

[0102] According to an embodiment of the inventive concept, the first driving pattern SP5, the second driving pattern SP6, the third driving pattern SP7 and the fourth driving pattern SP8 are respectively connected to the corresponding first driving trajectory line KSL1, the second driving trajectory line KSL2, the third driving trajectory line KSL3 and the fourth driving trajectory line KSL4. The driving trajectory lines KSL1, KSL2, KSL3 and KSL4 are arranged in the peripheral area NTA.

[0103] According to an embodiment of the inventive concept, corresponding driving track lines KSL1, KSL2, KSL3, and KSL4 among the driving track lines KSL1, KSL2, KSL3, and KSL4 may overlap each other on a plane. For example, first driving patterns SP5 and second driving patterns SP6 spaced apart from each other in the second direction DR2 are connected to the first driving line KSL1 and the second driving line KSL2, respectively. The first driving line KSL1 and the second driving line KSL2 partially overlap each other on a plane.

[0104] The third driving pattern SP7 and the fourth driving pattern SP8, which are spaced apart from the first driving pattern SP5 and the second driving pattern SP6 and spaced apart from each other in the second direction DR2, are connected to the third driving line KSL3 and the fourth driving line KSL4, respectively. The third driving line KSL3 and the fourth driving line KSL4 at least partially overlap each other on a plane. Each of the third driving line KSL3 and the fourth driving line KSL4 is spaced apart from each of the first driving line KSL1 and the second driving line KSL2.

[0105] According to an embodiment, each of the first drive pattern SP5 and the third drive pattern SP7 is disposed on a layer different from that of each of the first drive line KSL1 and the third drive line KSL3. Therefore, the first drive pattern SP5 is connected to the first drive line KSL1 through the third contact hole CNT3, and the third drive pattern SP7 is connected to the third drive line KSL3 through the fourth contact hole CNT4. The second drive pattern SP6 and the fourth drive pattern SP8 may be disposed on the same layer as the second drive line KSL2 and the fourth drive line KSL4, respectively, to have an integral shape.

[0106] According to an embodiment of the inventive concept, corresponding driving trace lines KSL1, KSL2, KSL3, and KSL4 connected to the driving electrodes among the driving trace lines KSL1, KSL2, KSL3, and KSL4 may overlap each other on a plane to reduce a space of a peripheral area NTA in which the driving trace lines KSL1, KSL2, KSL3, and KSL4 are disposed. Therefore, an electronic device according to an embodiment of the inventive concept may achieve a narrow frame.

[0107] Figure 8 is a plan view illustrating one region of an input sensing unit according to an embodiment of the inventive concept. Fig.9A is along Figure 8 A cross-sectional view taken along line III-III'. Fig. 9B is along Figure 8 A cross-sectional view taken along line IV-IV'. Fig. 9C is along Figure 8 A cross-sectional view taken along the line V-V'. Figures 5 to 6B The same components in the drawings will be denoted by the same reference numerals, and overlapping descriptions will be omitted.

[0108] Reference Figure 8 According to the embodiment, the sensing lines DSL1, DSL2, DSL3 and DSL4 may at least partially cross each other on a plane. For example, the first sensing line DSL1 and the second sensing line DSL2 are connected to the first sensing pattern SP1 and the third sensing pattern SP3, respectively. The first sensing line DSL1 and the second sensing line DSL2 at least partially overlap each other on a plane.

[0109] The third sensing line DSL3 is connected to the second sensing pattern SP2. In the first direction DR1, the second sensing pattern SP2 is disposed between the first sensing pattern SP1 and the third sensing pattern SP3. According to an embodiment, the third sensing line DSL3 connected to the second sensing pattern SP2 may be relatively farther from the sensing area TA than the first sensing line DSL1 and the second sensing line DSL2. The third sensing line DSL3 passes through the peripheral area NTA and is connected to the second sensing pattern SP2. Therefore, a portion of the third sensing line DSL3 connected to the second sensing pattern SP2 may overlap a portion of the second sensing line DSL2 on a plane.

[0110] Reference Fig.9A , the first sensing line DSL1 is disposed on the thin film encapsulation layer TFE. The first insulating layer IL1 is disposed on the first sensing line DSL1. The first insulating layer IL1 includes a fifth contact hole CNT5 passing therethrough.

[0111] The first sensing pattern SP1 and the second sensing line DSL2 are disposed on the first insulating layer IL1. The first sensing pattern SP1 and the second sensing line DSL2 are spaced apart from each other by the second insulating layer IL2 and are electrically insulated from each other by the second insulating layer IL2. The first sensing pattern SP1 is connected to the first sensing line DSL1 through the fifth contact hole CNT5. The second insulating layer IL2 is disposed on the first sensing pattern SP1 and the second sensing line DSL2.

[0112] Reference Fig. 9B The first sensing line DSL1 and the third sensing line DSL3 are disposed on the thin film encapsulation layer TFE. The first sensing line DSL1 and the third sensing line DSL3 are spaced apart from each other by the first insulating layer IL1 and are electrically insulated from each other by the first insulating layer IL1.

[0113] The third sensing pattern SP3 and the second sensing line DSL2 are disposed on the first insulating layer IL1. The third sensing pattern SP3 and the second sensing line DSL2 may be disposed on the same layer and connected to each other. The third sensing pattern SP3 and the second sensing line DSL2 may have substantially an integral shape. Fig. 9B , for ease of description, a boundary between the third sensing pattern SP3 and the second sensing line DSL2 is represented as a dotted line. The second insulating layer IL2 is disposed on the third sensing pattern SP3 and the second sensing line DSL2. According to an embodiment, the first sensing line DSL1 and the second sensing line DSL2, respectively connected to the first sensing pattern SP1 and the third sensing pattern SP3 spaced apart from each other, at least partially overlap each other.

[0114] Reference Fig. 9C, the third sensing line DSL3 is disposed on the thin film encapsulation layer TFE. The first insulating layer IL1 is disposed on the third sensing line DSL3. The first insulating layer IL1 includes a sixth contact hole CNT6 passing therethrough. The third sensing line DSL3 is connected to the second sensing pattern SP2 disposed between the first sensing pattern SP1 and the third sensing pattern SP3, and the first sensing pattern SP1 and the third sensing pattern SP3 are spaced apart from each other in the first direction DR1.

[0115] The second sensing pattern SP2, the second sensing line DSL2 and the fourth sensing line DSL4 are disposed on the first insulating layer IL1. The second sensing pattern SP2, the second sensing line DSL2 and the fourth sensing line DSL4 are spaced apart from each other by the second insulating layer IL2 and are electrically insulated from each other by the second insulating layer IL2.

[0116] The second sensing pattern SP2 is connected to the third sensing line DSL3 through the sixth contact hole CNT6. The second insulating layer IL2 is disposed on the second sensing pattern SP2, the second sensing line DSL2, and the fourth sensing line DSL4.

[0117] According to an embodiment, at least a portion of the third sensing line DSL3 connected to the second sensing pattern SP2 disposed between the sensing patterns SP1 and SP3 spaced apart from each other may overlap a portion of the second sensing line DSL2.

[0118] Fig.10 1 is a plan view showing one region of an input sensing unit according to an embodiment of the inventive concept. Figures 5 to 6B The same components in the drawings will be denoted by the same reference numerals, and overlapping descriptions will be omitted.

[0119] Reference Fig.10 ,and Figure 5 Differently, the sensing lines DSL-A and DSL-B overlapping each other on a plane may be disposed between the single lines SL-A and SL-B. That is, at least a portion of the lines disposed in the peripheral area NTA may include only single lines that do not overlap each other on a plane, and the sensing lines DSL-A and DSL-B overlapping each other on a plane may be spaced apart from the single lines SL-A and SL-B.

[0120] For example, the first sensing line DSL-A of the sensing lines DSL-A and DSL-B may be disposed on a different layer from the second sensing pattern SP2 and connected to the second sensing pattern SP2 through the contact hole CNT7. The second sensing line DSL-B may be disposed on the same layer as the third sensing pattern SP3 and directly connected to the third sensing pattern SP3.

[0121] The single lines SL-A and SL-B may be connected to the sensing patterns SP1 and SP3 through contact holes, or be disposed on the same layer as the sensing patterns SP1 and SP3 and directly connected to each other. However, embodiments of the inventive concept are not limited thereto.

[0122] According to an embodiment of the inventive concept, when traces connected to different electrodes among traces disposed in the peripheral area overlap on a plane, a space of the peripheral area can be reduced. Therefore, an electronic device according to an embodiment of the inventive concept can achieve a narrow frame.

[0123] The above-disclosed subject matter is considered to be illustrative rather than restrictive.

Claims

1. An electronic device, comprising: A display panel, the display panel comprising: a base layer; a pixel layer disposed on the base layer and comprising a plurality of pixels; and an encapsulation layer covering the pixel layer, the display panel being divided into a display area in which the plurality of pixels are disposed and a non-display area disposed adjacent to the display area on a plane; and An input sensing unit, the input sensing unit comprising: a first pattern and a second pattern, which are disposed on the display panel, overlap the display area, receive the same signal, and are disposed on the same layer while being spaced apart from each other; an insulating layer, which is disposed on the encapsulation layer; and a first line and a second line, which overlap the non-display area and are disposed on different layers from each other and the insulating layer is located between the first line and the second line, wherein the first line is connected to the first pattern and the second line is connected to the second pattern, wherein the first line overlaps at least a portion of the second line on the plane, One of the connection between the first pattern and the first line and the connection between the second pattern and the second line is connected through a contact hole passing through the insulating layer, and the other of the connection between the first pattern and the first line and the connection between the second pattern and the second line is directly connected on the same layer.

2. The electronic device according to claim 1, wherein: The insulating layer includes a first insulating layer directly disposed on the encapsulation layer and a second insulating layer directly disposed on the first insulating layer.

3. The electronic device according to claim 2, wherein: The first pattern and the first line are directly connected on the same layer, and At least a portion of the first line covers at least a portion of the first pattern.

4. The electronic device according to claim 2, wherein: The first pattern and the first line are directly connected on the same layer, and The first pattern and the first line have an integral shape.

5. The electronic device according to claim 1, further comprising: a third pattern disposed on the same layer as the first pattern and spaced apart from the first pattern and the second pattern; as well as A third line is connected to the third pattern.

6. The electronic device according to claim 5, wherein: The third pattern is spaced apart from the first pattern, and the second pattern is located between the third pattern and the first pattern, and The third line is disposed on the same layer as one of the first line and the second line.

7. The electronic device according to claim 5, wherein: The third pattern is disposed between the first pattern and the second pattern, and The third line is disposed on the same layer as the first line.

8. The electronic device according to claim 1, wherein: The encapsulation layer includes an organic layer and a plurality of inorganic layers covering the organic layer.

9. The electronic device according to claim 1, further comprising a sealing portion, wherein the sealing portion is arranged to overlap the non-display area. in, The sealing portion is disposed between the base layer and the encapsulation layer.

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