A current-limited power supply control circuit

Abstract

The application relates to the field of electronic technology, in particular to a current-limiting power supply control circuit which comprises an input end and an output end, further comprises a PNP triode Q2, the emitter of the PNP triode Q2 is connected with the input end, and the collector of the PNP triode Q2 is connected with the output end; further comprises a PNP triode Q1 for controlling the base current of the PNP triode Q2, the emitter of the PNP triode Q1 is connected with the input end, and the collector of the PNP triode Q1 is connected with the base of the PNP triode Q2; a delay circuit for preventing the power self-locking of the PNP triode Q1 and the PNP triode Q2 is connected between the input end and the ground. After the above structure is adopted, the amplification of the triode is utilized to control the size of the resistor R4, thereby the base current of the PNP triode Q2 is controlled, and the current of the output end is controlled; when the PNP triode Q1 is opened, the output end can normally output only when the input end is powered again; the circuit is simple, the cost is low, and the power consumption is low.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic technology, in particular to a current-limiting power supply control circuit. BACKGROUND

[0002] In many application occasions, in order to prevent overload, short circuit and the like, the current and voltage of the output circuit need to be limited. The common method is to use fuse or sampling resistance ADC reading method to limit current and prevent short circuit. Fuse is generally used to prevent short circuit but not to prevent overload, and although sampling resistance is a very feasible and effective method, the power consumption of sampling resistance cannot be ignored in some low-power circuits with power consumption requirements.

[0003] Chinese utility model patent CN 207603267 U discloses a current-limiting control circuit, which comprises a voltage reference source U1, a diode D1, a resistor R1, a triode Q1 and a resistor R2 connected in sequence to form a closed loop; the emitter of the triode Q1 is connected with one end of the resistor R2, the collector of the triode Q1 is connected with one end of the resistor R1, and the base of the triode Q1 is connected between the positive electrode of the diode D1 and the resistor R1; the negative electrode of the diode D1 is connected to the voltage reference source U1; the voltage reference source U1 is connected with the resistor R2 and leads out a connection to the VCC end and the positive electrode of a capacitor C1; the negative electrode of the capacitor C1 is grounded. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a current-limiting power supply control circuit with low power consumption and low cost.

[0005] To solve the above technical problems, the current-limiting power supply control circuit of the present application comprises an input end and an output end, further comprising a PNP triode Q2, the emitter of the PNP triode Q2 is connected with the input end, and the collector of the PNP triode Q2 is connected with the output end; further comprising a PNP triode Q1 for controlling the base current of the PNP triode Q2, the emitter of the PNP triode Q1 is connected with the input end, and the collector of the PNP triode Q1 is connected with the base of the PNP triode Q2; a delay circuit for preventing the PNP triode Q1 and the PNP triode Q2 from being self-locked after power-on is connected between the input end and the ground.

[0006] Preferably, the delay circuit comprises a first delay circuit for controlling the delay of the PNP triode Q1 and a second delay circuit for controlling the delay of the PNP triode Q2, and the delay of the first delay circuit is greater than the delay of the second delay circuit.

[0007] Preferably, the first delay circuit comprises a capacitor C1, a resistor R1 and a resistor R2, the capacitor C1, the resistor R1 and the resistor R2 are connected in series between the input end and the ground, and the base of the PNP transistor Q1 is connected between the capacitor C1 and the resistor R1.

[0008] Preferably, the circuit further comprises a resistor R3 for controlling the voltage of the output end when the control circuit is turned off, one end of the resistor R3 is connected between the resistor R1 and the resistor R2, and the other end of the resistor R3 is connected with the output end.

[0009] Preferably, the second delay circuit comprises a capacitor C2 and a resistor R4, the capacitor C2 and the resistor R4 are connected in series between the input end and the ground, and the middle point of the capacitor C2 and the resistor R4 is connected with the base of the PNP transistor Q2.

[0010] After the above structure is adopted, the application utilizes the amplification of the transistor to control the size of the resistor R4, thereby controlling the base current of the PNP transistor Q2, and controlling the current of the output end; the ratio of the resistor R1, the resistor R2 and the resistor R3 is utilized to control the on-off of the PNP transistor Q1, thereby controlling the state of the output end; when the PNP transistor Q1 is turned on, only when the input end is powered again, the output end can normally output; the circuit is simple, the cost is low, and the power consumption is low. BRIEF DESCRIPTION OF DRAWINGS

[0011] The application will be further described in detail below in combination with the drawings and specific embodiments.

[0012] Figure 1 The circuit schematic diagram of the current-limiting power supply control circuit of the application. DETAILED DESCRIPTION

[0013] As shown in the drawings, Figure 1 The current-limiting power supply control circuit of the application comprises an input end and an output end, further comprises a PNP transistor Q2, the emitter of the PNP transistor Q2 is connected with the input end, and the collector of the PNP transistor Q2 is connected with the output end; further comprises a PNP transistor Q1 for controlling the base current of the PNP transistor Q2, the emitter of the PNP transistor Q1 is connected with the input end, and the collector of the PNP transistor Q1 is connected with the base of the PNP transistor Q2; the delay circuit for preventing the PNP transistor Q1 and the PNP transistor Q2 from being power-on self-locking is connected between the input end and the ground.

[0014] The delay circuit includes a first delay circuit for controlling the delay of PNP transistor Q1 and a second delay circuit for controlling the delay of PNP transistor Q2, the delay of the first delay circuit is greater than the delay of the second delay circuit. The first delay circuit includes capacitor C1, resistor R1 and resistor R2, which are connected in series between the input terminal and the ground, the base of PNP transistor Q1 is connected between capacitor C1 and resistor R1. It also includes a resistor R3 for controlling the output voltage when the control circuit is off, one end of the resistor R3 is connected between resistor R1 and resistor R2, the other end of the resistor R3 is connected with the output terminal. The second delay circuit includes capacitor C2 and resistor R4, which are connected in series between the input terminal and the ground, the middle point of capacitor C2 and resistor R4 is connected with the base of PNP transistor Q2.

[0015] Wherein, the first capacitor C1 and the first resistor R1, the second resistor R2 form a delay circuit, the second capacitor C2 and the fourth resistor R4 form another delay circuit, in order to ensure that the power moment is not self-locking, that is, the second NPN transistor Q2 is opened before the first NPN transistor Q1, the delay formed by the first capacitor C1 and the first resistor R1, the second resistor R2 is greater than the delay formed by the second capacitor C2 and the fourth resistor R4. The first resistor R1, the second resistor R2 and the fourth resistor R4, the parameters of the matching should be able to completely turn off the second NPN transistor Q2 when the first NPN transistor Q1 is opened. Resistor R4 controls the base current of the first NPN transistor Q1, using the amplification principle of the transistor, the collector current of the first NPN transistor Q1 is controlled; at the same time, the collector current of the second NPN transistor Q2 is controlled, the ratio of resistor R2 and resistor R3 controls the voltage and current of the circuit when it is off.

[0016] The working principle of the present application is as follows: one end of the resistor R4 is connected to the base of the PNP transistor Q2, and the other end is connected to the ground, thus completing the control of the base current of the PNP transistor Q2 to control the output current of the collector of the PNP transistor Q2, that is, the current control of the first output terminal Vout; one end of the resistor R3 is connected to the collector of the PNP transistor Q2, and the other end is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the base of the PNP transistor Q1, one end of the resistor R2 is connected to the common end of the resistor R1 and the resistor R3, and the other end is connected to the ground, the ratio of the resistor R1, the resistor R2 and the resistor R3 controls the on-off of the PNP transistor Q1 and controls the voltage of the first output terminal Vout when it is off; the resistor R1 and the resistor R2 control the base current of the PNP transistor Q1 to control the on-off of the PNP transistor Q2. One end of the capacitor C1 is connected to the first input terminal Vin, and the other end is connected to the base of the PNP transistor Q1, the capacitor C2 is connected to the first input terminal Vin, and the other end is connected to the base of the PNP transistor Q2, the collector of the PNP transistor Q1 is connected to the base of the PNP transistor Q2, the capacitor C1 and the resistor R1 and the resistor R2 form a delay circuit, the capacitor C2 and the resistor R4 form a delay circuit, in order to ensure that the circuit is not self-locked at the moment of power-on, that is, the PNP transistor Q2 is opened earlier than the PNP transistor Q1, the delay formed by the capacitor C1 and the resistor R1 and the resistor R2 is greater than the delay formed by the capacitor C2 and the resistor R4. The first input terminal Vin is connected to the emitter of the PNP transistor Q1 and the emitter of the PNP transistor Q2.

[0017] When the first output terminal Vin is short-circuited or overloaded, the voltage of the collector of the PNP transistor Q2 decreases obviously, which is fed back to the base of the PNP transistor Q1, when the voltage of the base of the PNP transistor Q1 is less than the voltage of the first input terminal Vin by 0.7V, the PNP transistor Q1 is opened, the voltage of the emitter of the PNP transistor Q1 is fed back to the base of the PNP transistor Q2, and the voltage difference between the voltage of the first input terminal Vin and the voltage of the base of the PNP transistor Q2 is greater than 0.7V, the PNP transistor Q2 is turned off, and the circuit stops supplying power to the outside, only when the first input terminal Vin is powered again, the circuit can work normally again.

[0018] Although the specific embodiments of the present application are described above, those skilled in the art should understand that these are only examples, and various changes or modifications can be made to the embodiments without departing from the principles and essence of the present application, and the protection scope of the present application is only limited by the appended claims.

Claims

1. A current limited power supply control circuit comprising an input and an output, characterized by: The application also comprises a PNP triode Q2, the emitter of which is connected with the input end, and the collector of which is connected with the output end; a PNP triode Q1 for controlling the base current of the PNP triode Q2, the emitter of which is connected with the input end, and the collector of which is connected with the base of the PNP triode Q2; a delay circuit for preventing the PNP triode Q1 and the PNP triode Q2 from being self-locked by power between the input end and the ground; the delay circuit comprises a first delay circuit for controlling the delay of the PNP triode Q1 and a second delay circuit for controlling the delay of the PNP triode Q2, and the delay of the first delay circuit is greater than that of the second delay circuit; the second delay circuit comprises a capacitor C2 and a resistor R4, which are connected in series between the input end and the ground, and the middle point of the capacitor C2 and the resistor R4 is connected with the base of the PNP triode Q2.

2. A current limited power supply control circuit as claimed in claim 1, characterized in that: The first delay circuit comprises a capacitor C1, a resistor R1 and a resistor R2, which are connected in series between the input end and the ground, and the base of the PNP triode Q1 is connected between the capacitor C1 and the resistor R1.

3. A current limited power supply control circuit as claimed in claim 2, wherein: The application also comprises a resistor R3 for controlling the voltage of the output end when the control circuit is turned off, one end of the resistor R3 is connected between the resistor R1 and the resistor R2, and the other end of the resistor R3 is connected with the output end.

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