Display device

Abstract

A display device is provided. The display device includes: a first data line, located on a first interlayer insulating layer above a substrate; a first power line and a second power line, located on a second interlayer insulating layer, the second interlayer insulating layer covers the first data line; and a plurality of pixels. A first pixel among the plurality of pixels includes: a display element, including a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode, the second power line is connected to the counter electrode; and a driving thin film transistor, located between the substrate and the display element, and including a driving semiconductor layer, a driving gate electrode, a driving source electrode, and a driving drain electrode, the first interlayer insulating layer covers the driving gate electrode, and the first power line is connected to the driving source electrode.

Description

[0001] The Korean Patent Application No. 10-2018-0120604, filed on October 10, 2018 in the Korean Intellectual Property Office and entitled “DISPLAY DEVICE”, is hereby incorporated by reference in its entirety. Technical Field

[0002] Embodiments relate to a display device. Background Art

[0003] Display devices can be used to visually display information. The purposes of display devices have become more diverse. In addition, as display devices have become thinner and lighter, their scope of use has gradually expanded. Summary of the invention

[0004] The embodiment relates to a display device, which includes: a first data line located on a first interlayer insulating layer above a substrate; a first power line and a second power line located on a second interlayer insulating layer, the second interlayer insulating layer covering the first data line; and a plurality of pixels. A first pixel among the plurality of pixels includes: a display element including a pixel electrode, a counter electrode, and an intermediate layer located between the pixel electrode and the counter electrode, the second power line being connected to the counter electrode; and a driving thin film transistor located between the substrate and the display element and including a driving semiconductor layer, a driving gate electrode, a driving source electrode, and a driving drain electrode, the first interlayer insulating layer covering the driving gate electrode, and the first power line being connected to the driving source electrode.

[0005] The display device may further include: a storage capacitor including a first electrode and a second electrode. The first electrode may extend from the driving gate electrode, and the second electrode may be located on the first interlayer insulating layer and overlap the first electrode.

[0006] The display device may further include: a bias electrode located between the substrate and the driving semiconductor layer and overlapping the driving semiconductor layer.

[0007] The display device may further include: a sensing thin film transistor located above the substrate and including a sensing semiconductor layer, a sensing gate electrode, a sensing source electrode, and a sensing drain electrode. The bias electrode may be electrically connected to the sensing source electrode.

[0008] The bias electrode may overlap the storage capacitor, the first electrode and the second electrode may constitute a first capacitance, and the bias electrode and the first electrode may constitute a second capacitance.

[0009] The display device may further include: a planarization layer covering the first power line and the second power line. The pixel electrode may be located on the planarization layer and may be electrically connected to the driving thin film transistor through a first through hole defined in the planarization layer, and the second power line may be connected to the counter electrode through a second through hole defined in the planarization layer.

[0010] An area of ​​the second through hole may be greater than an area of ​​the first through hole.

[0011] The pixel electrode may include a groove corresponding to a shape of the second through hole.

[0012] The display device may further include: a second pixel adjacent to the first pixel; and a second data line extending over the first pixel and the second pixel and located in the same layer as the first data line. The first data line may be electrically connected to the first pixel, and the second data line may be electrically connected to the second pixel.

[0013] At least one of the first power line and the second power line may overlap the first data line.

[0014] Widths of the first power line and the second power line in the first direction may be greater than a width of the first data line in the first direction.

[0015] The pixel electrode may overlap the driving thin film transistor and may include a reflective layer.

[0016] The pixel electrode may not overlap the driving thin film transistor, and the counter electrode may include a reflective layer.

[0017] The driving semiconductor layer may include an oxide semiconductor.

[0018] The display device may further include: a switching thin film transistor located above the substrate; and a lower metal layer located between the substrate and the switching thin film transistor.

[0019] An embodiment also relates to a display device, comprising: a plurality of pixel circuits located above a substrate; and a plurality of display elements, respectively connected to the plurality of pixel circuits to realize an image, the display device comprising: a scan line extending along a first direction and connected to the plurality of pixel circuits arranged along the first direction; a first data line, a second data line and a reference voltage line, all extending in a second direction intersecting the first direction, arranged above the scan line, and a first interlayer insulating layer located between the scan line and the first data line, the second data line and the reference voltage line; and a first power line and a second power line, all extending along the second direction, arranged above the first data line, the second data line and the reference voltage line, and a second interlayer insulating layer located between the first data line, the second data line and the reference voltage line and the first power line and the second power line, the first power line is electrically connected to the pixel electrodes of the plurality of display elements, and the second power line is connected to the counter electrodes of the plurality of display elements.

[0020] The first data lines and the second data lines may be alternately connected to a plurality of pixel circuits arranged along the second direction.

[0021] The plurality of pixel circuits may include a first pixel circuit, a second pixel circuit, and a third pixel circuit adjacent to each other along the first direction, and the first power line may overlap a portion of the first pixel circuit, a portion of the third pixel circuit, and the second pixel circuit.

[0022] The second power line may be connected to the counter electrode through a via hole defined in the planarization layer, and the via hole overlaps the reference voltage line.

[0023] The reference voltage line may be connected to a reference voltage connection line extending in the first direction through a contact hole, and the reference voltage connection line may be commonly connected to three pixel circuits adjacent to each other.

[0024] Each of the plurality of pixel circuits may include three thin film transistors and one storage capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the accompanying drawings, in which:

[0026] Figure 1 shows a plan view of a display device according to an example embodiment;

[0027] Figure 2 Shows Figure 1 An equivalent circuit diagram of a pixel of a display device;

[0028] Figure 3 Shows Figure 2 A diagram showing the positions of the wiring of the pixel circuit, a plurality of thin film transistors, capacitors, etc.;

[0029] Figure 4 Shown along Figure 3 A cross-sectional view of a structure including an organic light emitting diode taken along line II';

[0030] Figure 5 Shown along Figure 3 A cross-sectional view taken along line II-II';

[0031] Figure 6 shows a plan view of a display device according to another example embodiment;

[0032] Figure 7 shows a plan view of a display device according to another example embodiment;

[0033] Figure 8 shows a cross-sectional view of a display device according to another example embodiment;

[0034] Fig. 9 shows a cross-sectional view of a display device according to another example embodiment;

[0035] Fig. 10A shows an equivalent circuit diagram of two adjacent pixels that may be provided to a display device according to another example embodiment;

[0036] Fig. 10B Shown according to Fig. 10A A diagram showing the driving timing of a pixel;

[0037] Fig.11 A plan view showing an arrangement of adjacent pixel circuits included in a display device according to another example embodiment;

[0038] Figure 12 to Figure 14 A plan view showing an arrangement relationship of a first power line, a second power line, a first data line, a second data line, and a reference voltage line according to an example embodiment; and

[0039] Fig.15 A plan view illustrating a shape of a pixel electrode according to example embodiments. DETAILED DESCRIPTION

[0040] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey example implementations to those skilled in the art. In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. The same reference numerals represent the same elements throughout.

[0041] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements in the list.

[0043] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component.

[0044] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] It will also be understood that the terms “comprises / includes” and / or variations thereof used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0046] It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, the layer, region or component may be directly or indirectly formed on the other layer, region or component. Thus, for example, intervening layers, regions or components may be present.

[0047] It will be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, the layer, region, or component may be "directly connected" to the other layer, region, or component, or may be "indirectly connected" to the other layer, region, or component with other layers, regions, or components located between them. For example, it will be understood that when a layer, region, or component is referred to as being "connected or electrically connected" to another layer, region, or component, the layer, region, or component may be "directly connected or directly electrically connected" to the other layer, region, or component, or may be "indirectly connected or indirectly electrically connected" to the other layer, region, or component with other layers, regions, or components located between them.

[0048] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0049] The display device may be a device that displays an image, and may include a liquid crystal display, an electrophoretic display, an organic light emitting display, an inorganic light emitting display, a field emission display, a surface conduction electron emitter display, a plasma display, and a cathode ray display. As an example, an organic light emitting display device is exemplarily described as a display device below.

[0050] Figure 1 is a plan view of a display device according to example embodiments.

[0051] Reference Figure 1 The display device includes a display area DA and a peripheral area PA, wherein the peripheral area PA is a non-display area around the display area DA. The peripheral area PA may be an area where no image is provided. The display area DA includes pixels PX, each of which includes a display element for providing a predetermined image.

[0052] Each pixel PX emits, for example, red light, green light, blue light, or white light, and may include, for example, an organic light emitting diode (OLED). In addition, each pixel PX may also include devices such as a thin film transistor (TFT) and a storage capacitor. The pixel PX may represent a sub-pixel that emits red light, green light, blue light, or white light.

[0053] A controller such as a scan driver and a data driver (each configured to apply an electrical signal to the pixels PX of the display area DA) may be arranged in the peripheral area PA. A pad unit connected to a printed circuit board on which the controller is mounted may be arranged in the peripheral area PA.

[0054] Figure 2 yes Figure 1 An equivalent circuit diagram of one pixel of a display device.

[0055] Reference Figure 2 , each pixel PX may include an OLED and a pixel circuit PC, the pixel circuit PC including a plurality of TFTs driving the OLED. The pixel circuit PC may include a driving TFT T1, a switching TFT T2, a sensing TFT T3, and a storage capacitor Cst. In other embodiments, various modifications may be made to the number of TFTs and the number of storage capacitors included in the pixel circuit PC or the structure of the pixel circuit PC.

[0056] The scan line SL may be connected to the gate electrode G2 of the switching TFT T2 , the data line DL may be connected to the source electrode S2 of the switching TFT T2 , and the first electrode CE1 of the storage capacitor Cst may be connected to the drain electrode D2 of the switching TFT T2 .

[0057] The switching TFT T2 may supply a data voltage (data signal) Dm of the data line DL to the first node N in response to a scan signal Sn from the scan line SL of each pixel PX.

[0058] The gate electrode G1 of the driving TFT T1 may be connected to the first node N, the source electrode S1 of the driving TFT T1 may be connected to the first power line PL1 configured to transmit the driving power voltage ELVDD, and the drain electrode D1 of the driving TFT T1 may be connected to the anode electrode of the OLED.

[0059] The driving TFT T1 may adjust the amount of current flowing through the OLED according to a gate-source voltage (Vgs) of the driving TFT T1 (eg, a voltage applied between the first power line PL1 and the first node N).

[0060] The gate electrode G3 of the sensing TFT T3 may be connected to the sensing control line SSL, the source electrode S3 of the sensing TFT T3 may be connected to the second node S, and the drain electrode D3 of the sensing TFT T3 may be connected to the reference voltage line RL. In example embodiments, the sensing TFT T3 may be controlled by the scan line SL instead of the sensing control line SSL.

[0061] The sensing TFT T3 may sense the potential of the anode electrode of the OLED. The sensing TFT T3 may supply a precharge voltage from the reference voltage line RL to the second node S in response to a sensing signal SSn from the sensing control line SSL, or supply the voltage of the anode electrode of the OLED to the reference voltage line RL via the second node S during a sensing period.

[0062] A first electrode CE1 of the storage capacitor Cst may be connected to the first node N, and a second electrode CE2 of the storage capacitor Cst may be connected to the second node S. The storage capacitor Cst may be charged based on a voltage difference between voltages supplied to the first node N and the second node S, respectively, and may supply a driving voltage to the driving TFT T1. For example, the storage capacitor Cst may be charged with a voltage difference between a data voltage Dm and a precharge voltage (Vpre) supplied to the first node N and the second node S, respectively.

[0063] The bias electrode BSM may be formed to face the driving TFT T1 and connected to the source electrode S3 of the sensing TFT T3. The bias electrode BSM may receive a voltage by cooperating with the potential of the source electrode S3 of the sensing TFT T3. Therefore, the driving TFT T1 may be stabilized. In an example embodiment, the bias electrode BSM may not be connected to the source electrode S3 of the sensing TFT T3, but may be connected to a separate bias wiring.

[0064] A counter electrode (eg, cathode) of the OLED may receive a common power voltage ELVSS via the second power line PL2 . The OLED may emit light based on a driving current from the driving TFT T1 .

[0065] As an example, Figure 2 The case where each pixel PX includes signal lines SL, SSL and DL, a reference voltage line RL, a first power line PL1 and a second power line PL2 is shown. In another embodiment, at least one of the signal lines SL, SSL and DL and the reference voltage line RL, the first power line PL1 and the second power line PL2 can be shared by adjacent pixels.

[0066] Figure 3 is a diagram showing the wiring of a pixel circuit PC, the positions of a plurality of thin film transistors, and capacitors according to an exemplary embodiment, Figure 4 is along Figure 3 A cross-sectional view of a structure including an OLED taken along line II', Figure 5 is along Figure 3 A cross-sectional view taken along line II-II'.

[0067] Reference Figure 3, the pixel circuit PC of the display device according to the present example embodiment may be connected to the scan line SL, the sensing control line SSL, the first mesh line ML1, the second mesh line ML2, and the reference voltage connection line RCL, all of which extend in the first direction.

[0068] The pixel circuit PC may be connected to a data line DL, a reference voltage line RL, a first power line PL1, and a second power line PL2, each extending in a second direction crossing the first direction.

[0069] In the present exemplary embodiment, the scan line SL, the sensing control line SSL, the first mesh line ML1 and the second mesh line ML2 may be arranged in the same layer. The data line DL and the reference voltage line RL may be arranged in the same layer and may be arranged above the scan line SL, and the first interlayer insulating layer 115 (see Figure 4 ) is located between the data line DL and the reference voltage line RL and the scan line SL. In addition, the first power line PL1 and the second power line PL2 may be arranged above the data line DL, and the second interlayer insulating layer 117 is located between the first power line PL1 and the second power line PL2 and the data line DL.

[0070] In the present example embodiment, the reference voltage connection line RCL may be disposed in the same layer as that of the semiconductor layer. The reference voltage connection line RCL may be disposed in the same layer as that of the scan line SL. The first mesh line ML1 and / or the second mesh line ML2 may be omitted.

[0071] The pixel circuit PC may include a driving TFT T1 , a switching TFT T2 , a sensing TFT T3 , and a storage capacitor Cst.

[0072] The semiconductor layers A1, A2, and A3 (of each of the driving TFT T1, the switching TFT T2, and the sensing TFT T3) may be arranged in the same layer and include the same material. For example, all of the semiconductor layers A1, A2, and A3 may include amorphous silicon or polycrystalline silicon. In addition, the semiconductor layers A1, A2, and A3 may include an oxide semiconductor material containing an oxide of at least one of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, Al, Cs, Ce, and Zn. In example embodiments, the semiconductor layers A1, A2, and A3 may include Zn oxide, In-Zn oxide, and Ga-In-Zn oxide as Zn oxide-based materials. In example embodiments, the semiconductor layers A1, A2, and A3 may include a semiconductor including IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O) in which ZnO contains a metal such as In, Ga, or Sn. The semiconductor layers A1, A2, and A3 may include a single layer or a multilayer.

[0073] The semiconductor layers A1, A2, and A3 may include a channel region, and may include a source region and a drain region located on two opposite sides of the channel region. The source region and the drain region may include a carrier concentration adjustment region. For example, in the case where the semiconductor layers A1, A2, and A3 include silicon, the source region and the drain region may be doped with impurities. For another example, in the case where the semiconductor layers A1, A2, and A3 include an oxide semiconductor, the source region and the drain region may include a region whose carrier concentration has been increased by a plasma process.

[0074] The gate electrodes G1, G2, and G3 may overlap the channel regions of the semiconductor layers A1, A2, and A3, respectively, and the gate insulating layer 113 (see Figure 4 ) are located between the gate electrodes G1, G2, and G3 and the semiconductor layers A1, A2, and A3. The source electrodes S1, S2, and S3 and the drain electrodes D1, D2, and D3 disposed on the first interlayer insulating layer 115 may be connected to the source region and the drain region through contact holes, respectively.

[0075] The gate electrode G1 of the driving TFT T1 may have an island shape. The gate electrode G1 may be used as the gate electrode G1 of the driving TFT T1, and may be used as the first electrode CE1 of the storage capacitor Cst. Therefore, the gate electrode G1 may be formed as a single body with the first electrode CE1 of the storage capacitor Cst. A portion of the gate electrode G1 may overlap the semiconductor layer A1 of the driving TFT T1, and another portion of the gate electrode G1 may overlap the second electrode CE2 of the storage capacitor Cst to constitute the first capacitor C1 (see Figure 4 ). In another embodiment, the first electrode CE1 of the storage capacitor Cst may be understood as extending from the gate electrode G1 overlapping the semiconductor layer A1 of the driving TFT T1.

[0076] The bias electrode BSM may be disposed under the driving TFT T1 to correspond to the gate electrode G1 and the first electrode CE1 of the storage capacitor Cst. The first electrode CE1 and the bias electrode BSM may constitute a second capacitor C2 (see Figure 4 ). One end of the gate electrode G1 may be connected to the drain electrode D2 of the switching TFT T2 through the first node contact hole CNT1.

[0077] The gate electrode G2 of the switching TFT T2 may be provided as a portion of the scan line SL. Therefore, the gate electrode G2 may be provided as a region protruding in the second direction from the scan line SL extending in the first direction. Therefore, the scan signal Sn from the scan line SL may be transmitted to the gate electrode G2, and the switching TFT T2 may operate in response to the scan signal Sn.

[0078] The gate electrode G3 of the sensing TFT T3 may be provided as a portion of the sensing control line SSL. Therefore, the sensing control line SSL may overlap the semiconductor layer A3 of the sensing TFT T3, and the overlapping region may function as the gate electrode G3. Therefore, the sensing signal SSn transmitted from the sensing control line SSL may be transmitted to the gate electrode G3, and the sensing TFT T3 may operate in response to the sensing signal SSn.

[0079] The drain electrode D1 of the driving TFT T1 may be integrally provided with the second electrode CE2 of the storage capacitor Cst and the source electrode S3 of the sensing TFT T3 and connected to the bias electrode BSM through the second node contact hole CNT2. The source electrode S1 of the driving TFT T1 may be connected to the first power line PL1 through the contact hole CNT3.

[0080] The source electrode S2 of the switching TFT T2 may be provided as a part of the data line DL and may transmit the data signal Dm of the data line DL to the source region of the switching TFT T2. One end of the drain electrode D2 of the switching TFT T2 may be connected to the first electrode CE1 of the storage capacitor Cst through the first node contact hole CNT1.

[0081] The source electrode S3 of the sensing TFT T3 may be connected to the drain electrode D1 of the driving TFT T1, and the drain electrode D3 may be arranged to correspond to the drain region of the semiconductor layer A3 of the sensing TFT T3. The drain region may be formed in a portion of a reference voltage connection line RCL arranged in the same layer as that of the semiconductor layer A3. The reference voltage connection line RCL may be connected to the reference voltage line RL through a contact hole CNT4.

[0082] The first electrode CE1 of the storage capacitor Cst may be formed integrally with the gate electrode G1, and the second electrode CE2 may overlap the first electrode CE1, and the first interlayer insulating layer 115 (see FIG. 1 ) may be formed integrally with the gate electrode G1. Figure 4 ) is located between the second electrode CE2 and the first electrode CE1. The second electrode CE2 can be connected to the connection electrode CM arranged above it through the contact hole CNT5. The connection electrode CM can be connected to the pixel electrode 310 of the OLED through the first through hole VH1 (see Figure 4 ). The connection electrode CM may be arranged in an island shape in the same layer as that of the first power line PL1 and the second power line PL2. The connection electrode CM may be spaced apart from the first power line PL1 and the second power line PL2.

[0083] The bias electrode BSM may be disposed on the first buffer layer 111 (see FIG. 1 ) below the first electrode CE1 of the storage capacitor Cst. Figure 4 ) and the second buffer layer 112 (see Figure 4). The bias electrode BSM and the first electrode CE1 of the storage capacitor Cst may constitute a second capacitor C2. One end of the bias electrode BSM may be connected to the source electrode S3 of the sensing TFT T3. Therefore, the bias electrode BSM may receive a voltage by cooperating with a voltage applied to the source electrode S3. For example, a separate bias voltage may be provided to the bias electrode BSM, or a voltage may not be applied to the bias electrode BSM.

[0084] The first power line PL1 and the second power line PL2 may extend in the second direction in the same layer. The first power line PL1 and the second power line PL2 may be voltage lines configured to transmit different voltages, respectively. The first power line PL1 may transmit a driving power voltage ELVDD, and the second power line PL2 may transmit a common power voltage ELVSS.

[0085] The first power line PL1 may be connected to the first mesh lines ML1 extending in the first direction through the contact holes CNT6. The driving power voltage ELVDD may be provided in a mesh structure through the first power line PL1 extending in the second direction and the first mesh lines ML1 extending in the first direction.

[0086] The second power line PL2 may be connected to the second mesh line ML2 extending in the first direction through the contact hole CNT7. The common power voltage ELVSS may be provided in a mesh structure through the second power line PL2 extending in the second direction and the second mesh line ML2 extending in the first direction. In example embodiments, the first mesh line ML1 and / or the second mesh line ML2 may be omitted.

[0087] The first power line PL1 may be connected to the source electrode S1 of the driving TFT T1 through the contact hole CNT3. The second power line PL2 may be connected to the counter electrode 330 of the OLED through the second through hole VH2 (see FIG. Figure 4 ).

[0088] The first and second power lines PL1 and PL2 may be arranged in a layer different from that of the data line DL, the reference voltage line RL, and the second electrode CE2 of the storage capacitor Cst. Therefore, the widths of the first and second power lines PL1 and PL2 may be easily adjusted.

[0089] In an example embodiment, at least one of the first power line PL1 and the second power line PL2 may overlap with the storage capacitor Cst. In an example embodiment, at least one of the first power line PL1 and the second power line PL2 may overlap with the data line DL. Although the drawings show that the second power line PL2 overlaps with the data line DL and the reference voltage line RL, the first power line PL1 may overlap with the data line DL, for example.

[0090] In example embodiments, respective widths W1 and W2 of the first power line PL1 and / or the second power line PL2 in the first direction may be greater than widths of the first electrode CE1, the second electrode CE2, and / or the bias electrode BSM of the storage capacitor Cst in the first direction. In example embodiments, the first power line PL1 or the second power line PL2 may cover a portion of the pixel circuit PC and at least a portion of an adjacent pixel circuit PC.

[0091] The widths W1 and W2 of the first power line PL1 and the second power line PL2 in the first direction may be greater than the width W1 of the data line DL. D The widths W1 and W2 of the first power line PL1 and the second power line PL2 in the first direction may be greater than the width W1 of the reference voltage line RL. R Therefore, the IR drop of the driving power supply voltage ELVDD or the common power supply voltage ELVSS can be minimized.

[0092] The first power line PL1 and the second power line PL2 may be arranged to cover most of the area of ​​one pixel circuit PC. In this case, the first power line PL1 and the second power line PL2 may be used as a shielding plate against external electrical signals. Considering parasitic capacitance, the first power line PL1 and the second power line PL2 may only cover a portion of one pixel circuit PC.

[0093] In a display device according to an example embodiment, having Figure 3 The pixel circuits PC of the same shape as described may be arranged as a plurality of pixel circuits PC having a configuration in which the pixel circuits PC are parallelly moved in the first and second directions. The pixel circuits PC included in the display device according to example embodiments may have a symmetrical shape with adjacent pixel circuits.

[0094] Hereinafter, a structure of a display device according to example embodiments is described according to a stacking order. Figure 4 The structures of the driving TFT T1 , the switching TFT T2 , and the storage capacitor Cst are mainly shown, and some elements may be omitted for clear description.

[0095] Reference Figure 4, at least one pixel of the display device according to the present exemplary embodiment includes an OLED located on the substrate 100. The OLED is a display element disposed above the substrate 100. The display device according to the present exemplary embodiment includes a driving TFT T1, a first interlayer insulating layer 115 covering a gate electrode G1 of the driving TFT T1, a data line DL disposed on the first interlayer insulating layer 115, a second interlayer insulating layer 117 covering the data line DL, and a first power line PL1 and a second power line PL2 disposed on the second interlayer insulating layer 117. The first power line PL1 may be connected to a source electrode S1 of the driving TFT T1, and the second power line PL2 may be connected to a counter electrode 330 of the OLED.

[0096] The display device according to the present example embodiment may further include a storage capacitor Cst connected to the driving TFT T1 and a bias electrode BSM disposed under the driving TFT T1 .

[0097] The bias electrode BSM may overlap the storage capacitor Cst. The first electrode CE1 and the second electrode CE2 of the storage capacitor Cst may constitute a first capacitor C1. The first electrode CE1 and the bias electrode BSM may constitute a second capacitor C2.

[0098] The substrate 100 may include, for example, a glass material, a ceramic material, a metal material, a flexible material or a bendable material. In the case where the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP). The substrate 100 may have a single-layer structure or a multi-layer structure including the above-mentioned materials. In the case where the substrate 100 has a multi-layer structure, the substrate 100 may also include an inorganic layer. In an example embodiment, the substrate 100 may have a structure of an organic material / inorganic material / organic material.

[0099] The first buffer layer 111 may increase the flatness of the top surface of the substrate 100. The first buffer layer 111 may include, for example, SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 and ZnO 2 One or more of .

[0100] A barrier layer may also be disposed between the substrate 100 and the first buffer layer 111. The barrier layer may prevent or minimize impurities from penetrating from the substrate 100 or the like into the semiconductor layers A1 and A2. The barrier layer may include, for example, an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic composite material. The barrier layer may have a single-layer structure or a multi-layer structure.

[0101] The bias electrode BSM may be disposed on the first buffer layer 111 to correspond to the driving TFT T1 and the storage capacitor Cst. The bias electrode BSM may be connected to the sensing TFT T3 (see Figure 5 ) of the source electrode S3 (see Figure 5 ), and may receive the voltage of the source electrode S3. The bias electrode BSM may prevent external light from reaching the semiconductor layer A1, which may help stabilize the operation of the driving TFT T1.

[0102] The second buffer layer 112 may cover the bias electrode BSM and may be formed over the entire surface of the substrate 100. The second buffer layer 112 may include, for example, SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 and ZnO 2 One or more of .

[0103] The semiconductor layers A1 and A2 may be arranged on the second buffer layer 112. The semiconductor layers A1 and A2 may include, for example, amorphous silicon or polycrystalline silicon. In another embodiment, the semiconductor layers A1 and A2 may include, for example, an oxide of one or more of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, Al, Cs, Ce, and Zn. In an example embodiment, the semiconductor layers A1 and A2 may include Zn oxide, In-Zn oxide, or Ga-In-Zn oxide as a Zn oxide-based material. In another embodiment, the semiconductor layers A1 and A2 may include a semiconductor including IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O) in which ZnO contains a metal such as In, Ga, or Sn. The semiconductor layers A1 and A2 may include a channel region and a source region and a drain region arranged on two opposite sides of the channel region. The semiconductor layers A1 and A2 may include a single layer or a multilayer.

[0104] The gate electrodes G1 and G2 may be disposed above the semiconductor layers A1 and A2, respectively, and the gate insulating layer 113 is located between the gate electrodes G1 and G2 and the semiconductor layers A1 and A2. The gate electrodes G1 and G2 may include, for example, one or more of Mo, Al, Cu, and Ti, and may include a single layer or multiple layers. For example, each of the gate electrodes G1 and G2 may include a single layer including Mo.

[0105] The first electrode CE1 of the storage capacitor Cst may extend from the gate electrode G1 of the driving TFT T1. In another embodiment, the first electrode CE1 of the storage capacitor Cst may be understood to be formed as a single body with the gate electrode G1. The first electrode CE1 of the storage capacitor Cst may overlap with the bias electrode BSM, and a second capacitor C2 may be formed between the first electrode CE1 and the bias electrode BSM. In this case, the second buffer layer 112 and the gate insulating layer 113 disposed between the first electrode CE1 and the bias electrode BSM may serve as a dielectric of the second capacitor C2.

[0106] The first interlayer insulating layer 115 may be provided to cover the gate electrodes G1 and G2. The first interlayer insulating layer 115 may include, for example, SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 and ZnO 2 One or more of .

[0107] The second electrode CE2 of the storage capacitor Cst, the source electrodes S1 and S2 , the drain electrode D2 , the data line DL, and the reference voltage line RL may be disposed on the first interlayer insulating layer 115 .

[0108] The second electrode CE2 of the storage capacitor Cst, the source electrodes S1 and S2, the drain electrode D2, the data line DL, and the reference voltage line RL may include a conductive material including, for example, one or more of Mo, Al, Cu, and Ti, and may include a single layer or a multilayer. For example, the second electrode CE2 of the storage capacitor Cst, the source electrodes S1 and S2, the drain electrode D2, the data line DL, and the reference voltage line RL may have a multilayer structure of Ti / Al / Ti.

[0109] The second electrode CE2 of the storage capacitor Cst may overlap the first electrode CE1, and the first interlayer insulating layer 115 is located between the second electrode CE2 and the first electrode CE1 and may constitute the first capacitance C1. In this case, the first interlayer insulating layer 115 may serve as a dielectric layer of the storage capacitor Cst.

[0110] The source electrodes S1 and S2 and the drain electrode D2 may be connected to respective source and drain regions of the semiconductor layers A1 and A2 through contact holes, respectively.

[0111] The second interlayer insulating layer 117 may be disposed to cover the second electrode CE2 of the storage capacitor Cst, the source electrodes S1 and S2, the drain electrode D2, the data line DL, and the reference voltage line RL. The second interlayer insulating layer 117 may include, for example, SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 and ZnO 2 One or more of .

[0112] The first and second power lines PL1 and PL2 and the connection electrode CM may be disposed on the second interlayer insulating layer 117. The first and second power lines PL1 and PL2 and the connection electrode CM may include a conductive material including one of Mo, Al, Cu and Ti, and may include a single layer or multiple layers including the above materials.

[0113] The first power line PL1 may be connected to the source electrode S1 of the driving TFT T1 through the contact hole CNT3. The contact hole CNT3 may pass through the second interlayer insulating layer 117 and expose a portion of the source electrode S1. A portion of the first power line PL1 may fill the inside of the contact hole CNT3 and thus may be connected to the source electrode S1.

[0114] The first power line PL1 may overlap at least a portion of the driving TFT T1 and / or a portion of the storage capacitor Cst. The second power line PL2 may overlap at least a portion of each of the switching TFT T2, the data line DL, and the reference voltage line RL.

[0115] The connection electrode CM may be connected to the second electrode CE2 of the storage capacitor Cst through the contact hole CNT5. The contact hole CNT5 may pass through the second interlayer insulating layer 117 and expose a portion of the second electrode CE2. A portion of the connection electrode CM may be inserted into the contact hole CNT5 and connected to the second electrode CE2.

[0116] A planarization layer 118 may be disposed on the first power line PL1 , the second power line PL2 , and the connection electrode CM. An OLED may be located above the planarization layer 118 .

[0117] The planarization layer 118 may include a single layer or multiple layers including an organic material. The planarization layer 118 may include a polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), or a polymer derivative having, for example, a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a mixture thereof. The planarization layer 118 may include an inorganic material. The planarization layer 118 may include SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 and ZnO 2 In the case where the planarization layer 118 includes an inorganic material, chemical planarization polishing may be performed. The planarization layer 118 may include both an organic material and an inorganic material.

[0118] The OLED may be disposed on the planarization layer 118 in the display area DA of the substrate 100. The OLED may include a pixel electrode 310, an intermediate layer 320 including an organic emission layer, and an opposing electrode 330.

[0119] A first through hole VH1 and a second through hole VH2 respectively exposing a portion of the connection electrode CM and a portion of the second power line PL2 may be formed in the planarization layer 118. The pixel electrode 310 may be connected to the connection electrode CM via the first through hole VH1. The connection electrode CM may be connected to the second electrode CE2 of the storage capacitor Cst, and the second electrode CE2 may be connected to the drain electrode D1 of the driving TFT T1 (see Figure 3 ). Therefore, the pixel electrode 310 may be electrically connected to the drain electrode D1 of the driving TFT T1.

[0120] The counter electrode 330 may be connected to the second power line PL2 through the second through hole VH2. The intermediate layer 320 of the OLED may include multiple layers, and during a process of forming the intermediate layer 320, at least one layer of the intermediate layer 320 may be disposed in the second through hole VH2.

[0121] In an embodiment, before forming the counter electrode 330, any intermediate layer 320 that may remain inside the second through hole VH2 may be removed by irradiating a laser into the second through hole VH2. In addition, after forming the counter electrode 330, the contact characteristics between the counter electrode 330 and the second power line PL2 may be improved by irradiating a laser into the second through hole VH2. In an example embodiment, the area of ​​the second through hole VH2 may be greater than the area of ​​the first through hole VH1. Therefore, the width W of the second through hole VH2 is V2 can be greater than the width W of the first through hole VH1 V1 .

[0122] In the present example embodiment, the second power line PL2 is disposed on the second interlayer insulating layer 117 which is a layer higher than the first interlayer insulating layer 115 on which the data line DL is disposed. Therefore, the laser irradiation process for contacting the opposite electrode 330 may be easily performed.

[0123] The pixel electrode 310 may include a (semi) transmissive electrode or a reflective electrode. In an example embodiment, the pixel electrode 310 may include a reflective layer including, for example, one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and a mixture thereof, and a transparent or semi-transparent electrode layer on the reflective layer. The transparent or semi-transparent electrode layer may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), one or more of indium gallium oxide (IGO) and aluminum zinc oxide (AZO).

[0124] The pixel defining layer 119 may be disposed on the planarization layer 118. The pixel defining layer 119 may define the emission area of ​​the pixel by including an opening corresponding to each sub-pixel in the display area DA (e.g., a first opening OP1 exposing at least a central portion of the pixel electrode 310). The pixel defining layer 119 may prevent arcing, etc., from occurring at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310.

[0125] The pixel defining layer 119 may include a second opening OP2 corresponding to the second through hole VH2 of the planarization layer 118. Laser may then be irradiated into the region of the second through hole VH2 by exposing a portion of the second power line PL2 through the second opening OP2 and the second through hole VH2.

[0126] The pixel defining layer 119 may be formed by a method such as spin coating using, for example, one or more organic insulating materials such as polyimide, polyamide, acrylic resin, BCB, or phenolic resin.

[0127] The intermediate layer 320 of the OLED may include an organic emission layer. The organic emission layer may include an organic material including a fluorescent material or a phosphorescent material that emits, for example, red light, green light, blue light, or white light. The organic emission layer may include a low molecular weight organic material or a polymer organic material. Functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be selectively arranged on or below the organic emission layer. The intermediate layer 320 may correspond to each of the plurality of pixel electrodes 310. The intermediate layer 320 may include a layer that is integral above the plurality of pixel electrodes 310.

[0128] The counter electrode 330 may include a light-transmitting electrode or a reflective electrode. In an exemplary embodiment, the counter electrode 330 may include a transparent or semi-transparent electrode and may include, for example, a metal thin film having a small work function and containing, for example, one or more of Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and mixtures thereof. Such as ITO, IZO, ZnO, or In 2 O 3 A transparent conductive oxide (TCO) layer may be further disposed on the metal film. The counter electrode 330 may be disposed throughout the display area DA and the peripheral area PA and disposed above the intermediate layer 320 and the pixel defining layer 119. The counter electrode 330 may be disposed as a whole throughout a plurality of OLEDs and may correspond to a plurality of pixel electrodes 310.

[0129] The counter electrode 330 may be connected to the second power line PL2 through the second opening OP2 and the second through hole VH2 .

[0130] The OLED may be susceptible to damage from external moisture or oxygen. Therefore, a thin film encapsulation layer may be arranged thereon and may cover and protect the OLED. The thin film encapsulation layer may cover the display area DA and extend to the outside of the display area DA. The thin film encapsulation layer may include, for example, an inorganic encapsulation layer including at least one inorganic material and an organic encapsulation layer including at least one organic material. In an example embodiment, the thin film encapsulation layer may have a structure including a first inorganic encapsulation layer / an organic encapsulation layer / a second inorganic encapsulation layer stacked therein.

[0131] For example, a spacer for preventing mask chopping may be disposed on the pixel defining layer 119. Various functional layers such as a polarizing layer configured to reduce external light reflection, a black matrix, a color filter, and / or a touch screen including a touch electrode may be disposed on the thin film encapsulation layer.

[0132] Figure 5 is along Figure 3 A cross-sectional view of the portion taken along line II-II'. Figure 5The connection structure of the sensing TFT T3 and the bias electrode BSM is mainly shown, and some elements may be omitted.

[0133] Reference Figure 5 , the sensing TFT T3 includes a semiconductor layer A3, a gate electrode G3, a source electrode S3, and a drain electrode D3. The gate electrode G3 overlaps the semiconductor layer A3, and the gate insulating layer 113 is located between the gate electrode G3 and the semiconductor layer A3. The source electrode S3 and the drain electrode D3 may be arranged on the first interlayer insulating layer 115 and connected to the semiconductor layer A3 through a contact hole.

[0134] The source electrode S3 and the drain electrode D3 may be covered by the second interlayer insulating layer 117, and the second power line PL2 may be disposed on the second interlayer insulating layer 117. The second power line PL2 may overlap the sensing TFT T3 and completely cover the sensing TFT T3.

[0135] One end of the bias electrode BSM may be connected to the source electrode S3 of the sensing TFT T3 through a second node contact hole CNT2 that passes through the first interlayer insulating layer 115 , the gate insulating layer 113 , and the second buffer layer 112 .

[0136] Figure 6 is a plan view of a display device according to another exemplary embodiment. Specifically, Figure 6 is a structure in which the pixel electrode 310 and the emission area EA defined by the first opening OP1 are arranged in accordance with example embodiments. Figure 3 A plan view of the arrangement of the pixel circuit PC.

[0137] Reference Figure 6 , the pixel electrode 310 may overlap the driving TFT T1 and the storage capacitor Cst of the pixel circuit PC. In addition, the pixel electrode 310 may overlap the first power line PL1 and the second power line PL2. The pixel electrode 310 is connected to the connection electrode CM through the first through hole VH1, and is connected to the storage capacitor Cst and the driving TFT T1 through the connection electrode CM. When the pixel circuit PC is driven, voltages may be applied to the pixel electrode 310 and the counter electrode 330 (see FIG. 1 ). Figure 4 ), and OLED (see Figure 4 The emission area EA may be defined by the first opening OP1 of the pixel defining layer 119.

[0138] The pixel electrode 310 may overlap the pixel circuit PC. Therefore, the emission area EA may overlap the driving TFT T1 and the storage capacitor Cst of the pixel circuit PC, and the first and second power lines PL1 and PL2.

[0139] As an example, the figure shows that the pixel electrode 310 and the emission area EA have a rectangular shape or a rounded rectangular shape. In other examples, the pixel electrode 310 and the emission area EA can have an irregular shape in which a depression is formed in one edge thereof. In addition, the pixel electrode 310 can have various shapes such as a rhombus shape, a hexagonal shape, an octagonal shape or a circular shape.

[0140] The structure in which the pixel electrode 310 and / or the emission area EA overlaps the driving TFT T1 and the storage capacitor Cst of the pixel circuit PC can be applied to emit light from the intermediate layer 320 (see FIG. 1 ) in the direction of the counter electrode 330. Figure 4 ) produces light in a top-emitting display device.

[0141] In this case, the pixel electrode 310 may be configured as a reflective electrode including a reflective layer. For example, the reflective layer may include one or more of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, and Cr. The reflective layer may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 A transparent or semi-transparent electrode layer of one or more of ITO, indium gallium oxide (IGO), and aluminum zinc oxide (AZO) may be further disposed on the reflective layer. According to example embodiments, the pixel electrode 310 may include three layers of ITO / Ag / ITO.

[0142] In this example embodiment, the electrode 330 (see Figure 4 ) may include a (semi) transparent electrode. For example, the counter electrode 330 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), one or more of indium gallium oxide (IGO) and aluminum zinc oxide (AZO), and may include a thin film having a thickness ranging from several nanometers to tens of nanometers to transmit light.

[0143] Figure 7 and Figure 8 is a diagram of a display device according to another example embodiment. Specifically, Figure 7 FIG. 1 is a diagram showing that the pixel electrode 310′ and the emission area EA′ defined by the first opening OP1 are arranged in a Figure 3 A plan view of the pixel circuit PC, Figure 8 is along Figure 7 A cross-sectional view taken along line III-III'. Figure 7 and Figure 8 In, with Figure 4 and Figure 6 The same reference numerals as those in the accompanying drawings represent the same elements.

[0144] Reference Figure 7 and Figure 8 According to the present exemplary embodiment, the emission area EA' of the OLED may not overlap with the driving TFT T1 and the storage capacitor Cst of the pixel circuit PC. In order to connect the pixel electrode 310' of the OLED to the connection electrode CM, a portion of the pixel electrode 310' may overlap with the pixel circuit PC. The emission area EA' defined by the first opening OP1 of the pixel defining layer 119 may not overlap with the driving TFT T1 and the storage capacitor Cst.

[0145] The above structure may be applied to a bottom emission type display device that emits light generated from an OLED toward substrate 100. By not arranging a structure that blocks or changes a light path in emission area EA', light emission toward the bottom surface of substrate 100 may be enhanced.

[0146] In this case, the pixel electrode 310' may include a (semi) transparent electrode. For example, the pixel electrode 310' may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), one or more of indium gallium oxide (IGO) and aluminum zinc oxide (AZO), and may include a thin film having a thickness ranging from several nanometers to tens of nanometers so as to transmit light.

[0147] As an example, the emission area EA' is shown in the figure as having a rectangular shape or a rounded rectangular shape. In another example, the emission area EA' may have an irregular shape in which a recess is formed in one edge thereof. In addition, the emission area EA' may have various shapes such as a diamond shape, a hexagonal shape, an octagonal shape, or a circular shape.

[0148] In this example embodiment, the counter electrode 330' may be provided as a reflective electrode including a reflective layer. For example, the reflective layer may include one or more of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, and Cr. The reflective layer may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 A transparent or semi-transparent electrode layer of one or more of ITO, indium gallium oxide (IGO) and aluminum zinc oxide (AZO) may be further arranged on the reflective layer. According to example embodiments, the counter electrode 330' may include three layers of ITO / Ag / ITO. According to example embodiments, an additional reflective layer may also be provided on the counter electrode 330'.

[0149] In the present example embodiment, each of the planarization layer 118 , the second interlayer insulating layer 117 , the first interlayer insulating layer 115 , the gate insulating layer 113 , the second buffer layer 112 , the first buffer layer 111 , and the substrate 100 disposed under the OLED may include a transparent material.

[0150] In example embodiments, a portion (corresponding to the portion of the OLED) of at least one of the planarization layer 118 , the second interlayer insulating layer 117 , the first interlayer insulating layer 115 , the gate insulating layer 113 , the second buffer layer 112 , and the first buffer layer 111 may be removed.

[0151] Fig. 9 is a cross-sectional view of a display device according to another example embodiment.

[0152] Reference Fig. 9 The display device according to the example embodiment includes an OLED (display element) arranged over a substrate 100, a driving TFT T1, a first interlayer insulating layer 115 covering a gate electrode G1 of the driving TFT T1, a data line DL on the first interlayer insulating layer 115, a second interlayer insulating layer 117 covering the data line DL, and first and second power lines PL1 and PL2 arranged on the second interlayer insulating layer 117. The first power line PL1 is connected to a source electrode S1 of the driving TFT T1, and the second power line PL2 is connected to a counter electrode 330 of the OLED.

[0153] The display device according to example embodiments may further include a storage capacitor Cst connected to the driving TFT T1 and a bias electrode BSM disposed under the driving TFT T1 .

[0154] The bias electrode BSM may overlap the storage capacitor Cst. The first electrode CE1 and the second electrode CE2 of the storage capacitor Cst may constitute a first capacitance C1, and the first electrode CE1 and the bias electrode BSM may constitute a second capacitance C2.

[0155] In the display device according to the present embodiment, a lower metal layer M2 corresponding to the semiconductor layer A2 may be further arranged below the switching TFT T2. The lower metal layer M2 may be arranged between the substrate 100 and the semiconductor layer A2, and may block light that may be incident to the semiconductor layer A2. The lower metal layer M2 may be arranged in the same layer as that of the bias electrode BSM, and may include the same material as that of the bias electrode BSM. For example, the lower metal layer M2 may include one or more of Mo, Al, Cu, and Ti, and may include a single layer or multiple layers.

[0156] The characteristics of the semiconductor layer A2 may be changed by light, and the change in the characteristics of the semiconductor layer A2 may change the characteristics of the switching TFT T2. In this example embodiment, the lower metal layer M2 may stabilize the characteristics of the switching TFT T2 to prevent the characteristics of the switching TFT T2 from being changed by external light.

[0157] In example embodiments, a voltage may be applied to the lower metal layer M2 , which may help stabilize characteristics of the switching TFT T2 .

[0158] In this example embodiment, a voltage may be applied to one or more of the bias electrode BSM and the lower metal layer M2. For example, a voltage may be applied to the bias electrode BSM, and a voltage may not be applied to the lower metal layer M2. In another embodiment, a first voltage may be applied to the bias electrode BSM, and a second voltage may be applied to the lower metal layer M2.

[0159] A sensing lower metal layer corresponding to the sensing TFT T3 may also be disposed under the sensing TFT T3 The sensing lower metal layer may be disposed in the same layer as that of the bias electrode BSM and may include the same material as that of the bias electrode BSM.

[0160] Fig. 10A shows an equivalent circuit diagram of two adjacent pixels in a display device according to another example embodiment, Fig. 10B is based on Fig. 10A Diagram of the driving timing of the pixel.

[0161] Reference Fig. 10A and Fig. 10B , Fig. 10A The nth pixel PX of the pixels arranged along the second direction is shown. n and the (n+1)th pixel PX n+1 The nth pixel PX n Connected to the first data line DL1, the (n+1)th pixel PX n+1 Connected to the second data line DL2. This means that the two data lines DL1 and DL2 may correspond to one pixel row arranged along the second direction.

[0162] The first data line DL1 may be connected to odd-numbered pixels among the pixels arranged along the second direction, and the second data line DL2 may be connected to even-numbered pixels among the pixels arranged along the second direction.

[0163] With this structure, data (DATA[n] and DATA[n+1]) can be written to each pixel by simultaneously driving the scan signals Sn and Sn+1 applied to the nth scan line SLn and the (n+1)th scan line SLn+1, respectively. nThe driving and (n+1)th pixel PX n+1 In a high-resolution display, the number of pixels included in the display area DA can be increased. By simultaneously performing the nth pixel PX n The driving and (n+1)th pixel PX n+1 The desired driving timing can be ensured even at high resolutions.

[0164] Fig.11 is a plan view of an arrangement of adjacent pixel circuits included in a display device according to another example embodiment.

[0165] Reference Fig.11 , the display device may include a first pixel circuit PC1, a second pixel circuit PC2, a third pixel circuit PC3, and a fourth pixel circuit PC4 arranged along a first direction. Each of the first pixel circuit PC1, the second pixel circuit PC2, the third pixel circuit PC3, and the fourth pixel circuit PC4 may include a driving TFT T1, a switching TFT T2, a sensing TFT T3, and a storage capacitor Cst.

[0166] In this example embodiment, the display device may include a scan line SL, a sensing control line SSL, a first mesh line ML1, a second mesh line ML2, and a reference voltage connection line RCL, all extending in a first direction. The display device may include a first data line DL1, a second data line DL2, a reference voltage line RL, a first power line PL1, and a second power line PL2, all extending in a second direction crossing the first direction.

[0167] The scan lines SL, the sensing control lines SSL, the first mesh lines ML1, and the second mesh lines ML2 may be commonly connected to the pixel circuits arranged along the first direction.

[0168] The reference voltage line RL extending in the second direction may be provided one by one to the three pixel circuits PC1, PC2, and PC3 each extending in the first direction. The reference voltage line RL may be connected to the reference voltage connection line RCL extending in the first direction through the contact hole CNT8, and may transmit the reference voltage to the three pixel circuits PC1, PC2, and PC3 adjacent to each other in common.

[0169] The reference voltage line RL may be provided one by one to every two pixel circuits each extending in the first direction, or may be provided one by one to one pixel circuit. Therefore, the reference voltage connection line RCL may be commonly connected to two pixel circuits, or may be connected to only one pixel circuit.

[0170] In the present example embodiment, the data lines DL1 and DL2 may include first data lines DL1 and second data lines DL2 alternately connected to pixels arranged along the second direction. Therefore, the first data line DL1 may be connected to the first pixel circuit PC1 through the contact hole CNT11. The second data line DL2 may not be connected to the first pixel circuit PC1, but may be connected to the 1a-th pixel circuit PC1a adjacent to the first pixel circuit PC1 along the second direction through the contact hole CNT12.

[0171] In example embodiments, the first and second data lines DL1 and DL2 may be arranged in the same layer as the second electrode CE2 of the storage capacitor Cst. In example embodiments, the first and second data lines DL1 and DL2 may be spaced apart from each other with the storage capacitor Cst therebetween.

[0172] As reference Fig. 10A and Fig. 10B As described above, driving time may be reduced by using the first data line DL1 and the second data line DL2, and thus a high-resolution display device may be implemented.

[0173] The first power line PL1 may overlap at least a portion of three pixel circuits PC1, PC2, and PC3 adjacent to each other along the first direction. For example, the first power line PL1 may overlap a portion of the first pixel circuit PC1 and a portion of the third pixel circuit PC3, and may overlap the entire area of ​​the second pixel circuit PC2. Various modifications may be made to the area of ​​the first power line PL1 overlapping the pixel circuits and the width of the first power line PL1.

[0174] The second power line PL2 may overlap at least a portion of two pixel circuits PC3 and PC4 that are adjacent to each other along the first direction. For example, the second power line PL2 may overlap a portion of the third pixel circuit PC3 and a portion of the fourth pixel circuit PC4. Various modifications may be made to the area of ​​the second power line PL2 overlapping the pixel circuits and the width of the second power line PL2.

[0175] The second through hole VH2 (through which the second power line PL2 is connected to the counter electrode 330 (see Figure 4 ) contact area) may be provided one by one to every three pixel circuits PC1, PC2 and PC3 arranged along the first direction. The second through hole VH2 may be arranged one by one to every two pixel circuits arranged along the first direction. The second through hole VH2 may overlap the reference voltage line RL.

[0176] In the present example embodiment, pixels PX adjacent to each other along the first direction may have a structure at least partially symmetrical with respect to a dotted line VL or a reference voltage line RL. For example, a first pixel circuit PC1 may include a second pixel circuit PC2, wherein the arrangement of a driving TFT T1, a sensing TFT T3, and a storage capacitor Cst has a symmetrical structure with respect to a dotted line VL based on the first pixel circuit PC1. The dotted line VL represents a line extending along the second direction between the first pixel circuit PC1 and the second pixel circuit PC2.

[0177] The third pixel circuit PC3 may include a fourth pixel circuit PC4 in which the arrangement of the driving TFT T1 , the sensing TFT T3 , and the storage capacitor Cst has a symmetrical structure with respect to the reference voltage line RL based on the third pixel circuit PC3 .

[0178] As an example, the arrangement structure of the switch TFT T2 is described as being the same as the first pixel circuit PC1 and the second pixel circuit PC2. In another example, the arrangement structure of the switch TFT T2 of the first pixel circuit PC1 and the arrangement structure of the switch TFT T2 of the second pixel circuit PC2 may be symmetrical with respect to the dotted line VL. In an example embodiment, the shapes of the pixel circuits PC1, PC2, PC3, and PC4 included in the display device may be different from each other.

[0179] Figure 12 to Figure 14 is a plan view of an arrangement relationship of a first power line PL1, a second power line PL2, a first data line DL1, a second data line DL2, and a reference voltage line RL according to an example embodiment.

[0180] Reference Fig.12 The first power line PL1 may be arranged on the first interlayer insulating layer 115 (see Figure 4 ) and may overlap with a plurality of wirings extending along the second direction. Fig.12 In the embodiment, one first power line PL1 may overlap four wirings extending along the second direction. Therefore, the first power line PL1 may overlap the first data line DL1 arranged in the first pixel circuit PC1 and the first data line DL1 and the second data line DL2 arranged in the second pixel circuit PC2, and overlap the second data line DL2 arranged in the third pixel circuit PC3.

[0181] The second power line PL2 may be disposed on the first interlayer insulating layer 115 (see Figure 4 ) and may overlap with a plurality of wirings extending along the second direction. Fig.12Thus, the second power line PL2 may overlap the first data line DL1 and the reference voltage line RL arranged in the third pixel circuit PC3, and overlap the second data line DL2 arranged in the fourth pixel circuit PC4.

[0182] The first power line PL1 and the second power line PL2 may cover most areas of the pixel circuit of the display device, which may help the first power line PL1 and the second power line PL2 to shield external electrical signals.

[0183] Reference Fig.13 and Fig.14 , at least one of the first power line PL1 and the second power line PL2 may be disposed over the first interlayer insulating layer 115 and may not overlap with the wiring extending in the second direction.

[0184] For example, Fig.13 As shown in , although the first power line PL1 is arranged above the second pixel circuit PC2, the first power line PL1 may not overlap the first data line DL1 and the second data line DL2. Fig.14 As shown in FIG, the first power line PL1 and the second power line PL2 may not overlap with the first data line DL1, the second data line DL2 and the reference voltage line RL arranged in the pixel circuit. This can help reduce parasitic capacitance that may occur between the first power line PL1 and the second power line PL2 and the data lines DL1 and DL2.

[0185] Fig.15 is a plan view of a shape of a pixel electrode according to example embodiments.

[0186] In this example embodiment, the shape of the pixel electrode 310 included in the pixel circuits PC1, PC2, PC3, and PC4 may be variously set. For example, each of the pixel electrodes 310a, 310c, and 310d adjacent to the second through hole VH2 may have a groove 310h recessed inwardly from one side thereof to correspond to the shape of the second through hole VH2. The pixel electrodes 310a, 310c, and 310d may also be formed in the shape of the emission area EA due to the groove 310h. The second through hole VH2 may overlap with the reference voltage line RL, and the pixel electrode 310c of the third pixel circuit PC3 and the pixel electrode 310d of the fourth pixel circuit PC4 may be symmetrical with respect to the reference voltage line RL.

[0187] The pixel electrode 310b not adjacent to the second through hole VH2 may have a substantially rectangular shape, and the emission area EA of the second pixel circuit PC2 may have a rounded rectangular shape. The shape and size of the pixel electrode 310 or the emission area EA may be variously set.

[0188] By way of summary and review, a display device may include a substrate divided into a display area and a peripheral area. The display area may include scan lines and data lines insulated from each other and a plurality of pixels. The display area may include a thin film transistor corresponding to each pixel and a pixel electrode electrically connected to the thin film transistor. The display area may include a pair of electrodes commonly provided for the pixels. The peripheral area may include various wirings, a scan driver, a data driver, a controller, etc. configured to transmit electrical signals to the display area.

[0189] As described above, the embodiment can provide a display device realizing high-quality images.

[0190] As described above, according to the example embodiment, the first power line and the second power line are arranged in a layer different from the layer of the data line. Therefore, the design of the first power line and the second power line can be easily modified while considering IR drop and parasitic capacitance. In addition, the second power line can be arranged in a layer higher than the layer of the data line. Therefore, the connection with the counter electrode can be simplified.

[0191] As described above, the embodiments relate to a display device for achieving high resolution and high quality.

[0192] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and will be construed only in a general and descriptive sense, and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art from the time of filing this application that, unless otherwise specifically noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display device, comprising: A first data line is located on a first interlayer insulating layer above the substrate; A first power line and a second power line are located on a second interlayer insulating layer, and the second interlayer insulating layer covers the first data line; as well as a plurality of pixels, wherein a first pixel among the plurality of pixels comprises: a display element, comprising a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode, wherein the second power line is connected to the counter electrode; and a driving thin film transistor, located between the substrate and the display element, and comprising a driving semiconductor layer, a driving gate electrode, a driving source electrode, and a driving drain electrode, wherein the first interlayer insulating layer covers the driving gate electrode, and the first power line is connected to the driving source electrode, wherein at least one of the first power line and the second power line overlaps with the first data line, and The widths of the first power line and the second power line in the first direction are greater than the width of the first data line in the first direction.

2. The display device according to claim 1, further comprising: A storage capacitor comprising a first electrode and a second electrode, wherein: The first electrode extends from the driving gate electrode, and The second electrode is located on the first interlayer insulating layer and overlaps the first electrode.

3. The display device according to claim 2, further comprising: The bias electrode is located between the substrate and the driving semiconductor layer and overlaps the driving semiconductor layer.

4. The display device according to claim 3, further comprising: a sensing thin film transistor, located above the substrate and comprising a sensing semiconductor layer, a sensing gate electrode, a sensing source electrode and a sensing drain electrode, Wherein, the bias electrode is electrically connected to the sensing source electrode.

5. The display device according to claim 3, wherein: The bias electrode overlaps the storage capacitor, The first electrode and the second electrode constitute a first capacitor, and The bias electrode and the first electrode form a second capacitor.

6. The display device according to claim 1, further comprising: A planarization layer, covering the first power line and the second power line, wherein: The pixel electrode is located on the planarization layer and is electrically connected to the driving thin film transistor through a first through hole defined in the planarization layer, and The second power line is connected to the counter electrode through a second through hole defined in the planarization layer.

7. The display device according to claim 6, wherein: An area of ​​the second through hole is greater than an area of ​​the first through hole.

8. The display device according to claim 6, wherein: The pixel electrode includes a groove corresponding to a shape of the second through hole.

9. The display device according to claim 1, further comprising: a second pixel, adjacent to the first pixel; as well as a second data line, which extends over the first pixel and the second pixel and is located in the same layer as the first data line, wherein: The first data line is electrically connected to the first pixel, and The second data line is electrically connected to the second pixel.

10. The display device according to claim 1, wherein: The pixel electrode overlaps the driving thin film transistor and includes a reflective layer.

11. The display device according to claim 1, wherein: The pixel electrode does not overlap with the driving thin film transistor, and The counter electrode includes a reflective layer.

12. The display device according to claim 1, wherein: The driving semiconductor layer includes an oxide semiconductor.

13. The display device according to claim 1, further comprising: A switch thin film transistor, located above the substrate; as well as The lower metal layer is located between the substrate and the switch thin film transistor.

14. A display device, comprising: A plurality of pixel circuits are located above the substrate; and a plurality of display elements, respectively connected to the plurality of pixel circuits to realize an image, the display device comprising: a scan line extending along a first direction and connected to the plurality of pixel circuits arranged along the first direction; A first data line, a second data line, and a reference voltage line, all extending in a second direction intersecting the first direction, are arranged above the scan line, and a first interlayer insulating layer is located between the scan line and the first data line, the second data line, and the reference voltage line; and a first power line and a second power line, both extending along the second direction, arranged above the first data line, the second data line and the reference voltage line, and a second interlayer insulating layer being located between the first data line, the second data line and the reference voltage line and the first power line and the second power line, the first power line being electrically connected to the pixel electrodes of the plurality of display elements, and the second power line being connected to the counter electrodes of the plurality of display elements, wherein at least one of the first power line and the second power line overlaps with the first data line, and Wherein, the widths of the first power line and the second power line in the first direction are greater than the width of the first data line in the first direction.

15. The display device according to claim 14, wherein: The first data lines and the second data lines are alternately connected to the plurality of pixel circuits arranged along the second direction.

16. The display device according to claim 14, wherein: The plurality of pixel circuits include a first pixel circuit, a second pixel circuit, and a third pixel circuit adjacent to each other along the first direction, and The first power supply line overlaps a portion of the first pixel circuit, the second pixel circuit, and a portion of the third pixel circuit.

17. The display device according to claim 14, wherein: The second power supply line is connected to the counter electrode through a through hole defined in the planarization layer, and The through hole overlaps the reference voltage line.

18. The display device according to claim 14, wherein: The reference voltage line is connected to a reference voltage connection line extending along the first direction through a contact hole, and The reference voltage connection line is commonly connected to three pixel circuits adjacent to each other.

19. The display device according to claim 14, wherein: Each of the plurality of pixel circuits includes three thin film transistors and one storage capacitor.

Images