Method of operating a resistive memory device

Abstract

A method for operating a resistive memory device is disclosed. A method for operating a resistive memory device for increasing a read margin includes: applying a write pulse to a memory cell so that the memory cell is programmed to a target resistance state; and applying a post-write pulse to the memory cell to increase the resistance of the memory cell in the target resistance state, wherein the post-write pulse is applied as a single pulse having at least n step voltage levels, n is an integer equal to or greater than 2, and the nth step voltage level of the post-write pulse is set to be lower than the minimum threshold voltage level of the target resistance state changed by the (n-1)th step voltage level of the post-write pulse.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2018-0121190 filed on October 11, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Example embodiments of the present inventive concept relate to a nonvolatile memory device, and more particularly, to a method of operating a resistive memory device, wherein a post-write pulse is applied in a reset-directional write operation to increase a read margin of the resistive memory device. Background Art

[0003] Resistive memory devices, such as phase change random access memory (PRAM), resistive RAM (RRAM), and magnetic RAM (MRAM), are referred to as nonvolatile memory devices. Resistive memory devices use variable resistance elements configured to store data based on changes in resistance states as memory cells. A cross-point-type resistive memory device can be configured by arranging the memory cells at the intersections between a plurality of bit lines and a plurality of word lines. The resistive memory device can apply a voltage to both ends of the memory cell and access the memory cell, and the accessed memory cell can store a logic "1" (or set data or a low resistance state) or a logic "0" (or reset data or a high resistance state) based on the threshold resistance of the memory cell.

[0004] After the memory cell is programmed, the resistance characteristics of the memory cell may degrade over time, so that the threshold voltage distribution caused by the low resistance state (set data) and the high resistance state (reset data) of the memory cell may be increased and modified at different resistance increase rates. Due to the relatively large increase in the resistivity of the set data, the sensing margin or reading margin between the set data and the reset data may be reduced, which may lead to a read error. That is, when the non-overlapping interval (e.g., the read window (or sensing window)) between the threshold voltage distribution caused by the low resistance state and the threshold voltage distribution caused by the high resistance state is narrow, a read error may occur in the read operation of the memory cell. Therefore, in order to reduce read errors in a resistive memory device and ensure the read margin of the resistive memory device, it would be beneficial to develop a method for operating a resistive memory device that can increase the read window. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a method of operating a resistive memory device, wherein a post-write pulse is applied in a reset direction write operation to increase resistance of a memory cell, thereby extending a read margin of the resistive memory device and reducing read errors.

[0006] According to some example embodiments of the inventive concept, a method of operating a resistive memory device including a memory cell is provided. The method includes: applying a write pulse to the memory cell so that the memory cell is in a target resistance state; and applying a post-write pulse to the memory cell to increase the resistance of the memory cell in the target resistance state. The post-write pulse is a single pulse having at least n step voltage levels (n is an integer equal to or greater than 2).

[0007] According to some example embodiments of the inventive concept, a method of operating a resistive memory device including a memory cell is provided. The method includes: applying a write pulse to the memory cell so that the memory cell is in a target resistance state; and applying at least n post-write pulses to the memory cell to increase the resistance of the memory cell in the target resistance state (n is an integer equal to or greater than 2).

[0008] According to some example embodiments of the inventive concept, a resistive memory device is provided, comprising: a memory cell array including memory cells; a write circuit configured to program the memory cells to a target resistance state; and a control circuit configured to control a write pulse and a post-write pulse to be applied to the memory cells, wherein the post-write pulse follows the write pulse. In response to the write pulse, the memory cells are programmed to the target resistance state, and in response to the post-write pulse, the resistance of the memory cells in the target resistance state increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a memory system according to some example embodiments;

[0011] Figure 2 According to some example embodiments, Figure 1 A block diagram of a memory device in a memory system;

[0012] Figure 3 According to some example embodiments Figure 2 A circuit diagram of a memory cell array;

[0013] Figure 4 According to some example embodiments Figure 3A diagram showing a cross-sectional structure of a memory cell;

[0014] Figure 5 is a diagram showing an example embodiment of the invention according to which Figure 4 A graph showing a write current of a memory cell;

[0015] Figure 6 is a diagram showing some example embodiments Figure 4 A graph of voltage-current (VI) characteristics of a selection element of a memory cell;

[0016] FIG. 7A to FIG. 7C is a diagram showing the Figure 4 A graph showing characteristics of a memory cell when the memory cell is a single-level cell (SLC);

[0017] Figure 8 is a diagram showing the Figure 4 A graph of distribution of memory cells relative to resistance when the memory cell is a multi-level cell (MLC);

[0018] Fig. 9 is a diagram of a method of operating a memory device according to some example embodiments;

[0019] FIG. 10A to FIG. 10D is a diagram showing some example embodiments Fig. 9 A graph of the post-write pulse;

[0020] FIG. 11A to FIG. 11D is a diagram showing some other example embodiments Fig. 9 A graph showing a modified example of a post-write pulse of;

[0021] Fig.12 is a flowchart of a method of writing to a memory device according to some example embodiments;

[0022] Fig.13 is a diagram for explaining a method of operating a memory device according to some example embodiments;

[0023] FIG. 14A to FIG. 14D is a diagram showing some example embodiments Fig.13 A graph of the post-write pulse;

[0024] FIG. 15A to FIG. 15D is a diagram showing some other example embodiments Fig.13 A graph showing a modified example of a post-write pulse of;

[0025] Fig.16 is a flowchart of a method of writing to a memory device according to some example embodiments;

[0026] Fig.17 is a circuit diagram of a write / read circuit of a memory device according to some example embodiments;

[0027] Fig.18 is a block diagram of a configuration of a memory system employing a memory device according to some example embodiments;

[0028] Fig.19 is a block diagram of a system to which a memory device according to some example embodiments is applied. DETAILED DESCRIPTION

[0029] Figure 1 is a block diagram of a memory system 1 according to some example embodiments.

[0030] Reference Figure 1 , the memory system 1 may include a memory controller 5 and a memory device 10. The memory device 10 may include a memory cell array 11, a write / read circuit 12, and a control circuit 13.

[0031] In response to a read request / write request from the host HOST, the memory controller 5 may control the memory device 10 to read data stored in the memory device 10 and / or write data to the memory device 10. The memory controller 5 may provide an address ADDR, a command CMD, and a control signal CTRL to the memory device 10, and control a program (or write) operation and a read operation on the memory device 10. In addition, write data DATA for a program operation and read data DATA for a read operation may be transmitted and received between the memory controller 5 and the memory device 10.

[0032] Although not in Figure 1, but the memory controller 5 may include a random access memory (RAM), a processing unit, a host interface, a memory interface, a read-only memory (ROM) and / or a non-volatile memory. The RAM may be used as an operating memory of the processing unit, and the processing unit may control the operation of the memory controller 5. For example, the processing unit of the memory controller 5 may be implemented as a microprocessor (MP) or a central processing unit (CPU), and the MP or CPU is configured to execute an operating system and / or a software program and perform specific calculations and / or tasks. The host interface may include a protocol configured to perform data exchange between the host HOST and the memory controller 5. For example, the memory controller 5 may be configured to communicate with the host HOST through at least one of various interface protocols (such as, universal serial bus (USB), host communication (MMC), peripheral component interconnect fast (PCI-E), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA), small computer system interface (SCSI), enhanced small device interface (ESDI) and integrated drive electronics (IDE)).

[0033] The memory cell array 11 may include a plurality of memory cells respectively arranged at regions where the plurality of first signal lines and the plurality of second signal lines intersect. In some example embodiments, the plurality of first signal lines may be a plurality of bit lines, and the plurality of second signal lines may be a plurality of word lines. In some other example embodiments, the plurality of first signal lines may be a plurality of word lines, and the plurality of second signal lines may be a plurality of bit lines.

[0034] In some example embodiments, the plurality of memory cells may include a resistive memory cell or a resistive memory cell, wherein the resistive memory cell or the resistive memory cell includes a variable resistance element having a variable resistance. For example, when the variable resistance element includes a phase change material whose resistance changes with temperature (e.g., germanium (Ge)-antimony (Sb)-tellurium (Te), GST), the memory device 10 may be a phase change RAM (PRAM). In some other example embodiments, when each variable resistance element includes an upper electrode, a lower electrode, and a transition metal oxide located between the upper electrode and the lower electrode, the memory device 10 may be a resistive RAM (RRAM). In some other example embodiments, when each variable resistance element includes an upper magnetic electrode, a lower magnetic electrode, and a dielectric material located between the upper magnetic electrode and the lower magnetic electrode, the memory device 10 may be a magnetic RAM (MRAM).

[0035] The write / read circuit 12 can program the memory cell and read the programmed memory cell. The write / read circuit 12 can program the memory cell to 2 mAccording to some example embodiments, the write / read circuit 12 may program the memory cell to any of two resistance states (m is an integer greater than 0) and read the programmed memory cell. m The write / read circuit 12 may program the memory cell to the target resistance state using a write pulse and a post-write pulse, and may read the programmed memory cell using a read voltage.

[0036] In a programming operation, the control circuit 13 may control a write pulse to be applied to the memory cell, and control a post-write pulse following the write pulse to be applied to the memory cell. The memory cell may be switched to a target resistance state in response to the write pulse, and the resistance of the memory cell in the target resistance state may increase in response to the post-write pulse. According to some example embodiments, the control circuit 13 may control the post-write pulse to be provided as a single pulse having at least n step voltage levels (n is an integer equal to or greater than 2), and control each of the at least n step voltage levels to increase by a predetermined amplitude (desired amplitude, specific amplitude). According to some other example embodiments, the control circuit 13 may control the post-write pulse to be provided as at least n multi-pulses, and control the voltage level of each of the at least n multi-pulses to increase by a predetermined amplitude (desired amplitude, specific amplitude).

[0037] The write / read circuit 12 and / or the control circuit 13 of the memory device 10 may be implemented using hardware or a combination of hardware and software. The hardware of the write / read circuit 12 and / or the control circuit 13 may be implemented using a processing circuit (such as, but not limited to, one or more processors, one or more central processing units (CPUs), one or more controllers, one or more arithmetic logic units (ALUs), one or more digital signal processors (DSPs), one or more microcomputers, one or more field programmable gate arrays (FPGAs), one or more systems on chips (SoCs), one or more programmable logic units (PLUs), one or more microprocessors, one or more application-specific integrated circuits (ASICs), or any other device capable of responding to and executing instructions in a defined manner). Software may include computer programs, program codes, instructions, or some combination thereof, for independently or collectively instructing or configuring hardware devices to operate as required. Computer programs and / or program codes may include programs or computer-readable instructions, software components, software modules, data files, data structures, etc. that can be implemented by one or more hardware devices (such as, one or more of the hardware devices mentioned above in conjunction with the write / read circuit 12 and / or the control circuit 13 of the memory device 10).

[0038] The memory controller 5 and the memory device 10 may be integrated into one semiconductor device. As a non-limiting example, the memory controller 5 and the memory device 10 may be integrated into one semiconductor device and constitute a memory card. For example, the memory controller 5 and the memory device 10 may be integrated into one semiconductor device and constitute a PC card (e.g., a Personal Computer Memory Card International Association (PCMCIA) card), a Compact Flash (CF) card, a Smart Media Card (SM / SMC), a Memory Stick, a Multimedia Card (MMC) (or a Miniaturized MMC (RS-MMC) or a Micro MMC), a Secure Digital (SD) card (or a Mini SD or Micro SD card), or a Universal Flash Storage (UFS) device. In another non-limiting example, the memory controller 5 and the memory device 10 may be integrated into one semiconductor device and constitute a solid state disk / drive (SSD).

[0039] Figure 2 According to some example embodiments, Figure 1 1 is a block diagram of a memory device 10 in a memory system 1 of the present invention. Figure 3 According to some example embodiments Figure 2 Circuit diagram of a memory cell array.

[0040] Reference Figure 2 The memory device 10 may include a memory cell array 11, a write / read circuit 12, a control circuit 13, a voltage generator 14, a row decoder 15 and a column decoder 16, and the write / read circuit 12 may include a write circuit 121 and a read circuit 122. Figure 2 These components of the storage device 10 and / or the write / read circuit 12 may be implemented as hardware or a combination of hardware and software, including but not limited to the above Figure 1 Various examples of the write / read circuit 12 and the control circuit 13 are discussed.

[0041] like Figure 3 As shown in , the memory cell array 11 may include word lines WL1 and WL2, which may extend in a first direction (X direction) and may be spaced apart from each other in a second direction (Y direction) perpendicular to the first direction (X direction). The memory cell array 11 may include bit lines BL1, BL2, BL3, and BL4, wherein the bit lines BL1, BL2, BL3, and BL4 may be spaced apart from the word lines WL1 and WL2 in a third direction (Z direction) and extend in the second direction (Y direction). The memory cell array 11 may be a two-dimensional (2D) memory. In some example embodiments, when the memory cell array 11 has a multi-layer structure, the memory cell array 11 may be a three-dimensional (3D) memory.

[0042] The memory cells MC may be arranged between the bit lines BL1, BL2, BL3, and BL4 and the word lines WL1 and WL2, respectively. Specifically, a plurality of memory cells MC may be arranged at a plurality of intersections between the bit lines BL1, BL2, BL3, and BL4 and the word lines WL1 and WL2, and each memory cell MC may include a selection element SW configured to select the variable resistance element R and a variable resistance element R configured to store information. The selection element SW may be referred to as a switching element or an access element. The number of word lines WL, the number of bit lines BL, and / or the number of memory cells MC may vary differently according to various example embodiments.

[0043] The memory cells MC may be arranged to have the same structure along the third direction (Z direction). For example, in the memory cells MC located between the word line WL1 and the bit line BL1, the selection element SW may be electrically connected to the word line WL1, the variable resistance element R may be electrically connected to the bit line BL1, and the variable resistance element R and the selection element SW may be connected in series. However, example embodiments of the inventive concept are not limited thereto. According to some other example embodiments, Figure 3 Unlike the embodiment shown in , the positions of the selection element SW and the variable resistance element R in the memory cell MC may be exchanged. For example, in the memory cell MC, the variable resistance element R may be connected to the word line WL1, and the selection element SW may be connected to the bit line BL1.

[0044] In the memory cell array 11, the selection element SW can control the flow of current flowing to the variable resistance element R according to the voltage applied to the word lines WL1 and WL2 and the bit lines BL1, BL2, BL3 and BL4. The selection element SW can control the flow of current so that the variable resistance element R can be changed to an amorphous state (high resistance state) or a crystalline state (low resistance state). That is, the selection element SW can be used as a bidirectional threshold switch (OTS) of a memory configured to switch the state of the variable resistance element R to any one of an on state and an off state.

[0045] The variable resistance element R may include a phase change material layer that can be reversibly transformed between a first state and a second state. The variable resistance element R is not limited thereto, and may include any variable resistor whose resistance changes according to an applied voltage. For example, in a selected memory cell MC, the resistance of the variable resistance element R may be reversibly transformed between a first state and a second state according to a voltage applied to the variable resistance element R.

[0046] According to the change in the resistance of the variable resistance element R, the memory cell MC can store digital information (such as data "0" or "1") and erase digital information from the memory cell MC. For example, the memory cell MC can write data in a high resistance state "0" and a low resistance state "1". Here, the transition from the high resistance state "0" to the low resistance state "1" may be referred to as a "set operation", and the transition from the low resistance state "1" to the high resistance state "0" may be referred to as a "reset operation". The memory cell MC according to some example embodiments is not limited to storing or erasing digital information including a high resistance state "0" and a low resistance state "1", but may store various resistance states.

[0047] Any memory cell MC can be accessed by selecting word lines WL1 and WL2 and bit lines BL1, BL2, BL3, and BL4. The memory cell MC can be programmed by applying a predetermined signal (expected signal, specific signal) between the word lines WL1 and WL2 and the bit lines BL1, BL2, BL3, and BL4. In addition, by measuring the current passing through the bit lines BL1, BL2, BL3, and BL4, the data of the corresponding memory cell MC (for example, programmed data) can be read according to the resistance of the variable resistance element R.

[0048] Return to reference Figure 2 , the write circuit 121 may be connected to the selected bit line BL and may provide a programming current to the selected memory cell MC to perform a programming operation (e.g., a write operation). Therefore, the write circuit 121 may input the data DATA to be stored to the memory cell array 11. Here, the programming current may be referred to as a write current.

[0049] When a write command is received from the memory controller 5, the write circuit 121 may perform a write operation on the memory cell MC. The write circuit 121 may perform a reset write operation for programming the memory cell MC in a direction in which the resistance of the memory cell MC increases. In the reset write operation, the write circuit 121 may program the memory cell MC to a target resistance state using a write pulse and a post-write pulse. The memory cell MC may be programmed to a target resistance state in response to the write pulse, and the resistance of the memory cell MC in the target resistance state may increase in response to the post-write pulse. In addition, the write circuit 121 may perform a set write operation for programming the memory cell MC in a direction in which the resistance of the memory cell MC decreases.

[0050] The read circuit 122 may be connected to the selected bit line BL and read the data DATA stored in the selected memory cell MC. When a read command is received from the memory controller 5, the read circuit 122 may perform a read operation on the memory cell MC. The read circuit 122 may read the data of each memory cell MC and provide the read result to the control circuit 13.

[0051] The control circuit 13 may output various control signals CTRL_OP and / or CTRL_VOL for writing data DATA into the memory cell array 11 and / or reading data DATA from the memory cell array 11 based on the command CMD, the address ADDR, and the control signal CTRL received from the memory controller 5. The control circuit 13 may provide the operation control signal CTRL_OP to the write / read circuit 12. The operation control signal CTRL_OP may include a write enable signal WEN, a write control signal WCS, a read enable signal REN, a precharge signal PRE, and / or a discharge signal DIS. In addition, the control circuit 13 may provide the voltage control signal CTRL_VOL to the voltage generator 14. In addition, the control circuit 13 may provide the row address X_ADDR to the row decoder 15, and may provide the column address Y_ADDR to the column decoder 16.

[0052] The control circuit 13 may control the memory cells MC of all or some areas of the memory block of the memory cell array 11 to be programmed to the target resistance state. The control circuit 13 may control a write pulse having a single voltage level to be applied to the memory cells MC. The memory cells MC may switch to the target resistance state in response to the write pulse.

[0053] In some example embodiments, the control circuit 13 may control a post-write pulse following the write pulse to be applied to the memory cell MC. In some example embodiments, the control circuit 13 may control the post-write pulse to be provided to the memory cell MC as a single pulse having at least n step voltage levels. The resistance of the memory cell MC in the target resistance state may increase in response to the post-write pulse having at least n step voltage levels.

[0054] In some other example embodiments, the control circuit 13 may control at least n post-write pulses following the write pulse to be applied to the memory cell MC. The resistance of the memory cell MC in the target resistance state may increase in response to the at least n post-write pulses.

[0055] The voltage generator 14 may generate various voltages based on the voltage control signal CTRL_VOL to perform a write operation and / or a read operation on the memory cell array 11. The voltage generator 14 may generate a first driving voltage V WL and a second driving voltage V for driving the plurality of bit lines BL BL .

[0056] The voltage generator 14 may generate a control voltage VC for controlling the magnitude of the write current I of the memory cell MC in a programming operation. The voltage generator 14 may generate the control voltage VC according to the voltage control signal CTRL_VOL. The control voltage VC may be used as a write pulse (refer to Fig. 9 WP in) and the post-write pulse (refer to Fig. 9 and Fig.13 The write current I supplied to the memory cell MC may be varied according to the control voltage VC applied to the write pulse WP and / or the post-write pulses P-WP and P-WPS.

[0057] The row decoder 15 may be connected to the memory cell array 11 through a plurality of word lines WL, and may activate a selected word line among the plurality of word lines WL in response to a row address X_ADDR received from the control circuit 13. The row decoder 15 may control a voltage applied to a selected word line among the plurality of word lines WL and / or control a connection relationship of the selected word line in response to the row address X_ADDR.

[0058] The column decoder 16 may be connected to the memory cell array 11 through a plurality of bit lines BL, and may activate a selected bit line among the plurality of bit lines BL in response to a column address Y_ADDR received from the control circuit 13. The column decoder 16 may control a voltage applied to a selected bit line among the plurality of bit lines BL and / or control a connection relationship of the selected bit line in response to the column address Y_ADDR. The column decoder 16 may be connected to the write / read circuit 12 through a data line DL.

[0059] Figure 4 According to some example embodiments Figure 3 FIG. 1 is a diagram showing a cross-sectional structure of a memory cell MC. Figure 4 The case where the cross-sectional structure of the memory cell MC is a regular quadrilateral structure is shown, but the example embodiments of the inventive concept are not limited thereto, and according to some other example embodiments, the cross-sectional structure of the memory cell MC may have various other shapes. For example, the cross-sectional structure of the memory cell MC may have various shapes (such as a semicircle, a semi-ellipse, a trapezoid, and / or a triangle).

[0060] Reference Figure 4, the memory cell MC may store digital information due to resistance changes between various resistance states including a high resistance state and a low resistance state. The memory cell MC may include a selection element layer 110, a variable resistance element layer 120, a lower electrode 130, an intermediate electrode 131, and an upper electrode 132. The lower electrode 130 and the upper electrode 132 may be spaced apart from each other. The lower electrode 130 may be electrically connected to a first conductive line 50, and the upper electrode 132 may be electrically connected to a second conductive line 60. The first conductive line 50 may be formed on the substrate 100. As a non-limiting example, the first conductive line 50 may be a word line (refer to Figure 3 The second conductor 60 may be a bit line (refer to Figure 3 One of BL1, BL2, BL3 and BL4).

[0061] The selection element layer 110 and the variable resistance element layer 120 may be disposed (located) between the lower electrode 130 and the upper electrode 132. For example, the selection element layer 110 may be formed (located) closer to (closer to) the lower electrode 130 than the upper electrode 132. The selection element layer 110 may be electrically connected to the lower electrode 130. The variable resistance element layer 120 may be disposed (located) between the upper electrode 132 and the selection element layer 110. The variable resistance element layer 120 may be formed (located) closer to (closer to) the upper electrode 132 than the lower electrode 130. The variable resistance element layer 120 may be electrically connected to the upper electrode 132.

[0062] although Figure 4 The case where the selection element layer 110 is more adjacent to (closer to) the substrate 100 than the variable resistance element layer 120 is shown, but example embodiments of the inventive concept are not limited thereto. According to some other example embodiments, Figure 4 Unlike the example embodiment shown in , the variable resistance element layer 120 may be more adjacent to (closer to) the substrate 100 than the selection element layer 110 .

[0063] The intermediate electrode 131 may be located between the selection element layer 110 and the variable resistance element layer 120. The intermediate electrode 131 may be electrically connected to each of the selection element layer 110 and the variable resistance element layer 120. The selection element SW of the memory cell MC may correspond to a combination of the selection element layer 110, the lower electrode 130, and the intermediate electrode 131, and the variable resistance element R of the memory cell MC may correspond to a combination of the variable resistance element layer 120, the upper electrode 132, and the intermediate electrode 131.

[0064] Each of the lower electrode 130, the middle electrode 131, and the upper electrode 132 may include various metals, metal oxides, and / or metal nitrides. For example, each of the lower electrode 130, the middle electrode 131, and the upper electrode 132 may include aluminum (Al), copper (Cu), titanium nitride (TiN), titanium aluminum nitride (TixAlyNz), iridium (Ir), platinum (Pt), silver (Ag), gold (Au), polysilicon, tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), nickel (Ni), cobalt (Co), chromium (Cr), antimony (Sb), iron (Fe), molybdenum (Mo), palladium (Pd), tin (Sn), zirconium (Zr), zinc (Zn), iridium oxide (IrO 2 ) and / or strontium zirconate (StZrO 3 ).

[0065] The variable resistance element layer 120 may include a resistance change layer whose resistance changes according to an electric field. As a non-limiting example, according to some example embodiments, when the variable resistance element layer 120 includes a transition metal oxide, the memory device 10 may be an RRAM. According to some other example embodiments, when the variable resistance element layer 120 includes a phase change material whose resistance changes with temperature, the memory device 10 may be a PRAM. According to some other example embodiments, when the variable resistance element layer 120 includes two magnetic electrodes and a dielectric material between the magnetic electrodes, the memory device 10 may be an MRAM.

[0066] For example, the variable resistance element layer 120 may include a phase change material whose resistance state changes due to Joule heat. The variable resistance element layer 120 may include a mixture of germanium, antimony and tellurium (Ge-Sb-Te, GST). In some example embodiments, the variable resistance element layer 120 may include a chalcogenide material, wherein the chalcogenide material contains at least two elements selected from silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi), indium (In), tin (Sn) and selenium (Se). In some other example embodiments, the variable resistance element layer 120 may include a chalcogenide material, wherein the chalcogenide material contains impurities of at least one element selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P) and sulfur (S).

[0067] For example, the selection element layer 110 may be used as a bidirectional threshold switch (OTS) including a chalcogenide switching material. The chalcogenide switching material may include a chalcogenide material, wherein the chalcogenide material is further doped with at least one element selected from nitrogen (N), oxygen (O), phosphorus (P), and sulfur (S). In some example embodiments, the chalcogenide switching material may include arsenic (As) or selenium (Se), and may further include at least two elements selected from silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), selenium (Se), indium (In), and tin (Sn).

[0068] The GST material of the variable resistance element layer 120 can be programmed between an amorphous state having a relatively high resistivity and a crystalline state having a relatively low resistivity. For example, the GST material can be programmed by heating. The amplitude and length of time of heating can determine whether the GST material remains in the amorphous state (high resistance state) or in the crystalline state (low resistance state). High resistivity and low resistivity can indicate programming value logic "0" and logic "1", respectively, and can be sensed by measuring the resistivity of the GST material. Conversely, high resistivity and low resistivity can indicate programming value logic "1" and logic "0", respectively.

[0069] Figure 5 is a diagram showing an example embodiment of the invention according to which Figure 4 FIG. 5 is a graph of the write current I of the memory cell MC.

[0070] Reference Figure 5 In order to place the variable resistance element layer 120 in an amorphous state (high resistance state or reset state), a high reset write current Irst may be applied to the memory cell MC for a short time, and then the high reset write current Irst may be eliminated. In order to place the variable resistance element layer 120 in a crystalline state (low resistance state or set state), a set write current Iset lower than the reset write current Irst may be applied to the memory cell MC, and the applied set write current Iset may be maintained (for example, the set write current Iset may be applied to the memory cell MC for a period of time relatively longer than the reset write current Irst) to crystallize the variable resistance element layer 120 and then eliminate the applied set write current Iset. According to the above method, the memory cell MC may be set to any one of a crystalline state and an amorphous state. Here, TP1 represents the crystallization temperature of the variable resistance element layer 120, and TP2 represents the melting point of the variable resistance element layer 120.

[0071] Figure 6 is a diagram showing some example embodiments Figure 4 Graph showing voltage-current (VI) characteristics of a selection element SW of a memory cell MC.

[0072] Reference Figure 6, the selection element SW of the memory cell MC may be implemented as a bidirectional threshold switch (OTS) including a chalcogenide switching material. The first curve 61 shows the VI relationship in a state (first state) in which no current is supplied to the selection element SW. Here, the selection element SW may be used as a switching element having a threshold voltage Vt, wherein the threshold voltage Vt has a first voltage level 63. When the voltage gradually increases in a state in which each of the voltage and the current is 0, the current hardly flows through the selection element SW until the voltage reaches the threshold voltage Vt having the first voltage level 63. Subsequently, once the voltage exceeds the threshold voltage Vt, the current flowing through the selection element SW increases rapidly, and the voltage applied to the selection element SW may be reduced to a saturation voltage Vs, wherein the saturation voltage Vs has a second voltage level 64 lower than the first voltage level 63. Here, it should be noted that the numbers "63" and "64" are reference characters and do not represent actual voltage values.

[0073] The second curve 62 shows the VI relationship in the state (second state) in which the current is supplied to the selection element SW. When the current supplied to the selection element SW becomes higher than the first current level 66, the voltage applied to the selection element SW may become slightly higher than the second voltage level 64. For example, when the current supplied to the selection element SW increases significantly from the first current level 66 to the second current level 67, the voltage applied to the selection element SW may increase slightly from the second voltage level 64. That is, once the current flows through the selection element SW, the voltage applied to the selection element SW may be substantially maintained at the saturation voltage Vs. If the current supplied to the selection element SW decreases to the first current level 66 or lower, the selection element SW may be switched to a high resistance state again, and the current may be effectively blocked until the voltage applied to the selection element SW increases to the threshold voltage Vt. Here, the first current level 66 may be referred to as a holding current level. Here, it should be noted that the numbers "66" and "67" are reference characters and do not represent actual current values.

[0074] FIG. 7A to FIG. 7C is a diagram showing the Figure 4 is a graph showing characteristics of a memory cell when the memory cell MC is a single-layer cell (SLC).

[0075] Fig. 7A , where SLC is a memory cell MC programmed with 1 bit. Fig. 7A In FIG. 1 , the horizontal axis represents the threshold voltage Vth of the memory cell MC, and the vertical axis represents the number of the memory cell MC. The variable resistance element R of the memory cell MC can have a low resistance state LRS or a high resistance state HRS. By applying a set write current (refer to Figure 5The operation of switching the variable resistance element R from the high resistance state HRS to the low resistance state LRS by applying a reset write current (refer to Iset in FIG. 1 ) to the memory cell MC may be referred to as a set operation or a set write operation. Figure 5 The operation of switching the variable resistance element R from the low resistance state LRS to the high resistance state HRS by using Irst in FIG. 1 may be referred to as a reset operation or a reset write operation.

[0076] A specific voltage between the distribution caused by the low resistance state LRS and the distribution caused by the high resistance state HRS may be set as a read voltage Vread. In a read operation on the memory cell MC, when the read data is equal to or higher than the read voltage Vread, the read data may be determined as reset data (logic "0") in the high resistance state HRS, and when the read data is lower than the read voltage Vread, the read data may be determined as set data (logic "1") in the low resistance state LRS.

[0077] exist Fig. 7A In the ideal threshold voltage distribution of , it can be seen that based on the read voltage Vread, the read window Wread is relatively wide. The read window Wread refers to the non-overlapping threshold voltage interval between the distribution caused by the low resistance state LRS and the distribution caused by the high resistance state HRS. When the read window Wread is wide, in the read operation of the memory cell MC, the probability of read error of the reset data (logic "0") and / or the set data (logic "1") may be small. However, after the memory cell MC is programmed, the resistance characteristics of the memory cell MC may deteriorate with respect to time, such as Figure 7B and Figure 7C as shown in .

[0078] Figure 7B 1 shows an exemplary characteristic of a memory cell programmed with reset write current Irst applied to reset data (logic "0"). Figure 7B , the abscissa represents time and the ordinate represents resistance. Initially, the resistivity of the target memory cell MC may be such that the variable resistance element R may have a high resistance. However, after the memory cell MC is programmed with reset data (logic "0"), the resistance of the memory cell MC may greatly increase with respect to time.

[0079] Figure 7C 1 shows exemplary characteristics of a memory cell programmed with a set write current Iset to set data (logic "1"). Figure 7C, the abscissa represents time and the ordinate represents resistance. Initially, the resistivity of the target memory cell MC may be such that the variable resistance element R may have a low resistance. However, after the memory cell MC is programmed with set data (logic "1"), the resistance of the memory cell MC may increase slightly with respect to time.

[0080] like Figure 7B and Figure 7C As shown in , after the memory cell MC is programmed, as time passes, the distribution caused by the low resistance state LRS and the high resistance state HRS can be modified by changing the resistance of the programmed memory cell MC. Therefore, the read window Wread between the modified distributions caused by the low resistance state LRS and the high resistance state HRS can be compared to the ideal read window Wread (for example, referring to Fig. 7A ) is narrow. In addition, the read window Wread may be further reduced with respect to time. Such a narrowing of the read window Wread over time may indicate a reduction in the sensing margin or reading margin between the set data (logical "1") and the reset data (logical "0"). As a result, the sensing or reading of the reset data (logical "0") and / or the set data (logical "1") may become uncertain, slow and / or generally unreliable. Therefore, due to the reduction in the read window Wread, the accuracy, speed and / or reliability of the resistive memory device may be degraded. Therefore, increasing the read window Wread between the low resistance state LRS and the high resistance state HRS is beneficial to ensuring the read margin of the memory cell MC and thereby reducing read errors.

[0081] Figure 8 is a diagram showing the Figure 4 A graph showing the distribution of the memory cell MC with respect to the resistance when the memory cell MC is a multi-layer cell (MLC). Figure 8 In FIG. 1 , the abscissa represents the threshold voltage Vth, and the ordinate represents the number of memory cells MC. VR1, VR2, and VR3 are read voltages.

[0082] Reference Figure 8 , when the memory cell MC is an MLC programmed with 2 bits, the memory cell MC may have one resistance state among the first resistance state RS1, the second resistance state RS2, the third resistance state RS3, and the fourth resistance state RS4. However, the example embodiments of the inventive concept are not limited thereto, and in some other example embodiments, the plurality of memory cells may include a triple-layer cell (TLC) configured to store 3-bit data. Therefore, each of the plurality of memory cells may have one resistance state among eight resistance states. In some other example embodiments, the plurality of memory cells may include memory cells each of which may store 4 bits or more of data.

[0083] Each of the resistance states RS1, RS2, RS3, and RS4 may correspond to any one of data "00", data "01", data "10", and data "11". In some example embodiments, the resistance levels of data "11", data "01", data "00", and data "10" may increase in sequence. That is, the first resistance state RS1 may correspond to data "11", the second resistance state RS2 may correspond to data "01", the third resistance state RS3 may correspond to data "00", and the fourth resistance state RS4 may correspond to data "10".

[0084] Compared to SLC, since MLC has a narrow read window between resistance distributions, read errors may occur due to small changes in threshold voltage. In addition, after the MLC is programmed, when the read window between resistance distributions is further reduced with respect to time, further read errors may occur. Therefore, in order to ensure the read margin of the MLC and thereby reduce read errors, it may be beneficial to increase the non-overlap read window between the first resistance state RS1, the second resistance state RS2, the third resistance state RS3, and the fourth resistance state RS4.

[0085] Fig. 9 2 is a diagram for explaining a method of operating a memory device according to some example embodiments.

[0086] Reference Fig. 9 , when the memory cell (refer to Figure 3 MC in Fig. 7A When the SLC shown in , a programming operation may be performed so that a target resistance state caused by reset data to be programmed into the memory cell MC has a high resistance state HRS. The operation of programming the reset data may be performed using a write pulse WP and a post-write pulse P-WP.

[0087] When a write pulse WP is supplied to the memory cell MC, the write current is reset (refer to Figure 5 The post-write pulse P-WP may be applied to the memory cell MC, and thus, the memory cell MC may be switched to the high resistance state HRS. After the write pulse WP, the post-write pulse P-WP may be applied to the memory cell MC. According to some example embodiments, the post-write pulse P-WP may be provided as a single pulse having at least n step voltage levels (n is an integer equal to or greater than 2). Hereinafter, the post-write pulse P-WP having four step voltage levels (1), (2), (3), and (4) will be described.

[0088] According to some example embodiments, the four step voltage levels (1), (2), (3), and (4) of the post-write pulse P-WP may increase with a constant amplitude ΔV. Also, according to some example embodiments, each of the four step voltage levels (1), (2), (3), and (4) of the post-write pulse P-WP may have a constant width ΔW.

[0089] When the write post pulse P-WP is applied to the memory cell MC, the memory cell MC may change from the high resistance state HRS caused by the write pulse WP to one of the first to fourth rear high resistance states HRS1 to HRS4. In response to the write post pulse P-WP, the first to fourth rear high resistance states HRS1 to HRS4 may move in a direction in which the resistance of the high resistance state HRS increases. Therefore, according to some example embodiments, a read window Wread between a distribution caused by the low resistance state LRS and a distribution caused by the high resistance state HRS due to the write pulse WP may be extended to an extended read window Wread_extend between a distribution caused by the low resistance state LRS and a distribution caused by the fourth rear high resistance state HRS4 due to the write post pulse P-WP.

[0090] FIG. 10A to FIG. 10D is a diagram showing some example embodiments Fig. 9 Graph of the post-write pulse P-WP. Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D The first step voltage level (1), the second step voltage level (2), the third step voltage level (3) and the fourth step voltage level (4) of the post-write pulse P-WP are specifically shown respectively.

[0091] exist Fig. 10A In the memory cell (refer to Figure 3 The memory cell MC in the high resistance state HRS may be switched to the high resistance state HRS in response to the write pulse WP supplied to the memory cell MC. The memory cell MC in the high resistance state HRS may have a threshold voltage equal to or higher than a minimum threshold voltage VHRS required to switch the memory cell MC to the high resistance state HRS. The first step voltage level (1) of the post-write pulse P-WP may be set to a voltage level VSP1 lower than the minimum threshold voltage VHRS of the high resistance state HRS. Figure 3 By applying the first step voltage level (1) of the post-write pulse P-WP of the MC in FIG. 1 , the memory cell MC can be switched to the first post high resistance state HRS1.

[0092] exist Fig. 10BIn the embodiment, the second step voltage level (2) of the write post pulse P-WP can be set to a voltage level VSP2 lower than the minimum threshold voltage VHRS1 of the first post high resistance state HRS1. Figure 3 By applying the second step voltage level (2) of the post-write pulse P-WP of the MC in FIG. 1 , the memory cell MC can be switched to the second post high resistance state HRS2.

[0093] exist Fig. 10C In the embodiment, the third step voltage level (3) of the post-write pulse P-WP can be set to a voltage level VSP3 lower than the minimum threshold voltage VHRS2 of the second post-high resistance state HRS2. Figure 3 By the third step voltage level (3) of the post-write pulse P-WP of the MC in FIG. 1 , the memory cell MC can be switched to the third post-high resistance state HRS3.

[0094] exist Fig. 10D In the embodiment, the fourth step voltage level (4) of the post-write pulse P-WP can be set to a voltage level VSP4 lower than the minimum threshold voltage VHRS3 of the third post-high resistance state HRS3. Figure 3 By the fourth step voltage level (4) of the post-write pulse P-WP of the MC in FIG. 1 , the memory cell MC can be switched to the fourth post-high resistance state HRS4.

[0095] exist FIG. 10A to FIG. 10D , the first step voltage level (1) or VSP1 of the post-write pulse P-WP may be set to a level lower than the minimum threshold voltage VHRS of the target resistance state (e.g., the high resistance state HRS) due to the previous write pulse WP. The nth step voltage level of the post-write pulse P-WP may be set to a level lower than the minimum threshold voltage level of the target resistance state (e.g., the (n-1)th high resistance state) changed by the (n-1)th step voltage level of the post-write pulse P-WP.

[0096] Here, the nth step voltage level of the post-write pulse P-WP may be set to be lower than the minimum threshold voltage level of the (n-1)th high resistance state changed by the (n-1)th step voltage level of the post-write pulse P-WP, thereby preventing the memory cell MC from being reprogrammed to a resistance state other than the target resistance state. The memory cell MC may be programmed to 2 m Assume, as a non-limiting example, that the target resistance state of the memory cell MC is Figure 8In this case, when the nth step voltage level of the post-write pulse P-WP is set to be higher than the minimum threshold voltage level of the (n-1)th high resistance state, the memory cell MC is not programmed to the second resistance state RS2, but may be programmed to the third resistance state RS3 or the fourth resistance state RS4.

[0097] FIG. 11A to FIG. 11D is a diagram showing some other example embodiments Fig. 9 FIG. 1 is a graph of a modified example of the post-write pulse P-WP. FIG. 11A to FIG. 11D The step voltage levels of the post-write pulse P-WP are shown to be set to various amplitudes (for example, refer to Fig.11A and Fig. 11B ) and / or width (e.g., refer to Fig. 11C and 11D ) are non-limiting examples.

[0098] exist Fig.11A , the first step voltage level (1), the second step voltage level (2), the third step voltage level (3), and the fourth step voltage level (4) of the post-write pulse P-WPa may be increased at different amplitudes. Assuming that the difference between the first step voltage level (1) and the second step voltage level (2) of the post-write pulse P-WPa is ΔV1, the difference between the second step voltage level (2) and the third step voltage level (3) of the post-write pulse P-WPa is ΔV2, and the difference between the third step voltage level (3) and the fourth step voltage level (4) of the post-write pulse P-WPa is ΔV3. The increase amplitudes of the second step voltage level (2), the third step voltage level (3), and the fourth step voltage level (4) of the post-write pulse P-WPa may be set to gradually increasing values ​​(e.g., ΔV1<ΔV2<ΔV3).

[0099] exist Fig. 11B In the embodiment, the increase amplitudes of the second step voltage level (2), the third step voltage level (3) and the fourth step voltage level (4) of the post-write pulse P-WPb may be set to gradually decreasing values ​​(eg, ΔV1>ΔV2>ΔV3).

[0100] exist Fig. 11C, the widths of the first step voltage level (1), the second step voltage level (2), the third step voltage level (3), and the fourth step voltage level (4) of the post-write pulse P-WPc may be set to respective different values. Assume that the width of the first step voltage level (1) of the post-write pulse P-WPc is ΔW1, the width of the second step voltage level (2) of the post-write pulse P-WPc is ΔW2, the width of the third step voltage level (3) of the post-write pulse P-WPc is ΔW3, and the width of the fourth step voltage level (4) of the post-write pulse P-WPc is ΔW4. The widths of the first step voltage level (1), the second step voltage level (2), the third step voltage level (3), and the fourth step voltage level (4) of the post-write pulse P-WPc may be set to gradually decreasing values ​​(e.g., ΔW1>ΔW2>ΔW3>ΔW4).

[0101] exist Fig.11D In the embodiment, the widths of the first step voltage level (1), the second step voltage level (2), the third step voltage level (3) and the fourth step voltage level (4) of the post-write pulse P-WPd can be set to gradually increasing values ​​(for example, ΔW1<ΔW2<ΔW3<ΔW4).

[0102] According to some example embodiments, referring to FIG. 11A to FIG. 11D The amplitudes and / or widths of the first step voltage level (1), the second step voltage level (2), the third step voltage level (3) and the fourth step voltage level (4) of the described post-write pulses P-WPa, P-WPb, P-WPc and P-WPd may be optionally combined and / or modified. For example, as described with reference to FIG. 11A to FIG. 11D As described, the first step voltage level (1) or VSP1 of each of the post-write pulses P-WPa, P-WPb, P-WPc, and P-WPd may be set to be lower than the minimum threshold voltage level VHRS of the target resistance state (e.g., the high resistance state HRS) of the previous write pulse WP, and the nth step voltage level of each of the post-write pulses P-WPa, P-WPb, P-WPc, and P-WPd may be set to be lower than the minimum threshold voltage level of the target resistance state (e.g., the (n-1)th high resistance state) changed by the (n-1)th step voltage level of each of the post-write pulses P-WPa, P-WPb, P-WPc, and P-WPd. Therefore, the memory cell MC may be prevented from being reprogrammed to a resistance state other than the target resistance state.

[0103] Fig.12 is a flowchart of a method of writing to a memory device according to some example embodiments.

[0104] Reference Figure 1 , Figure 2 , Fig. 9 and Fig.12 In operation S1210, the memory device 10 may perform a write operation via control of the write operation by the memory controller 5. The control circuit 13 of the memory device 10 may control each of the memory cells MC of all or some areas of the memory block in the memory cell array 11 to be programmed to a target resistance state. The target resistance state may be the resistance state to which the memory cell MC is programmed. m A resistance state having a relatively high resistance level (eg, a reset direction resistance state) among resistance states (m is a natural number greater than 0) is selected.

[0105] In operation S1220, the control circuit 13 may control a write pulse WP having a single voltage level to be applied to the memory cell MC in the write operation. The memory cell MC may be switched to a target resistance state in response to the write pulse WP.

[0106] In operation S1230, the control circuit 13 may control a post-write pulse P-WP following the write pulse WP to be applied to the memory cell MC. According to some example embodiments, the control circuit 13 may control the post-write pulse P-WP to be provided to the memory cell MC as a single pulse having at least n step voltage levels (n is an integer equal to or greater than 2). According to some example embodiments, the control circuit 13 may control the amplitude and / or width of the at least n step voltage levels to be variously changed.

[0107] In the above-described method of writing to the memory device 10, since the post-write pulse P-WP is applied to the memory cell MC, the resistance of the memory cell MC in the target resistance state is moved to a higher resistance. Therefore, the memory device 10 can extend the read window Wread_extend between the distribution caused by the low resistance state LRS and the distribution caused by the post-write pulse P-WP, and ensure the read margin of the memory cell MC, thereby reducing read errors.

[0108] Fig.13 2 is a diagram for explaining a method of operating a memory device according to some example embodiments.

[0109] Reference Fig.13 , four post-write pulses P-WPS can be used without using a reference Fig. 9 The single post-write pulse P-WP having four step voltage levels (1), (2), (3) and (4) is used to perform the operation of programming the reset data. Fig.13 Four post-write pulses P-WPS are illustrated, but example embodiments of the inventive concepts are not limited thereto, and various numbers of post-write pulses P-WPS may be used according to some other example embodiments.

[0110] When a write pulse WP is supplied to the memory cell MC, the write current is reset (refer to Figure 5 The Irst in the write pulse WP may be applied to the memory cell MC so that the memory cell MC may be switched to the high resistance state HRS. A post-write pulse P-WPS that may follow the write pulse WP may be provided to the memory cell MC. The post-write pulse P-WPS may be provided as at least n multi-pulses (n is an integer equal to or greater than 2). Hereinafter, a non-limiting example in which the post-write pulse P-WPS includes four post-write pulses (a), (b), (c), and (d) will be described.

[0111] According to some example embodiments, the first post-write pulse (a), the second post-write pulse (b), the third post-write pulse (c), and the fourth post-write pulse (d) of the post-write pulse P-WPS may increase with a constant amplitude ΔV. In addition, according to some example embodiments, each of the first post-write pulse (a), the second post-write pulse (b), the third post-write pulse (c), and the fourth post-write pulse (d) of the post-write pulse P-WPS may have a constant width ΔW.

[0112] When the write post pulse P-WPS is applied to the memory cell MC, the memory cell MC may change from the high resistance state HRS caused by the write pulse WP to one of the first rear high resistance state HRSa to the fourth rear high resistance state HRSd. In response to the write post pulse P-WPS, the first rear high resistance state HRSa to the fourth rear high resistance state HRSd may move in the direction of increasing resistance of the high resistance state HRS. Therefore, the read window Wread between the distribution caused by the low resistance state LRS and the distribution caused by the high resistance state HRS due to the write pulse WP can be extended to the extended read window Wread_extend between the distribution caused by the low resistance state LRS and the distribution caused by the fourth rear high resistance state HRSd due to the fourth write post pulse (d).

[0113] FIG. 14A to FIG. 14D is a diagram showing some example embodiments Fig.13 Graph of the post-write pulse P-WPS. FIG. 14A to FIG. 14D A first post-write pulse (a), a second post-write pulse (b), a third post-write pulse (c), and a fourth post-write pulse (d) of the post-write pulse P-WPS are specifically shown, respectively.

[0114] exist Fig.14A In the memory cell (refer to Figure 3The memory cell MC in the high resistance state HRS may be switched to the high resistance state HRS in response to the write pulse WP supplied to the memory cell MC. The memory cell MC in the high resistance state HRS may have a threshold voltage equal to or higher than a minimum threshold voltage VHRS required to switch the memory cell MC to the high resistance state HRS. The first post-write pulse (a) may be set to a voltage level VSPa having a voltage lower than the minimum threshold voltage VHRS of the high resistance state HRS. The memory cell MC may be switched to the high resistance state HRS in response to the write pulse WP supplied to the memory cell MC. Figure 3 The first post-write pulse (a) of MC in FIG. 1 switches to the first post-high resistance state HRSa.

[0115] exist Fig. 14B In the embodiment, the second post-write pulse (b) may be set to have a voltage level VSPb lower than the minimum threshold voltage VHRSa of the first post-high resistance state HRSa. The memory cell MC may respond to the voltage provided to the memory cell (refer to Figure 3 The second post-write pulse (b) of MC in FIG. 1 switches to the second post-high resistance state HRSb.

[0116] exist Fig. 14C In the embodiment, the third post-write pulse (c) may be set to have a voltage level VSPc lower than the minimum threshold voltage VHRSb of the second post high resistance state HRSb. The memory cell MC may respond to the voltage provided to the memory cell (refer to Figure 3 The MC in FIG. 1 is switched to the third post-write high resistance state HRSc by the third post-write pulse (c) of MC in FIG.

[0117] exist Fig.14D In the embodiment, the fourth post-write pulse (d) may be set to have a voltage level VSPd lower than the minimum threshold voltage VHRSc of the third post-high resistance state HRSc. The memory cell MC may respond to the voltage provided to the memory cell (refer to Figure 3 The fourth post-write pulse (d) of MC in is switched to the fourth post-high resistance state HRSd.

[0118] exist FIG. 14A to FIG. 14D , the voltage level VSPa of the first post-write pulse (a) may be set to a level lower than the minimum threshold voltage VHRS of the target resistance state (e.g., the high resistance state HRS) due to the previous write pulse WP. The voltage level of the nth post-write pulse may be set to a level lower than the minimum threshold voltage level of the target resistance state (e.g., the (n-1)th high resistance state) changed by the (n-1)th post-write pulse.

[0119] Here, the voltage level of the nth post-write pulse may be set to be lower than the minimum threshold voltage level of the (n-1)th high resistance state changed by the (n-1)th post-write pulse, thereby preventing the memory cell MC from being reprogrammed to a resistance state other than the target resistance state. The memory cell MC may be programmed to 2 m Assume, as a non-limiting example, that the target resistance state of the memory cell MC is Figure 8 In this case, when the voltage level of the nth post-write pulse is set to be higher than the minimum threshold voltage level of the (n-1)th high resistance state, the memory cell MC is not programmed to the second resistance state RS2, but may be programmed to the third resistance state RS3 or the fourth resistance state RS4.

[0120] Figures 15A to 15D is a diagram showing some other example embodiments Fig.13 A graph of a modified example of the post-write pulse P-WPS. FIG. 15A to FIG. 15D The post-write pulse P-WPS is shown to be set to have various amplitudes (for example, refer to Fig.15A and Fig. 15B ) and / or width (e.g., refer to Fig. 15C and Fig.15D ) are non-limiting examples.

[0121] exist Fig.15A , the first post-write pulse (a), the second post-write pulse (b), the third post-write pulse (c), and the fourth post-write pulse (d) of the post-write pulse P-WPSa may increase at different amplitudes. Assume that the voltage difference between the first post-write pulse (a) and the second post-write pulse (b) is ΔVa, the voltage difference between the second post-write pulse (b) and the third post-write pulse (c) is ΔVb, and the voltage difference between the third post-write pulse (c) and the fourth post-write pulse (d) is ΔVc. The increase amplitudes of the second post-write pulse (b), the third post-write pulse (c), and the fourth post-write pulse (d) of the post-write pulse P-WPSa may be set to gradually increasing values ​​(e.g., ΔVa<ΔVb<ΔVc).

[0122] exist Fig. 15B , the increase amplitudes of the second post-write pulse (b), the third post-write pulse (c), and the fourth post-write pulse (d) of the post-write pulse P-WPSb may be set to gradually decreasing values ​​(eg, ΔVa>ΔVb>ΔVc).

[0123] exist Fig. 15C, the widths of the first post-write pulse (a), the second post-write pulse (b), the third post-write pulse (c), and the fourth post-write pulse (d) of the post-write pulse P-WPSc may be set to respective different values. Assume that the width of the first post-write pulse (a) is ΔWa, the width of the second post-write pulse (b) is ΔWb, the width of the third post-write pulse (c) is ΔWc, and the width of the fourth post-write pulse (d) is ΔWd. The widths of the first post-write pulse (a), the second post-write pulse (b), the third post-write pulse (c), and the fourth post-write pulse (d) of the post-write pulse P-WPSc may be set to gradually decreasing values ​​(e.g., ΔWa>ΔWb>ΔWc>ΔWd).

[0124] exist Fig.15D In the embodiment, the widths of the first post-write pulse (a), the second post-write pulse (b), the third post-write pulse (c), and the fourth post-write pulse (d) of the post-write pulse P-WPSd can be set to gradually increasing values ​​(e.g., ΔWa<ΔWb<ΔWc<ΔWd).

[0125] According to some example embodiments, referring to FIG. 15A to FIG. 15D The amplitudes and / or widths of the first post-write pulse (a), the second post-write pulse (b), the third post-write pulse (c), and the fourth post-write pulse (d) of the described post-write pulses P-WPSa, P-WPSb, P-WPSc, and P-WPSd may be optionally combined and / or modified. As an example, as shown in FIG. FIG. 14A to FIG. 14D As described above, the first voltage level VSPa of the first post-write pulse (a) of the post-write pulses P-WPSa, P-WPSb, P-WPSc and P-WPSd may be set to be lower than the minimum threshold voltage level VHRS of the target resistance state (e.g., the high resistance state HRS) due to the previous write pulse WP, and the voltage level of the nth post-write pulse of the post-write pulses P-WPSa, P-WPSb, P-WPSc and P-WPSd may be set to be lower than the minimum threshold voltage level VHRS of the target resistance state (e.g., the (n-1)th high resistance state) changed by the (n-1)th post-write pulse.

[0126] Fig.16 is a flowchart of a method of writing to a memory device according to some example embodiments.

[0127] Reference Figure 1 , Figure 2 , Fig.13 and Fig.16In operation S1610, the memory device 10 may perform a write operation via control of the write operation by the memory controller 5. The control circuit 13 of the memory device 10 may control each of the memory cells MC of all or some areas of the memory block in the memory cell array 11 to be programmed to a target resistance state. The target resistance state may be the resistance state to which the memory cell MC is programmed. m A resistance state having a relatively high resistance level (ie, a reset direction resistance state) among resistance states (m is an integer greater than 0) is selected.

[0128] In operation S1620, the control circuit 13 may control a write pulse WP having a single voltage level to be applied to the memory cell MC in the write operation. The memory cell MC may be switched to a target resistance state in response to the write pulse WP.

[0129] In operation S1630, the control circuit 13 may control a post-write pulse P-WPS following the write pulse WP to be applied to the memory cell MC. According to some example embodiments, the control circuit 13 may control the post-write pulse P-WPS including at least n multi-pulses (n is an integer equal to or greater than 2) to be provided to the memory cell MC. According to some example embodiments, the control circuit 13 may control the amplitude and / or width of the at least n post-write pulses P-WPS to be variously changed.

[0130] In the above-described method of writing to the memory device 10, since the post-write pulse P-WPS is applied to the memory cell MC as n multi-pulses, the resistance of the memory cell MC in the target resistance state is moved to a higher resistance. Therefore, the memory device 10 can extend the read window Wread_extend between the distribution caused by the low resistance state LRS and the distribution caused by the post-write pulse P-WPS, and ensure the read margin of the memory cell MC, thereby reducing read errors.

[0131] Fig.17 is a circuit diagram of a write / read circuit 12 of a memory device according to some example embodiments.

[0132] Reference Fig.17 , the memory cell MC may be located at a region where the bit line BL crosses the word line WL, and may include a variable resistance element R and a selection element SW. The column decoder 16 may include a bit line selection transistor Ty, wherein the bit line selection transistor Ty may connect the memory cell MC to the write / read circuit 12 in response to the column selection signal Yi. The write / read circuit 12 may include a write circuit 121 and a read circuit 122. Hereinafter, a case where the column selection signal Yi is activated to connect the memory cell MC to the write / read circuit 12 will be described.

[0133] The write circuit 121 may provide a write current I for programming the memory cell MC. The write circuit 121 may include a first transistor T11 and a second transistor T12, a current pulse provider CPG, and a latch circuit LC. When the write enable signal WEN is activated, the first transistor T11 may be turned on so that the write circuit 121 may be connected to the memory cell MC.

[0134] The current pulse provider CPG may include a third transistor T13, a fourth transistor T14, and a fifth transistor T15. The third transistor T13 and the fourth transistor T14 may constitute a current mirror, and the fifth transistor T15 may provide a write current I in response to a control voltage VC applied to a gate of the fifth transistor T15. The control voltage VC may be used as a reference. Figures 9 to 13 The types of write pulse WP, post-write pulse P-WP and / or post-write pulse P-WPS described above are applied.

[0135] The latch circuit LC may output a gate voltage in response to the write control signal WCS so that the second transistor T12 is selectively turned on according to the logic level of the input data DI. The input data DI may be data derived from the data DATA provided by the memory controller 5.

[0136] In some example embodiments, when the write control signal WCS indicates a reset direction write operation, the latch circuit LC may turn on the second transistor T12 when the logic level of the input data DI is '0' and may turn off the second transistor T12 when the logic level of the input data DI is '1'.

[0137] In some other example embodiments, when the write control signal WCS indicates a set direction write operation, the latch circuit LC may turn off the second transistor T12 when the logic level of the input data DI is "0", and may turn on the second transistor T12 when the logic level of the input data DI is "1".

[0138] The read circuit 122 may read data stored in the memory cell MC. The read circuit 122 may include a first transistor T21, a second transistor T22, a third transistor T23, and a sense amplifier SA. When the read enable signal REN is activated, the first transistor T21 may be turned on, and the read circuit 122 may be connected to the memory cell MC.

[0139] When the precharge signal PRE is activated, the second transistor T22 may be turned on and the bit line BL may be precharged to the precharge voltage Vpre. On the other hand, when the discharge signal DIS is activated, the third transistor T23 may be turned on and the bit line BL may be discharged to the ground voltage.

[0140] The sense amplifier SA can sense the voltage VSN With reference voltage V ref The comparison is performed, and output data DO indicating whether the memory cell MC is in the on state or the off state can be output based on the result of the comparison. ref can be set to read voltage (e.g., reference Figure 8 The output data DO may be provided as data DATA to the outside of the memory device 10 (eg, to the memory controller 5).

[0141] Fig.18 is a memory device according to some example embodiments (eg, referring to Figure 1 10). A block diagram of a configuration of a memory system 1800 having a memory device 10).

[0142] Reference Fig.18 , the memory system 1800 may include a memory controller 1810, a plurality of non-volatile memory devices (NVM) 1820 to 182n, and a volatile memory device (VM) 1830. The memory controller 1810 may control write operations and / or read operations of the plurality of non-volatile memory devices 1820 to 182n in response to a request from a host HOST connected to the memory system 1800. The memory controller 1810 (or its processing unit) may be implemented as a microprocessor (MP) or a central processing unit (CPU), and the MP or CPU is configured to execute an operating system and / or software program and perform specific calculations and / or tasks.

[0143] In some example embodiments, the host HOST can be any computing system (such as a personal computer (PC), a server computer, a workstation, a laptop computer, a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television (digital TV), a set-top box, a music player, a portable game console and / or a navigation system).

[0144] A plurality of nonvolatile memory devices 1820 to 182n may be used as storage media of the memory system 1800. For example, each of the nonvolatile memory devices 1820 to 182n may be a resistive memory device. The plurality of nonvolatile memory devices 1820 to 182n may be connected to the memory controller 1810 through a channel. In response to a request provided from the host HOST through the channel, each of the nonvolatile memory devices 1820 to 182n may perform a write operation and / or a read operation.

[0145] The volatile memory device 1830 may temporarily store write data provided from the host HOST and / or read data from the nonvolatile memory devices 1820 to 182n. The volatile memory device 1830 may store metadata and / or cache data to be stored in the nonvolatile memory devices 1820 to 182n. For example, the volatile memory device 1830 may include a dynamic RAM (DRAM) or a static RAM (SRAM).

[0146] Each of the nonvolatile memory devices 1820 to 182n may be a reference Figures 1 to 17 The memory device 10 described corresponds to a resistive memory device. Each of the nonvolatile memory devices 1820 to 182n may include: a memory cell array 11 including memory cells; a write circuit 121 configured to program the memory cells to a target resistance state; and a control circuit 13 configured to control a write pulse and a post-write pulse following the write pulse to be applied to the memory cells. The memory cells may be programmed to the target resistance state in response to the write pulse, and the resistance of the memory cells in the target resistance state may increase in response to the post-write pulse.

[0147] Fig.19 is a block diagram of a system 1900 to which a memory device according to some example embodiments is applied.

[0148] Reference Fig.19 , system 1900 may include a processing unit 1910, a volatile memory unit 1920, a resistive memory unit 1930, and a mass storage unit 1940. System 1900 may be a general-purpose or special-purpose computer system (such as a mobile device, a personal computer (PC), a server computer, a programmable home appliance, and / or a mainframe computer).

[0149] Combined with Fig.19 The functional "units" described in some example embodiments of the present invention may be classified as modules for independent implementation. For example, a module may be implemented as a custom very large scale integration (VLSI) circuit or a hardware circuit including off-the-shelf semiconductors (such as gate arrays, logic chips, transistors and / or other discrete components). A module may be implemented as a programmable hardware device (e.g., a programmable gate array, programmable gate logic, and a programmable gate device). In addition, a module may be implemented as such a hardware circuit or hardware device in combination with software including, for example, executable code, objects, programs, and / or functions. It will also be understood by those of ordinary skill in the art that, according to some example embodiments, each functional unit or module of system 1900 may be implemented by a separate hardware circuit or hardware device, and according to some other example embodiments, multiple functional units or modules of system 1900 may be implemented by a single hardware circuit or hardware device combination.

[0150] The processing unit 1910 may execute an operating system and a plurality of software programs and perform specific calculations and / or tasks. For example, the processing unit 1910 may be a microprocessor (MP) or a central processing unit (CPU).

[0151] The volatile memory unit 1920 may refer to a medium configured to store data for a short period of time or temporarily as an operation memory or a cache memory of the system 1900. The volatile memory unit 1920 may include at least one memory device, for example, a DRAM.

[0152] The resistive memory cell 1930 may be used as a cache for the large-capacity storage unit 1940. Frequently accessed data and / or some data of an application and / or an operating system may be stored in the resistive memory cell 1930. The resistive memory cell 1930 may include at least one memory device (e.g., PRAM). Since the resistive memory cell 1930 accesses data at a higher speed than when the large-capacity storage unit 1940 (e.g., a hard disk drive (HDD)) accesses data, the resistive memory cell 1930 may be used as a cache. The resistive memory cell 1930 may refer to Figures 1 to 17 Some example embodiments shown in are implemented.

[0153] The resistive memory cell 1930 may include: a memory cell array including memory cells; a write circuit configured to program the memory cells to a target resistance state; and a control circuit configured to control a write pulse and a post-write pulse following the write pulse to be applied to the memory cells. The memory cells may be programmed to the target resistance state in response to the write pulse, and the resistance of the memory cells in the target resistance state may increase in response to the post-write pulse.

[0154] The mass storage unit 1940 may be implemented as a hard disk drive (HDD), a solid state drive (SSD), a peripheral component interconnect express (PCI-e) memory module, or a non-volatile memory express (NVMe). Optionally, at least one layer of the mass storage unit 1940 may be implemented as at least one network accessible device and / or service (e.g., multiple clients, multiple servers, server farms, server clusters, application servers, and / or message servers connected to NVMe-over Fabric (NVMe-oF) and / or remote direct memory access (RDMA). The mass storage unit 1940 may refer to a storage medium in which the system 1900 intends to store user data for a long time. The mass storage unit 1940 may store applications, program data, etc.

[0155] As described above, the various components (e.g., write / read circuits and / or control circuits) of the memory controller (e.g., processing unit) and / or memory device can be implemented as hardware or a combination of hardware and software. When the hardware device is a computer processing device (e.g., one or more processors, CPUs, controllers, ALUs, DSPs, microcomputers, microprocessors, etc.), the computer processing device can be configured to execute the program code by performing arithmetic, logic, and input / output operations according to the program code. Once the program code is loaded into the computer processing device, the computer processing device can be programmed to execute the program code, thereby converting the computer processing device into a dedicated computer processing device. In a more specific example, when the program code is loaded into the processor, the processor is programmed to execute the program code and its corresponding operations, thereby converting the processor into a dedicated processor. In another example, the hardware device can be an integrated circuit (e.g., ASIC) customized as a dedicated processing circuit.

[0156] A hardware device (such as a computer processing device) may run an operating system (OS) and one or more software applications running on the OS. The computer processing device may also access, store, manipulate, process, and create data in response to the execution of the software. For simplicity, some example embodiments may be illustrated as a computer processing device; however, those skilled in the art will appreciate that the hardware device may include multiple processing elements and multiple types of processing elements. For example, the hardware device may include multiple processors or a processor and a controller. In addition, other processing configurations (such as parallel processors) are feasible.

[0157] The software and / or data may be permanently or temporarily implemented in any type of storage medium, including but not limited to any machine, component, physical or virtual device, or computer storage medium or device capable of providing instructions or data to a hardware device or providing instructions or data interpreted by a hardware device. The software may also be distributed on networked computer systems so that the software is stored and executed in a distributed manner. Specifically, for example, the software and data may be stored by one or more computer-readable recording media (including tangible or non-transitory computer-readable storage media as discussed herein).

[0158] According to some example embodiments, the storage medium may also include one or more storage devices located at the unit and / or device. One or more storage devices may be tangible or non-transitory computer-readable storage media (such as random access memory (RAM), read-only memory (ROM), permanent mass storage device (such as disk drive) and / or any other similar data storage mechanism capable of storing and recording data). One or more storage devices may be configured to store computer programs, program codes, instructions, or some combinations thereof for one or more operating systems and / or for implementing some example embodiments described herein. Computer programs, program codes, instructions, or some combinations thereof may also be loaded from a separate computer-readable storage medium to one or more storage devices and / or one or more computer processing devices using a drive mechanism. Such a separate computer-readable storage medium may include a universal serial bus (USB) flash drive, a memory stick, a Blu-ray / DVD / CD-ROM drive, a memory card, and / or other similar computer-readable storage media. Computer programs, program codes, instructions, or some combinations thereof may be loaded from a remote data storage device to one or more storage devices and / or one or more computer processing devices via a network interface rather than via a computer-readable storage medium. In addition, the computer program, program code, instruction, or some combination thereof may be loaded from a remote computing system to one or more storage devices and / or one or more processors via a network, wherein the remote computing system is configured to transmit and / or distribute the computer program, program code, instruction, or some combination thereof. The remote computing system may transmit and / or distribute the computer program, program code, instruction, or some combination thereof via a wired interface, an air interface, and / or any other similar medium. Although the present invention has been specifically shown and described with reference to some example embodiments of the present invention, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method of operating a resistive memory device comprising a memory cell, the method comprising: applying a write pulse to the memory cell so that the memory cell is changed to a target resistance state; as well as applying a post-write pulse to the memory cell to increase the resistance of the memory cell in the target resistance state, wherein the post-write pulse is a single pulse having at least n step voltage levels, n being an integer equal to or greater than 2, each of the at least n step voltage levels having a time period less than the write pulse, wherein the step of applying a write pulse to the memory cell and the step of applying a post-write pulse to the memory cell are performed based on a write control signal and input data to be written into the memory cell through a latch circuit, The at least n step voltage levels have different time periods.

2. The method according to claim 1, wherein: The target resistance state is the 2 m A resistance state having a relatively high resistance level among resistance states, where m is an integer greater than 0.

3. The method according to claim 2, wherein: The step of applying a post-write pulse to the memory cell includes increasing each of the at least n step voltage levels of the post-write pulse by a specific amplitude.

4. The method according to claim 3, wherein: A first step voltage level of the at least n step voltage levels of the post-write pulse is set to be lower than a minimum threshold voltage level of a target resistance state due to the write pulse.

5. The method according to claim 3, wherein: An nth step voltage level of the at least n step voltage levels of the post-write pulse is set to be lower than a minimum threshold voltage level of a target resistance state changed by an (n-1)th step voltage level of the post-write pulse.

6. The method according to claim 3, wherein: The increasing amplitudes of the at least n step voltage levels are set to be equal to each other.

7. The method according to claim 3, wherein: The increasing amplitudes of the at least n step voltage levels are set to be different from each other.

8. The method according to claim 7, wherein: The increasing amplitudes of the at least n step voltage levels are set to increase gradually.

9. The method according to claim 7, wherein: The increasing amplitudes of the at least n step voltage levels are set to gradually decrease.

10. The method according to claim 1, wherein: The memory unit includes: a first electrode and a second electrode, spaced apart from each other; a selection element between the first electrode and the second electrode and closer to the second electrode than to the first electrode, wherein the selection element comprises a chalcogenide switching material; and The variable resistance element, between the first electrode and the selection element, includes a phase change material.

11. A method of operating a resistive memory device comprising a memory cell, the method comprising: applying a write pulse to the memory cell so that the memory cell is changed to a target resistance state; as well as applying at least n post-write pulses to the memory cell to increase the resistance of the memory cell in the target resistance state, wherein n is an integer equal to or greater than 2, each of the at least n post-write pulses having a time period shorter than the write pulse, wherein the step of applying a write pulse to the memory cell and the step of applying the at least n post-write pulses to the memory cell are performed based on a write control signal and input data to be written into the memory cell through a latch circuit, The at least n post-write pulses have different time periods.

12. The method according to claim 11, wherein: The target resistance state is the 2 m A resistance state having a relatively high resistance level among resistance states, where m is an integer greater than 0.

13. The method according to claim 12, wherein: The step of applying the at least n post-write pulses to the memory cell includes increasing a voltage level of each of the at least n post-write pulses by a specific magnitude.

14. The method according to claim 13, wherein: A voltage level of a first post-write pulse of the at least n post-write pulses is set to be lower than a minimum threshold voltage level of a target resistance state due to the write pulse.

15. The method according to claim 14, wherein: A voltage level of an nth post-write pulse of the at least n post-write pulses is set lower than a minimum threshold voltage level of a target resistance state changed by a voltage level of an (n-1)th post-write pulse.

16. The method according to claim 13, wherein: The voltage levels of the at least n post-write pulses increase with the same amplitude.

17. The method according to claim 13, wherein: The voltage levels of the at least n post-write pulses increase at different amplitudes.

18. The method according to claim 17, wherein: The voltage levels of the at least n post-write pulses increase with gradually increasing amplitudes.

19. The method according to claim 17, wherein: The voltage levels of the at least n post-write pulses increase in a gradually decreasing amplitude.

20. The method according to claim 11, wherein: The memory unit includes: a first electrode and a second electrode, spaced apart from each other; a selection element between the first electrode and the second electrode and closer to the second electrode than to the first electrode, wherein the selection element comprises a chalcogenide switching material; and The variable resistance element is between the first electrode and the selection element, wherein the variable resistance element includes a phase change material.

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