Semiconductor packaging device and manufacturing method thereof

Abstract

This invention provides a semiconductor packaging apparatus and a method for manufacturing the same. The semiconductor packaging apparatus includes a transparent carrier, a first patterned conductive layer, a second patterned conductive layer, and a first insulating layer. The transparent carrier has a first surface, a second surface opposite to the first surface, and a third surface extending between the first and second surfaces. The first patterned conductive layer is disposed on the first surface of the transparent carrier. The first patterned conductive layer has a first surface coplanar with the third surface of the transparent carrier. The second patterned conductive layer is disposed on the first surface of the transparent carrier and is electrically isolated from the first patterned conductive layer. The first insulating layer is disposed on the transparent carrier and covers the first patterned conductive layer.

Description

Technical Field

[0001] This application generally relates to a semiconductor packaging device, and more particularly to a semiconductor packaging device comprising a transparent carrier. Background Technology

[0002] Monomerization operations (which may include grinding, optical (e.g., laser cutting), mechanical (e.g., scraper / blade cutting), and chemical (e.g., etching)) can be performed on wafers or panels to manufacture semiconductor packages. Controlling the monomerization operations to avoid damage to the wafer or panel or semiconductor package (e.g., cracking, peeling, or other problems) can be challenging. It can also be challenging to use optical techniques to manufacture semiconductor packages with transparent materials. Summary of the Invention

[0003] In one aspect, according to some embodiments, a semiconductor packaging device includes a transparent carrier, a first patterned conductive layer, a second patterned conductive layer, and a first insulating layer. The transparent carrier has a first surface, a second surface opposite to the first surface, and a third surface extending between the first and second surfaces. The first patterned conductive layer is disposed on the first surface of the transparent carrier. The first patterned conductive layer has a first surface coplanar with the third surface of the transparent carrier. The second patterned conductive layer is disposed on the first surface of the transparent carrier and is electrically isolated from the first patterned conductive layer. The first insulating layer is disposed on the transparent carrier and covers the first patterned conductive layer.

[0004] In another embodiment, according to some embodiments, a semiconductor packaging device includes a transparent carrier, a first patterned conductive layer, and a first transparent insulating layer. The transparent carrier has a first surface, a second surface opposite to the first surface, and a third surface extending between the first and second surfaces. The first patterned conductive layer is disposed on the first surface of the transparent carrier. The first patterned conductive layer has a first surface coplanar with the third surface of the transparent carrier. The first transparent insulating layer is disposed on the transparent carrier and covers the first patterned conductive layer.

[0005] In another aspect, according to some embodiments, a method of manufacturing a semiconductor packaging device includes: forming a patterned conductive layer on a cleavage path of a transparent carrier; forming trenches through the patterned conductive layer and into the transparent carrier by a cleaving operation along the cleavage path; grinding the transparent carrier at a second surface opposite to the patterned conductive layer to form a plurality of monomerized transparent carrier units; attaching the plurality of monomerized transparent carrier units to an adhesive layer; and monomerizing the adhesive layer by a laser operation. The alignment of the laser operation is based on the patterned conductive layer. Attached Figure Description

[0006] Aspects of this application will be readily understood from the following detailed description, which is read in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale, and that the dimensions of the features depicted in the drawings may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A A cross-sectional view illustrating a semiconductor packaging device according to some embodiments of this application.

[0008] Figure 1B A cross-sectional view illustrating a semiconductor packaging device according to some embodiments of this application.

[0009] Figure 2A A cross-sectional view illustrating a semiconductor packaging device according to some embodiments of this application.

[0010] Figure 2B A cross-sectional view illustrating a semiconductor packaging device according to some embodiments of this application.

[0011] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I and Figure 3J This application illustrates operations for manufacturing a semiconductor packaging apparatus according to some embodiments.

[0012] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I and Figure 4J This application illustrates operations for manufacturing a semiconductor packaging apparatus according to some embodiments.

[0013] Common reference numerals are used throughout the drawings and embodiments to indicate the same or similar elements. Detailed Implementation

[0014] When optical techniques (e.g., laser techniques) are used to monolithize semiconductor package structures with transparent materials (e.g., transparent carriers and / or transparent insulating layers), alignment for the optical techniques may fail because the transparent materials may not properly detect or identify the cut lines of the semiconductor package structure.

[0015] In some embodiments of this application, an opaque material / layer is disposed on the dicing ridges of a glass carrier / panel / plate during the manufacture of the semiconductor package device, and a portion of such an opaque material / layer remains near (or close to / adjacent to) the sidewalls / edges of the semiconductor package device after the monomerization / dicing / cutting / separation operation. When optical monomerization techniques are applied, the opaque material / layer can improve alignment.

[0016] Figure 1A The illustration shows a cross-sectional view of a semiconductor packaging device 1a according to some embodiments of this application. The semiconductor packaging device 1a includes a transparent carrier 10, patterned conductive layers 20, 50, 51 and 60, insulating layers 30, 40 and 61, a metal layer 62 and an adhesive material 70.

[0017] The transparent carrier 10 has a surface 101. The transparent carrier 10 has a surface 102 opposite to the surface 101. The transparent carrier 10 has a surface 10s (e.g., a side or lateral surface) extending between the surface 101 and the surface 102. The transparent carrier 10 may comprise glass or other transparent materials. The transparent carrier 10 may serve as a substrate for a semiconductor package device 1a. The transparent carrier 10 may reduce electrical leakage or insertion loss in the semiconductor package device 1a.

[0018] A patterned conductive layer 60 is disposed on the surface 101 of the transparent carrier 10. The patterned conductive layer 60 is electrically isolated from the patterned conductive layer 20. In some embodiments of this application, the patterned conductive layer 60 may be part of an integrated passive device (IPD). In some embodiments of this application, the patterned conductive layer 60 may be part of a metal-insulator-metal (MIM) structure. For example, in... Figure 1A In the embodiments shown, the insulating layer 61, the metal layer 62, and the patterned conductive layer 60 can form an IPD or MIM structure. The patterned conductive layer 60 may contain gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof.

[0019] An insulating layer 30 is disposed on the transparent carrier 10. The insulating layer 30 is disposed on at least a portion of the patterned conductive layer 60. The insulating layer 30 covers at least a portion of the patterned conductive layer 60. The insulating layer 30 may contain a transparent material. The insulating layer 30 may be transparent. The insulating layer 30 may contain a passivation material. The insulating layer 30 may contain a dielectric material.

[0020] A patterned conductive layer 51 is disposed on the insulating layer 30. The patterned conductive layer 51 is electrically connected to the metal layer 62. The patterned conductive layer 51 may be a redistributable layer (RDL). The patterned conductive layer 51 may contain gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof. A patterned conductive layer 50 is disposed on the patterned conductive layer 51. The patterned conductive layer 50 is electrically isolated from the patterned conductive layer 20. The patterned conductive layers 50 and 51 may form an under-bump metallization (UBM) structure. The patterned conductive layer 50 may contain gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof.

[0021] A patterned conductive layer 20 is disposed on the surface 101 of the transparent carrier 10. The patterned conductive layer 20 has a surface 20s coplanar with the surface 10s of the transparent carrier 10. The patterned conductive layer 20 is disposed on the insulating layer 30. The sidewalls 30s of the insulating layer 30 are covered by the patterned conductive layer 20. The patterned conductive layer 20 may have a “Z” shape (e.g., it may include two horizontally extending portions offset from each other (e.g., not vertically projected onto each other) and connected by a third vertical portion). The patterned conductive layer 20 may contain an opaque material. The patterned conductive layer 20 may be opaque. The patterned conductive layer 20 may contain the same material as the patterned conductive layer 50. The patterned conductive layer 20 and the patterned conductive layer 50 may be formed simultaneously or integrally. In some embodiments of this application, the patterned conductive layer 20 is electrically isolated from other conductive elements / layers within the semiconductor package device 1a (e.g., from all other conductive elements / layers explicitly described herein).

[0022] An insulating layer 40 is disposed on an insulating layer 30. An insulating layer 40 is disposed on a patterned conductive layer 50. An insulating layer 40 is disposed on a patterned conductive layer 20. An insulating layer 40 covers at least a portion of the patterned conductive layer 20. The sidewalls 40s of the insulating layer 40 are not coplanar with the surface 20s of the patterned conductive layer 20. The patterned conductive layer 20 has a surface 201 connected to the surface 20s (e.g., substantially perpendicular to and connected to the surface 20s). The surface 201 of the patterned conductive layer 20 is exposed from the insulating layer 40. An insulating layer 40 covers the patterned conductive layer 51. An insulating layer 40 covers at least a portion of the patterned conductive layer 50. The surface 501 of the patterned conductive layer 50 is exposed from the insulating layer 40. The insulating layer 40 may contain a transparent material. The insulating layer 40 may be transparent. The insulating layer 40 may contain a passivation material. The insulating layer 40 may contain a dielectric material.

[0023] Adhesive material 70 is disposed on surface 102 of transparent carrier 10. Adhesive material 70 may comprise a transparent material. Adhesive material 70 may comprise a die attachment film (DAF). Adhesive material 70 can be used to attach semiconductor package device 1a to another device or circuit board.

[0024] Figure 1B A cross-sectional view of a semiconductor packaging device 1b according to some embodiments of this application is shown. The semiconductor packaging device 1b is similar to the semiconductor packaging device 1a, but has at least the following differences.

[0025] The surface 40s of the insulating layer 40 is coplanar with the surface 20s of the patterned conductive layer 20 and the surface 10s of the transparent carrier 10. The exposed surface 201 of the patterned conductive layer 20 in the semiconductor packaging device 1a is covered by the insulating layer 40 in the semiconductor packaging device 1b.

[0026] Figure 2A A cross-sectional view of a semiconductor packaging device 2a according to some embodiments of this application is shown. The semiconductor packaging device 2a is similar to the semiconductor packaging device 1a, but has at least the following differences.

[0027] An insulating layer 30 is disposed on the patterned conductive layer 20. The insulating layer 30 covers a portion of the patterned conductive layer 20. The sidewalls 30s of the insulating layer 30 are covered by an insulating layer 40. The patterned conductive layer 20 and the patterned conductive layer 60 are coplanar. The patterned conductive layer 20 and the patterned conductive layer 60 may contain the same material. The patterned conductive layer 20 and the patterned conductive layer 60 may be formed simultaneously or integrally.

[0028] Figure 2B A cross-sectional view of a semiconductor packaging device 2b according to some embodiments of this application is shown. The semiconductor packaging device 2b is similar to the semiconductor packaging device 2a, but has at least the following differences.

[0029] The surface 40s of the insulating layer 40 is coplanar with the surface 20s of the patterned conductive layer 20 and the surface 10s of the transparent carrier 10. The exposed surface 201 of the patterned conductive layer 20 in the semiconductor packaging device 2a is covered by the insulating layer 40 in the semiconductor packaging device 2b.

[0030] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I and Figure 3J The operation of a semiconductor packaging apparatus 3j according to some embodiments of this application is illustrated.

[0031] refer to Figure 3AA patterned conductive layer 60 is formed on a transparent carrier 10a. An insulating layer 61 is formed on the patterned conductive layer 60. A metal layer 62 is formed on the insulating layer 61. The patterned conductive layer 60, the insulating layer 61, and the metal layer 62 can form an IPD or MIM structure. The patterned conductive layer 60 can be an electrode of an electronic component. The patterned conductive layer 60 can be formed by, for example, but not limited to, plating operations.

[0032] refer to Figure 3B An insulating layer 30 is formed on a transparent carrier 10a. The insulating layer 30 is formed on a patterned conductive layer 60. The insulating layer 30 can be formed by, for example, but not limited to, coating, printing, or screening operations. An opening O1 is formed in the insulating layer 30 to expose the metal layer 62. A void S1 is formed in the insulating layer 30 to expose the transparent carrier 10a. The portion of the transparent carrier 10a exposed to the void S1 includes a cleavage for monomerization. The opening O1 and the void S1 can be formed by, for example, but not limited to, etching and / or photolithography operations.

[0033] refer to Figure 3C A patterned conductive layer 51 is formed on the insulating layer 30. The patterned conductive layer 51 can be formed by, for example, but not limited to, plating operations. The patterned conductive layer 51 may include an RDL structure.

[0034] refer to Figure 3D A patterned conductive layer 50 is formed on a patterned conductive layer 51. The patterned conductive layer 50 can be formed by, for example, but not limited to, plating operations. Patterned conductive layers 50 and 51 can form a UBM structure. A patterned conductive layer 20 is formed on an insulating layer 30. The patterned conductive layer 20 is formed on a transparent carrier 10a. The patterned conductive layer 20 is formed on a cutout in the transparent carrier 10a. Patterned conductive layers 20 and 51 can be formed simultaneously or integrally. Patterned conductive layers 20 and 51 can be formed by the same operation. Patterned conductive layer 20 can be electrically isolated from patterned conductive layers 60, 51, and 52.

[0035] refer to Figure 3E An insulating layer 40 is formed on the insulating layer 30. The insulating layer 40 covers the patterned conductive layer 20 and the patterned conductive layer 50. An etching operation is performed to expose the surface 501 of the patterned conductive layer 50 from the insulating layer 40. An etching operation is also performed to expose the surface 201 of the patterned conductive layer 20 from the insulating layer 40.

[0036] Figure 3F , Figure 3G and Figure 3H The operations shown can constitute a pre-grinding cutting (DBG) operation. (Reference) Figure 3FA cutting or semi-cutting operation is performed along the cutting path of the transparent carrier 10a to form a groove 80 that passes through the patterned conductive layer 20 and enters the transparent carrier 10a.

[0037] refer to Figure 3G Attach the protective tape P1 to Figure 3F The structure. Protective tape P1 can be attached via a lamination process.

[0038] refer to Figure 3H A grinding operation is performed to remove a portion of the transparent carrier 10a. Multiple monomerized transparent carriers 10 are formed.

[0039] refer to Figure 3I Multiple monomerized transparent carriers 10 are attached to the adhesive layer 70a. The protective tape P1 is then removed. The adhesive layer 70a may contain a grain attachment film (DAF).

[0040] refer to Figure 3J The adhesive layer 70a is monomerized into multiple adhesive layers 70. The monomerization operation can be performed by optical operations (such as laser operations). The patterned conductive layer 20 can act as alignment marks for the monomerization operation. Alignment for laser operations can be based on the patterned conductive layer 20. A semiconductor package device 3j is formed. The semiconductor package device 3j can be similar to... Figure 1A The semiconductor packaging device 1a in the example is the same as it. If Figure 3F If the cutting operation is performed using a wide blade, then... Figure 3J The semiconductor packaging device 3j in the middle can be similar to Figure 1B The semiconductor packaging device 1b in the example is the same as that in the example.

[0041] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I and Figure 4J The operation of a semiconductor packaging device 4j according to some embodiments of this application is illustrated.

[0042] refer to Figure 4A , Figure 4A The operation shown is similar to Figure 3A The operation shown involves the patterned conductive layer 20 being formed separately on the transparent carrier 10a. The patterned conductive layer 20 is formed on the cut lines of the transparent carrier 10a. The patterned conductive layer 20 and the patterned conductive layer 60 can be formed simultaneously or as a single unit. The patterned conductive layer 20 and the patterned conductive layer 60 can be formed through the same operation.

[0043] refer to Figure 4B , Figure 4B The operation shown is similar to Figure 3B The operation shown in the figure involves an insulating layer 30 being formed on the patterned conductive layer 20, and a void S1 being formed in the insulating layer 30 to expose the outside of the patterned conductive layer 20.

[0044] refer to Figure 4C , Figure 4C The operation shown in the text and Figure 3C The operation is the same as shown in the diagram. A patterned conductive layer 51 is formed on the insulating layer 30.

[0045] refer to Figure 4D A patterned conductive layer 50 is formed on a patterned conductive layer 51. The patterned conductive layer 50 can be formed by, for example, but not limited to, plating operations. The patterned conductive layers 50 and 51 can form a UBM structure. The patterned conductive layers 60, 51 and 50 can be electrically isolated from the patterned conductive layer 20.

[0046] refer to Figure 4E An insulating layer 40 is formed on the insulating layer 30. The insulating layer 40 covers the patterned conductive layer 20 and the patterned conductive layer 50. An etching operation is performed to expose the surface 501 of the patterned conductive layer 50 from the insulating layer 40. An etching operation is also performed to expose the surface 201 of the patterned conductive layer 20 from the insulating layer 40.

[0047] Figure 4F , Figure 4G and Figure 4H The operation shown can be referred to as pre-grinding cutting (DBG) operation. (See reference) Figure 4F A cutting or semi-cutting operation is performed along the cutting path of the transparent carrier 10a to form a groove 80 that passes through the patterned conductive layer 20 and enters the transparent carrier 10a.

[0048] refer to Figure 4G Attach the protective tape P1 to Figure 4F The structure. Protective tape P1 can be attached via a lamination process.

[0049] refer to Figure 4H A grinding operation is performed to remove a portion of the transparent carrier 10a. Multiple monomerized transparent carriers 10 are formed.

[0050] refer to Figure 4I Multiple monomerized transparent carriers 10 are attached to the adhesive layer 70a. The protective tape P1 is then removed. The adhesive layer 70a may contain a grain attachment film (DAF).

[0051] refer to Figure 4JThe adhesive layer 70a is monomerized into multiple adhesive layers 70. The monomerization operation can be performed by optical operations (such as laser operations). The patterned conductive layer 20 can act as alignment marks for the monomerization operation. Alignment for laser operations can be based on the patterned conductive layer 20. A semiconductor package device 4j is formed. The semiconductor package device 4j can be similar to... Figure 2A The semiconductor packaging device 2a in the example is the same as that in the example. It should be noted that if... Figure 4F If the cutting operation is performed using a wide blade, then... Figure 4J The semiconductor packaging device 4j in the middle can be similar to Figure 2B The semiconductor packaging device 2b in the example is the same as that in the example.

[0052] As used herein, the term "transparent" can mean a material having a transmittance of about 50% or more, about 70% or more, or about 90% or more to the light exposed to the material. The term "opaque" can mean a material having a transmittance of less than about 50%, less than about 30%, or less than about 10% to the light exposed to the material.

[0053] As used herein, the terms “approximately,” “substantially,” “roughly,” and “about” are used to describe and account for small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation clearly occurred and examples in which the event or situation is very close to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two values ​​can be considered "substantially" or "approximately" the same. For example, "substantially" vertical can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0054] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, the two surfaces can be considered coplanar or substantially coplanar. If the difference between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, the surface can be considered flat or substantially flat.

[0055] Unless the context clearly specifies otherwise, the singular terms “a / an” and “described” as used herein may include multiple indicators. In the description of some embodiments, a component positioned “on” or “above” another component may cover situations where the preceding component is directly on the following component (e.g., in physical contact with the following component) and situations where one or more intervening components are located between the preceding and following components.

[0056] Although this application has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of this application. Those skilled in the art will readily understand that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of this application as defined by the appended claims. Illustrations may not be drawn to scale. Due to variations in the class of manufacturing processes, there may be differences between the process reproduction in this application and actual equipment. Other embodiments of this application may exist that are not specifically described. This specification and accompanying drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition of substances, methods, or processes to the objectives, spirit, and scope of this application. All such modifications are intended within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it will be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this application.

Claims

1. A semiconductor package device comprising: a transparent carrier having a first surface, a second surface opposite the first surface, and a third surface extending between the first surface and the second surface; a first patterned conductive layer disposed on the first surface of the transparent carrier, the first patterned conductive layer having a first surface coplanar with the third surface of the transparent carrier; a second patterned conductive layer disposed on the first surface of the transparent carrier and electrically isolated from the first patterned conductive layer; and a first transparent insulating layer disposed on the transparent carrier and covering the first patterned conductive layer; and an adhesive material disposed on the second surface of the transparent carrier, the adhesive material comprising a transparent material.

2. The semiconductor package device of claim 1, wherein the first patterned conductive layer is configured to serve as an alignment mark defining a lateral surface of the adhesive material.

3. The semiconductor package device of claim 2, wherein the lateral surface of the adhesive material is aligned with the third surface of the transparent carrier and the lateral surface of the adhesive material is aligned with the first surface of the first patterned conductive layer.

4. The semiconductor package device of claim 1, further comprising a second transparent insulating layer disposed between the transparent carrier and the first transparent insulating layer and having vertical lateral surfaces, wherein the vertical lateral surfaces of the second transparent insulating layer contact vertical lateral surfaces of the first patterned conductive layer.

5. The semiconductor package device of claim 4, wherein a first portion of a top surface of the second transparent insulating layer is covered by the first transparent insulating layer and a second portion of the top surface of the second transparent insulating layer is covered by the first patterned conductive layer.

6. The semiconductor package device of claim 4, further comprising a third patterned conductive layer disposed between the transparent carrier and the second transparent insulating layer, wherein the semiconductor package device further comprises an integrated passive device, wherein the third patterned conductive layer is part of the integrated passive device.

7. The semiconductor package device of claim 4, wherein the second patterned conductive layer is disposed on the second transparent insulating layer and is partially covered by the first transparent insulating layer, and a portion of a top surface of the second patterned conductive layer is exposed from the first transparent insulating layer.

8. The semiconductor package device of claim 1, wherein the first patterned conductive layer comprises an upper portion, a middle portion, and a lower portion, wherein a vertical lateral surface of the middle portion of the first patterned conductive layer contacts a vertical lateral surface of the first transparent insulating layer, and a portion of a top surface of the lower portion of the first patterned conductive layer is exposed from the first transparent insulating layer.

9. A semiconductor package device comprising: a transparent carrier having a first surface, a second surface opposite the first surface, and a third surface extending between the first surface and the second surface; ​ ​ a first patterned conductive layer disposed on the first surface of the transparent carrier, the first patterned conductive layer having a first surface coplanar with the third surface of the transparent carrier; a first transparent insulating layer disposed on the transparent carrier and covering the first patterned conductive layer; a second patterned conductive layer disposed on the first surface of the transparent carrier and electrically isolated from the first patterned conductive layer by the first transparent insulating layer; and a transparent adhesive material disposed on the second surface of the transparent carrier, wherein a portion of a top surface of the transparent adhesive material is exposed from the transparent carrier.

10. The semiconductor package device of claim 9, wherein the first patterned conductive layer is configured to serve as an alignment mark that defines a lateral surface of the transparent adhesive material.

11. The semiconductor package device of claim 10, wherein the lateral surface of the transparent adhesive material is aligned with the third surface of the transparent carrier and the lateral surface of the transparent adhesive material is aligned with the first surface of the first patterned conductive layer.

12. The semiconductor package device of claim 9, further comprising a second transparent insulating layer disposed between the transparent carrier and the first transparent insulating layer and having vertical lateral surfaces, wherein the vertical lateral surfaces of the second transparent insulating layer contact vertical lateral surfaces of the first patterned conductive layer.

13. The semiconductor package device of claim 9, wherein the first patterned conductive layer comprises an upper portion, a middle portion, and a lower portion, wherein a vertical lateral surface of a middle portion of the first patterned conductive layer contacts a vertical lateral surface of the first transparent insulating layer and a portion of a top surface of a lower portion of the first patterned conductive layer is exposed from the first transparent insulating layer.

14. A semiconductor package device, comprising: a transparent carrier having a first surface, a second surface opposite the first surface, and a third surface extending between the first surface and the second surface; a first patterned conductive layer disposed on the first surface of the transparent carrier, the first patterned conductive layer having a first surface coplanar with the third surface of the transparent carrier; a second patterned conductive layer disposed on the first surface of the transparent carrier and electrically isolated from the first patterned conductive layer; a first transparent insulating layer disposed on the transparent carrier and covering the first patterned conductive layer; and a transparent adhesive material disposed on the second surface of the transparent carrier, wherein the transparent adhesive material is configured to attach the semiconductor package device to another device.

15. The semiconductor package device of claim 14, wherein the other device is a circuit board. ​ ​

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