Vertical storage device

Abstract

A vertical memory device includes a substrate having a cell array region and a step region. Gate electrodes are spaced apart from each other in a first direction and a third direction. A channel extends through the gate electrode in the cell array region along the first direction. Each gate electrode extends along a second direction. Ends of one or more gate electrodes in the second direction form a first step structure on the step region of the substrate. The first step structure includes a first step, a second step, and a third step sequentially arranged in the third direction. Each first step has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0121516 filed on October 12, 2018 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to memory, and more particularly, to vertical memory devices. Background Art

[0004] When manufacturing a VNAND flash memory device, sacrificial layers and insulating layers are alternately and repeatedly stacked. Some sacrificial layers are patterned to form steps in a step region where a contact plug connected to an upper wiring is formed, and an etching process may be performed using a photoresist pattern that partially covers the steps to form a mold having a step structure. As the number of steps included in the mold increases, the area of ​​the mold may increase, so that the integration of the VNAND flash memory device may decrease. Summary of the invention

[0005] A vertical memory device includes a substrate having a cell array region and a step region at least partially surrounding the cell array region. A plurality of gate electrodes are spaced apart from each other in each of a first direction and a third direction in the cell array region and the step region of the substrate. Each of the plurality of gate electrodes extends along a second direction. The first direction is substantially perpendicular to an upper surface of the substrate. The third direction is substantially parallel to an upper surface of the substrate. The second direction is substantially parallel to an upper surface of the substrate and intersects the third direction. A channel extends along a first direction in the cell array region of the substrate. The channel extends through at least one of the plurality of gate electrodes. Ends of the plurality of gate electrodes in the second direction form a first step structure on the step region of the substrate. The first step structure includes a plurality of first steps, a second step, and a third step sequentially arranged in the third direction. Each of the plurality of first steps has a first length in the third direction. The second step has a second length greater than the first length in the third direction. The third step has a third length greater than the second length in the third direction.

[0006] A vertical memory device includes a substrate having a cell array region and a stepped region at least partially surrounding the cell array region. A plurality of gate electrodes are spaced apart from each other in each of a first direction and a third direction in the cell array region and the stepped region of the substrate. Each of the plurality of gate electrodes extends along a second direction. The first direction is substantially perpendicular to an upper surface of the substrate. The third direction is substantially parallel to an upper surface of the substrate. The second direction is substantially parallel to an upper surface of the substrate and intersects the third direction. A channel extends along a first direction in the cell array region of the substrate. The channel extends through at least one of the plurality of gate electrodes. Ends of the plurality of gate electrodes in the second direction form a first stepped structure and a second stepped structure on the stepped region of the substrate. Each of the first stepped structure and the second stepped structure has a step. The first stepped structure and the second stepped structure are symmetrical to each other in the third direction. A mold is disposed between the first stepped structure and the second stepped structure. The mold contacts the sidewalls of the first stepped structure and the second stepped structure and includes an insulating material.

[0007] A vertical memory device includes a substrate having a cell array region and a step region at least partially surrounding the cell array region. A plurality of gate electrodes are spaced apart from each other in each of a first direction and a third direction in the cell array region and the step region of the substrate. Each of the plurality of gate electrodes extends along a second direction. The first direction is substantially perpendicular to an upper surface of the substrate. The third direction is substantially parallel to an upper surface of the substrate. The second direction is substantially parallel to an upper surface of the substrate and intersects with the third direction. A channel extends along a first direction in the cell array region of the substrate. The channel extends through at least one of the plurality of gate electrodes. Ends of the plurality of gate electrodes in the second direction form a step structure on the step region of the substrate. The step structure includes first to sixth step layers stacked sequentially in the first direction. The length of the first to sixth step layers in the third direction gradually decreases from the lowest one toward the highest one. Each of the first and second step layers includes ends of four gate electrodes arranged in the third direction among the plurality of gate electrodes. Each of the third and fourth step layers includes ends of three gate electrodes arranged in the third direction among the plurality of gate electrodes. The fifth step layer includes ends of two gate electrodes arranged in the third direction among the plurality of gate electrodes. The sixth stepped layer includes an end portion of one of the plurality of gate electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure and its many attendant aspects will be better understood and thereby more fully appreciated by reference to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figures 1 to 42 are a plan view, a cross-sectional view, and a perspective view illustrating a method of manufacturing a vertical memory device according to an exemplary embodiment of the inventive concept;

[0010] Fig.43 and Fig.44is a cross-sectional view illustrating a vertical memory device according to an exemplary embodiment of the inventive concept; and

[0011] Fig.45 is along Fig.39 FIG. 1 is a cross-sectional view taken along line EE′ of FIG. 1 , illustrating a vertical memory device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0012] The above and other aspects and features of a vertical memory device and a method of manufacturing the same according to exemplary embodiments of the inventive concept will be easily understood by the following detailed description with reference to the accompanying drawings.

[0013] Figures 1 to 42 are a plan view, a cross-sectional view, and a perspective view illustrating a method of manufacturing a vertical memory device according to an exemplary embodiment of the inventive concept. Figure 1 , Fig.13 , Fig. 20 , Fig.24 , Fig.29 , Fig.31 , Fig.33 , Figure 36 to Figure 37 and Fig.39 It is a floor plan. Figure 2 , Figure 4 , Figure 6 , Figure 21 to Figure 23 , Figures 25 to 28 , Fig.30 , Fig.32 , Figure 34 to Figure 35 , Fig.38 and Figure 40 to Figure 42 is a cross-sectional view, and Figure 3 , Figure 5 , Figures 7 to 12 and Figures 14 to 19 It is a perspective view.

[0014] Fig.13 , Fig. 20 , Fig.24 and Fig.36 It is shown Figure 1 The floor plan of Area X, Fig.29 , Fig.31 , Fig.33 , Fig.37 and Fig.39 It is shown Figure 1 The floor plan of Area Y, and Figure 3 , Figure 5 , Figures 7 to 12 and Figures 14 to 19 It is shown Figure 1 A perspective view of Area X.

[0015] Figure 4 and Fig.21 is along Figure 1 The cross-sectional view taken along line AA′ in Figure 6 , Figure 22 to Figure 23 , Fig.28 , Fig.30 and Fig.40 is along Figure 1 The cross-sectional view taken along line BB′ in Figure 25 to Figure 27 and Fig.41 is along Figure 1 The cross-sectional view taken along the CC′ line in Fig.32 , Figure 34 to Figure 35 and Fig.38 is along Figure 1 The cross-sectional view taken along the DD′ line in Figure 2 and Fig.42 is along Figure 1 Cross-sectional view taken along line EE′.

[0016] Hereinafter, a direction substantially perpendicular to the substrate upper surface plane may be defined as a first direction, and two directions intersecting each other along the substrate upper surface plane may be defined as a second direction and a third direction, respectively. In an exemplary embodiment of the inventive concept, the second direction and the third direction may be substantially perpendicular to each other.

[0017] refer to Figure 1 , the substrate 500 may include a first region I and a second region II at least partially surrounding the first region I.

[0018] The substrate 500 may include silicon, germanium, silicon germanium, or a III-V compound such as GaP, GaAs, GaSb, etc. In some exemplary embodiments of the present inventive concept, the substrate 500 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In exemplary embodiments of the present inventive concept, the first region I of the substrate 500 may be a cell array region in which a memory cell may be formed, and the second region II of the substrate 500 may be a step region in which a contact plug connected to the memory cell is formed.

[0019] In an exemplary embodiment of the present invention, the vertical memory device may have a cell-covered periphery (COP) structure. For example, the circuit pattern for driving the memory cell may not be formed at the periphery of the memory cell, but may be formed below the memory cell. Therefore, the circuit pattern area and the cell array area may be vertically stacked on the substrate 500, and the circuit pattern may also be referred to as a lower circuit pattern. However, the present invention is not limited thereto, and even if the vertical memory device has a COP structure, the substrate 500 may further include a peripheral circuit area at least partially surrounding the second area II, in which some circuit patterns may be formed.

[0020] Figure 1The X region shown in is a portion of the second region II of the substrate 500, and the Y region includes a portion of the X region and a portion of the first region I of the substrate 500 adjacent thereto in the second direction. In an exemplary embodiment of the inventive concept, a plurality of X regions may be provided in the third direction, and the Y region may be provided on each of opposite sides of the X region in the third direction. Portions of the substrate 500 where the X region and the Y region overlap each other may be referred to as a third region III and a fourth region IV, respectively. A portion of the X region between the third region III and the fourth region IV may be referred to as a fifth region V.

[0021] refer to Figure 2 , a circuit pattern may be formed on the substrate 500 , and a first lower interlayer insulating layer 570 and a second lower interlayer insulating layer 630 may be formed on the substrate 500 to cover the circuit pattern.

[0022] The substrate 500 may include a field region on which the isolation pattern 510 is formed and an active region on which the isolation pattern 510 is not formed. The isolation pattern 510 may be formed by, for example, a shallow trench isolation (STI) process.

[0023] The circuit pattern may include a transistor, a lower contact plug, a lower wiring, a lower via, etc. For example, a transistor may be formed, the transistor including a lower gate structure 550 on a substrate 500 and a first impurity region 505 adjacent to the lower gate structure 550 at an upper portion of an active region of the substrate 500. The lower gate structure 550 may include a lower gate insulating pattern 520, a lower gate electrode 530, and a lower gate mask 540 stacked sequentially.

[0024] A first lower interlayer insulating layer 570 may be formed on the substrate 500 to cover the transistor, and a lower contact plug 560 may extend through the first lower interlayer insulating layer 570 to contact the first impurity region 505. A first lower wiring 580 may be formed on the first lower interlayer insulating layer 570 to contact an upper surface of the lower contact plug 560. A first lower via 590, a second lower wiring 600, a second lower via 610, and a third lower wiring 620 may be sequentially stacked on the first lower wiring 580. In an exemplary embodiment of the inventive concept, a plurality of third lower wirings 620 may be formed in the third direction. Each of the first to third lower wirings 580, 600, and 620 and each of the first lower via 590 and the second lower via 610 may be formed by a damascene process or a patterning process.

[0025] A second lower interlayer insulating layer 630 may be formed on the first lower interlayer insulating layer 570 to cover the first to third lower wirings 580 , 600 , and 620 and the first and second lower vias 590 and 610 .

[0026] Various circuit patterns may be formed on the substrate 500 , however, these circuit patterns are not shown in the drawings to reduce the complexity of the drawings.

[0027] refer to Figure 3 and Figure 4 , a base pattern 100 may be formed on the second lower interlayer insulating layer 630 , and an insulating layer 110 and a sacrificial layer 120 may be sequentially formed on the base pattern 100 .

[0028] The base pattern 100 may include a semiconductor material, such as silicon. The insulating layer 110 may include an oxide, such as silicon oxide. The sacrificial layer 120 may include a material having an etching selectivity relative to the insulating layer 110, such as a nitride such as silicon nitride.

[0029] A portion of the sacrificial layer 120 on the second region II of the substrate 500 may be removed to form a first opening exposing the insulating layer 110 , and a first dividing pattern 130 may be formed to fill the first opening.

[0030] In an exemplary embodiment of the present inventive concept, a plurality of first dividing patterns 130 may be formed in a third direction on each of the third region III and the fourth region IV of the substrate 500. In the figure, three first dividing patterns 130 are shown in each of the third region III and the fourth region IV. The first dividing patterns 130 may include oxide, such as silicon oxide.

[0031] refer to Figure 5 and Figure 6 , the insulating layer 110 and the sacrificial layer 120 may be further alternately and repeatedly formed on the sacrificial layer 120 and the first dividing pattern 130 , so that the insulating layer 110 and the sacrificial layer 120 may be alternately stacked in the first direction.

[0032] Including Figure 5 The insulating layer 110 may not be seen in the perspective view, but the sacrificial layer 120 is shown, and it should be understood that the insulating layer 110 is disposed thereunder. The etching process for the sacrificial layer 120 may be performed not only on the sacrificial layer 120 but also on the insulating layer 110, wherein each insulating layer 110 may form a pair with one sacrificial layer 120 immediately thereunder, and for ease of explanation, when the etching process is described with reference to the perspective view, the insulating layer 110 will not be described.

[0033] refer to Figure 7 A first photoresist may be formed on the uppermost sacrificial layer 120 to cover edge portions of the first region I and the second region II adjacent thereto, and the uppermost sacrificial layer 120 may be etched using the first photoresist as an etching mask to form a first sacrificial pattern 122 having a rectangular ring shape that at least partially surrounds the uppermost sacrificial layer 120 on the first region I of the substrate 500.

[0034] However, Figure 7 Only a portion of the second region II of the substrate 500, that is, the X region, is shown, and thus only a portion of the first sacrificial pattern 122 having a rectangular ring shape, for example, a stripe-shaped portion extending in the third direction is shown. Hereinafter, instead of the complete shapes of various sacrificial patterns that can be formed on the second region II of the substrate 500 by etching the sacrificial layer 120, only the shapes of the various sacrificial patterns in the X region will be described. During the formation of the mold shown with reference to the perspective view, the portion of the sacrificial layer 120 on the first region I of the substrate 500 may always be covered so as not to be etched.

[0035] After forming the first sacrificial pattern 122 , the first photoresist pattern may be removed by, for example, an ashing process and / or a stripping process.

[0036] refer to Figure 8 , a second photoresist pattern 132 and a third photoresist pattern 134 may be formed on the sacrificial layer 120 of the second level starting from the uppermost level (hereinafter, the nth level starting from the uppermost level will be referred to as the nth level for short) in the sacrificial layer 120, the second photoresist pattern 132 covering the first sacrificial pattern 122 and having a length in the second direction greater than that of the first sacrificial pattern 122, the third photoresist pattern 134 covering a portion of the sacrificial layer 120 in the X region and having a rectangular shape in a plan view, which may be spaced apart from the second photoresist pattern 132 in the second direction, and the second photoresist pattern and the third photoresist pattern may be used as etching masks to etch the sacrificial layer 120 of the second level.

[0037] Therefore, a first sacrificial pattern 122 may be further formed at the second level, and the length of the first sacrificial pattern 122 at the second level may be greater than the length of the first sacrificial pattern 122 at the first level. A second sacrificial pattern 124 may be formed at the second level, spaced apart from the first sacrificial pattern 122 at the second level, and may have a rectangular shape in a plan view.

[0038] refer to Fig. 9 A first trimming process may be performed in which the areas of the second photoresist pattern 132 and the third photoresist pattern 134 are reduced, and the first and second sacrificial patterns 122 and 124 and the third-level sacrificial layer 120 may be etched using the reduced second photoresist pattern 132 and the third photoresist pattern 134 as etching masks.

[0039] Therefore, the length of the first sacrificial pattern 122 of the second level in the second direction may be reduced, and the first sacrificial pattern 122 may be further formed at the third level. The area of ​​the second sacrificial pattern 124 of the second level may be reduced, and the second sacrificial pattern 124 may be further formed at the third level.

[0040] In an exemplary embodiment of the present inventive concept, the first trimming process may be performed through an exposure process of the second and third photoresist patterns 132 and 134 and a development process of unexposed portions of the second and third photoresist patterns 132 and 134 .

[0041] refer to Fig.10 For example, after reducing the areas of the second and third photoresist patterns 132 and 134, the first and second sacrificial patterns 122 and 124 and the fourth-level sacrificial layer 120 may be etched using the reduced second and third photoresist patterns 132 and 134 as etching masks.

[0042] Therefore, the length of the first sacrificial pattern 122 in the second direction of the second and third levels can be reduced, and the first sacrificial pattern 122 can be further formed at the fourth level. In addition, the area of ​​the second sacrificial pattern 124 in the second and third levels can be reduced, and the second sacrificial pattern 124 can be further formed at the fourth level.

[0043] refer to Fig.11 For example, after reducing the areas of the second photoresist patterns 132 and the third photoresist patterns 134, the first and second sacrificial patterns 122 and 124 and the fifth-level sacrificial layer 120 may be etched using the reduced second and third photoresist patterns 132 and 134 as etching masks.

[0044] Therefore, the length of the first sacrificial pattern 122 in the second direction of the second to fourth levels can be reduced, and the first sacrificial pattern 122 can be further formed at the fifth level. In addition, the area of ​​the second sacrificial pattern 124 in the second to fourth levels can be reduced, and the second sacrificial pattern 124 can be further formed at the fifth level.

[0045] refer to Fig.12 and Fig.13 For example, after reducing the areas of the second photoresist patterns 132 and the third photoresist patterns 134, the first and second sacrificial patterns 122 and 124 and the sixth-level sacrificial layer 120 may be etched using the reduced second and third photoresist patterns 132 and 134 as etching masks.

[0046] Therefore, the length of the first sacrificial pattern 122 in the second direction of the second to fifth levels can be reduced, and the first sacrificial pattern 122 can be further formed at the sixth level. In addition, the area of ​​the second sacrificial pattern 124 in the second to fifth levels can be reduced, and the second sacrificial pattern 124 can be further formed at the sixth level.

[0047] The second photoresist pattern 132 and the third photoresist pattern 134 may be removed.

[0048] Therefore, the first sacrificial patterns 122 may be stacked at six levels in a stair shape on the seventh-level sacrificial layer 120 , and the second sacrificial patterns 124 may be stacked at five levels in a stair shape on the seventh-level sacrificial layer 120 , spaced apart from the first sacrificial layer 122 .

[0049] A structure such as the first sacrificial pattern 122 or the second sacrificial pattern 124 stacked in a stair shape in the first direction may be referred to as a “stair structure.” Each layer forming the stair structure may be referred to as a “step layer,” and a portion of each step layer that is not covered by an upper step layer but is exposed may be referred to as a “step.”

[0050] In an exemplary embodiment of the present inventive concept, the first stepped structure consisting of the seventh-level sacrificial layer 120 on the third region III of the substrate 500 and the second sacrificial patterns 124 stacked at five levels thereon may include first, second, third, fourth, fifth, and sixth steps, which may have a first length L1, a second length L2, a third length L3, a fourth length L4, a fifth length L5, and a sixth length L6 in the third direction, respectively. In an exemplary embodiment of the present inventive concept, the fifth length L5 may be greater than the fourth length L4 and the sixth length L6, and the fourth length L4 and the sixth length L6 may be greater than the first to third lengths L1, L2, and L3. In addition, the fourth length L4 and the sixth length L6 may be substantially the same as each other, and the first to third lengths L1, L2, and L3 may be substantially the same as each other.

[0051] The first to sixth lengths L1 to L6 of the first to sixth steps in the third direction may be achieved by controlling the reduction rate of the third photoresist pattern 134 during the trimming process. For example, as the number of repetitions of the trimming process for the photoresist pattern increases, the difference between the desired reduction rate and the actual reduction rate of the photoresist pattern may increase. Therefore, after the fourth trimming process, the area of ​​the uppermost one of the second sacrificial patterns 124 that may be formed by the etching process using the third photoresist pattern 134 may have a large difference from the desired area, and therefore, the length of the sixth step in the third direction may be too large, so that the length of the fifth step in the third direction may be too small.

[0052] In the present inventive concept, considering the error that may be generated during the fourth trimming process, the reduction rate of the third photoresist pattern 134 can be increased so that the length of the fifth step can be no less than the lengths of the other steps. In addition, considering the error that may be generated during the third trimming process, the reduction rate of the third photoresist pattern 134 can be increased so that the length of the fourth step can be no less than the lengths of the first to third steps below. Therefore, the fourth length L4 of the fourth step can be greater than the first to third lengths L1, L2 and L3 of the first to third steps below, the fifth length L5 of the fifth step can be greater than the fourth length L4 of the fourth step, and the sixth length L6 of the sixth step can be substantially the same as or similar to the fourth length L4.

[0053] A second stepped structure may be formed on the fourth region IV of the substrate 500, and the first stepped structure and the second stepped structure may be symmetrical about a straight line extending in the second direction therebetween. For example, the second stepped structure may be composed of a sacrificial layer 120 of the seventh level on the fourth region IV of the substrate 500 and second sacrificial patterns 124 stacked in five levels thereon, and may include seventh, eighth, ninth, tenth, eleventh and twelfth steps, which may have a first length L1, a second length L2, a third length L3, a fourth length L4, a fifth length L5 and a sixth length L6 in the third direction, respectively.

[0054] refer to Fig.14 , a fourth photoresist pattern 140 may be formed on the seventh-level sacrificial layer 120 to cover the first sacrificial pattern 122 and a portion of the second sacrificial pattern 124 adjacent thereto.

[0055] refer to Fig.15 , the second sacrificial pattern 124 and one or more of the sacrificial layers 120 at the seventh to twelfth levels, respectively, may be etched using the fourth photoresist pattern 140 as an etching mask.

[0056] Therefore, the third sacrificial patterns 126 having a length in the second direction greater than that of the first sacrificial patterns 122 may be formed at the seventh to twelfth levels, respectively, and portions of the second sacrificial patterns 124 not covered by the fourth photoresist patterns 140 may be moved to the eighth to twelfth levels, respectively. The remaining portions of the second sacrificial patterns 124 covered by the fourth photoresist patterns 140 may be transformed into fourth sacrificial patterns 128 on the third sacrificial patterns 126 at the seventh level, respectively.

[0057] refer to Fig.16 , a fifth trimming process of reducing the area of ​​the fourth photoresist pattern 140 may be performed to expose a portion of the fourth sacrificial pattern 128 .

[0058] refer to Fig.17The exposed fourth sacrificial pattern 128 , the second sacrificial pattern 124 , and the third sacrificial pattern 126 , and one or more of the sacrificial layers 120 at the thirteenth to eighteenth levels, respectively, may be etched using the fourth photoresist pattern 140 as an etching mask.

[0059] Therefore, the third sacrificial patterns 126 at the seventh to twelfth levels, respectively, may be reduced to a length less than the previous length, and the third sacrificial patterns 126 may be further formed at the thirteenth to eighteenth levels, respectively, having a length greater than that of the third sacrificial patterns 126 at the seventh to twelfth levels. The exposed portions of the fourth sacrificial patterns 128 may be moved from the second to sixth levels to the eighth to twelfth levels, respectively, and hereinafter may be referred to as fifth sacrificial patterns 129, respectively. The portions of the second sacrificial patterns 124 not covered by the fourth photoresist pattern 140 may be moved from the eighth to twelfth levels to the fourteenth to eighteenth levels, respectively.

[0060] Can be repeated and referenced Fig.16 and Fig.17 The processes shown are basically the same or similar processes.

[0061] refer to Fig.18 After removing the fourth photoresist pattern 140, the same process as reference Fig.14 The processes shown are basically the same or similar processes.

[0062] For example, the fifth photoresist pattern 142 may be formed on the sacrificial layer 120 at a given level to cover the first sacrificial pattern 122 , the third to fifth sacrificial patterns 126 , 128 , and 129 , and a portion of the second sacrificial pattern 124 adjacent thereto.

[0063] refer to Figures 19 to 22 , can be repeatedly executed and referenced Figures 15 to 17 The process shown is substantially the same as or similar to the process, so that a fifth sacrificial pattern 129 can be further formed at a desired level, and a stepped structure each of which can include the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 can be formed on the second region II of the substrate 500. The stepped structure together with the sacrificial layer 120 remaining on the first region I of the substrate 500 can form a mold.

[0064] In an exemplary embodiment of the present invention, the first sacrificial pattern 122 may form a third stepped structure, wherein the length of the step layer in the second direction gradually decreases from the lowest level toward the highest level, and the third sacrificial pattern 126 may form a fourth stepped structure, wherein the length of the step layer in the second direction decreases from the lowest level toward the highest level in units of several levels (for example, six levels).

[0065] The second sacrificial pattern 124 can form a fifth stepped structure, in which the length of the step layer in each direction of the second direction and the third direction gradually decreases from the lowest level toward the highest level, and the fourth sacrificial pattern 128 can form a sixth stepped structure, in which the length of the step layer in each direction of the second direction and the third direction gradually decreases from the lowest level toward the highest level.

[0066] In an exemplary embodiment of the inventive concept, the fifth sacrificial patterns 129 on the third and fourth regions III and IV of the substrate 500 may form seventh and eighth stepped structures, respectively, in which the length of the stepped layers in the third direction gradually decreases from the lowermost level toward the uppermost level.

[0067] The seventh step structure may include first to sixth step layers stacked sequentially in the first direction, and the first to sixth steps of the first to sixth step layers may be sequentially arranged in this order in the third direction. The first to sixth steps may have first to sixth lengths L1, L2, L3, L4, L5 and L6 in the third direction, respectively. In an exemplary embodiment of the present inventive concept, the fifth length L5 may be greater than the fourth length L4 and the sixth length L6, and the fourth length L4 and the sixth length L6 may be greater than the first to third lengths L1, L2 and L3. In addition, the fourth length L4 and the sixth length L6 may be substantially the same as each other, and the first to third lengths L1, L2 and L3 may be substantially the same as each other.

[0068] The seventh step structure and the eighth step structure may be spaced apart from each other in the third direction and may be symmetrical with respect to a straight line extending between them in the second direction. Therefore, the eighth step structure may include the seventh, eighth, ninth, tenth, eleventh and twelfth step layers stacked sequentially from the lowest level toward the highest level in the first direction, and the seventh to twelfth steps of the seventh to twelfth step layers may be sequentially arranged in this order in the third direction.

[0069] refer to Fig.23 , a thickness of one or more of the first to fifth sacrificial patterns 122 , 124 , 126 , 128 , and 129 on the second region II of the substrate 500 at an end portion in the second direction or the third direction may be increased.

[0070] In an exemplary embodiment of the present inventive concept, portions of the insulating layer 110 on the steps of the third to eighth stepped structures may be removed to expose the ends of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 of the steps, and a material substantially the same as that of the sacrificial layer 120 may be deposited on the exposed ends of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129, so that the thickness of the ends of one or more of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 may be increased. Therefore, the ends of one or more of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 may have a top surface higher than the top surface of the respective other portions, and a thickness greater than the thickness of the respective other portions.

[0071] refer to Fig.24 and Fig.25 , a first etching mask 170 having a second opening 180 exposing the fifth region V of the substrate 500 and the lowermost sacrificial layer 120 may be formed on the first and second regions I and II of the substrate 500. The thickness of one or more ends of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 on the fifth region V of the substrate 500 and the lowermost sacrificial layer 120 may be reduced.

[0072] In an exemplary embodiment of the present inventive concept, reference is made to Fig.23 The increased thickness of the end portion of one or more of the illustrated first to fifth sacrificial patterns 122 , 124 , 126 , 128 , and 129 may be reduced to the original thickness on the fifth region V of the substrate 500 and the lowermost sacrificial layer 120 .

[0073] refer to Fig.26 , you can refer to Fig.24 and Fig.25 The etching process shown will refer to Fig.23 The increased thickness of the end portion of one or more of the illustrated first to fifth sacrificial patterns 122 , 124 , 126 , 128 , and 129 is reduced to a thickness less than the original thickness.

[0074] In addition, reference Fig. 27 , you can refer to Fig.24 and Fig.25 The etching process shown completely removes the reference Fig.23The ends of one or more of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 are shown. Therefore, the uppermost first sacrificial pattern 122 in the third stepped structure, the uppermost second sacrificial pattern 124 in the fourth stepped structure, the uppermost fourth sacrificial pattern 128 in the sixth stepped structure, and the uppermost fifth sacrificial pattern 129 between the seventh and eighth stepped structures can be removed on the fifth region V of the substrate 500.

[0075] refer to Fig.28 , a first interlayer insulating layer 200 may be formed on the substrate 500 to cover the mold including the third to eighth stepped structures that may be alternately and repeatedly stacked on the sacrificial layers 120 and the insulating layers 110 of the first region I of the substrate 500 and the second region II of the substrate 500, and the first interlayer insulating layer 200 may be planarized until the upper surface of the uppermost insulating layer 110 is exposed. The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0076] A second interlayer insulating layer 210 may be formed on the mold and the first interlayer insulating layer 200. The first interlayer insulating layer 200 and the second interlayer insulating layer 210 may each include an oxide, such as silicon oxide. In an exemplary embodiment of the present inventive concept, the first interlayer insulating layer 200 and the second interlayer insulating layer 210 may be formed as a portion of the insulating layer 110.

[0077] refer to Fig.29 and Fig.30 , a second etching mask may be formed on the second interlayer insulating layer 210. The second interlayer insulating layer 210, the insulating layer 110, and the sacrificial layer 120 may all be etched using the second etching mask to form a channel hole therethrough, thereby exposing the upper surface of the base pattern 100 on the first region I of the substrate 500. The second structure filling the channel hole may be formed as follows.

[0078] After removing the second etching mask, a semiconductor pattern 230 may be formed to partially fill the channel hole. For example, a selective epitaxial growth (SEG) process may be performed using the exposed upper portion of the substrate pattern 100 as a seed to form the semiconductor pattern 230 filling the lower portion of the channel hole. The height of the upper surface of the semiconductor pattern 230 may be between the height of the lower surface and the upper surface of the second-level insulating layer 110 upward from the upper surface of the substrate pattern 100.

[0079] A first barrier layer, a charge storage layer, a tunnel insulating layer, and a first spacer layer may be sequentially formed on the sidewalls of the channel hole, the upper surface of the semiconductor pattern 230, and the upper surface of the second interlayer insulating layer 210. The first spacer layer may be anisotropically etched to form a first spacer on the sidewalls of the channel hole. The tunnel insulating layer, the charge storage layer, and the first barrier layer may be etched using the first spacer as an etching mask to form a tunnel insulating pattern 260, a charge storage pattern 250, and a first barrier pattern 240 each having a cup shape with a bottom opening on the semiconductor pattern 230 and on the sidewalls of the channel hole, respectively. During the etching process, the upper portion of the semiconductor pattern 230 may also be partially removed. The tunnel insulating pattern 260, the charge storage pattern 250, and the first barrier pattern 240 may form a charge storage structure 270 together.

[0080] The first spacer and the charge storing pattern 250 may each include a nitride, such as silicon nitride. The tunnel insulating pattern 260 and the first barrier pattern 240 may each include an oxide, such as silicon oxide.

[0081] After removing the first spacer, a channel layer may be formed on the exposed semiconductor pattern 230, the tunnel insulating pattern 260, and the second interlayer insulating layer 210. A filling layer may be formed on the channel layer to fill the remaining portion of the channel hole. The filling layer and the channel layer may be planarized until the upper surface of the second interlayer insulating layer 210 may be exposed to form a filling pattern 290. The channel layer may thereby be transformed into a channel 280. The filling pattern 290 may include an oxide, such as silicon oxide.

[0082] The upper portion of the first structure including the filling pattern 290, the channel 280 and the charge storage structure 270 may be removed to form a trench. A capping pattern 300 may be formed to fill the trench. The channel 280 and the capping pattern 300 may each include polysilicon or single crystal silicon that is undoped or lightly doped with impurities.

[0083] In an exemplary embodiment of the present inventive concept, a plurality of channels 280 may be formed in each of the second direction and the third direction to form a channel array.

[0084] In an exemplary embodiment of the present inventive concept, the channel array may include a first channel column 280a and a second channel column 280b, the first channel column 280a including a first channel arranged in the second direction, the second channel column 280b including a second channel arranged in the second direction and spaced apart from the first channel column 280a in the third direction. The first channel included in the first channel column 280a may be arranged to form an acute angle with respect to the second channel included in the second channel column 280b and the second direction or the third direction. Therefore, the first channel and the second channel may be arranged in a zigzag pattern.

[0085] The first channel column 280a and the second channel column 280b may be alternately and repeatedly arranged in the third direction. In an exemplary embodiment of the present invention, five first channel columns 280a and four second channel columns 280b may be alternately arranged in the third direction to form a channel block. Hereinafter, the four channel columns arranged in the third direction in a channel block may be respectively referred to as the first channel column 280a, the second channel column 280b, the third channel column 280c, and the fourth channel column 280d. A channel column at the center position in the third direction in the channel block may be referred to as the fifth channel column 280e, and the other four channel columns arranged in the third direction in the channel block may be respectively referred to as the first channel column 280a, the second channel column 280b, the third channel column 280c, and the fourth channel column 280d.

[0086] The first to fourth channel columns 280a, 280b, 280c, and 280d arranged in the third direction may form a channel group. Fig.29 A channel array including four channel blocks spaced apart from each other in the third direction is shown, and each channel block includes two channel groups arranged in the third direction, and the fifth channel column 280e is disposed between the two channel groups. However, the number of channel columns included in each channel block or the number of channels included in each channel group may not be limited to the above number. The channel 280 of the fifth channel column 280e may be a dummy channel.

[0087] refer to Fig.31 and Fig.32 The second dividing pattern 310 may be formed through one or more of the sacrificial layer 120 and the insulating layer 110 on the first region I of the substrate 500 and a portion of the second region II of the substrate 500 adjacent thereto.

[0088] The second dividing pattern 310 may be formed by forming a third etch mask on the second interlayer insulating layer 210 , etching the second interlayer insulating layer 210 using the third etch mask, etching one or more of the insulating layer 110 and the sacrificial layer 120 to form a third opening therethrough and filling an insulating material.

[0089] In an exemplary embodiment of the present inventive concept, the second dividing pattern 310 may extend in the second direction between two channel groups in the channel block. Thus, the second dividing pattern 310 may extend through upper portions of the channels 280 included in the fifth channel column 280 e.

[0090] In an exemplary embodiment of the inventive concept, the second dividing pattern 310 may extend not only through the upper portion of the channel 280, but also through the second interlayer insulating layer 210, one or more of the sacrificial layers 120 of the upper two levels, and one or more of the insulating layers 110 of the upper two levels, and may also extend through a portion of the insulating layer 110 of the third level from the top. The second dividing pattern 310 may extend not only on the first region I of the substrate 500, but also on the second region II of the substrate 500 in the second direction so as to penetrate the upper step layer of the third stepped structure. Therefore, the sacrificial layers 120 of the upper two levels and the first sacrificial pattern 122 may be divided in the third direction by the second dividing pattern 310.

[0091] refer to Fig.33 and Fig.34 , a third interlayer insulating layer 320 can be formed on the second interlayer insulating layer 210, the covering pattern 300 and the second dividing pattern 310, a fourth etching mask can be formed on the third interlayer insulating layer 320, and the second interlayer insulating layer 210 and the third interlayer insulating layer 320, the insulating layer 110 and the sacrificial layer 120 can be etched using the fourth etching mask to form a fourth opening 330 and a fifth opening 340 therethrough, thereby exposing the upper surface of the base pattern 100.

[0092] In an exemplary embodiment of the present inventive concept, each of the fourth opening 330 and the fifth opening 340 may extend in the second direction between the channel blocks on the first region I and the second region II of the substrate 500. A plurality of fourth openings 330 and a plurality of fifth openings 340 may be formed in the third direction. For example, one channel block may be disposed between adjacent openings of the fourth opening 330 and the fifth opening 340, and the channel block may be disposed on each of the opposite sides of the fifth channel column 280e, thereby including two channel groups, each channel group including four channel columns.

[0093] Due to the formation of the fourth opening 330 and the fifth opening 340 , the sacrificial layer 120 may be divided into a plurality of pieces, each of which may extend in the second direction, and the insulating layer 110 may be transformed into the insulating patterns 115 , each of which may extend in the second direction.

[0094] In an exemplary embodiment of the present inventive concept, the fourth opening 330 may extend continuously on the first region I and the second region II of the substrate 500, however, the fifth opening 340 may be blocked on the second region II of the substrate 500. Therefore, the sacrificial layers 120 extending in the second direction on each of the opposite sides of the fifth opening 340 in the third direction may be connected to each other on the second region II of the substrate 500. In an exemplary embodiment of the present inventive concept, the connection portion that may connect the sacrificial layers 120 to each other may overlap with the first sacrificial pattern 122 and the first dividing pattern 130 of the third level included in the third stepped structure in the first direction.

[0095] In an exemplary embodiment of the present inventive concept, the fourth opening 330 may overlap each of the opposite edges of the X region, and thus four channel blocks may be disposed between the fourth openings 330 adjacent in the third direction. In addition, the fifth opening 340 may be formed between the channel blocks in the X region, and thus one channel block may be formed between the fifth openings 340 adjacent in the third direction. Therefore, the four sacrificial layers 120 extending in the second direction in the X region may be connected to each other through the connecting portion. However, one or more of the sacrificial layers 120 of the lowest level may be separated from each other by the first dividing pattern 130.

[0096] In an exemplary embodiment of the present invention, when forming the fourth opening 330 and the fifth opening 340, a sixth opening 350 may also be formed to extend through the second interlayer insulating layer 210 and the third interlayer insulating layer 320, the insulating layer 110, and the first to fifth sacrificial patterns 122, 124, 126, 128 and 129 to expose the upper surface of the base pattern 100.

[0097] The sixth opening 350 may extend in the second direction on the second region II of the substrate 500 to divide each of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 in the third direction. In a plan view, the sixth opening 350 may extend from one of the first sacrificial patterns 122 included in the third stepped structure to one end of the second region II of the substrate 500.

[0098] refer to Fig.35 and Fig.36 After removing the fourth etching mask, the sacrificial layer 120 and the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 exposed by the fourth to sixth openings 330, 340, and 350 may be removed to form gaps between the insulating patterns 115 adjacent in the first direction. Thus, a portion of the sidewall of the second dividing pattern 310, a portion of the outer sidewall of the first barrier pattern 240, and a portion of the sidewall of the semiconductor pattern 230 may be exposed.

[0099] A second barrier layer 370 may be formed on exposed portions of the sidewalls of the second dividing pattern 310, exposed portions of the outer sidewalls of the first barrier pattern 240, exposed portions of the sidewalls of the semiconductor pattern 230, inner walls of the gaps, surfaces of the insulating patterns 115, upper surfaces of the base patterns 100, and upper surfaces of the third interlayer insulating layer 320. A gate conductive layer may be formed on the second barrier layer 370 to fill the rest of the gaps. A gate barrier layer may be further formed between the second barrier layer 370 and the gate conductive layer.

[0100] The second barrier layer 370 may include a metal oxide such as aluminum oxide, the gate conductive layer may include a metal such as tungsten, and the gate barrier layer may include a metal nitride such as titanium nitride, tantalum nitride, or the like.

[0101] The gate conductive layer may be partially removed to form a gate conductive pattern in the gap, and when the gate barrier layer is formed, the gate barrier layer may be partially removed to form a gate barrier pattern. The gate conductive pattern and the gate barrier pattern may form a gate electrode.

[0102] In an exemplary embodiment of the present inventive concept, the gate electrode may extend in the second direction, and a plurality of gate electrodes may be formed in the first direction. In addition, a plurality of gate electrodes may also be formed in the third direction. For example, the gate electrodes may be spaced apart from each other in the third direction by the fourth opening 330. In addition, each gate electrode may be divided into pieces in the third direction by the fifth opening 340, and these pieces may be connected to each other by connecting portions, which may be formed on the second region II of the substrate 500 and overlap with the first dividing pattern 130. Each gate electrode (except the gate electrodes of the upper two levels) extending in the second direction on the second region II of the substrate 500 may also be divided in the third direction by the sixth opening 350.

[0103] The gate electrode may include first to third gate electrodes 382, ​​384, and 386 sequentially stacked in the first direction. In an exemplary embodiment of the present inventive concept, the first gate electrode 382 may be formed at the lowest level, the third gate electrode 386 may be formed at the upper two levels, and the second gate electrode 384 may be formed at multiple levels between the first gate electrode 382 and the third gate electrode 386.

[0104] The gate electrode may be formed by replacing the first to fifth sacrificial patterns 122 , 124 , 126 , 128 , and 129 of the third to eighth stepped structures on the second region II of the substrate 500 , and thus the third to eighth stepped structures may include the gate electrode.

[0105] As described above, the thickness of the end portions of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 on the fifth region V of the substrate 500 may be smaller than the thickness of the end portions of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 on the third region III and the fourth region IV of the substrate 500. Therefore, when a gap is formed by removing the sacrificial layer 120 exposed by the fourth to sixth openings 330, 340, and 350 and the first to fifth sacrificial patterns 122, 124, 126, 128, and 129, a removal rate of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 on the fifth region V of the substrate 500 may be smaller than a removal rate of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 on the third region III and the fourth region IV of the substrate 500, which may not be completely removed but may at least partially remain. Fig.36 As shown in FIG. 5 , both edge portions of the first to fifth sacrificial patterns 122 , 124 , 126 , 128 , and 129 on the fifth region V of the substrate 500 may be removed to be replaced with gate electrodes, however, central portions thereof may not be removed and may at least partially remain as a mold.

[0106] refer to Fig.37 and Fig.38 Impurities may be implanted into an upper portion of the substrate pattern 100 exposed by the fourth opening 330 and the fifth opening 340 to form a second impurity region 105 .

[0107] A second spacer layer may be formed on the upper surface of the base pattern 100 exposed by the fourth to sixth openings 330 , 340 , and 350 , the sidewalls of the fourth to sixth openings 330 , 340 , and 350 , and the upper surface of the third interlayer insulating layer 320 , and the second spacer layer may be anisotropically etched to form a second spacer 390 on each sidewall of the fourth to sixth openings 330 , 340 , and 350 .

[0108] A first common source line (CSL) 400 and a second common source line (CSL) 410 may be formed in the fourth opening 330 and the fifth opening 340 , respectively, on the second impurity region 105 , and a third dividing pattern 420 may be formed in the sixth opening 350 on the substrate pattern 100 .

[0109] In an exemplary embodiment of the present inventive concept, a conductive layer may be formed on the exposed upper surface of the base pattern 100, the second spacer 390, and the third interlayer insulating layer 320 to fill the fourth to sixth openings 330, 340, and 350, and the conductive layer may be planarized until the upper surface of the third interlayer insulating layer 320 may be exposed to form the first CSL 400 and the second CSL 410 and the third dividing pattern 420. During the planarization process, a portion of the second barrier layer 370 on the third interlayer insulating layer 320 may also be removed. The first CSL 400 and the second CSL 410 may be formed in the fourth opening 330 and the fifth opening 340, respectively, to contact the upper surface of the second impurity region 105.

[0110] refer to Figures 39 to 42 After forming a fourth interlayer insulating layer 430 on the third interlayer insulating layer 320, the first CSL 400 and the second CSL 410, the third dividing pattern 420, the second spacer 390 and the second barrier layer 370, a contact plug 440 may be formed through the first to fourth interlayer insulating layers 200, 210, 320 and 430, the insulating pattern 115 and the second barrier layer 370 on the third region III and the fourth region IV of the substrate 500 to contact the upper surfaces of the first to third gate electrodes 382, ​​384 and 386. A through via 450 may be formed through the first to fourth interlayer insulating layers 200, 210, 320 and 430, the insulating pattern 115, the sacrificial layer 120, the base pattern 100 and the second lower interlayer insulating layer 630 to contact the upper surface of the third wiring 620 on the fifth region V of the substrate 500.

[0111] Each contact plug 440 may contact the upper surface of at least one step included in the third to eighth stepped structures. For example, the contact plug 440 may contact the upper surface of the step of the seventh stepped structure, thereby being arranged in the third direction. In addition, the contact plug 440 may contact the upper surface of the step of the seventh stepped structure that may be arranged in the second direction, thereby being arranged in the second direction.

[0112] The through vias 450 may be formed in the third direction between the seventh stepped structure and the eighth stepped structure. For example, six through vias 450 may be formed between the seventh and eighth stepped structures.

[0113] The contact plug 440 and the through via 450 may include metal and / or metal nitride. Upper wiring and more vias may be further formed to complete the fabrication of the vertical memory device.

[0114] The vertical memory device manufactured by the above process may include gate electrodes 382, ​​384, and 386 spaced apart from each other in each of the first and third directions on a substrate 500 including a first region I and a second region II, and a channel 280 extending through one or more of the gate electrodes 382, ​​384, and 386 along the first direction on the first region I of the substrate 500. The end portions of one or more of the gate electrodes 382, ​​384, and 386 on the second region II of the substrate 500 in the second direction may form a seventh step structure and an eighth step structure. The seventh step structure may include first to sixth steps sequentially stacked from the lowest step toward the uppermost step in the first direction and also arranged in the third direction, and the eighth step structure may include seventh to twelfth steps corresponding thereto. The seventh step structure and the eighth step structure may be formed on the third region III and the fourth region IV of the substrate 500, respectively. In an exemplary embodiment of the present inventive concept, the first to sixth steps may have first to sixth lengths L1, L2, L3, L4, L5, and L6, respectively, and the fifth length L5 may be greater than the fourth length L4 and the sixth length L6, and the fourth length L4 and the sixth length L6 may be greater than the first to third lengths L1, L2, and L3. In an exemplary embodiment of the present inventive concept, the fourth length L4 and the sixth length L6 may be substantially the same as each other, and the first to third lengths L1, L2, and L3 may be substantially the same as each other. However, a portion of the gate electrodes 382, ​​384, and 386 may remain on the fifth region V of the substrate 500, so if these portions are included, the sixth step may have a seventh length L7 greater than the fifth length L5.

[0115] In an exemplary embodiment of the present invention, a plurality of seventh stepped structures may be formed at different heights in the second direction, and a plurality of eighth stepped structures may be formed at different heights in the second direction. In an exemplary embodiment of the present invention, a mold including insulating patterns 115 and fifth sacrificial patterns 129 alternately and repeatedly stacked in the first direction may remain between the seventh stepped structure and the eighth stepped structure and contact the sidewalls of the seventh stepped structure and the eighth stepped structure. The lower surface of the fifth sacrificial pattern 129 may be substantially coplanar with the lower surface of the corresponding step of each of the seventh stepped structure and the eighth stepped structure, and the upper surface of the fifth sacrificial pattern 129 may be lower than the upper surface of the corresponding step. In an exemplary embodiment of the present invention, the seventh stepped structure and the eighth stepped structure may be symmetrical relative to the mold.

[0116] In an exemplary embodiment of the inventive concept, a contact plug 440 may be formed on each of the first to sixth steps of the seventh stepped structure. The distances between the contact plugs 440 on the first to sixth steps in the third direction may be a first distance D1, a second distance D2, a third distance D3, a fourth distance D4, and a fifth distance D5, and the fourth distance D4 and the fifth distance D5 may be greater than the first to third distances D1, D2, and D3. In an exemplary embodiment of the inventive concept, the fourth distance D4 and the fifth distance D5 may be substantially the same as each other, and the first to third distances D1 to D3 may be substantially the same as each other.

[0117] In an exemplary embodiment of the present inventive concept, a vertical memory device may include a circuit pattern on a substrate 500 and a base pattern 100 above the circuit pattern. Gate electrodes 382, ​​384, and 386, a channel 280, and a mold may be formed on the base pattern 100. A through via 450 may extend through the mold and the base pattern 100 to be electrically connected to the circuit pattern. Thus, a plurality of through vias 450 may be formed.

[0118] In an exemplary embodiment of the present inventive concept, each of the first CSL 400 and the second CSL 410 may extend in the second direction to divide each of the gate electrodes 382, ​​384, and 386 in the third direction. The first CSL 400 may extend continuously in the second direction on the first region I and the second region II of the substrate 500. The second CSL 410 may extend in the second direction on the first region I and the second region II of the substrate 500, but may be disconnected on the second region II of the substrate 500.

[0119] In an exemplary embodiment of the inventive concept, the first CSL 400 may contact a sidewall of the first step or penetrate the sixth step. The second CSL 410 may be formed between the first CSLs 400 to contact a sidewall of the third step, penetrate the fourth step, or penetrate the fifth step.

[0120] In an exemplary embodiment of the inventive concept, the vertical memory device may further include third dividing patterns 420, each of which extends in the second direction between adjacent CSLs of the first CSL 400 and the second CSL 410 to divide each of the gate electrodes 382, ​​384, and 386 in the third direction. The third dividing pattern 420 may contact a sidewall of the second step, contact a sidewall of the fourth step, penetrate the fifth step, or penetrate the sixth step.

[0121] In an exemplary embodiment of the present inventive concept, in the first to sixth stepped layers of the seventh stepped structure, each of the first stepped layer and the second stepped layer may be formed by the ends of four second gate electrodes 384 in the third direction. Each of the third stepped layer and the fourth stepped layer may be formed by the ends of three second gate electrodes 384 in the third direction. The fifth stepped layer may be formed by the ends of two second gate electrodes 384 in the third direction. The sixth stepped layer may be formed by one second gate electrode 384.

[0122] In an exemplary embodiment of the present inventive concept, the first to sixth step layer may include first to sixth steps, and a length in the third direction of at least one of the first to sixth steps may be different from lengths of the other steps of the first to sixth steps.

[0123] The vertical memory device may include a seventh step structure and an eighth step structure, each of which may include a plurality of steps, for example, six steps, in the third direction, so that even if many gate electrodes are stacked in the first direction, the length of the vertical memory device in the second direction may not increase much. In addition, the length of the step of the step layer in the third direction may be appropriately adjusted so that only one contact plug 440 can be formed on each step.

[0124] Fig.43 and Fig.44 is a cross-sectional view illustrating a vertical memory device according to an exemplary embodiment of the inventive concept. Fig.43 is along Figure 1 The cross-sectional view taken along the CC′ line is Fig.44 is along Fig.39 The vertical memory device can be connected with Figures 39 to 42 The vertical memory device of FIG. 1 is substantially the same, except for the fifth region of the substrate. Therefore, the same reference numerals may refer to the same elements, and if details are omitted, it can be assumed that these details are at least similar to the details of the corresponding elements already described.

[0125] refer to Fig.43 and Fig.44 , the mold between the seventh step structure and the eighth step structure may not include the fifth sacrificial pattern 129 corresponding to the sixth step and the twelfth step, which can be achieved by referring to Fig. 27 The process shown is accomplished by completely removing the uppermost step in each staircase structure.

[0126] Fig.45 is along Fig.39 FIG. 1 is a cross-sectional view taken along line EE′ of FIG. 1 , illustrating a vertical memory device according to an exemplary embodiment of the inventive concept. Fig.45 Reference Figures 39 to 42Schematic diagram of the connection between the contact plug 440 and the through via 450 in a vertical memory device is shown.

[0127] refer to Fig.45 , one or more through vias 450 may be electrically connected to one or more contact plugs 440 on the steps of the seventh stepped structure, and one or more through vias 450 may be electrically connected to one or more contact plugs 440 on the steps of the eighth stepped structure. In the figure, three through vias 450 are electrically connected to three contact plugs 440 on the steps of the seventh stepped structure, respectively, and three through vias 450 are electrically connected to three contact plugs 440 on the steps of the eighth stepped structure, respectively, but the inventive concept is not limited thereto.

[0128] The through via 450 and the contact plug 440 may be electrically connected to each other through an upper wiring 480 of the same level.

[0129] While exemplary embodiments of the present inventive concept have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A vertical storage device, include: A substrate including a cell array region and a stepped region at least partially surrounding the cell array region; a plurality of gate electrodes spaced apart from each other in each of a first direction and a third direction in the cell array region and the step region of the substrate, wherein each of the plurality of gate electrodes extends along a second direction, wherein the first direction is perpendicular to an upper surface of the substrate, wherein the third direction is parallel to the upper surface of the substrate, and wherein the second direction is parallel to the upper surface of the substrate and intersects the third direction; as well as a channel extending along the first direction in the cell array region of the substrate, wherein the channel extends through at least one of the plurality of gate electrodes, wherein the ends of the plurality of gate electrodes in the second direction form a first stepped structure on the stepped region of the substrate, The first step structure includes a plurality of first steps, second steps and third steps sequentially arranged in the third direction, and Each of the plurality of first steps has a first length in the third direction, the second step has a second length in the third direction greater than the first length, and the third step has a third length in the third direction greater than the second length. 2 . The vertical storage device of claim 1 , wherein each of the plurality of first steps, the second steps, and the third steps is sequentially arranged from a lowermost level to an uppermost level in the first direction.

3. The vertical storage device according to claim 1 , wherein the first staircase structure comprises the plurality of first steps, the second steps, the third steps, and the fourth steps sequentially arranged in the third direction, and A fourth length of the fourth step in the third direction is greater than the third length. The vertical storage device according to claim 1 , wherein the first stepped structure comprises three first steps. 5 . The vertical memory device according to claim 4 , wherein a plurality of first stepped structures including the first stepped structure are respectively arranged at different levels in the second direction. 6 . The vertical memory device of claim 1 , further comprising first, second, and third contact plugs disposed on upper surfaces of the first, second, and third steps, respectively. 7 . The vertical memory device of claim 6 , wherein a distance between the second contact plug and the third contact plug in the third direction is greater than a distance between the first contact plugs in the third direction. 8 . The vertical memory device according to claim 7 , wherein a distance between the second contact plug and a first contact plug adjacent thereto among the first contact plugs is the same as a distance between the first contact plugs. 9 . The vertical memory device of claim 1 , further comprising a mold disposed adjacent to the first stepped structure in the third direction, the mold contacting a sidewall of the first stepped structure. 10 . The vertical memory device of claim 9 , wherein the mold includes first and second insulating patterns that are alternately and repeatedly stacked in the first direction. 11 . The vertical memory device of claim 10 , wherein each of the first insulating patterns comprises nitride, and a lower surface thereof is coplanar with a lower surface of a corresponding one of the first to third steps. 12 . The vertical memory device of claim 11 , wherein an upper surface of each of the first insulating patterns is lower than an upper surface of the corresponding step among the first to third steps. 13 . The vertical memory device of claim 9 , further comprising a second stepped structure, wherein the first stepped structure and the second stepped structure are symmetrical with respect to the mold in the third direction.

14. The vertical memory device according to claim 9, further comprising a base pattern disposed on the substrate, wherein the plurality of gate electrodes, the channel and the mold are formed on the base pattern.

15. The vertical storage device according to claim 14, further comprising: include: a circuit pattern disposed between the substrate and the base pattern; as well as A through via extends through the mold and the base pattern to be electrically connected to the circuit pattern.

16. The vertical storage device according to claim 15, wherein the through via comprises a plurality of through vias, and The vertical memory device further includes a first contact plug, a second contact plug, and a third contact plug contacting upper surfaces of the first step, the second step, and the third step, respectively.

17. The vertical storage device according to claim 16, further comprising: include: a second stepped structure, wherein the first stepped structure and the second stepped structure are symmetrical with respect to the mold in the third direction, wherein the second stepped structure comprises a plurality of first steps, second steps and third steps sequentially arranged in the third direction; as well as The fourth contact plug, the fifth contact plug and the sixth contact plug contact the upper surfaces of the first step, the second step and the third step of the second stepped structure respectively. One or more through vias among the plurality of through vias are electrically connected to at least one of the first to third contact plugs, and other through vias among the plurality of through vias are electrically connected to at least one of the fourth to sixth contact plugs. 18 . The vertical memory device of claim 1 , further comprising a common source line extending along the second direction on the substrate, the common source line dividing each of the plurality of gate electrodes in the third direction.

19. The vertical storage device according to claim 18, wherein the first stepped structure comprises each of the plurality of first steps, the second steps, the third steps, and the fourth steps sequentially arranged in the third direction, and The common source line includes a first common source line and a second common source line, the first common source line contacts a sidewall of a lowermost first step among the plurality of first steps, and the second common source line penetrates the fourth step.

20. The vertical storage device according to claim 19, wherein the first stepped structure comprises three first steps, and The common source line includes a third common source line, a fourth common source line and a fifth common source line, the third common source line contacts a side wall of an uppermost first step among the plurality of first steps, the fourth common source line penetrates the second step, and the fifth common source line penetrates the third step.

21. A vertical storage device, include: A substrate including a cell array region and a stepped region at least partially surrounding the cell array region; a plurality of gate electrodes spaced apart from each other in each of a first direction and a third direction in the cell array region and the step region of the substrate, wherein each of the plurality of gate electrodes extends along a second direction, wherein the first direction is perpendicular to an upper surface of the substrate, wherein the third direction is parallel to the upper surface of the substrate, and wherein the second direction is parallel to the upper surface of the substrate and intersects the third direction; as well as a channel extending along the first direction in the cell array region of the substrate, wherein the channel extends through at least one of the plurality of gate electrodes, wherein ends of the plurality of gate electrodes in the second direction form a first stepped structure and a second stepped structure on the stepped region of the substrate, wherein each of the first stepped structure and the second stepped structure has a step, and wherein the first stepped structure and the second stepped structure are symmetrical to each other in the third direction, and wherein the mold is disposed between the first stepped structure and the second stepped structure, wherein the mold contacts sidewalls of the first stepped structure and the second stepped structure and comprises an insulating material, wherein the mold includes first insulating patterns and second insulating patterns alternately and repeatedly stacked in the first direction, and A lower surface of each of the first insulating patterns is coplanar with a lower surface of a corresponding gate electrode among the plurality of gate electrodes in the second direction, and is coplanar with a lower surface of a corresponding step among the steps in the third direction. 22 . The vertical memory device of claim 21 , wherein the mold extends along the second direction on the stepped region of the substrate and contacts sidewalls of the plurality of gate electrodes in the second direction.

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