Programmable IMON Accuracy in Power Systems

Abstract

To compensate for inaccuracies in the reported current values ​​output from the voltage regulator (VR) to the processor, the VR can be tested and a load line determined so that the processor can calculate the inaccuracy. This load line can be programmed into the BIOS as an offset, and the BIOS value is used from then on so that the CPU can determine what the true inaccuracy is, rather than the inaccuracy claimed by the VR manufacturer. These values ​​can be used during operation to control CPU turbo mode and CPU throttling.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is derived from and incorporated by reference into U.S. non-provisional application serial number 15 / 717,702, filed on September 27, 2017, and claims priority to that date for all applicable subject matter. Technical Field

[0003] Various embodiments of the present invention relate to the control of the power supply for a computer system. Specifically, signals from a voltage regulator to a processor enable the processor to calculate the voltage it should receive on each rail. Background Art

[0004] For the purposes of this document, IMON is the name of the signal that represents the level of output current for the voltage output of a voltage regulator. Other documents may use other names to describe the same thing. Typically, there is a separate IMON for each VR output voltage (5V, 12V, etc.). Since power equals voltage multiplied by current, the accuracy of the processor's power calculation is directly proportional to the accuracy of the IMON signal. This accuracy can be important. For example, if the processor concludes that it is not consuming its power allocation, the processor may enter Turbo mode, and if the processor determines that it is exceeding its power allocation, the processor may throttle its performance. Therefore, inaccuracies in the IMON signal may cause the processor to perform poorly or exceed its specified performance goals.

[0005] VRs from the same manufacturing batch may have different levels of accuracy. Thus, an OEM may want a VR with an accuracy of + / - 5%, but receive one with an accuracy of only + / - 20%, for example, with the difference reflecting the cost savings in the VR. This difference can result in a performance loss in the associated processor. For example, a more expensive, high-performance processor may only achieve the performance of a cheaper, low-performance processor simply because it incorrectly limits the power it receives from the VR based on inaccurate IMON readings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Some embodiments of the present invention may be better understood by referring to the following description and the accompanying drawings which are used to illustrate embodiments of the present invention. In the drawings:

[0007] Figure 1 A system of multiple voltage regulators (VRs) delivering power to multiple loads is shown.

[0008] Figure 2 A table showing values ​​representing a load line according to an embodiment of the present invention is shown.

[0009] Figure 3A diagram showing two load lines according to some embodiments of the present invention.

[0010] Figure 4 A flow chart illustrating a method for managing power consumption according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0011] In the following description, numerous specific details are set forth. However, it should be understood that embodiments of the present invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail in order to avoid obscuring the understanding of this description.

[0012] References to "one embodiment," "an embodiment," "example embodiment," "embodiments," etc., indicate that the embodiment(s) of the invention described herein may include particular features, structures, or characteristics, but not every embodiment is required to include those particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.

[0013] In the following description and claims, the terms "coupled" and "connected" and their derivatives may be used. It should be understood that these terms are not intended as synonyms for each other. On the contrary, in specific embodiments, "connected" is used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" is used to indicate that two or more elements cooperate with each other or interact with each other, but the two or more elements may or may not have intermediate physical or electrical components between them.

[0014] As used in the claims, unless otherwise specified, the use of ordinal adjectives "first," "second," "third," etc. to describe common elements merely indicates that different instances of similar elements are mentioned and is not intended to imply that the elements so described must be in a given sequence, whether temporally, spatially, in order, or in any other manner.

[0015] Embodiments of the present invention may be implemented in whole or in part in software and / or firmware. The software and / or firmware may take the form of instructions contained in or on a non-transitory computer-readable storage medium. These instructions may be read and executed by one or more processors to enable the execution of the operations described herein. The medium may be internal or external to a device containing (multiple) processors, and may be internal or external to the device performing the operations. The instructions may take any suitable form, such as, but not limited to, source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. Such computer-readable media may include any tangible, non-transitory medium for storing information in a form readable by one or more computers, such as, but not limited to, read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory, and the like.

[0016] Various embodiments of the present invention can utilize programmable load lines to communicate IMON accuracy to a processor. For example, it is possible to convert the IMON accuracy to different load line values ​​and program these values ​​accordingly. For example, if the IMON accuracy is significantly lower than specified, a load line steeper than the actual load line achieved can be programmed. Accordingly, the processor (which believes it has a steeper load line than is actually achieved) can allocate a lower frequency / performance for a given power to avoid over-throttling.

[0017] Similarly, if the IMON has a higher accuracy than specified, a load line that is shallower than actually achieved can be programmed in. Accordingly, the processor (believing it has a load line that is shallower than actually achieved) can allocate a higher frequency / performance for a given power than would otherwise be used.

[0018] Figure 1 A system of multiple voltage regulators (VRs) delivering power to multiple loads is shown. Each VR #1-5 can output a different voltage. Each load #1-4 can represent a different module, circuit, or device that consumes power from one or more of the indicated VRs. The circles indicate which loads are coupled to which VRs in this particular example. For example, VR #1 can deliver its voltage to load #1, VR #2 can deliver its voltage to load #2, VR #3 can deliver its voltage to loads #3 and #4, while VR #4 and VR #5 are not connected to any of the illustrated loads.

[0019] There are various ways to communicate the accuracy of the current (IMON) from the VR to the processor system that uses it. Embodiments of the present invention may communicate this information through a "load line."

[0020] Figure 2A table showing load line values ​​according to an embodiment of the present invention is shown. These values ​​are provided as examples only and do not necessarily represent actual values ​​in a real system. As can be seen in the first column, each row in the table represents a different level of accuracy, with accuracy decreasing as one moves down the table. Similarly, the second column shows the relative cost of each level of accuracy, with decreasing accuracy equating to reduced cost. The number 100% represents the cost of the most expensive IMON. As can be seen in the third column, at 1.5 milliohms, the actual load line achieved is consistent across all examples.

[0021] However, as shown in the fourth column, the CPU (or other device) can program the load line to a different value by adding an offset to the actual implemented load line. As shown, the programmed value of the load line can increase as the accuracy of the IMON decreases, resulting in better performance expectations for a given workload, while the amount of improvement increases as the IMON inaccuracy decreases. Figure 2 In this case, a programmed offset of the IMON with 20% inaccuracy produces only a 10% performance loss.

[0022] Figure 3 Graph showing two load lines according to some embodiments of the present invention. These are shown as examples to illustrate the concepts, but the values ​​shown should not be taken as representative of any real world implementation. Figure 3 The upper line with a shallower slope in the figure may represent an IMON with a higher accuracy. The lower line with a steeper slope may represent an IMON with a lower accuracy relative to the upper line. In actual implementation, a single load line may be used to represent a specific load line of VR, but in Figure 3 Two load lines are shown in FIG. 1 to illustrate their relationship to each other.

[0023] Regarding this figure, the horizontal axis can be interpreted as a percentage of the maximum output current generated by the VR, ranging from 0% to 100%. On the right-hand vertical axis, the frequency loss a% is indicated. In the example shown, the higher accuracy IMON load line corresponds to a frequency loss ranging from 0% at no output current to approximately 5% at 100% output current. Similarly, the lower accuracy IMON load line corresponds to a frequency loss ranging from 0% at no output current to approximately 10% at 100% output current.

[0024] The left-hand vertical axis shows the percentage of gate voltage required for 100% performance, ranging from 100% gate voltage at 0 output current to a smaller amount of gate voltage required for higher output currents. These readings can be mapped to frequency loss percentages by simply drawing a horizontal line across the graph and looking at the percentage of gate voltage and frequency loss percentage where the horizontal line intersects the load line.

[0025] Figure 4 A flow chart illustrating a method of managing power consumption according to an embodiment of the present invention is shown. In flow chart 400, at 410, an original equipment manufacturer (OEM) or other entity may determine a desired IMON accuracy based on a cost-performance tradeoff. Such a tradeoff may be based on, for example, Figure 2 Tables such as those shown in Figure 3 Based on the accuracy and the associated table or chart, the OEM can program the loadline value into the BIOS at 420. In some embodiments, the BIOS and associated VR can be included on the same die. Each wafer can produce multiple dies, each with its own separate VR and BIOS, where the accuracy of the VR and IMON signals is different for each die.

[0026] After the actions at 410 and 420, in some embodiments, the CPU may be in a non-operating state for a period of time, such as when the CPU is being boxed, shipped, and sold. However, when the CPU enters operation, at 430, the CPU may read the programmed load line value and calculate the expected gate voltage based on that programmed load line. At 440, the CPU may determine the maximum turbo setting and / or PL1 frequency based on the programmed values. For the purposes of this document, PL1 refers to the maximum CPU power that the system cooling solution can maintain indefinitely without interruption.

[0027] Example

[0028] The following examples relate to specific embodiments:

[0029] Example 1 includes a device for controlling power, the device comprising a CPU and a memory, wherein the CPU is configured to: read a programmed load line value from a BIOS; calculate an expected gate voltage using the load line value; and determine a maximum turbo mode based on the programmed load line.

[0030] Example 2 includes the apparatus of Example 1, wherein the programmed load line is used to indicate IMON accuracy.

[0031] Example 3 includes the apparatus of Example 1, wherein the programmed load line is to indicate an offset from an implemented load line.

[0032] Example 4 includes a method of power control, the method comprising: reading a programmed load line value from a BIOS; calculating a gate voltage using the load line value; and determining a maximum turbo mode based on the programmed load line.

[0033] Example 5 includes the method of Example 4, wherein the programmed load line is indicative of IMON accuracy.

[0034] Example 6 includes the method of Example 4, wherein the programmed load line indicates an offset from an implemented load line.

[0035] Example 7 includes a computer-readable non-transitory storage medium comprising instructions that, when executed by one or more processors, cause operations to be performed, the operations comprising: reading a programmed load line value from a BIOS; calculating a gate voltage using the load line value; and determining a maximum turbo mode based on the programmed load line.

[0036] Example 8 includes the medium of Example 7, wherein the programmed load line indicates IMON accuracy.

[0037] Example 9 includes the medium of Example 7, wherein the programmed load line indicates an offset from an implemented load line.

[0038] Example 10 includes an apparatus for controlling power, the apparatus configured to: select a first IMON accuracy based on a first cost / performance tradeoff and select a second IMON accuracy based on a second cost / performance tradeoff; program a first load line into a first BIOS based on the selected first IMON accuracy; and program a second load line into a second BIOS based on the selected second IMON accuracy.

[0039] Example 11 includes the apparatus of Example 10, wherein the first BIOS is to be contained on a first die having a first voltage regulator, and the second BIOS is to be contained on a second die having a second voltage regulator.

[0040] Example 12 includes the apparatus of Example 11, wherein the first load line is used to indicate a first IMON accuracy, and the second load line is used to indicate a second IMON accuracy different from the first IMON accuracy.

[0041] Example 13 includes the apparatus of Example 11, wherein the first load line is used to indicate an offset from the implemented load line.

[0042] Example 14 includes a method of controlling power, the method comprising: selecting a first IMON accuracy based on a first cost / performance tradeoff and selecting a second IMON accuracy based on a second cost / performance tradeoff; programming a first load line into a first BIOS based on the selected first IMON accuracy; and programming a second load line into a second BIOS based on the selected second IMON accuracy.

[0043] Example 15 includes the method of Example 14, wherein the first load line indicates a first IMON accuracy, and the second load line indicates a second IMON accuracy different from the first IMON accuracy.

[0044] Example 16 includes the method of Example 14, wherein the first load line indicates an offset from the implemented load line.

[0045] Example 17 includes a computer-readable non-transitory storage medium containing instructions that, when executed by one or more processors, cause operations to be performed, the operations comprising: selecting a first IMON accuracy based on a first cost / performance tradeoff and selecting a second IMON accuracy based on a second cost / performance tradeoff; programming a first loadline into a first BIOS based on the selected first IMON accuracy; and programming a second loadline into the BIOS based on the selected second IMON accuracy.

[0046] Example 18 includes the medium of Example 17, wherein the first load line indicates a first IMON accuracy and the second load line indicates a second IMON accuracy different from the first IMON accuracy.

[0047] Example 19 includes the medium of Example 17, wherein the first load line indicates a deviation from the implemented load line.

[0048] Example 20 includes an apparatus for controlling power, the apparatus comprising means for: reading a programmed load line value from a BIOS; calculating a gate voltage using the load line value; and determining a maximum turbo mode based on the programmed load line.

[0049] Example 21 includes the apparatus of Example 20, wherein the programmed load line includes means for indicating an accuracy of the IMON.

[0050] Example 22 includes the apparatus of Example 20, wherein the programmed load line includes means for indicating an offset from the implemented load line.

[0051] Example 23 includes an apparatus for controlling power, the apparatus comprising means for: selecting a first IMON accuracy based on a first cost / performance tradeoff and selecting a second IMON accuracy based on a second cost / performance tradeoff; programming a first load line into a first BIOS based on the selected first IMON accuracy; and programming a second load line into a second BIOS based on the selected second IMON accuracy.

[0052] Example 24 includes the apparatus of Example 23, wherein the first BIOS is to be contained on a first die having a first voltage regulator, and the second BIOS is to be contained on a second die having a second voltage regulator.

[0053] Example 25 includes the apparatus of Example 23, wherein the first load line includes means for indicating a first IMON accuracy, and the second load line is for indicating a second IMON accuracy different from the first IMON accuracy.

[0054] Example 26 includes the apparatus of Example 23, wherein the first load line is used to indicate an offset from the implemented load line.

[0055] The foregoing description is intended to be illustrative rather than restrictive. Various modifications will occur to those skilled in the art. Those modifications are intended to be included in the various embodiments of the present invention, which are limited only by the scope of the appended claims.

Claims

1. A device for controlling power, the device comprising: A CPU and a memory, wherein the CPU is configured to: Read the programmed load line value from BIOS; calculating an expected gate voltage using the load line value; and Determines the maximum turbo mode based on the programmed load line. The programmed load line is used to indicate the IMON accuracy.

2. The device according to claim 1, wherein The programmed load line indicates the offset from the achieved load line.

3. A power control method, comprising: Read the programmed load line value from BIOS; calculating a gate voltage using the load line value; and Determines the maximum turbo mode based on the programmed load line. The programmed load line indicates the IMON accuracy.

4. The method according to claim 3, wherein: The programmed load line indicates the offset from the achieved load line.

5. A computer-readable non-transitory storage medium comprising instructions that, when executed by one or more processors, cause operations to be performed, the operations comprising: Read the programmed load line value from BIOS; calculating a gate voltage using the load line value; as well as Determines the maximum turbo mode based on the programmed load line. The programmed load line indicates the IMON accuracy.

6. The medium according to claim 5, wherein The programmed load line indicates the offset from the achieved load line.

7. A device for controlling power, the device being configured to: selecting a first IMON accuracy based on a first cost / performance tradeoff, and selecting a second IMON accuracy based on a second cost / performance tradeoff; programming a first load line into the first BIOS based on the selected first IMON accuracy; as well as A second loadline is programmed into the second BIOS based on the selected second IMON accuracy.

8. The apparatus of claim 7, wherein: The first BIOS is intended to be included on a first die having a first voltage regulator, and the second BIOS is intended to be included on a second die having a second voltage regulator.

9. The apparatus of claim 8, wherein: The first load line is used to indicate a first IMON accuracy, and the second load line is used to indicate a second IMON accuracy different from the first IMON accuracy.

10. The apparatus of claim 8, wherein: The first load line is used to indicate a deviation from the realized load line.

11. A method for controlling power, comprising: selecting a first IMON accuracy based on a first cost / performance tradeoff, and selecting a second IMON accuracy based on a second cost / performance tradeoff; programming a first load line into the first BIOS based on the selected first IMON accuracy; as well as A second loadline is programmed into the second BIOS based on the selected second IMON accuracy.

12. The method of claim 11, wherein: The first load line indicates a first IMON accuracy, and the second load line indicates a second IMON accuracy different from the first IMON accuracy.

13. The method of claim 11, wherein: The first load line indicates an offset from the achieved load line.

14. A computer-readable non-transitory storage medium comprising instructions that, when executed by one or more processors, cause operations to be performed, the operations comprising: selecting a first IMON accuracy based on a first cost / performance tradeoff, and selecting a second IMON accuracy based on a second cost / performance tradeoff; programming a first load line into the first BIOS based on the selected first IMON accuracy; as well as A second loadline is programmed into the second BIOS based on the selected second IMON accuracy.

15. The medium of claim 14, wherein The first load line indicates a first IMON accuracy, and the second load line indicates a second IMON accuracy different from the first IMON accuracy.

16. The medium of claim 14, wherein The first load line indicates an offset from the achieved load line.

Images