Conductive via and metal line terminal manufacturing and the structure obtained therefrom

Abstract

Conductive via and metal line termination fabrication is described. In an example, an interconnect structure includes a first interlayer dielectric (ILD) on a hard mask layer, wherein the ILD includes a first ILD opening and a second ILD opening. The interconnect structure also includes an etch stop layer (ESL) on the ILD layer, wherein the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and wherein the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure also includes a first via in the first via opening; a second ILD layer on the first ESL; a metal line in the second ILD layer, wherein the metal line contacts the first via, and wherein the metal line includes a first metal opening, and wherein the metal line includes a second metal opening aligned with the second ILD opening and the second ESL opening to form a second via opening. The interconnect structure also includes a metal line termination in the first metal opening, and further includes a second via in the metal line, wherein the second via is in the second via opening.

Description

Technical Field

[0001] Embodiments of the present disclosure are in the field of semiconductor structures and processing, and more particularly, conductive via and metal line termination fabrication and resulting structures. Background Art

[0002] Over the past several decades, the shrinking of features in integrated circuits has been the driving force behind the growing semiconductor industry. The shrinking to smaller and smaller features enables an increased density of functional units on the limited real estate of a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be included on a chip, resulting in the manufacture of products with increased capacity. But the quest for greater capacity is not without its problems. The necessity to optimize the performance of each device becomes increasingly apparent.

[0003] Integrated circuits typically include conductive microelectronic structures, which are referred to in the art as vias, for electrically connecting metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Integrated circuits may also include non-conductive spaces or discontinuities between metals, which are referred to in the art as metal line terminations. Vias and metal line terminations are typically formed by photolithography. Representatively, for example, with respect to vias, a photoresist layer may be spin-coated on a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and the exposed layer may then be developed to form an opening in the photoresist layer. Next, an opening for a via may be etched in the dielectric layer by using the opening in the photoresist layer as an etching mask. This opening is referred to as a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form a via. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The embodiments will be easily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, the same reference numerals represent similar structural elements. In the figures of the accompanying drawings, the embodiments are shown by way of example and not limitation.

[0005] Figure 1A , 1B , 1C, 1D, 1E, 1F, 1G, 1H, II, 1J, 1K, 1L, 1M and 1N show cross-sectional views of portions of an interconnect structure layer according to an embodiment of the present disclosure, representing various operations involved in the process of forming conductive vias and metal line ends for back-end-of-line (BEOL) interconnect manufacturing.

[0006] Figure 2 An interconnect structure according to an embodiment of the present disclosure is shown.

[0007] Figure 3An integrated circuit with conductive via and metal line termination formation for BEOL interconnect fabrication according to another embodiment of the present disclosure is shown.

[0008] Figure 4 A computing device according to one implementation of an embodiment of the present disclosure is shown.

[0009] Figure 5 An interposer that implements one or more embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0010] In the past, the size and spacing of vias have been progressively reduced, and it is expected that the size and spacing of vias will continue to be progressively reduced in the future, at least for some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.). One measure of via size is the critical dimension of the via opening. One measure of via spacing is via pitch. Via pitch represents the center-to-center distance between the closest adjacent vias.

[0011] When very small vias are patterned at very small pitches using such photolithography processes, several challenges of their own are present, especially when the pitch is about 70-90 nanometers (nm) or less and / or when the critical dimension of the via opening is about 35 nm or less. One such challenge is that the overlap between the via and the overlying interconnect and the overlap between the via and the underlying land interconnect typically needs to be controlled to a high tolerance on the order of one-quarter of the via pitch. As the via pitch continues to shrink over time, the overlay tolerance tends to shrink along with it at a rate even faster than the photolithography equipment can keep up.

[0012] Another such challenge is that the critical dimensions of via openings typically tend to shrink faster than the resolution capabilities of lithography scanners. Scaling techniques exist to shrink the critical dimensions of via openings. But the amount of shrinkage is often limited by the minimum via pitch, and the ability to shrink the process so that it is sufficiently optical proximity correction (OPC) neutral and does not significantly compromise line width roughness (LWR) and / or critical dimension uniformity (CDU).

[0013] Yet another such challenge is that the LWR and / or CDU characteristics of a photoresist generally need to be improved as the critical dimensions of the via openings decrease in order to maintain the same overall ratio of the critical dimension budget. However, currently, the LWR and / or CDU characteristics of most photoresists do not improve as fast as the critical dimensions of the via openings decrease.

[0014] Another such challenge is that extremely small via pitches are often below the resolution capabilities of even extreme ultraviolet (EUV) lithography scanners. As a result, several different lithography masks are often used, which tends to increase costs. At a certain point, if the pitch continues to decrease, it will become impossible to use EUV scanners to print via openings for these extremely small pitches, even with the aid of multiple masks.

[0015] Another such challenge is related to edge placement errors. Interconnect structures often require a single etch stop layer between critical layers. In the patterning process, etching a via from the layer above often requires penetrating the etch stop layer to land on the metal below the via. Lithographic limitations introduced by shrinking (e.g., resolution and alignment) can cause the via pattern to be too large and may undesirably land on two adjacent metal lines, which can be referred to as edge placement errors.

[0016] Thus, there is a need for improvements in the art of back end metallization manufacturing for fabricating conductive vias and metal line terminations.

[0017] Conductive via and metal line termination fabrication and the resulting structures are described. In the following description, many specific details are set forth, such as specific integration and material schemes, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other cases, in order to avoid unnecessarily obscuring the embodiments of the present disclosure, well-known features such as integrated circuit design layouts are not described in detail. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0018] Certain terms may also be used in the following description for reference purposes only and are therefore not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below," and "under" refer to directions referenced in the accompanying drawings. Terms such as "front," "rear," "top," "bottom," "rear," and "side" describe the orientation and / or position of components within a consistent but arbitrary reference system, which is made clear by reference to the text and related drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0019] One or more embodiments relate to the manufacture of conductive vias and metal line ends. As described in more detail below, in combination with alternating lower layers, a pinhole ashing patterning process can be used to pattern single inlaid gate vias, metal line ends, and dual inlaid diffusion vias, which may also be referred to as trench vias. By definition, a conductive via or via falls on a previous layer of metal pattern, while a metal line end or line end forms a non-conductive space in the metal line. In this case, due to the relaxation of restrictions on lithographic equipment, the embodiments described herein achieve a more robust interconnect manufacturing scheme. This interconnect manufacturing scheme can be used to save a lot of alignment / exposure, and can be used to reduce the total process operations and processing time, which would otherwise be required to pattern such components using conventional methods, for example, including the patterning of alternating lower layers and the separate formation of metal lines, vias, and line ends. Other benefits can include improving yield, or preventing short circuits to the wrong line due to, for example, edge placement errors.

[0020] Figure 1A-1N Cross-sectional views of portions of an integrated circuit layer according to an embodiment of the present disclosure are shown, representing various operations in a process involving formation of conductive vias and metal line ends for BEOL interconnect fabrication. In the illustrations of the described operations, for some operations, a top view illustrating a cross-grid may be shown on the left, a front cross-sectional view may be shown on the upper right, and a side cross-sectional view may be shown on the lower right. These views may be referred to herein as top views and cross-sectional views. In addition, a figure may include one or more elements that have a reference number in one figure but may not be repeated in subsequent figures, in which case the previous reference number applies to any subsequent instance of the element in a figure that does not include the previously shown reference number.

[0021] refer to Figure 1A , forming an interconnect structure 100 including a first cross-grid structure 102 as a starting point for fabricating conductive vias and metal line terminations. The first cross-grid structure 102 may include a first sacrificial cross-grid 104 on a first film stack 110. The first sacrificial cross-grid 104 may include a first cross-grid material 106, such as but not limited to a metal, such as but not limited to aluminum, titanium, zirconium, or tantalum; various oxides, nitrides, or carbides, such as but not limited to aluminum oxide, titanium oxide, zirconium oxide, tantalum oxide, titanium nitride, tantalum nitride, silicon nitride, silicon carbide, or silicon dioxide; or a semiconductor, such as but not limited to amorphous silicon. For example, the material for the sacrificial cross-grid 104 may be selected based at least in part on the etch selectivity.

[0022] The first film stack 110 may include a first sacrificial layer 112, which may include a first sacrificial material; on a first interlayer dielectric (ILD) layer 114, which may include a first ILD material; and on a hard mask layer 116, which may include a hard mask material. Although shown as a single layer, the first sacrificial layer 112 may include more than one layer, and each layer may include the same material as another layer or a different material than another layer. Additionally or alternatively, a portion of the first sacrificial layer 112 may be or become part of the sacrificial cross grid 104. The first sacrificial layer 112 may include materials such as, but not limited to, metals, such as, for example, but not limited to, aluminum, titanium, zirconium, or tantalum; various oxides, nitrides, or carbides, such as, but not limited to, aluminum oxide, titanium oxide, zirconium oxide, tantalum oxide, titanium nitride, tantalum nitride, silicon nitride, silicon carbide, or silicon dioxide; or semiconductors, such as, but not limited to, amorphous silicon. For example, the material for the first sacrificial layer 112 may be selected based at least in part on the etch selectivity.

[0023] The hard mask layer 116 may include a first via guide portion 116A adjacent to a second via guide portion 116B. The hard mask material of the first via guide portion 116A is a hard mask material different from the hard mask material of the second via guide portion 116B and the hard mask layer 116. Representatively, the hard mask material of the second via guide portion 116A may include a dielectric material that is chemically different from the material of the first via guide portion 116A and the hard mask layer 116 sufficiently to allow the hard mask material of the second via guide portion 116B to be selectively etched relative to the first via guide portion 116A and the hard mask layer 116. Representative dielectric materials may include, but are not limited to, various oxides, nitrides, and carbides, such as silicon oxide, titanium oxide, hafnium oxide, aluminum oxide, oxynitride, zirconium oxide, hafnium silicate, lanthanum oxide, silicon nitride, boron nitride, amorphous carbon, silicon carbide, and other similar dielectric materials. For example, in the case where the hard mask layer 116 may be formed using silicon oxide, and the first via guide portion 116A may include silicon nitride, the second via guide portion 116B may include silicon carbide.

[0024] Thus, the resulting structure 100 may include a hard mask layer 116 having first via guide portions 116A of one hard mask material alternating with second via guide portions 116B of another, different hard mask material. Additionally, each of the first via guide portions 116A and the second via guide portions 116B may be separated by a third hard mask material (i.e., the material of the hard mask layer 116) that is different from the hard mask material of each of the via guide portions 116A and 116B. In this regard, a hard mask layer 116 having at least three different hard mask materials having different etch selectivities all within a single hard mask layer may be formed. The at least three different hard mask materials may alternate throughout the hard mask layer 116 such that no two identical hard mask materials contact each other within the hard mask layer 116. Although described as using three different materials in the hard mask layer 116, the hard mask layer 116 may include more or fewer materials.

[0025] In an embodiment, the first via guide portion 116A or the second via guide portion 116B may be a gate via guide portion, such as a guide portion for a gate contact of a metal oxide semiconductor field effect transistor (MOSFET) device. In an embodiment, the first via guide portion 116B or the second via guide portion 116B may be a diffusion via guide portion, such as a guide portion for a diffusion contact, such as a source or drain contact of a MOSFET device. Although the via guide portions 116A and 116B may be described with respect to MOSFET devices, the embodiments herein are not limited to MOSFET devices. The embodiments herein may be used with any other type of device, such as, but not limited to, a bipolar junction transistor (BJT) device. In such an embodiment, the first via guide portion 116A or the second via guide portion 116B may be a base contact, an emitter contact, or a collector contact via guide portion. Figure 1A Further shown is a semiconductor substrate 120 which may include a gate contact 122 and a diffusion contact 124 which may be, for example, a source or a drain of a MOSFET device.

[0026] The first sacrificial cross-grid 104 may include a plurality of potential gate via locations 130, which may include gate via placeholder material 132. The potential gate via locations 130 may be locations where all possible gate vias may be formed in the first cross-grid structure 102. The first sacrificial cross-grid 102 may also include activated gate via locations 140, which may be a subset of the potential gate via locations 130, which may include gate via openings 142 from which the gate via placeholder material 132 has been removed. The first cross-grid material 106 may surround the potential gate via locations 130 and the activated gate via locations 140.

[0027] In an embodiment, the gate via placeholder material 132 may be removed at the potential gate via location 130 by an isotropic etching process. In one such embodiment, the gate via placeholder material 132 may be an organic polymer, such as a carbon hard mask (CHM), and the isotropic etching process, which may be referred to as "pinhole ashing," may be an isotropic plasma ashing (oxygen plasma) or a wet cleaning process. Thus, the isotropic etching process may be used in conjunction with a hole shrinking process, wherein the pinholes are patterned in, for example, a mask layer (e.g., a relatively thin low temperature oxide mask layer) formed on an underlying structure. The openings in the mask layer may be substantially smaller than the exposed sacrificial placeholder material. The formation of an opening that may be relatively smaller than the exposed placeholder material may provide significantly increased tolerance to edge placement errors. Relative to the selection and patterning of the actual via location, the process effectively "shrinks" the via location to the size of the "pinhole." In an embodiment, the mask layer may be patterned with openings by first forming and patterning a photosensitive material on the mask layer by a photolithography process such as a positive photolithography process, and then patterning the mask layer by an etching process. This process may be referred to as a pinhole ashing process.

[0028] The subset of potential gate via locations 140 may include any number of potential gate via locations from one potential gate via location to all potential gate via locations 130. In addition, the orthogonal lines in the first sacrificial cross grid 104 that intersect to form the potential gate via locations 130 may be spaced apart at a constant pitch and have a constant width. In other embodiments, the pitch need not be constant and the width need not be constant. It should be understood that the sacrificial cross grid 104 may be manufactured by a variety of methods, including but not limited to, for example, a pitch halving method, a pitch quartering method, 193nm immersion lithography (193i), extreme ultraviolet (EUV) and / or electron beam direct write (EBDW) lithography, directed self-assembly (DSA), directed selective growth, and the like.

[0029] Used to form Figure 1A The cross grid structure and the following Figure 1E and 1H Process operations for the cross-grid structure in the embodiment of the present invention may involve depositing layers to create lines that intersect to form a plurality of potential via or plug locations, etching through the layers to identify a subset of potential via or plug locations. The layers may include a cap directly on the line through which a final etch may be performed to identify a subset of potential via or plug locations, remove placeholder material therefrom, and create an airtight seal to protect unidentified locations in the subset of potential via or plug locations from the etching plasma. In addition, the embodiment of the present invention may include a cap directly on the line through which a final etch may be performed to identify a subset of potential via or plug locations, remove placeholder material therefrom, and create an airtight seal to protect unidentified locations in the subset of potential via or plug locations from the etching plasma. Figure 1A and the following Figure 1EThe description or drawings of the cross-grid structures in FIG. 1 and II may not include various layers or process operations that may be necessary to form the sacrificial cross-grid. However, for the sake of clarity, such layers or process operations may not be included because they do not affect the overall concept. Similarly, in the embodiments of the present invention, layers, features, or other aspects may be hidden or may be in the background. However, for the sake of clarity, such layers, features, or other aspects may not be included, described, or shown because they do not affect the overall concept.

[0030] refer to Figure 1B , the first film stack material may be removed from the bottom of the activated gate via location 140. In an embodiment, the first film stack material may be removed up to a gate via guide portion, such as the second via guide portion 116B, where the gate via guide portion is above or beside a gate contact, such as the gate contact 122. In an embodiment, the first film stack material may be removed up to a gate contact, such as the gate contact 122 below or beside the first via guide portion 116A or the second via guide portion 116B. In an embodiment, removing the first stack material from the bottom of the activated first via location 140 may include applying an anisotropic etching technique. In an embodiment, applying an anisotropic etching technique may include using a dry etching process. The etching process may be anisotropic, meaning that material accessible in the activated first via location 140 may be selectively etched in a particular direction, such as toward the hard mask layer 116. This may enable, for example, the ability to define features that may include straight or relatively straight edges so as to avoid, for example, creating electrical shorts with adjacent features.

[0031] refer to Figure 1C , the activated gate via location 140 may be filled with a first conductive material 150 to form a gate via 160. In an embodiment, the first conductive material may be composed of materials such as, but not limited to, aluminum, titanium, zirconium, hafnium, vanadium, ruthenium, cobalt, nickel, palladium, platinum, copper, tungsten, or gold, silver, or alloys thereof. In an embodiment, the gate via may be formed by a single damascene metallization process. In a single damascene metallization process, metal features, such as metal lines and vias, may each be formed in a separate process operation.

[0032] In an embodiment, the activated gate via location 140 may be filled with an excess of conductive material 150, and a subsequent polishing operation and a planarization operation may be performed. In the case of planarizing the excess conductive material 150 after deposition, a chemical mechanical polishing (CMP) process may be used. However, in another embodiment, the activated via location 140 is filled with a non-metallic overfill, and the polishing operation is omitted. In an embodiment, the conductive material 150 may be a single material layer, or may be formed of several layers including a conductive liner layer and a filling layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, physical vapor deposition, or spin coating, may be used to fill the activated gate via location 140 with the conductive material 150.

[0033] refer to Figure 1D , the first sacrificial cross grid 104 may be removed to expose a surface 170 of the first ILD layer 114 and a surface 162 of the gate via 160 in the first ILD layer 114, wherein removing the first sacrificial cross grid 104 may include removing a remaining portion of the first film stack 110 above the first ILD layer 114. The surface 170 of the first ILD layer 114 and the surface 162 of the gate via 160 may be planarized after removing the first sacrificial cross grid 104. In an embodiment, removing the first sacrificial cross grid 104 may include applying an isotropic etching technique. In an embodiment, applying an isotropic etching technique may include using a wet etch. The etching process may be isotropic, meaning that material may be etched in more than one direction to remove material wherever it is exposed.

[0034] refer to Figure 1E , a second cross-grid structure 202 may be formed on the surface 170 of the first ILD layer 114. The second cross-grid structure 202 may include a second sacrificial cross-grid 204 on the second film stack 210. The second sacrificial cross-grid 204 may include a first portion 204A and a second portion 204B. The second sacrificial cross-grid 204 may include a second cross-grid material 206, such as, but not limited to, aluminum, titanium, zirconium, or tantalum; various oxides, nitrides, or carbides, such as, but not limited to, aluminum oxide, titanium oxide, zirconium oxide, tantalum oxide, titanium nitride, tantalum nitride, silicon nitride, silicon carbide, or silicon dioxide; or a semiconductor, such as, but not limited to, amorphous silicon. For example, the material for the sacrificial cross-grid 204 may be selected based at least in part on the etch selectivity.

[0035] The second sacrificial cross grid 204 may include a plurality of potential plug locations 230, which may include plug placeholder material 232. The potential plug locations 230 may be locations where all possible plugs and metal line ends may be formed in the second cross grid structure 202. The second sacrificial cross grid 204 may further include a subset of the potential plug locations 230, which are activated plug locations 240, which may include plug openings 242 from which the plug placeholder material 232 has been removed. The second cross grid material 206 may surround the potential plug locations 230 and the activated plug locations 240.

[0036] The subset of potential plug locations 240 may include any number of potential plug locations from one potential plug location to all potential plug locations 230. In addition, the orthogonal lines in the second sacrificial cross grid 204 that intersect to form the potential plug locations 240 may be spaced apart at a constant pitch and have a constant width. In other embodiments, the pitch need not be constant, and the width need not be constant. It should be understood that the second sacrificial cross grid 204 may be manufactured by a variety of methods, including but not limited to a pitch-halving method, a pitch-quartering method, 193nm immersion lithography (193i), extreme ultraviolet (EUV) and / or electron beam direct write (EBDW) lithography, directed self-assembly (DSA), directed selective growth, etc.

[0037] The second film stack 210 may include a second sacrificial layer 212, which may include a second sacrificial layer material; on a second ILD layer 214, which may include a second ILD layer material; on an etch stop layer (ESL) 216, which may include an ESL material, which may also be referred to herein as an ES material. The ESL material may include a dielectric material, which may include, but is not limited to, various oxides, nitrides, and carbides, such as silicon oxide, titanium oxide, hafnium oxide, aluminum oxide, oxynitride, zirconium oxide, hafnium oxide, lanthanum oxide, silicon nitride, boron nitride, amorphous carbon, silicon carbide, and other similar dielectric materials. Although shown as a single layer, the second sacrificial layer 212 may include more than one layer, and each layer may include the same or different material as another layer. Additionally or alternatively, a portion of the second sacrificial layer 212 may be or become part of the second sacrificial cross grid 204. The second sacrificial layer 212 may include materials such as, but not limited to, metals such as, but not limited to, aluminum, titanium, zirconium, or tantalum; various oxides, nitrides, or carbides such as, but not limited to, aluminum oxide, titanium oxide, zirconium oxide, tantalum oxide, titanium nitride, tantalum nitride, silicon nitride, silicon carbide, or silicon dioxide; or semiconductors such as, but not limited to, amorphous silicon. For example, the material for the second sacrificial layer 212 may be selected based at least in part on the etch selectivity.

[0038] refer to Figure 1F, the activated plug position 240 can be filled with a plug placeholder material 250 to form a plug 260. The plug placeholder material 250 can be any material suitable for forming a plug, such as an oxide. In an embodiment, the activated plug position 240 can be filled with an excess of plug placeholder material 250, and a subsequent polishing operation and a planarization operation can be performed. In the case of planarizing the plug placeholder material 250 after deposition, a CMP process can be used. However, in another embodiment, the activated plug position 240 is filled with a non-metallic overfill, and the polishing operation is omitted. In an embodiment, the plug placeholder material 250 can be a single material layer, or can be formed of several layers. Any suitable deposition process, such as electroplating, chemical vapor deposition, physical vapor deposition, or spin coating, can be used to fill the activated plug position 240 with the plug placeholder material 250.

[0039] refer to Figure 1G , the second portion 204B of the second sacrificial cross grid 204 may be removed to form a metal line end 270 under the plug 260 in the first portion 204A of the second sacrificial cross grid 204, wherein the metal line end 270 may include the ILD material 214X of the second ILD layer 214, and further form an ILD line 280 on the surface 290 of the ESL 216, wherein the ILD line 280 also includes the ILD material 214X. In addition, the second sacrificial layer material 212X may be located between the plug placeholder material 250 and the second ILD layer material 214X on both the metal line end 270 and the ILD line 280. Removing the first portion of the second sacrificial cross grid 204 may transfer the pattern for the plug 260 into the second ILD layer 214. In an embodiment, removing a portion of the second sacrificial cross grid 204 may include applying an isotropic etching technique. In an embodiment, applying the isotropic etching technique may use a wet etching process. In an embodiment, plug 260 and metal line end 270 may include sidewalls, and a liner may be deposited by, for example, atomic layer deposition to protect the sidewalls from damage due to subsequent processing.

[0040] refer to Figure 1H , a third cross-grid structure 302 may be formed on the ESL 216. The third cross-grid structure 302 may include a third sacrificial cross-grid 304. The third sacrificial cross-grid 304 may include a third cross-grid material 306, such as but not limited to a metal, such as but not limited to aluminum, titanium, zirconium, or tantalum; various oxides, nitrides, or carbides, such as but not limited to aluminum oxide, titanium oxide, zirconium oxide, tantalum oxide, titanium nitride, tantalum nitride, silicon nitride, silicon carbide, or silicon dioxide; or a semiconductor, such as but not limited to amorphous silicon. For example, the material for the sacrificial cross-grid 304 may be selected based at least in part on the etch selectivity.

[0041] The third sacrificial cross-grid 304 may include a plurality of potential diffusion via locations 330, which may include diffusion via placeholder material 332. The potential diffusion via locations 330 may be locations where all possible diffusion vias may be formed in the third cross-grid structure 302. The third sacrificial cross-grid 304 may further include a subset of the potential diffusion via locations 330, which are activated diffusion via locations 340, which may include diffusion via openings 342 from which the diffusion via placeholder material 332 has been removed. The third cross-grid material 306 may surround the potential diffusion via locations 330 and the activated diffusion via locations 340.

[0042] The subset of potential diffusion via locations 340 may include any number of potential diffusion via locations from one potential diffusion via location to all potential diffusion via locations 330. In addition, the orthogonal lines in the third sacrificial cross grid 304 that intersect to form the potential diffusion via locations 340 may be spaced apart at a constant pitch and have a constant width. In other embodiments, the pitch need not be constant, and the width need not be constant. It should be understood that the third sacrificial cross grid 304 may be manufactured by a variety of methods, including but not limited to a pitch-halving method, a pitch-quartering method, 193nm immersion lithography (193i), extreme ultraviolet (EUV) and / or electron beam direct write (EBDW) lithography, directed self-assembly (DSA), directed selective growth, and the like.

[0043] Referring to FIG. II, the ESL material and the ILD material may be removed from the bottom of the activated diffusion via location 340 to the diffusion via guide portion (e.g., the first via guide portion 116A) of the hard mask layer 116. In an embodiment, the removal of the ESL material and the ILD material from the bottom of the activated second via location 340 to the diffusion via guide portion of the hard mask layer 116 may include applying an anisotropic etching technique. In an embodiment, applying the anisotropic etching technique may include using a dry etching process. In another embodiment, the removal of the ESL material and the ILD material from the bottom of the activated second via location 340 to the first via guide portion 116B of the hard mask layer 116 may include applying an isotropic etching technique. In an embodiment, applying the isotropic etching technique may use a wet etching process.

[0044] refer to Figure 1J , a diffusion via placeholder material 350 may be deposited in the activated diffusion via locations 340. The diffusion via placeholder material may be, for example, CHM.

[0045] refer to Figure 1K, removing the third sacrificial cross grid 304 to form trenches 360 between the ILD lines 280 on the surface 290 of the ESL 216. In an embodiment, removing the third sacrificial cross grid 304 may include applying an isotropic etching technique. In an embodiment, applying the isotropic etching technique may use a wet etching process.

[0046] refer to Figure 1L , a diffusion via guide portion under the activated diffusion via location 340, which may be, for example, the first via guide portion 116A, may be removed. In an embodiment, removing the diffusion via guide portion under the activated diffusion via location 340 may include applying an anisotropic etching technique. Removing the ESL 216 between the ILD lines 280 may result in the ESL material 216X of the ESL 216 under the second ILD material 214X in the ILD line 280 becoming part of the ILD line 280 and becoming part of the metal line end 270.

[0047] refer to Figure 1M , the activated diffusion via location 340 and the trench 360 may be filled with a second conductive metal 370 to form a diffusion via 380 and a metal line 390, respectively, wherein the surface 162 of the gate via 160 is in contact with the metal line 390. In an embodiment, the diffusion via 380 and the metal line 390 may be formed by a dual damascene metallization process. In a dual damascene metallization process, metal features, such as vias or metal lines, may be formed separately like a single damascene metallization process. However, the metal features may be filled with metal at the same time, rather than filling one metal feature in one operation and another metal feature in another operation. Filling the metal features simultaneously may result in a reduced number of process operations, and may enable self-alignment of the vias and metal lines, since the cross-grid pattern forming the trench for the metal line 390 may be reused as a template to produce the diffusion via 380. Filling the metal features simultaneously may also reduce resistance caused by the metal barrier / seed deposition necessary to prevent electromigration and provide seeds for metal deposition. The metal barrier / seed layer is typically more resistive than the metal (eg, copper) that may be used to form vias or metal lines.

[0048] In an embodiment, the activated diffusion via location 340 may be filled with an excess of the second conductive material 370, and a subsequent polishing operation and a planarization operation may be performed. In the case of planarizing the excess second conductive material 370 after deposition, a chemical mechanical polishing (CMP) process may be used. However, in another embodiment, the activated via location 340 is filled with a non-metallic overfill, and the polishing operation is omitted. In an embodiment, the second conductive material 370 may be a single material layer, or may be formed of several layers including a conductive liner layer and a filling layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, physical vapor deposition, or spin coating, may be used to fill the activated gate via location 340 with the second conductive material 370.

[0049] refer to Figure 1N , the remaining second sacrificial layer material 212X may be removed to expose the surface 282 of the ILD line 280, the surface 382 of the diffusion via 380, and the surface 392 of the metal line 390, wherein removing the remaining second sacrificial layer 212 may include removing the plug 260. After removing the second sacrificial layer remaining on the ILD line 280, the surface 282 of the ILD line 280, the surface 382 of the diffusion via 380, and the surface 392 of the metal line 390 may be planarized. In an embodiment, a chemical mechanical polishing (CMP) process may be used to remove the second sacrificial layer 212 remaining on the ILD line 280.

[0050] Although embodiments herein may be described in terms of a plurality of vias, metal line terminations, metal lines, or ILD lines, embodiments herein may include a single via, a single metal line termination, a single metal line, or a single ILD line. Although embodiments herein may be described in terms of a single via, metal line termination, metal line, or ILD line, embodiments herein may include any number of vias, metal line terminations, metal lines, or ILD lines. Although embodiments herein may be described as including a particular number of vias, metal line terminations, metal lines, or ILD lines, embodiments herein may include any number of vias, metal line terminations, metal lines, or ILD lines.

[0051] Although the embodiments of the present invention may be described in terms of gate vias and gate contacts of MOSFET devices, or in terms of diffusion vias for diffusion contacts (such as the source or drain of a MOSFET device), the embodiments of the present invention are not limited to MOSFET devices. The embodiments of the present invention may be used with any other type of device, which may be used with an interconnect structure such as interconnect structure 100. Such other types of devices may include, for example, but not limited to, BJT devices. In such embodiments, the vias described herein may be base contact vias, emitter contact vias, or collector contact vias. In addition, in embodiments, the vias may be generally referred to as first vias, second vias, etc.

[0052] Figure 2 A cross-sectional view of an interconnect structure for an integrated circuit according to an embodiment of the present disclosure is shown. In an embodiment, the interconnect structure 200 may include an ILD layer 204A on a hard mask layer 202A, wherein the ILD layer 204A may include a first ILD layer opening (not shown) and a second ILD layer opening (not shown). An ESL 206A may be on the ILD layer 204A. The ESL layer 206A may include a first ILD material 206B, and the ESL 206A may include a first ESL opening (not shown) aligned with the first ILD opening to form a gate via opening (not shown). The ESL 206A may further include a second ILD opening (not shown) aligned with the second ILD opening.

[0053] The interconnect structure 200 may further include a gate via 208A in the first via opening, wherein the gate via 208A may include a first metal fill 208B, as described above. The interconnect structure 200 may further include a second ILD layer (not shown) on the ESL 206A, wherein the second ILD layer may include a second ILD material (not shown). The interconnect structure 200 may further include a metal line 212A in the second ILD layer, wherein the metal line 212A contacts the gate via, and wherein the metal line 212A may include a first metal opening (not shown), and wherein the metal line 212A may include a second metal opening (not shown) aligned with the second ILD opening and the ESL opening to form a second via opening (not shown).

[0054] The interconnect structure 200 may further include a metal line end 220A in the first metal opening to electrically isolate the first portion 212C of the metal line 212A from the second portion 212D of the metal line 212A using the first metal opening, wherein the metal line end 220A may include a third dielectric material 220B and an ES material 220C between the first ESL 206A and the second dielectric material 220B. The interconnect structure 200 may further include a diffusion via 230A in the second via opening, wherein the diffusion via may include a second metal filler 212B.

[0055] In an embodiment, the first via is a gate via and the second via is a diffusion via. In an embodiment, the ESL 206A may include a metal oxide. In an embodiment, the first ILD layer 204A and the second ILD layer 212A may include the same dielectric material. In an embodiment, the second ILD layer 212A and the metal line end 220A may include the same dielectric material. In an embodiment, the ES material may include a metal oxide. In an embodiment, the first metal filler 212B and the second metal filler 220B may include, for example but not limited to, aluminum, titanium, zirconium, hafnium, vanadium, ruthenium, copper, nickel, palladium, platinum, copper, tungsten, gold or silver or an alloy thereof. In an embodiment, the hard mask layer 202A may include a first material 202B adjacent to a second material 202C, wherein the first material 202B can remain if the second material 202C is etched, and wherein the second material 202C can remain if the first material 202B is etched.

[0056] Figure 3 , a cross-sectional view of an integrated circuit structure is shown. The integrated circuit structure 300 may include a first ILD layer 304A on a hard mask layer 302A, wherein the hard mask layer may include a first material 302B adjacent to a second material 302C, wherein the first material 302B can remain if the second material 302C is removed, for example, by etching, and wherein the second material 302C can remain if the first material 302B is removed, for example, by etching. The integrated circuit structure 300 may further include an ESL 306A on the first ILD layer 304A. The integrated circuit structure 300 may further include a gate via 308A passing through a first alignment opening (not shown) in the first ILD layer 304A and the ESL 306A. The integrated circuit structure 300 may further include a second ILD layer (not shown) on the ESL 306A.

[0057] The integrated circuit structure 300 may further include a metal line 312A in the second ILD layer, wherein the metal line 312A contacts the gate via 308A. The integrated circuit structure 300 may further include a metal line end 320A in the metal line 312A to electrically isolate the first portion 312C of the metal line from the second portion 312D of the metal line 312A. The integrated circuit structure 300 may further include a diffusion via 330A passing through the metal line 312A, the ESL 306A, and the second alignment opening (not shown) in the first ILD layer 304A.

[0058] The integrated circuit structure 300 may further include a semiconductor device 330A. The semiconductor device 330A may include a semiconductor substrate 332A, a gate contact 340A on the semiconductor substrate 332A, wherein the gate via 308A contacts the gate contact 340A by removing a portion of the first material 302B in the metal layer 302A. The semiconductor device 330A may further include a diffusion contact 350A on the semiconductor substrate 330A, wherein the diffusion via 330A contacts the diffusion contact 350A by removing a portion of the second material 302C in the metal layer.

[0059] Then you can combine Figure 1N or Figure 2 The resulting structure described is used as the basis for forming subsequent vias and metal line terminations. Figure 1N or Figure 2 The structure may represent a final metal interconnect layer in an integrated circuit. It should be understood that the above process operations may be practiced in an alternative order, without necessarily performing each operation and / or additional process operations may be performed. Although the above process for fabricating conductive vias and metal line terminations for BEOL interconnect structures has been described in detail with respect to selected operations (e.g., Figure 1A-1N ), but it should be understood that additional or intermediate operations used for manufacturing may include standard microelectronic manufacturing processes, such as lithography, etching, thin film deposition, planarization (e.g., chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, and / or any other operation related to the manufacture of microelectronic components. For the above process flow that may use spacer-based spacing partitioning, the application of directed self-assembly (DSA) processes may be used instead in one or more locations in the process flow. In any case, the resulting structure enables the manufacture of vias directly located at the center of the underlying metal line, which may be referred to as self-aligned vias. That is, the via may be wider, narrower, or the same thickness as the underlying metal line, for example due to an imperfect selective etching process. However, in an embodiment, the center of the via may be directly aligned (matched) with the center of the metal line. Thus, in an embodiment, offsets caused by conventional lithography / dual mosaic patterning that would otherwise have to be accommodated are not a factor in the resulting structure described herein.

[0060] The above embodiments can be implemented to achieve strong self-alignment and alleviate edge placement issues that would otherwise plague conventional patterning methods. Thus, adjacent metal features have different etch stop materials so that even if the via pattern spans adjacent metal lines, selective via etching drives the via to fall on the correct metal line below the via. Embodiments can be implemented to enable the integration of pinhole ash patterning processes, single damascene metallization processes, and dual damascene metallization processes and colored lower layers. This can be demonstrated, for example, by vias and metal line ends manufactured using single and dual damascene metallization processes and dual-layer ILD stacks and additional etch stop layers relative to conventional interconnect structures. For example, this enables the integration of pre-formed vias and plugs onto a hard mask layer with a selected via guide portion using an isotropic etching process, and combines a single damascene metallization process with a dual damascene metallization process. Therefore, embodiments can be implemented to enable the integration of pinhole ash patterning processes and patterned gate vias and diffusion vias, and the vias do not have to be patterned in a separate etching process. Embodiments may be implemented to achieve robust interconnect reliability and low via / contact resistance.

[0061] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material may consist of or may include a layer of a dielectric material or an insulating material. Examples of suitable dielectric materials may include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), nitrides of silicon (e.g., silicon nitride (Si3N4)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The ILD material may be formed by conventional techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition techniques.

[0062] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. A common example is a structure using a copper line and a barrier layer that may or may not include copper and the surrounding ILD material. As used herein, the term metal may include alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer, a stack or alloy of different metals, etc. Therefore, the interconnect may be a single material layer, or may be formed by several layers including a conductive liner layer and a filling layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition may be used to form the interconnect. In an embodiment, the interconnect is composed of a barrier layer and a conductive filling material. In one embodiment, the barrier layer is a tantalum or tantalum nitride layer, or a combination thereof. In one embodiment, the conductive filling material is a material such as, but not limited to, copper, aluminum, titanium, zirconium, hafnium, vanadium, ruthenium, cobalt, nickel, palladium, platinum, tungsten, silver, or gold or its alloy. Interconnects are sometimes also referred to as traces, wires, lines, metals, metal lines, or simply interconnects in the art.

[0063] In an embodiment, as also used throughout this specification, a hard mask material (and in some cases an etch stop layer) is composed of a material different from the interlayer dielectric material. In one embodiment, different hard mask materials may be used in different regions to provide different growth or etching selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer may include a silicon nitride layer (e.g., silicon nitride) or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials, such as silicon carbide. In another embodiment, the hard mask material may include a metallic substance. For example, a hard mask or other covering material may include a nitride layer (e.g., titanium nitride) of titanium or another metal. Potentially smaller amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hard mask layers known in the art may be used, depending on the particular embodiment. The hard mask layer may be formed by CVD, PVD, or by other deposition techniques.

[0064] It should be understood that Figure 1A-1NThe layers and materials described in , 2, and 3 are typically formed on or above an underlying semiconductor substrate or structure, such as one or more underlying device layers of an integrated circuit. In an embodiment, the underlying semiconductor substrate represents a common workpiece used to manufacture integrated circuits. The semiconductor substrate typically includes a wafer or other silicon chip or another semiconductor material. Suitable semiconductor substrates may include, but are not limited to, single crystal silicon, polycrystalline silicon, silicon on insulator (SOI), and compound semiconductors, such as gallium arsenide (GaAs) or other III-V semiconductor substrates, as well as similar substrates formed from other semiconductor materials. Depending on the stage of manufacturing, semiconductor substrates typically include transistors, integrated circuits, etc. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. In addition, the lower level interconnect layers may be manufactured on the underlying Figure 1N The structure shown in (i.e., from Figure 1A start).

[0065] The embodiments disclosed herein can be used to manufacture a variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memories can be manufactured. Moreover, the integrated circuits or other microelectronic devices can be used in various electronic devices known in the art. For example, in computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic devices, etc. The integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0066] Figure 4 A computing device 400 is shown in accordance with one embodiment of the present disclosure. The computing device 400 houses a board 402. The board 402 may include a number of components, including, but not limited to, a processor 404 and at least one communication chip 406. The processor 404 is physically and electrically coupled to the board 402. In some embodiments, the at least one communication chip 406 is also physically and electrically coupled to the board 402. In further embodiments, the communication chip 406 is part of the processor 404.

[0067] Depending on its application, computing device 400 may include other components that may or may not be physically and electrically coupled to board 402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, encryption processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0068] The communication chip 406 implements wireless communication for transmitting data to and from the computing device 400. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through non-solid media by using modulated electromagnetic radiation. The term does not imply that the relevant devices do not contain any wires, although in some embodiments they may not. The communication chip 406 can implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and thereafter. The computing device 400 may include multiple communication chips 406. For example, the first communication chip 406 may be dedicated to short-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 406 may be dedicated to long-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0069] The processor 404 of the computing device 400 includes an integrated circuit die packaged within the processor 404. In some implementations of the present disclosure, the integrated circuit die of the processor includes one or more structures, such as conductive vias and metal line terminals, manufactured according to implementations of embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0070] The communication chip 406 also includes an integrated circuit die packaged within the communication chip 406. According to another embodiment of the invention, the integrated circuit die of the communication chip includes one or more structures such as conductive vias and metal line terminals fabricated according to implementations of embodiments of the present disclosure.

[0071] In further implementations, another component housed in computing device 400 may include an integrated circuit die that includes one or more structures such as conductive vias and metal line terminals fabricated in accordance with implementations of embodiments of the present disclosure.

[0072] In various embodiments, computing device 400 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video camera. In further embodiments, computing device 400 may be any other electronic device that processes data.

[0073] Figure 5 An interposer 500 is shown that includes one or more embodiments of the present disclosure. The interposer 500 is an intermediate substrate for bridging a first substrate 502 to a second substrate 504. The first substrate 502 may be, for example, an integrated circuit die. The second substrate 504 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of the interposer 500 is to extend the connection to a wider spacing or to reroute the connection to a different connection. For example, the interposer 500 may couple the integrated circuit die to a ball grid array (BGA) 506 that may then be coupled to the second substrate 504. In some embodiments, the first substrate 502 and the second substrate 504 are attached to opposite sides of the interposer 500. In other embodiments, the first substrate 502 and the second substrate 504 are attached to the same side of the interposer 500. In further embodiments, three or more substrates are interconnected through the interposer 500.

[0074] The interposer 500 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In further embodiments, the interposer may be formed of alternating rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0075] The interposer 500 may include metal interconnects 508 and vias 510, including but not limited to through silicon vias (TSVs) 512. The interposer 500 may also include embedded devices 514, including passive devices and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 500. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used to manufacture the interposer 500.

[0076] Thus, embodiments of the present disclosure include conductive via and metal line termination fabrication and resulting structures.

[0077] Some non-limiting examples are provided below.

[0078] Example

[0079] Example 1 may include an interconnect structure comprising: a first interlayer dielectric (ILD) on a hard mask layer, wherein the ILD includes a first ILD opening and a second ILD opening; an etch stop layer (ESL) on the ILD layer, wherein the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and wherein the ESL layer includes a second ESL opening aligned with the second ILD opening; a first via in the first via opening; a second ILD layer on the first ESL; a metal line in the second ILD layer, wherein the metal line contacts the first via, and wherein the metal line includes a first metal opening, and wherein the metal line includes a second metal opening aligned with the second ILD opening and the second ESL opening to form a second via opening; a metal line end in the first metal opening; and a second via in the metal line, wherein the second via is in the second via opening.

[0080] Example 2 may include the interconnect structure of Example 1 or some other example herein, wherein the first via is a gate via, and wherein the second via is a diffusion via.

[0081] Example 3 may include the interconnect structure of Example 1, 2, or some other example herein, wherein the first ILD layer includes a first dielectric material and the second ILD layer includes a second dielectric material.

[0082] Example 4 may include the interconnect structure of Example 3 or some other example herein, wherein the first ILD layer and the second ILD layer include a same dielectric material.

[0083] Example 5 may include the interconnect structure of Example 1, 2, or some other example herein, wherein the second ILD layer and the metal line end include the same dielectric material.

[0084] Example 6 may include the interconnect structure of Example 1, 2, or some other example herein, wherein the hard mask layer includes a first material adjacent to a second material, wherein the first material can remain if the second material is etched.

[0085] Example 7 may include the interconnect structure of Example 6 or some other example herein, further including: a semiconductor device, wherein the semiconductor device includes a semiconductor substrate; a gate contact on the semiconductor substrate, wherein the first via is a gate via that contacts the gate contact by removing a portion of the first material in the hard mask layer; and a diffusion contact on the semiconductor substrate, wherein the second via is a diffusion via that contacts the diffusion contact by removing a portion of the second material in the hard mask layer.

[0086] Example 8 may include a method of manufacturing an interconnect structure for an integrated circuit, the method comprising: forming a first cross grid structure including a first sacrificial cross grid on a first film stack, wherein the first sacrificial cross grid structure includes a plurality of potential gate via locations, the potential gate via locations including a gate via placeholder material, and wherein a subset of the potential gate via locations are activated gate via locations, the activated gate via locations including gate via openings from which the gate via placeholder material has been removed; removing the first film stack material from a bottom of the activated gate via locations up to a gate contact; filling the activated gate via locations with a first conductive material to form a gate via; removing the first sacrificial cross grid; , to expose a surface of a first ILD layer of the first film stack and a surface of a gate via in the first ILD layer, wherein removing the first sacrificial cross grid includes removing a remaining portion of the first film stack above the first ILD layer; forming a second cross grid structure on the surface of the first ILD layer, the second cross grid structure including a second sacrificial cross grid on the second film stack, wherein the second sacrificial cross grid includes a first portion, a second portion, and a plurality of potential plug locations including a plug placeholder material, and wherein a subset of the potential plug locations are activated plug locations, the activated plug locations including plug openings from which the plug placeholder material has been removed; filling the activated plug locations with the plug placeholder material to form plug openings; a plug; removing a second portion of the second sacrificial cross grid to form a metal line end under the plug in a first portion of the second sacrificial cross grid, wherein the metal line end includes an ILD material of an ILD layer of the second film stack, and further forming an ILD line on a surface of an etch stop layer (ESL) of the second film stack, wherein the ILD line includes the ILD material; forming a third cross grid structure including a third sacrificial cross grid on the ESL, wherein the third sacrificial cross grid includes a plurality of potential diffusion via locations, the potential diffusion via locations including the diffusion via placeholder material, and wherein a subset of the potential diffusion via locations are activated diffusion via locations, the activated diffusion via locations including the activated diffusion via locations having been removed therefrom The invention relates to a method for forming a gate via placeholder material by forming an opening of the gate via placeholder material; removing the ESL material and the first ILD material from the bottom of the activated diffusion via location to the diffusion via guide portion in the hard mask layer in the first film stack; removing the third sacrificial cross grid to form a trench between the ILD lines on the surface of the ESL; removing the diffusion via guide portion; filling the activated diffusion via location with a second conductive material to form a diffusion via; filling the trench with the second conductive material to form a metal line, wherein the surface of the gate via contacts the metal line; removing the sacrificial material of the sacrificial layer of the second film stack to expose the surface of the metal line, the ILD line, the metal line end and the diffusion via, wherein removing the sacrificial material of the sacrificial layer of the second film stack includes removing the plug.

[0087] Example 9 may include the method of Example 8 or some other example herein, wherein removing the first film stack material from a bottom of the activated gate via location includes applying an anisotropic etching technique.

[0088] Example 10 may include the method of Example 9 or some other example herein, wherein applying the anisotropic etching technique includes using a dry etching process.

[0089] Example 11 may include the method of Example 8, 9, or some other example herein, wherein filling the activated gate via location with a first conductive material to form a gate via includes: filling the activated gate via location with excess first conductive material; and polishing the excess first conductive material to remove the excess first conductive material.

[0090] Example 12 may include the method of Example 8, 9, or some other example herein, further comprising removing the first film stack material from a bottom of the activated gate via location to a gate via guide portion in the hard mask layer in the first film stack, wherein the gate via guide portion is above the gate contact.

[0091] Example 13 may include the method of Example 8, 9, or some other example herein, wherein the plug and the metal line end include sidewalls, and wherein the method further includes depositing a liner by atomic layer deposition to protect the sidewalls.

[0092] Example 14 may include the method of Example 8, 9, or some other example herein, wherein removing the third sacrificial cross grid includes applying an isotropic etching technique.

[0093] Example 15 may include the method of Example 8, 9, or some other example herein, further comprising depositing a diffusion via placeholder material in the activated diffusion via locations.

[0094] Example 16 may include the method of Example 8, 9, or some other example herein, wherein filling the activated diffusion via location with the second conductive material to form the diffusion via includes filling the activated diffusion via location with excess second conductive material; and polishing the excess second conductive material.

[0095] Example 17 may include a method of manufacturing an interconnect structure for an integrated circuit, the method comprising: forming a first cross-grid structure including a sacrificial cross-grid on a first film stack, wherein the first cross-grid structure includes a plurality of potential gate via locations, the potential gate via locations including a gate via placeholder material, and wherein a subset of the potential gate via locations are activated gate via locations, the activated gate via locations including gate via openings from which the gate via placeholder material has been removed; removing the first film stack material from a bottom of the activated gate via locations up to a gate contact; forming a gate via in a first ILD layer of the first film stack , wherein the gate via includes a first conductive material in an activated gate via location; exposing a surface of the first ILD layer; forming a second cross-grid structure on the first ILD layer, the second cross-grid structure including a second sacrificial cross-grid on the second film stack, wherein the second sacrificial cross-grid includes a first portion, a second portion, and a plurality of potential plug locations including a plug placeholder material, wherein a subset of the potential plug locations are activated plug locations, the activated plug locations including openings from which the plug placeholder material has been removed; forming plugs including the plug material in the activated plug locations; and removing the first portion of the second sacrificial cross-grid to form a plug in the second film stack. forming a metal line terminal below the plug on a surface of an etch stop layer (ESL) of the film stack, wherein the metal line terminal comprises an ILD material of an ILD layer of the second film stack, forming an ILD line on a surface of the ESL by removing a first portion of a second sacrificial cross grid, wherein the ILD line comprises the ILD material; forming a third cross grid structure comprising a third sacrificial cross grid on the ESL, wherein the third sacrificial cross grid comprises a plurality of potential diffusion via locations, wherein the potential diffusion via locations comprise diffusion via placeholder material, and wherein a subset of the potential diffusion via locations are activated diffusion via locations, wherein the activated diffusion via locations comprise the first portion of the second sacrificial cross grid that has been removed from the first portion of the second sacrificial cross grid; except for the opening of the diffusion via placeholder material; removing the ESL material and the ILD material from the bottom of the activated diffusion via location to the diffusion contact; depositing the diffusion via placeholder material in the activated via location; forming a trench between the ILD lines on the surface of the ESL; forming a diffusion via including a second conductive material in the activated diffusion via location; forming a metal line including the second conductive material in the trench, wherein the surface of the gate via contacts the metal line; and removing the sacrificial material of the sacrificial layer of the second film stack to planarize the surface of the metal line, the ILD line, the metal line end and the diffusion via, wherein removing the sacrificial material of the sacrificial layer of the second film stack includes removing the plug.

[0096] Example 18 may include the method of Example 17 or some other example herein, wherein exposing the surface of the first ILD layer includes removing the first sacrificial cross grid, wherein removing the first sacrificial cross grid includes removing a remaining portion of the first film stack over the first ILD layer.

[0097] Example 19 may include the method of Example 17, 18, or some other example herein, further comprising removing the ESL material and the ILD material from the bottom of the activated diffusion via location to a diffusion via guide portion in the hard mask layer in the first film stack, wherein the diffusion via guide portion is above the diffusion contact.

[0098] Example 20 may include the method of Example 17, 18, or some other example herein, wherein forming trenches between ILD lines on the ESL surface includes removing the third sacrificial cross grid.

[0099] Various embodiments may include any suitable combination of the above embodiments, including alternative (or) embodiments of the embodiments described above in conjunction (and) (e.g., "and" may be "and / or"). In addition, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions stored thereon, which, when executed, result in the operations of any of the above embodiments. In addition, some embodiments may include an apparatus or system having any suitable modules for performing the various operations of the above embodiments.

[0100] The above description of the illustrated embodiments (including what is described in the Abstract) is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. Although specific embodiments and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure as will be appreciated by those skilled in the relevant art.

[0101] These modifications may be made to the embodiments of the present disclosure in light of the above specific embodiments. The terms used in the appended claims should not be interpreted as limiting the various embodiments of the present disclosure to the specific embodiments disclosed in the specification and claims. Rather, the scope will be determined entirely by the following claims, which should be interpreted in accordance with established principles of claim interpretation.

Claims

1. An interconnect structure comprising: a first interlayer dielectric (ILD) layer on the hard mask layer, wherein the first interlayer dielectric layer includes a first interlayer dielectric opening and a second interlayer dielectric opening; an etch stop layer (ESL) on the first interlayer dielectric layer, wherein the etch stop layer includes a first etch stop layer opening aligned with the first interlayer dielectric opening to form a first via opening, and wherein the etch stop layer includes a second etch stop layer opening aligned with the second interlayer dielectric opening; a first via in the first via opening; a second interlayer dielectric layer on the first etch stop layer; a metal line in the second interlayer dielectric layer, wherein the metal line contacts the first via, and wherein the metal line includes a first metal opening, and wherein the metal line includes a second metal opening aligned with the second interlayer dielectric opening and the etch stop layer opening to form a second via opening; A metal line end in the first metal opening; and A second via in the metal line, wherein the second via is in the second via opening.

2. The interconnect structure according to claim 1, wherein: The first via is a gate via, and wherein the second via is a diffusion via.

3. The interconnect structure according to claim 1 or 2, wherein: The first interlayer dielectric layer includes a first dielectric material, and the second interlayer dielectric layer includes a second dielectric material.

4. The interconnect structure according to claim 3, wherein: The first interlayer dielectric layer and the second interlayer dielectric layer include the same dielectric material.

5. The interconnect structure according to claim 1 or 2, wherein: The second interlayer dielectric layer and the metal line terminal include a same dielectric material.

6. The interconnect structure according to claim 1 or 2, wherein: The hard mask layer includes a first material adjacent to a second material, wherein the first material can remain if the second material is etched.

7. The interconnect structure of claim 6, further comprising: A semiconductor device, wherein the semiconductor device comprises: Semiconductor substrate; a gate contact on the semiconductor substrate, wherein the first via is a gate via contacting the gate contact by removing a portion of the first material in the hard mask layer; and A diffusion contact on the semiconductor substrate, wherein the second via is a diffusion via contacting the diffusion contact by removing a portion of the second material in the hard mask layer.

8. A method of manufacturing an interconnect structure for an integrated circuit, the method comprising: forming a first cross-grid structure including a first sacrificial cross-grid on a first film stack, wherein the first cross-grid structure includes a plurality of potential gate via locations including a gate via placeholder material, and wherein a subset of the potential gate via locations are activated gate via locations including gate via openings from which the gate via placeholder material has been removed; removing the first film stack material from the bottom of the activated gate via location to the gate contact; filling the activated gate via location with a first conductive material to form a gate via; removing the first sacrificial cross grid to expose a surface of the first interlayer dielectric layer of the first film stack and a surface of the gate via in the first interlayer dielectric layer, wherein removing the first sacrificial cross grid comprises removing a remaining portion of the first film stack above the first interlayer dielectric layer; forming a second cross-grid structure on a surface of the first interlayer dielectric layer, the second cross-grid structure comprising a second sacrificial cross-grid on a second film stack, wherein the second sacrificial cross-grid comprises a first portion, a second portion, and a plurality of potential plug locations comprising a plug placeholder material, and wherein a subset of the potential plug locations are activated plug locations comprising plug openings from which the plug placeholder material has been removed; filling the activated plug location with a plug placeholder material to form a plug; removing a second portion of the second sacrificial cross grid to form a metal line end under the plug in a first portion of the second sacrificial cross grid, wherein the metal line end comprises an interlayer dielectric material of a second interlayer dielectric layer of the second film stack, and further forming an interlayer dielectric line on a surface of an etch stop layer (ESL) of the second film stack, and wherein the interlayer dielectric line comprises an interlayer dielectric material; forming a third cross-grid structure including a third sacrificial cross-grid on the etch stop layer, wherein the third sacrificial cross-grid includes a plurality of potential diffusion via locations including a diffusion via placeholder material, and wherein a subset of the potential diffusion via locations are activated diffusion via locations including openings from which the diffusion via placeholder material has been removed; removing etch stop layer material and first interlayer dielectric material from a bottom of the activated diffusion via location through a diffusion via guide portion in a hard mask layer in the first film stack; removing the third sacrificial cross grid to form trenches between the interlayer dielectric lines on a surface of the etch stop layer; removing the diffusion via guide portion; filling the activated diffusion via location with a second conductive material to form a diffusion via; Filling the trench with the second conductive material to form a metal line, wherein a surface of the gate via is in contact with the metal line; and The sacrificial material of the sacrificial layer of the second film stack is removed to expose surfaces of the metal line, the interlayer dielectric line, the metal line end, and the diffusion via, and wherein removing the sacrificial material of the sacrificial layer of the second film stack includes removing the plug.

9. The method according to claim 8, wherein: Removing the first film stack material from the bottom of the activated gate via location includes applying an anisotropic etching technique.

10. The method according to claim 9, wherein: Applying the anisotropic etching technique includes using a dry etching process.

11. The method according to claim 8 or 9, wherein: Filling the activated gate via location with the first conductive material to form the gate via includes: filling the activated gate via location with an excess of first conductive material; and The excess first conductive material is polished to remove the excess first conductive material.

12. The method of claim 8 or 9, further comprising removing the first film stack material from a bottom of the activated gate via location up to a gate via guide portion in a hard mask layer in the first film stack, wherein The gate via guide portion is above the gate contact.

13. The method according to claim 8 or 9, wherein: The plug and the metal line end include sidewalls, and wherein the method further comprises depositing a liner by atomic layer deposition to protect the sidewalls.

14. The method according to claim 8 or 9, wherein: Removing the third sacrificial cross grid includes applying an isotropic etching technique.

15. The method of claim 8 or 9, further comprising depositing a diffusion via placeholder material in the activated diffusion via locations.

16. The method according to claim 8 or 9, wherein: Filling the activated diffusion via location with the second conductive material to form the diffusion via includes: filling the activated diffusion via locations with an excess of a second conductive material; and The excess second conductive material is polished.

17. A method of manufacturing an interconnect structure for an integrated circuit, the method comprising: forming a first cross-grid structure including a first sacrificial cross-grid on a first film stack, wherein the first cross-grid structure includes a plurality of potential gate via locations including a gate via placeholder material, and wherein a subset of the potential gate via locations are activated gate via locations including gate via openings from which the gate via placeholder material has been removed; removing the first film stack material from the bottom of the activated gate via location to the gate contact; forming a gate via in a first interlayer dielectric layer of the first film stack, wherein the gate via comprises a first conductive material in the activated gate via location; exposing a surface of the first interlayer dielectric layer; forming a second cross-grid structure on the first interlayer dielectric layer, the second cross-grid structure comprising a second sacrificial cross-grid on a second film stack, wherein the second sacrificial cross-grid comprises a first portion, a second portion, and a plurality of potential plug locations comprising a plug placeholder material, and wherein a subset of the potential plug locations are activated plug locations comprising openings from which the plug placeholder material has been removed; forming a plug including a plug material in the activated plug location; forming a metal line terminal below the plug on a surface of an etch stop layer (ESL) of the second film stack by removing a first portion of the second sacrificial cross grid, wherein the metal line terminal comprises an interlayer dielectric material of a second interlayer dielectric layer of the second film stack; forming an interlayer dielectric line on a surface of the etch stop layer by removing a first portion of the second sacrificial cross grid, wherein the interlayer dielectric line comprises an interlayer dielectric material of the second interlayer dielectric layer; forming a third cross-grid structure including a third sacrificial cross-grid on the etch stop layer, wherein the third sacrificial cross-grid includes a plurality of potential diffusion via locations including a diffusion via placeholder material, and wherein a subset of the potential diffusion via locations are activated diffusion via locations including openings from which the diffusion via placeholder material has been removed; removing etch stop layer material and said interlayer dielectric material from a bottom of said activated diffusion via location to a diffusion contact; depositing a diffused via placeholder material in the activated via location; forming trenches between the interlayer dielectric lines on a surface of the etch stop layer; forming a diffusion via comprising a second conductive material in the activated diffusion via location; forming a metal line including the second conductive material in the trench, wherein a surface of the gate via is in contact with the metal line; and The sacrificial material of the sacrificial layer of the second film stack is removed to planarize the surfaces of the metal line, the interlayer dielectric line, the metal line end, and the diffusion via, wherein removing the sacrificial material of the sacrificial layer of the second film stack includes removing the plug.

18. The method according to claim 17, wherein: Exposing a surface of the first interlayer dielectric layer includes removing the first sacrificial cross grid, wherein removing the first sacrificial cross grid includes removing a remaining portion of the first film stack over the first interlayer dielectric layer.

19. The method of claim 17 or 18, further comprising removing the etch stop layer material and the interlayer dielectric material from the bottom of the activated diffusion via location to the diffusion via guide portion in the hard mask layer in the first film stack, wherein The diffusion via guide portion is above the diffusion contact.

20. The method according to claim 17 or 18, wherein: Forming the trench between the interlayer dielectric lines on the surface of the etch stop layer includes removing the third sacrificial cross grid.

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