Method and system for calculating the value of the first neuron in the first layer of a neural network

Abstract

The present application discloses a method and device for improving the defect tolerance of a hardware-based neural network. In one embodiment, a method for calculating a value on a first neuron of a first layer in a neural network includes: receiving a first pattern of a storage cell array; determining a second pattern of the storage cell array according to a third pattern; determining at least one pair of columns of the storage cell array according to the first pattern and the second pattern; switching input data of two columns in each pair of the at least one pair of columns of the storage cell array; and switching output data of the two columns in each pair of the at least one pair of columns of the storage cell array to determine the value on the first neuron of the first layer.

Description

Technical Field

[0001] Embodiments of the present application relate to a method for calculating a value on a first neuron of a first layer in a neural network. Background Art

[0002] Artificial neural networks (ANNs), inspired by animal brains, are one of the main tools used in machine learning. Neural networks consist of an input layer and an output layer. In common ANN implementations, the signal at the connection between artificial neurons is a real number, and the output of each artificial neuron is calculated by some nonlinear functions of the sum of the inputs of each artificial neuron. The connection between artificial neurons is called an "edge". Artificial neurons and edges usually have weights that are adjusted as learning proceeds. An increase or decrease in weight indicates that the strength of the signal at the connection between two neurons increases or decreases. Artificial neurons may have a threshold value so that a signal is sent only when an aggregate signal crosses this threshold value. Typically, artificial neurons are aggregated into layers. Different layers may perform different kinds of transformations on the inputs of the different layers. The signal travels from the first layer (input layer) to the last layer (output layer), which may be after crossing the layers multiple times.

[0003] Therefore, the network of neurons is connected by edges with different transmission efficiencies. The information flowing through the edge is multiplied by a constant that reflects the efficiency and accuracy of the edge. In hardware-based ANNs, the weights of neurons can be programmed on cells of a storage cell array. Defective cells in the storage cell array can affect the accuracy with which signals travel between neurons in the corresponding layer. Therefore, it is necessary to develop a method to improve the tolerance of artificial neural networks to defective cells in the storage cell array. Summary of the invention

[0004] In one embodiment, a method for calculating a value on a first neuron in a first layer of a neural network includes: receiving a first pattern of a storage cell array, wherein the storage cell array includes a plurality of storage cells, and the plurality of storage cells are configured into a plurality of columns and a plurality of rows; determining a second pattern of the storage cell array using a third pattern; determining at least one pair of columns of the storage cell array according to the first pattern and the second pattern; switching input data of two columns in each of the at least one pair of columns of the storage cell array; performing bit-by-bit calculation using the input data stored in the plurality of storage cells; and switching output data of the two columns in each of the at least one pair of columns of the storage cell array to determine the value on the first neuron in the first layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale. In fact, the size and geometry of the various features may be arbitrarily increased or decreased for the sake of clarity of illustration.

[0006] Figure 1 An example diagram of a fully connected network of an artificial neural network (ANN) according to some embodiments of the present disclosure is shown.

[0007] Figure 2 An exemplary weight pattern between the input layer and the hidden layer in a network according to some embodiments of the present disclosure is shown.

[0008] Figure 3A FIG. 1 shows an exemplary defect pattern of a memory cell array according to some embodiments of the present disclosure [D] N×M .

[0009] Figure 3B FIG. 1 shows an exemplary defect pattern of a memory cell array according to some embodiments of the present disclosure [D] N×M .

[0010] Figure 4A A graph according to some embodiments of the present disclosure is shown, which shows the relationship between the number of injection defects and the accuracy degradation value in the first memory cell array and the second memory cell array.

[0011] Figure 4B A graph showing the relationship between incorrect count and number of errors is shown according to some embodiments of the present disclosure.

[0012] Figure 4C A graph according to some embodiments of the present disclosure is shown, wherein the graph shows a graph with a second weight pattern [X] 10×64 The accuracy drop value at each column of the corresponding second storage cell array.

[0013] Figure 5A A schematic diagram is shown for rearranging weight patterns and input data on a memory cell array according to some embodiments of the present disclosure.

[0014] Figure 5B A schematic diagram is shown for rearranging weight patterns and input data on a memory cell array according to some embodiments of the present disclosure.

[0015] Fig. 6A A block diagram of a system for determining a value on a neuron on a hidden layer of a network according to some embodiments of the present disclosure is shown.

[0016] Figure 6B A block diagram of a system for determining a value on a neuron on a hidden layer of a network according to some embodiments of the present disclosure is shown.

[0017] Fig. 7A A flow chart showing a method according to some embodiments of the present disclosure that uses a neural network macro to perform calculations on values ​​on each of the neurons on a hidden layer of a network.

[0018] Figure 7B A flow chart of a method 730 for swapping I / Os through a state machine in the selector 614 is shown according to some embodiments of the present disclosure.

[0019] Figure 7C A table according to some embodiments of the present disclosure is shown, the table having Figure 7B Exemplary data of the exchange process presented in .

[0020] Figure 8 A block diagram of a system for determining a value on a neuron on a hidden layer of a network according to some embodiments of the present disclosure is shown.

[0021] Fig. 9 A flow chart showing a method according to some embodiments of the present disclosure that performs calculations on values ​​on each of the neurons on a hidden layer of a network.

[0022] Description of Figure Numbers

[0023] 100: Fully connected network / network

[0024] 102, 104, W 1,1 , W 1,2 , W 1,3 , W 1,M , W 2,1 , W 2,2 , W 2,3 , W 2,M , W 3,1 , W 3,2 , W 3,3 , W 3,M , W 4,1 , W N,1 , W N,2 , W N,3 , W N,M , W M,1 , X 1,1 , X 2,1 , X 3,1 , X N,1 : Weight

[0025] 106, 106-1, 106-2, 106-3, 106-4, 106-M, 108, 108-1, 108-2, 108-3, 108-N, 110, 110-1, 110-2, 110-P: Neurons

[0026] 112: Input layer

[0027] 114: Hidden Layer

[0028] 116: Output layer

[0029] 118, 120, 200, [W] N×M , [W] 64×64 , [W]' N×M , [X] P×N , [X] 10×64 , [X] 64×10 : Weight pattern

[0030] 202, 202-1, 202-2, 202-3, 202-a, 202-b, 202-j, 202-M, 302, 302-1, 302-2, 302-3, 302-j, 302-M: Column

[0031] 204-1, 204-2, 204-3, 204-N, 304, 304-1, 304-2, 304-3, 304-N, #, #1, #2, #3, #4, #5, #6, #7, #8, #9, #10: Row

[0032] 206: Weighted Pattern Sensitivity (WPS) / First WPS

[0033] 300, [D] N×M , [D1] 64×64 , [D1] N×M , [D2] 10×64 :Defect pattern / detection pattern

[0034] 306, 306-1, 306-2: Defect Pattern Indicator (DPI)

[0035] 400, 410, 420: curve graph

[0036] 402, 422: Accuracy reduction value

[0037] 404: Injection Flaw

[0038] 412: Incorrect Count

[0039] 414: Error number

[0040] 426: Curve

[0041] 500, 510: Schematic diagram

[0042] 512: Faulty Bit Count (FBC)

[0043] 514: Statistical Severity (SS)

[0044] 600, 660, 800: System

[0045] 602: Memory Macro

[0046] 604: Storage Cell Array

[0047] 606: Write Drive (WD)

[0048] 608: Multiplexer (MUX)

[0049] 610: Sense amplifier (SA)

[0050] 612: Control circuit

[0051] 614, 616: Selector

[0052] 618: Memory

[0053] 620: Controller

[0054] 622: Input

[0055] 624: Weighted Pattern Sensitivity (WPS)

[0056] 630: Output

[0057] 650: Neural Network Macros / Network Macros / System Interfaces

[0058] 700, 730, 900: Method

[0059] 702, 704, 706, 708, 710, 712, 714, 716, 718, 720, 732, 734, 736, 738, 902, 904, 906, 908, 910, 912, 914, 916, 918, 920: Operation

[0060] 740: Table

[0061] 802: Buffer

[0062] 804: Processor

[0063] 806: EN signal

[0064] a1, a2, a3, a4, a M , b1, b2, b3, b N , c1, c2, c3, cP :value

[0065] temp 1: first temporary parameter

[0066] temp 2: Second temporary parameter

[0067] [A], [A] M×1 , [A]' 1×M , [A]' M×1 : Input data

[0068] [B] N×M , [B]' N×M : Output data DETAILED DESCRIPTION

[0069] The following disclosure sets forth various exemplary embodiments for implementing the different features of the subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, it should be understood that when an element is said to be "connected to" or "coupled to" another element, the element may be directly connected to or coupled to the other element, or one or more intermediate elements may also be present.

[0070] There are two fundamentally different options for implementing neural networks: software simulation in a conventional computer or a dedicated hardware solution that can significantly reduce execution time. Software simulation can help develop and debug new algorithms and benchmark them using small networks. However, if you want to use a large network, software simulation is not enough. The problem is the time required for the learning process, which can increase exponentially depending on the size of the network. However, a neural network that does not learn is quite boring. But the main purpose of building dedicated hardware is to provide a platform for efficient adaptive systems that can update the parameters of the system over time. Therefore, a new hardware solution is necessary. A hardware-based solution using a storage cell array can provide improved power efficiency. The intrinsic differences between storage cells in a storage cell array (for example, the type and address of defective storage cells in a storage cell array) are usually caused by the manufacturing process, which leads to intrinsic differences between different storage cell arrays. The separate training process of different storage cell arrays can significantly increase the cost overhead. The present disclosure presents various embodiments of methods and devices that can improve the defect tolerance of hardware-based neural networks.

[0071] Figure 1 An example diagram of a fully connected network 100 of an artificial neural network (ANN) according to some embodiments of the present disclosure is shown. The network 100 includes an input layer 112, a hidden layer 114, and an output layer 116. It should be noted that the network 100 is only an example and is not intended to limit the present disclosure. Therefore, it should be understood that the network 100 may be used in Figure 1An additional hidden layer 114 is provided between the input layer 112 and the output layer 116 in the embodiment of the present invention, and each layer (i.e., 112, 114, and 116) may include a different number of neurons, which is within the scope of the present application. It should also be noted that the values ​​on the neurons may be determined using different algorithms, which is also within the scope of the present application.

[0072] In the illustrated embodiment, the input layer 112 includes a plurality of neurons 106. Each of the plurality of neurons 106 includes a corresponding value, namely, a1 on neuron 106-1, a2 on neuron 106-2, a3 on neuron 106-3, ..., and a on neuron 106-M. M , where M is a positive integer. In some embodiments, the value of the neuron 106 on the input layer 112 is [A] M×1 =[a1; a2; a3; ...; a M ]. In addition, the hidden layer 114 includes a plurality of neurons 108. Each of the plurality of neurons 108 includes a corresponding value, namely, b1 on the neuron 108-1, b2 on the neuron 108-2, b3 on the neuron 108-3, ..., and b on the neuron 108-N. N , where N is a positive integer. In some embodiments, the value of the neuron 108 on the hidden layer 114 is [B] N×1 =[b1; b2; b3; ...; b N ]. Similarly, according to some embodiments, the output layer 116 includes a plurality of neurons 110. Each of the plurality of neurons 110 includes a corresponding value, namely c1, c2, c3, ..., and c P , where P is a positive integer. In some embodiments, the value of the neuron 110 on the output layer 116 is [C] P×1 =[c1; c2; c3; ...; c P ].

[0073] In some embodiments, each of the plurality of neurons 106 in the input layer 112 is coupled to each of the plurality of neurons 108 in the hidden layer 114 through a plurality of corresponding weights 102. For example, the weights W 1,1 , W 2,1 , ..., and W M,1 For coupling the neurons 106-1, 106-2, 106-3, ..., 106-M of the input layer 112 and the neurons 108-1 of the hidden layer 114. In some embodiments, each of the corresponding weights 102 between the neurons 106 of the input layer 112 and the neurons 108 of the hidden layer 114 has a value of "0" or a value of "1". In some embodiments, the corresponding weights (W i,j) 102 represents the value of the corresponding neuron 106 (a i ) for the value of the corresponding neuron 108 (i.e. b j ), where i≤M, j≤N, i and j are positive integers.

[0074] Similarly, each of the plurality of neurons 108 in the hidden layer 114 is coupled to each of the plurality of neurons 110 in the output layer 116 through a plurality of corresponding weights 104. For example, weights X 1,1 , X 2,1 , ..., and X N,1 For coupling between neurons 108-1, 108-2, 108-3, ..., and 108-N of hidden layer 114 and neuron 110-1 of output layer 116. In some embodiments, each of the corresponding weights 104 between neurons 108 of hidden layer 114 and neurons 110 of output layer 116 has a value of "0" or a value of "1". In some embodiments, the corresponding weights (X j,k ) 104 also represents the value of the corresponding neuron 108 (b j ) for the value of the corresponding neuron 110 (c k ), where j≤N, k≤P, j and k are positive integers.

[0075] In some embodiments, weights 102 and 104 are trained weights obtained through a training process according to predefined algorithms and methods. In some embodiments, the training algorithm is a back-propagation algorithm in which the weights of the network are repeatedly adjusted to minimize the difference between the actual output vector and the output vector seen. In some embodiments, weight training can be performed on-chip using a hardware memory cell array or off-chip using software. In some embodiments, the weights of the network are determined assuming a defect-free memory cell array.

[0076] In some embodiments, all values ​​of weights 102 between input layer 112 and hidden layer 114 are grouped together to form a first weight pattern [W] having N rows and M columns. N×M 118. In some embodiments, all weights 104 between the hidden layer 114 and the output layer 116 are grouped together to form a second weight pattern [X] having P rows and N columns. P×N 120. In some embodiments, during implementation, the first weight pattern [W] N×M 118 can be implemented by a first memory cell array and a second weight pattern [X] P×N120 is implemented by the second memory cell array. In some embodiments, the first memory cell array includes a memory cell array having an N×M size and the second memory cell array includes a memory cell array having a P×N size.

[0077] Figure 2 1 shows an exemplary weight pattern 200 between the input layer 112 and the hidden layer 114 in the network 100 according to some embodiments of the present disclosure. In the illustrated embodiment, the weight patterns 200 (e.g., the first weight pattern [W] N×M 118) to obtain a weight pattern sensitivity (WPS) 206. In the illustrated embodiment, the WPS 206 includes 1 row and M columns. In some embodiments, the first weight pattern [W] N×M 118 includes N rows (i.e., 204-1, 204-2, ..., and 204-N) and M columns (i.e., 202-1, 202-2, ..., and 202-M). In some embodiments, the corresponding first weight pattern [W] N×M The first WPS 206 of 118 may be determined according to the number of "0"s or the number of "1"s in the column 202. For example, when the first weight pattern [W] N×M When the number of "1"s in column 202-j of 118 is equal to or greater than a predefined threshold, S in WPS 206 j is determined to be 1, where j≤M and j is a positive integer. Similarly, when the first weight pattern [W] N×M When the number of "1"s in column 202-j of 118 is less than a predefined threshold, S in WPS 206 j The value of is determined to be "0". In some embodiments, for the corresponding weight pattern [W] N×M 118, there is a WPS 206.

[0078] In some embodiments, the value in WPS 206 is determined by comparing the number of "1"s in a column of the weight pattern to a multi-level threshold. For example, when the number of "1"s in a column of the weight pattern is equal to or greater than 0 and less than 5, the WPS value of this column is 0; when the number of "1"s in a column of the weight pattern is equal to or greater than 5 and less than 10, the WPS value of the column is 1; when the number of "1"s in a column of the weight pattern is equal to or greater than 10 and less than 15, the WPS value of the column is 2; and when the number of "1"s in a column of the weight pattern is equal to or greater than 15 and less than the size of the column (e.g., N), the WPS value of the column is 3.

[0079] Figure 3AFIG. 1 shows an exemplary defect pattern of a memory cell array according to some embodiments of the present disclosure [D] N×M 300. In the illustrated embodiment, a memory cell array having a size of N×M is measured to store a first weight pattern [W] N×M 118 and determining the value on each of the neurons 108 of the hidden layer 114 to obtain the defect pattern [D] N×M 300. In some embodiments, the memory cell array may include one of the following: a plurality of registers, a plurality of e-fuses, a static random access memory (SRAM), and a portion of the memory cell array.

[0080] In some embodiments, the defect pattern [D] N×M 300 is obtained by writing "0" or "1" in each of the storage cells in the array and then measuring the logic state stored on each of the storage cells in the array. When a storage cell written with "1" is measured as "0", then this storage cell is determined to be defective, and more specifically, has a "set-to-reset" defect; and when a storage cell written with "0" is measured as "1", then this storage cell is also determined to be defective, and more specifically, has a "reset-to-set" defect. In some other embodiments, when a storage cell written with "1" or "0" is also measured as "1" or "0", this storage cell is determined to be stable and therefore non-defective. In some embodiments, when the storage cell is stable, D ij =1; and when the storage cell is defective, D ij =0, where i and j are positive integers, i≤M and j≤N.

[0081] In some embodiments, the defect pattern indicator (DPI) 306 may be based on the corresponding defect pattern [D] N×M The number of defective memory cells in each of the M columns 302 of 300 is obtained. In some embodiments, for a defect pattern [D] including N rows 304 and M columns 302, N×M 300, DPI 306 includes 1 row and M columns. In some embodiments, when the defect pattern [D] N×M When the number of defective memory cells in column 302-j of 300 is equal to or greater than a predefined threshold, the corresponding d in DPI 306 is j is determined to be "0"; and when the defect pattern [D] N×MWhen the number of defective memory cells in column 302-j of 300 is less than a predefined threshold, the corresponding d in DPI 306 is j is determined to be "1".

[0082] Figure 3B FIG. 1 shows an exemplary defect pattern of a memory cell array according to some embodiments of the present disclosure [D] N×M 300. In the illustrated embodiment, a memory cell array having a size of N×M is measured to store a first weight pattern [W] N×M 118 and determining the value on each of the neurons 108 of the hidden layer 114 to obtain the defect pattern [D] N×M 300. In some embodiments, the memory cell array may include one of: a plurality of registers, a plurality of electrical fuses, a static random access memory (SRAM), and a portion of the memory cell array.

[0083] In some embodiments, the defect pattern [D] N×M 300 is obtained by writing "0" or "1" in each of the storage cells in the array, and then measuring the logic state stored on each of the storage cells in the array. When a storage cell written with "1" is measured as "0", then this storage cell is determined to be defective, and more specifically, has a "set to reset" defect; and when a storage cell written with "0" is measured as "1", then this storage cell is also determined to be defective, and more specifically, has a "reset to set" defect. In some other embodiments, when a storage cell written with "1" or "0" is also measured as "1" or "0", this storage cell is determined to be stable and therefore non-defective.

[0084] In some embodiments, a defect pattern indicator (DPI) 306 may be obtained based on the number of defective memory cells in the column 302. In some embodiments, the DPI 306 includes 1 row and m columns, where m=log2M, and M is the corresponding defect pattern [D]. N×M 300. In some embodiments, when the defect pattern [D] N×M When the number of defective memory cells in the column 302-j of the memory 300 is equal to or greater than a predefined threshold, the DPI 306 is determined as the address of the column 302-j. For example, when the second column 302-2 and the last column 302-M are determined as the columns including defective memory cells greater than the predefined threshold, for the column 302-2, the DPI-1 306-1 is [00...1] and for the column 302-M, the DPI-2 306-2 is [11...1].

[0085] FIG. 4A to FIG. 4CThe simulation results using the network 100 according to some embodiments of the present disclosure are shown. In some embodiments, the network 100 includes an input layer 112, a hidden layer 114, and an output layer 116, wherein the input layer 112 includes N=64 neurons, the hidden layer 114 includes M=64 neurons, and the output layer 116 includes P=10 neurons. In addition, the network 100 includes 2 weight patterns, namely the first weight pattern [W] 64×64 and the second weight pattern [X] 64×10 In some embodiments, the first weight pattern is stored in a first memory cell array and the second weight pattern is stored in a second memory cell array. In some embodiments, the first memory cell array includes an array of memory cells having a size of 64×64 and the second memory cell array includes an array of memory cells having a size of 10×64.

[0086] Figure 4A A graph 400 is shown according to some embodiments of the present disclosure, which shows the relationship between the number of injection defects 404 in the first memory cell array and the second memory cell array and the accuracy degradation value 402. In some embodiments, the accuracy degradation value is determined by the following equation:

[0087] Accuracy reduction value = accuracy before defect injection - accuracy after defect injection

[0088] Wherein the accuracy degradation value 402 in % is the accuracy difference before and after the defective cell (hereinafter referred to as "defect") is introduced into the corresponding memory cell array. In some embodiments, the number of implanted defects 404 of each memory cell array is manually introduced to create a first defect pattern [D1] of the first memory cell array. 64×64 and a second defect pattern [D2] of a second memory cell array 10×64 In some embodiments, after a corresponding weight pattern (e.g., [W] is determined by a training process (e.g., determined off-chip using software assuming a non-defective memory cell array), N×M and [X] P×N )After that, defects are injected into the corresponding memory cell array.

[0089] In the illustrated embodiment, when 1 defect is injected into the first storage cell array, the accuracy degradation value 402 is equal to 0.024%; when 2 defects are injected into the first storage cell array, the accuracy degradation value is equal to 0.047%; when 3 defects are injected into the first storage cell array, the accuracy degradation value is equal to 0.070%; when 4 defects are injected into the first storage cell array, the accuracy degradation value is equal to 0.094%; and when 5 defects are injected into the first storage cell array, the accuracy degradation value is equal to 0.113%.

[0090] In the illustrated embodiment, when 1 defect is injected into the second storage cell array, the accuracy degradation value is equal to 0.012%; when 2 defects are injected into the second storage cell array, the accuracy degradation value is equal to 0.024%; when 3 defects are injected into the second storage cell array, the accuracy degradation value is equal to 0.036%; when 4 defects are injected into the second storage cell array, the accuracy degradation value is equal to 0.047%; and when 5 defects are injected into the second storage cell array, the accuracy degradation value is equal to 0.058%.

[0091] In the illustrated embodiment, when 1 defect is injected into each of the first memory cell array and the second memory cell array, the accuracy degradation value is equal to 0.042%; when 2 defects are injected into each of the first memory cell array and the second memory cell array, the accuracy degradation value is equal to 0.074%; when 3 defects are injected into each of the first memory cell array and the second memory cell array, the accuracy degradation value is equal to 0.104%; when 4 defects are injected into each of the first memory cell array and the second memory cell array, the accuracy degradation value is equal to 0.139%; and when 5 defects are injected into each of the first memory cell array and the second memory cell array, the accuracy degradation value is equal to 0.167%.

[0092] In the illustrated embodiment, the accuracy degradation caused by the injection defects in the first memory cell array is more significant than the accuracy degradation caused by the same number of injection defects in the second memory cell array. Figure 4A As shown in , injecting defects into the first memory cell array may cause a more significant accuracy degradation than the accuracy degradation caused by injecting defects into the second memory cell array. Figure 4A It can be observed from the simulation results shown in that the second memory cell array has a smaller number of neuron activations received from the output of the first memory cell array (e.g., the number of "1"s at the output of the first memory cell array), and therefore the number of defects in the second memory cell array that can cause the same amount of accuracy degradation is smaller. It should be noted that this trend also applies to other numbers of injected defects.

[0093] Figure 4B A graph 410 is shown showing a relationship between an incorrect count 412 and a number of errors 414 according to some embodiments of the present disclosure. In some embodiments, the number of errors 414 is the number of incorrectly classified test images (e.g., an input image with the number 8 is recognized and classified as the number 6 after passing through the entire artificial neural network). In some embodiments, to introduce a 1-to-0 defect, the weights of 1 stored in the cells of the storage cell array are modified to 0. Similarly, in some other embodiments, to introduce a 0-to-1 defect, the weights of 0 stored in the cells of the storage cell array are modified to 1.

[0094] Figure 4C A graph 420 is shown according to some embodiments of the present disclosure, wherein the graph 420 shows a graph with a second weight pattern [X] 10×64 120 corresponding to the second storage cell array at each column of the accuracy drop value 422. Specifically, in this simulation, the curve 426 is the second weight pattern [X] 10×64 120 is a graph of the number of "1"s in each column versus the row #. In the embodiment shown, the second weight pattern [X] 10×64 The number of "1"s in row #0 to row #10 of 120 is 16, 17, 13, 13, 12, 15, 16, 17, 13 and 15, respectively. In the illustrated embodiment, the accuracy degradation values ​​in row 1 are 1.13, 2.27 and 3.79 at 1 defect, 2 defects and 3 defects, respectively; the accuracy degradation values ​​in row 2 are 1, 2.62 and 5.31 at 1 defect, 2 defects and 3 defects, respectively; the accuracy degradation values ​​in row 3 are 2.97, 7.90 and 16.94 at 1 defect, 2 defects and 3 defects, respectively; the accuracy degradation values ​​in row 4 are 4.02, 8.06 and 12.56 at 1 defect, 2 defects and 3 defects, respectively; the accuracy degradation values ​​in row 5 are 3.68, 10.52 and 23 at 1 defect, 2 defects and 3 defects, respectively. 14; at 1 defect, 2 defects, and 3 defects, the accuracy drop values ​​in row 6 were 2.83, 7.31, and 14.52, respectively; at 1 defect, 2 defects, and 3 defects, the accuracy drop values ​​in row 7 were 2.45, 5.06, and 9.54, respectively; at 1 defect, 2 defects, and 3 defects, the accuracy drop values ​​in row 8 were 1.76, 3.98, and 6.78, respectively; at 1 defect, 2 defects, and 3 defects, the accuracy drop values ​​in row 9 were 3.35, 7.42, and 12.77, respectively; and at 1 defect, 2 defects, and 3 defects, the accuracy drop values ​​in row 10 were 3.16, 7.94, and 14.52, respectively.

[0095] In the illustrated embodiment, when the number of "1"s in the column of the weight pattern is large, the accuracy degradation value 442 is small; and when the number of "1"s in the column of the weight pattern is small, the accuracy degradation value 442 is large. As shown in this simulation result, the number of "1"s in the column of the weight pattern is associated with the accuracy degradation value 442. When the number of "1"s in the column of the weight pattern is large, the accuracy degradation value is small, and therefore, the column with a large number of "1"s in the weight pattern is therefore tolerant or less sensitive to defects in the column of the storage cells of the storage cell array. Similarly, when the number of "1"s in the column of the weight pattern is small, the accuracy degradation value is large, and therefore, the column with a small number of "1"s in the weight pattern is sensitive or less tolerant to defects in the column of the storage cells of the storage cell array.

[0096] Figure 5A A schematic diagram 500 for rearranging weight patterns and input data on a storage cell array according to some embodiments of the present disclosure is shown. In some embodiments, the rearrangement is determined based on a weight pattern sensitivity (WPS) 206 and a corresponding defect pattern 300 of the storage cell array. In the illustrated embodiment, the WPS 206 includes 1 row and M columns, and each column includes a binary number that represents the relationship between the number of 1s in the column of the corresponding weight pattern and a predefined threshold. For example, if the number of 1s in the column of the corresponding weight pattern is equal to or greater than the predefined threshold, the corresponding element in the WPS 206 is equal to 1; and if the number of 1s in the column of the corresponding weight pattern is less than the predefined threshold, the corresponding element in the WPS 206 is equal to 0. In the illustrated embodiment, the last column of the WPS 206 is 1 and the first column of the WPS 206 is 0. In the illustrated embodiment, the defect pattern 300 shows the number of defective cells (i.e., defects) in the storage cell array. In the illustrated embodiment, the first column in the storage cell array is defect-free and the last column of the storage cell array contains the largest number of defects (e.g., 2 defects). According to WPS 206 and inspection pattern 300, column 1 of the storage cell array receives the corresponding weights and input data originally specified for column M of the storage cell array; and column M of the storage cell array receives the corresponding weights and input data originally specified for column 1 of the storage cell array, so that the column with the least number of defects is used to store the weights and corresponding input data that are most sensitive to defects.

[0097] Figure 5BA schematic diagram 510 for rearranging weight patterns and input data on a storage cell array according to some embodiments of the present disclosure is shown. In some embodiments, the rearrangement is determined based on a weight pattern sensitivity (WPS) 206 and a corresponding defect pattern 300. In the illustrated embodiment, the WPS 206 includes 1 row and M columns, and each column includes a non-binary number. In some embodiments, the value in the WPS 206 is determined by comparing the number of positive weights in a column of the weight pattern with a multi-level threshold. For example, when the number of positive weights in a column of the weight pattern is equal to or greater than 0 and less than 5, the WPS value of this column is 0; when the number of positive weights in a column of the weight pattern is equal to or greater than 5 and less than 10, the WPS value of this column is 1; when the number of positive weights in a column of the weight pattern is equal to or greater than 10 and less than 15, the WPS value of this column is 2; and when the number of positive weights in a column of the weight pattern is equal to or greater than 15 and less than the size of the column (for example, Figure 2 When N is 0, the WPS value of this column is 3.

[0098] In the illustrated embodiment, the defect pattern 300 shows a mapping of defective cells (i.e., defects) in a storage cell array. In the illustrated embodiment, a failure bit count (FBC) 512 for each column can be determined based on a given defect pattern 300, and the failure bit count 512 is the number of defects in each column. In the illustrated embodiment, the first column of the storage cell array includes 0 defects, the second column of the storage cell array includes 2 defects, the third column of the storage cell array includes 1 defect, ..., the M-2 column of the storage cell array includes 0 defects, the M-1 column of the storage cell array includes 2 defects, and the M-th column of the storage cell array includes 1 defect. In the illustrated embodiment, the statistics severity (SS) 514 is determined as the product of the FBC 512 and the WPS 206.

[0099] According to SS 514, column 1 of the storage cell array receives the corresponding weights and input data originally specified for column M-1 of the storage cell array; and column M-1 of the storage cell array receives the corresponding weights and input data originally specified for column 1 of the storage cell array. Similarly, column 2 of the storage cell array receives the corresponding weights and input data originally specified for column M-2 of the storage cell array; and column M-2 of the storage cell array receives the corresponding weights and input data originally specified for column 2 of the storage cell array.

[0100] In some embodiments, when there are not enough good columns to swap, it is necessary to start from one direction (eg, from left to right, from low address to high address, from low IO number to high IO number, etc.).

[0101] It should be noted that FIG. 5A to FIG. 5B This is merely an example and is not intended to be limiting. Different numbers of defects in the memory cell array that require rearrangement, different values ​​of the weight pattern, and different positions and numbers of columns are all within the scope of the present application.

[0102] Fig. 6A A block diagram of a system 600 for determining a value on a neuron 108 on a hidden layer 114 of a network 100 according to some embodiments of the present disclosure is shown. It should be noted that the system 600 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional functional blocks may be provided in or coupled to the system 600, and some other functional blocks may only be briefly described herein.

[0103] exist Fig. 6A In the illustrated embodiment, the system 600 includes a neural network macro 650, wherein the neural network macro 650 includes a memory macro 602. In some embodiments, the memory macro 602 includes a memory cell array 604, and the memory cell array 604 includes a plurality of memory cells. In some embodiments, the plurality of memory cells are arranged in a column-row configuration, wherein each column has a bit line (BL) and a bitline bar (BLB), and each row has a word line (WL). More specifically, the BL and BLB of each column are respectively coupled to a plurality of memory cells arranged in this column, and each memory cell in this column is arranged on a different row and coupled to a corresponding (different) WL. That is, each memory cell of the memory cell array 604 is coupled to the BL of the column of the memory cell array 604, the BLB of the column of the memory cell array 604, and the WL of the row of the memory cell array 604. In some embodiments, the BL and the BLB are arranged in parallel in the vertical direction, and the WL is arranged in parallel in the horizontal direction (i.e., perpendicular to the BL and the BLB). In some embodiments, the WLs of each row of memory cells in the memory cell array 604 are connected together.

[0104] In some embodiments, each of the memory cells of the memory cell array 604 includes at least one transistor. In some other embodiments, each of the plurality of memory cells of the memory cell array 604 may include one of the following: a memristor, a resistive random access memory (ReRAM, RRAM), a phase change random access memory (PCRAM, PCM), a magnetoresistive random access memory (MRAM), a conductive bridge random access memory (CBRAM), a floating gate flash memory (FLASH), and a static random access memory (SRAM).

[0105] In some embodiments, the memory macro 602 further includes a write driver (WD) 606, a multiplexer (MUX) 608, a sense amplifier (SA) 610, and a control circuit 612. In some embodiments, the WD 606 is configured to provide the necessary voltage and / or current required to program the memory cell array 604. In some embodiments, the MUX 608 is configured to select a path for forwarding an input signal to an output. In some embodiments, the SA 610 is configured to compare a voltage or current generated during a read operation with a predefined threshold.

[0106] In some embodiments, the control circuit 612 is a representative device and may include a processor, a memory, an input / output interface, a communication interface, and a system bus. The processor may include any processing circuit system that is operable to control the operation and performance of the control circuit 612 of the memory macro 602. In various aspects, the processor may be implemented as a general-purpose processor, a chip multiprocessor (CMP), a special-purpose processor, an embedded processor, a digital signal processor (DSP), a network processor, an input / output (I / O) processor, a media access control (MAC) processor, a radio baseband processor, a co-processor, a microprocessor (e.g., a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, and / or a very long instruction word (VLIW) microprocessor) or other processing device. The processor may also be implemented by a controller, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), etc.

[0107] In various aspects, the processor can be arranged to run an operating system (OS) and various applications. Examples of OS include operating systems generally named by the trademark names of Apple OS, Microsoft Windows OS, Android OS, and any other proprietary or open source OS, for example.

[0108] In some embodiments, at least one non-transitory computer-readable storage medium containing computer-executable instructions thereon is provided, wherein the computer-executable instructions, when executed by at least one processor, cause the at least one processor to perform an embodiment of the method described herein. Such a computer-readable storage medium may be contained in a memory.

[0109] In some embodiments, the memory may include any machine-readable or computer-readable medium capable of storing data (including both volatile / non-volatile memory and removable / non-removable memory). The memory may include at least one non-volatile storage unit. To name just a few examples, the non-volatile storage unit can store one or more software programs. The software program may include, for example, an application, user data, device data, and / or configuration data, or a combination thereof. The software program may include instructions that can be executed by various components of the control circuit 612 of the memory macro 602.

[0110] For example, the memory may include a read-only memory (ROM), a random-access memory (RAM), a dynamic random access memory (DRAM), a double-data-rate dynamic random access memory (DDR-DRAM), a synchronous dynamic random access memory (SDRAM), a static random access memory (SRAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (e.g., a NOR flash memory or a NAND flash memory), a content addressable memory (CAM), a polymer memory (e.g., a ferroelectric polymer memory), a phase change memory (e.g., a bidirectional memory), a ferroelectric memory, a silicon-oxide-nitride-oxide-silicon (SONOS) memory, a disk memory (e.g., a 32-bit x-ray diffraction pattern), a 32-bit x-ray diffraction pattern, ... memory) (e.g., floppy disk, hard drive, optical disk, magnetic disk) or card (e.g., magnetic card, optical card) or any other type of medium suitable for storing information.

[0111] In one embodiment, the memory may include an instruction set in the form of a file for performing the method described herein for generating one or more timing libraries. The instruction set can be stored in any acceptable form of machine-readable instructions (including source code or various appropriate programming languages). Some examples of programming languages ​​that can be used to store instruction sets include, but are not limited to, Java, C, C++, C#, Python, Objective-C, Visual Basic, or .NET programming. In some embodiments, a compiler or interpreter is included to convert the instruction set into a machine executable code for execution by the processor.

[0112] In some embodiments, the I / O interface may include any suitable mechanisms or components to at least enable a user to provide input (i.e., test / request and / or test / normal mode, etc.) to the control circuit 612 of the memory macro 602 and enable the control circuit 612 of the memory macro 602 to provide output control to other components of the memory macro 602 (e.g., the memory cell array 604, the WD 606, the MUX 608, and the SA 610).

[0113] In some embodiments, the neural network macro 650 further includes two selectors 614 / 616. In some embodiments, the selectors 614 and 616 are configured to Figure 5A and Figure 5B The inputs are swapped by the rearrangement discussed in to form a mapped input to the storage cell array 604.

[0114] In some embodiments, the neural network macro 650 also includes a memory 618. In some embodiments, the memory may include any machine-readable or computer-readable medium capable of storing data (including both volatile / non-volatile memory and removable / non-removable memory). The memory may include at least one non-volatile storage unit. For example, the memory may include a read-only memory (ROM), a random access memory (RAM), a dynamic random access memory (DRAM), a double data rate dynamic random access memory (DDR-DRAM), a synchronous dynamic random access memory (SDRAM), a static random access memory (SRAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (e.g., NOR flash or NAND flash), a content addressable memory (CAM), a polymer memory (e.g., a ferroelectric polymer memory), a phase change memory (e.g., a bidirectional memory), a ferroelectric memory, a silicon-oxide-nitride-oxide-silicon (SONOS) memory, a disk memory (e.g., a floppy disk, a hard drive, an optical disk, a magnetic disk) or a card (e.g., a magnetic card, an optical card) or any other type of medium suitable for storing information.

[0115] In one embodiment, memory 618 includes FIG. 3A to FIG. 3B Defect pattern in any acceptable form as discussed in [D1], in the form of a file or machine-readable instructions N×M In some embodiments, the memory 618 includes addresses of corresponding defective memory cells in the memory cell array 604. In some embodiments, the defect pattern pre-stored in the memory 618 is determined by programming the measurement memory cell array 604 during the manufacturing process.

[0116] In some embodiments, the neural network macro 650 further includes a controller 620. In some embodiments, the controller 620 is configured to receive a defect pattern from the memory 618 and receive a weight pattern sensitivity (WPS) 624. In some embodiments, the controller 620 is further configured to determine a switching decision based on the defect pattern 300 and the WPS 206 to instruct the selector 614 / 616 to implement an I / O switch. In some embodiments, the selector 614 / 616 and the controller 620 may be configured outside the system interface 650. In some embodiments, the outside of the system interface 650 further includes at least one of the following: a processing unit, a sensing unit, and a power regulation unit, all of which are not shown.

[0117] Figure 6B A block diagram of a system 660 for determining a value on a neuron 108 on a hidden layer 114 of a network 100 according to some embodiments of the present disclosure is shown. It should be noted that the system 660 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional functional blocks located in or coupled to the system 660 may be provided, and some other functional blocks may only be briefly described herein.

[0118] exist Figure 6BIn the illustrated embodiment, the system 660 includes a neural network macro 650, wherein the neural network macro 650 includes a memory macro 602 and a memory 618. In some embodiments, the memory macro 602 includes a memory cell array 604, and the memory cell array 604 includes a plurality of memory cells. In some embodiments, the plurality of memory cells are arranged in a column-row configuration, wherein each column has a memory bit line (BL) and an anti-memory bit line (BLB), and each row has a word line (WL). More specifically, the BL and BLB of each column are respectively coupled to a plurality of memory cells arranged in this column, and each memory cell in this column is arranged on a different row and coupled to a corresponding (different) WL. That is, each memory cell of the memory cell array 604 is coupled to the BL of the column of the memory cell array 604, the BLB of the column of the memory cell array 604, and the WL of the row of the memory cell array 604. In some embodiments, the BL and the BLB are arranged in parallel in the vertical direction, and the WL is arranged in parallel in the horizontal direction (i.e., perpendicular to the BL and the BLB). In some embodiments, the WLs of each row of memory cells in the memory cell array 604 are connected together.

[0119] In some embodiments, each of the memory cells of the memory cell array 604 includes at least one transistor. In some other embodiments, each of the plurality of memory cells of the memory cell array 604 may include one of the following: a memristor, a resistive random access memory (ReRAM, RRAM), a phase change random access memory (PCRAM, PCM), a magnetoresistive random access memory (MRAM), a conductive bridge random access memory (CBRAM), a floating gate flash memory (FLASH), and a static random access memory (SRAM).

[0120] In some embodiments, the memory macro 602 further includes a write driver (WD) 606, a multiplexer (MUX) 608, a sense amplifier (SA) 610, and a control circuit 612. In some embodiments, the WD 606 is configured to provide the necessary voltage and / or current required to program the memory cell array 604. In some embodiments, the MUX 608 is configured to select a path for forwarding an input signal to an output. In some embodiments, the SA 610 is configured to compare a voltage or current generated during a read operation with a predefined threshold.

[0121] In some embodiments, the control circuit 612 is a representative device and may include a processor, a memory, an input / output interface, a communication interface, and a system bus. The processor may include any processing circuit system that can operate to control the operation and performance of the control circuit 612 of the memory macro 602. In various aspects, the processor may be implemented as a general-purpose processor, a chip multiprocessor (CMP), a special-purpose processor, an embedded processor, a digital signal processor (DSP), a network processor, an input / output (I / O) processor, a media access control (MAC) processor, a radio baseband processor, a coprocessor, a microprocessor (e.g., a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, and / or a very long instruction word (VLIW) microprocessor) or other processing device. The processor may also be implemented by a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), etc.

[0122] In various aspects, the processor can be arranged to run an operating system (OS) and various applications. Examples of OS include operating systems generally named by the trademark names of Apple OS, Microsoft Windows OS, Android OS, and any other proprietary or open source OS, for example.

[0123] In some embodiments, at least one non-transitory computer-readable storage medium containing computer-executable instructions thereon is provided, wherein the computer-executable instructions, when executed by at least one processor, cause the at least one processor to perform an embodiment of the method described herein. Such a computer-readable storage medium may be contained in a memory.

[0124] In some embodiments, the memory may include any machine-readable or computer-readable medium capable of storing data (including both volatile / non-volatile memory and removable / non-removable memory). The memory may include at least one non-volatile storage unit. The non-volatile storage unit is capable of storing one or more software programs. To name just a few examples, the software program may include, for example, an application, user data, device data, and / or configuration data, or a combination thereof. The software program may include instructions that can be executed by various components of the control circuit 612 of the memory macro 602.

[0125] For example, the memory may include read-only memory (ROM), random access memory (RAM), dynamic random access memory (DRAM), double data rate dynamic random access memory (DDR-DRAM), synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory (e.g., NOR flash memory or NAND flash memory), content addressable memory (CAM), polymer memory (e.g., ferroelectric polymer memory), phase change memory (e.g., bidirectional memory), ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, disk storage (e.g., floppy disk, hard drive, optical disk, magnetic disk) or card (e.g., magnetic card, optical card), or any other type of medium suitable for storing information.

[0126] In one embodiment, the memory may include an instruction set in the form of a file for performing the method of generating one or more timing libraries described herein. The instruction set can be stored in any acceptable form of machine-readable instructions (including source code or various appropriate programming languages). Some examples of programming languages ​​that can be used to store instruction sets include, but are not limited to, Java, C, C++, C#, Python, Objective-C, Visual Basic, or .NET programming. In some embodiments, a compiler or interpreter is included to convert the instruction set into a machine executable code for execution by a processor.

[0127] In some embodiments, the memory 618 may include any machine-readable or computer-readable medium capable of storing data (including both volatile / non-volatile memory and removable / non-removable memory). The memory 618 may include at least one non-volatile storage unit. For example, the memory 618 may include a read-only memory (ROM), a random access memory (RAM), a dynamic random access memory (DRAM), a double data rate dynamic random access memory (DDR-DRAM), a synchronous dynamic random access memory (SDRAM), a static random access memory (SRAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (e.g., NOR flash or NAND flash), a content addressable memory (CAM), a polymer memory (e.g., a ferroelectric polymer memory), a phase change memory (e.g., a bidirectional memory), a ferroelectric memory, a silicon-oxide-nitride-oxide-silicon (SONOS) memory, a disk memory (e.g., a floppy disk, a hard drive, an optical disk, a magnetic disk) or a card (e.g., a magnetic card, an optical card) or any other type of medium suitable for storing information.

[0128] In one embodiment, memory 618 includes FIG. 3A to FIG. 3B Defect pattern in any acceptable form as discussed in [D1], in the form of a file or machine-readable instructions N×M In some embodiments, the memory 618 includes addresses of corresponding defective memory cells in the memory cell array 604. In some embodiments, the defect pattern pre-stored in the memory 618 is determined by programming the measurement memory cell array 604 during the manufacturing process.

[0129] In some embodiments, the network macro 650 is coupled to the first selector 614, the second selector 616, and the controller 620. In some embodiments, the system 660 further includes two selectors 614 / 616. In some embodiments, the selectors 614 and 616 are configured to Figure 5A and Figure 5B The inputs are swapped by the rearrangement discussed in to form a mapped input to the storage cell array 604.

[0130] In some embodiments, the controller 620 is configured to receive the defect pattern from the memory 618 and receive the weighted pattern sensitivity (WPS) 624. In some embodiments, the controller 620 is further configured to determine a swap decision based on the defect pattern 300 and the WPS 206 to instruct the selector 614 / 616 to implement the I / O swap. In some embodiments, the system 660 further includes at least one of the following: a processing unit, a sensing unit, and a power regulation unit, all of which are not shown and are located outside the neural network macro 650.

[0131] Fig. 7A A flowchart of a method 700 is shown according to some embodiments of the present disclosure, wherein the method 700 uses the system 600 or 660 to perform calculations on the values ​​of each of the neurons 108 on the hidden layer 114 of the network 100. In some embodiments, the operations of the method 700 are performed by Figure 1 , Figure 3, Figure 5 and FIG. 6A to FIG. 6B For the convenience of discussion, the corresponding components shown in Figure 1 , Figure 3, Figure 5 and FIG. 6A to FIG. 6B The following embodiments of method 700 are described. The illustrated embodiments of method 700 are merely examples of weight rearrangement according to the weight pattern sensitivity (WPS) of the weight pattern. Therefore, it should be understood that any of the various operations may be omitted, reordered, and / or added while remaining within the scope of the present disclosure.

[0132] Method 700 begins with operation 702, in which a defect pattern [D1] of cell array 604 is stored according to some embodiments. N×M300 is loaded into the controller 620. In some embodiments, the defect pattern [D1] N×M 300 includes the address of the defective memory cell in the memory cell array 604. In some embodiments, a defect pattern indicator (DPI) 306 may be loaded into the controller 620. In some embodiments, the DPI 306 includes 1 row and m columns, where m=log2M, and M is the corresponding defect pattern [D1] N×M 300. In some embodiments, when the defect pattern [D] N×M When the number of defective memory cells in the column 302-j of 300 is equal to or greater than a predefined threshold, the DPI 306 is determined as the address of the column 302-j. In some other embodiments, for a corresponding defect pattern [D1] including N rows and M columns, N×M 300, DPI 306 may also include N rows and 1 column. In some embodiments, when the defect pattern [D1] N×M When the number of defective memory cells in column 302-j of 300 is equal to or greater than a predefined threshold, the d in DPI 306 is j is determined to be "0"; and when the defect pattern [D1] N×M When the number of defective memory cells in column 302-j of 300 is less than a predefined threshold, the corresponding d in DPI 306 is j is determined as "1". In some embodiments, the defect pattern [D1] N×M 300 or DPI 306 may be stored in memory 618 .

[0133] In some embodiments, before operation 702, the defect pattern [D1] may be determined by measuring the memory cell array 604. N×M . In some embodiments, operation 702 also includes writing a preconfigured logical state (e.g., "1") to each of the plurality of storage cells in the storage cell array 604 and measuring the stored logical state. When the stored logical state in the storage cell is consistent with the preconfigured logical state (e.g., both are "1"), the storage cell is stable and defect-free. When the stored logical state in the storage cell is different from the preconfigured logical state (e.g., the stored logical state is "0"), the storage cell is determined to be defective, and therefore, the storage cell is a defect in the storage cell array 604. Specifically, the storage cell has a "1" to "0" defect. Similarly, when "0" is written to the storage cell and the stored logical state is "1", the storage cell is also determined to have a "0" to "1" defect. In some embodiments, operation 702 may be performed by a neural network system or by a memory manufacturer during the manufacturing process.

[0134] The method 700 continues with operation 704, where the weight pattern sensitivity (WPS) 206 is loaded into the controller 620 according to some embodiments. In the illustrated embodiment, the WPS 206 includes 1 row and M columns. In some embodiments, the corresponding weight pattern [W] may be determined based on the number of "0"s or the number of "1"s in the column 202. N×M For example, when the number of "1"s in column 202-j is equal to or greater than a predefined threshold, the S in WPS 206 is j is determined to be 1, where j≤N and j is a positive integer. Similarly, when the number of "1"s in column 202-j is less than a predefined threshold, S in WPS 206 j is determined to be "0". In some embodiments, for the corresponding weight pattern [W] N×M 118, there is a WPS 206. In some embodiments, the WPS 206 can be externally obtained and / or adjusted by the user.

[0135] In some embodiments, the value in WPS 206 is determined by comparing the number of positive weights in a column of the weight pattern to a multi-level threshold. For example, when the number of positive weights in a column of the weight pattern is equal to or greater than 0 and less than 5, the WPS value for this column is 0; when the number of positive weights in a column of the weight pattern is equal to or greater than 5 and less than 10, the WPS value for this column is 1; when the number of positive weights in a column of the weight pattern is equal to or greater than 10 and less than 15, the WPS value for this column is 2; and when the number of positive weights in a column of the weight pattern is equal to or greater than 15 and less than the size of the column (e.g., Figure 2 When N is 0, the WPS value of this column is 3.

[0136] Method 700 continues with operation 706, where the controller 620 performs a pairing operation between the WPS 206 and the corresponding weight pattern 118 [W] according to some embodiments. N×M Defect pattern [D1] N×M 300. In some other embodiments, the WPS 206 is compared to the DPI 306 by the controller 620. In some other embodiments, the WPS 206 is determined to be consistent with the defect pattern [D1] N×M 300 is the product of the number of defects in each column.

[0137] The method 700 continues with operation 708, where a swap decision is determined by the controller 620 according to some embodiments. In some embodiments, the column in the memory cell array 604 having the highest number of defects and the highest number of ones in the corresponding weight pattern is determined to receive the weights and input data originally stored on the column in the memory cell array 604 having the lowest number of defects and the lowest number of ones in the corresponding weight pattern. In some other embodiments, the swap decision is determined according to the WPS 206 and the defect pattern [D1] N×M 300 to determine the statistical severity (SS) 514. In some embodiments, the column with the highest number of SS 514 in the storage cell array 604 of the storage cell array is determined to receive the weights and input data originally stored on the column with the lowest number of SS 514 in the storage cell array 604.

[0138] Method 700 continues with operation 710, where the weight pattern [W] is set according to some embodiments. N×M 118 is loaded as input 622 into the neural network macro 650. In some embodiments, the weight pattern [W] N×M 118 is determined by a training process using software without considering the memory cell array 604 and potential defects of the memory cell array 604 caused by the corresponding manufacturing process. In some embodiments, the weight pattern [W] N×M 118 is loaded into the neural network macro 650 as input 622 through a selector 614 located outside the neural network macro 650.

[0139] Method 700 continues with operation 712, where the weight pattern [W] is adjusted according to some embodiments. N×M 118 performs rearrangement to determine the rearranged weight pattern [W] by exchanging I / O' N×M In some embodiments, the rearranged weight pattern [W]' N×M is determined according to the swap decision determined in operation 708. For example, the weight pattern [W] at the input N×M 118 and the corresponding weight pattern [W] in the storage cell array 604 N×M The column 202-a corresponding to the column with the highest number of defects and the highest number of 1s in 118 and the weight pattern [W] at the input N×M 118 and the storage cell array 604 in the corresponding weight pattern [W] N×M The row 202-b corresponding to the row with the lowest number of defects and the lowest number of 1s in 118 is switched, where a and b are positive integers and both are less than M. In some embodiments, this rearrangement process can be performed as follows Figure 7B is explained in.

[0140] Figure 7B A flow chart of a method 730 for switching I / O through a state machine in a selector 614 according to some embodiments of the present disclosure is shown. The method 730 begins with operation 732, in which data is provided at an input I / O of the selector 614 according to some embodiments. In some embodiments, a corresponding weight pattern [W] is provided at the input I / O of the selector 614 N×M 118. In some embodiments, the selector 614 is located inside the neural network macro 650. In some embodiments, the selector 614 can be selected and implemented according to the needs of the user. In some embodiments, the data can be one of the following: weight pattern [W] N×M 118 and data input [A], which will be discussed in further detail below.

[0141] Method 730 continues with operation 734, where data in at least two exchange I / Os is stored according to some embodiments. In some embodiments, the exchange I / O is associated with a weight pattern [W] N×M The data in columns 202-a and 202-b correspond to input I / Os in 118. In some embodiments, the data in columns 202-a and 202-b are stored in two corresponding temporary parameters.

[0142] Method 730 continues with operation 736, where two mask arrays are prepared and output I / Os are determined according to some embodiments. In some embodiments, the two mask arrays (including an OR_mask and an AND_mask) are selected by selector 614 based on the data content of the exchange I / O at input 622 (e.g., weight pattern [W] N×M 118) is generated by the columns 202-a and 202-b of the selector 614. In some embodiments, the output I / O of the selector 614 is determined by the following operations:

[0143] Output I / O = Input I / O | OR_mask & AND_mask, where "|" is a bitwise OR operator and "&" is a bitwise AND operator.

[0144] Method 730 continues with operation 738, where data on the output I / O is determined according to some embodiments. In some embodiments, according to the weight pattern [W] N×M and the two mask arrays to determine the rearranged weight pattern [W]' N×MFor example, data in column 202-a stored in the first temporary parameter is loaded into the output I / O corresponding to column 202-b and data in column 202-b stored in the second temporary parameter is loaded into the output I / O corresponding to column 202-a.

[0145] In some embodiments, method 730 continues with operation 734 according to some embodiments.

[0146] Figure 7C Table 740 is shown according to some embodiments of the present disclosure, and table 740 has Figure 7B In the embodiment shown, the input I / O includes 8 bits (01011010), and according to Fig. 7A The process described in determines that the third bit and the fifth bit will be swapped. In some embodiments, the third I / O includes data 011 stored on the first temporary parameter (e.g., temp 1), and the fifth I / O includes data 101 stored on the second temporary parameter (i.e., temp 2). In some embodiments, the first mask (i.e., an OR mask) includes 8 bits and the third bit is 1, while all other bits of the first mask are 0; the second mask (i.e., an AND mask) also includes 8 bits and the fifth bit is 0, while all other bits of the second mask are 1. After the operation, the output I / O includes 8 bits, i.e., 01110010. In addition, the third I / O in the output I / O outputs data 101 and the fifth I / O in the output I / O outputs data 011.

[0147] Method 700 proceeds to operation 714, where the rearranged weight pattern [W]′ is converted into a new weight pattern according to some embodiments. N×M The rearranged weight pattern [W] is loaded into the storage cell array 604. In some embodiments, the rearranged weight pattern [W] is written by storing "0" or "1" in the corresponding storage cell of the storage cell array 604. N×M In some embodiments, the columns in the storage cell array 604 having the highest number of defects and the highest number of ones in the corresponding weight pattern receive the weights originally stored in the columns in the storage cell array 604 having the lowest number of defects and the lowest number of ones in the corresponding weight pattern. Similarly, the columns in the storage cell array 604 having the lowest number of defects and the lowest number of ones in the corresponding weight pattern receive the weights originally stored in the columns in the storage cell array 604 having the highest number of defects and the highest number of ones in the corresponding weight pattern. All other columns receive their corresponding weights without further modification.

[0148] Method 700 continues with operation 716, where the values ​​on the neurons 106 of the input layer 112 are loaded into the neural network macro 650 according to some embodiments. In some embodiments, the values ​​on the neurons 106 of the input layer 112 are input data [A] M×1 In some embodiments, the input data [A] M×1 Can be loaded from the output of a previous process.

[0149] Method 700 continues with operation 712, where, according to some embodiments, the input data [A] M×1 Rearrange to determine the rearranged input data [A]' M×1 In some embodiments, the rearranged input data [A]' M×1 is determined according to the swap decision determined in operation 708. In some embodiments, before loading into the storage cell array 604, the rearranged input data [A]' M×1 Input data transposed from columns to rows ([A]' 1×M ). In some embodiments, according to the above Figure 7B The method 730 discussed in the above obtains the rearranged input data [A]' M×1 .

[0150] Method 700 continues with operation 714, in which the rearranged and transposed input data [A]′ is processed according to some embodiments. 1×M Loaded into storage cell array 604.

[0151] Method 700 continues with operation 718, where mapping output data [B]′ is determined according to some embodiments. N×M In some embodiments, the mapping output data [B]' N×M is determined according to a predetermined algorithm. In some embodiments, the rearranged input data [A]' 1×M and the rearranged weight pattern [W]' N×M The processing is performed in the corresponding storage cell through intra-bit multiplication.

[0152] Method 700 continues with operation 720, where output data [B] is determined according to some embodiments. N×M In some embodiments, the output data [B] N×M The output data is mapped according to the exchange decision [B]' N×M Continue to refer to Figure 7B, the output data on the column 202-a of the memory cell array is then output on the output I / O of the corresponding column 202-b. Similarly, the output data on the column 202-b of the memory cell array is then output on the output I / O of the corresponding column 202-b. In some embodiments, the swap decision is received by the selector 616 from the controller 620. In some embodiments, operation 720 is performed by the selector 616 at the output.

[0153] Figure 8 A block diagram of a system 800 for determining a value on a neuron 108 on a hidden layer 114 of a network 100 according to some embodiments of the present disclosure is shown. It should be noted that the system 800 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional functional blocks may be provided in or coupled to the system 800, and some other functional blocks may only be briefly described herein.

[0154] exist Figure 8 In the illustrated embodiment, the system 800 includes a neural network macro 650, wherein the neural network macro 650 includes a memory macro 602. In some embodiments, the memory macro 602 includes a memory cell array 604, and the memory cell array 604 includes a plurality of memory cells. In some embodiments, the plurality of memory cells are arranged in a column-row configuration, wherein each column has a bit line (BL) and an anti-bit line (BLB), and each row has a word line (WL). More specifically, the BL and BLB of each column are respectively coupled to a plurality of memory cells arranged in this column, and each memory cell in this column is arranged on a different row and coupled to a corresponding (different) WL. That is, each memory cell of the memory cell array 604 is coupled to the BL of the column of the memory cell array 604, the BLB of the column of the memory cell array 604, and the WL of the row of the memory cell array 604. In some embodiments, the BL and the BLB are arranged in parallel in the vertical direction, and the WL is arranged in parallel in the horizontal direction (i.e., perpendicular to the BL and the BLB). In some embodiments, the WLs of each row of memory cells in the memory cell array 604 are connected together.

[0155] In some embodiments, each of the memory cells of the memory cell array 604 includes at least one transistor. In some other embodiments, each of the plurality of memory cells of the memory cell array 604 may include one of the following: a memristor, a resistive random access memory (ReRAM, RRAM), a phase change random access memory (PCRAM, PCM), a magnetoresistive random access memory (MRAM), a conductive bridge random access memory (CBRAM), a floating gate flash memory (FLASH), and a static random access memory (SRAM).

[0156] In some embodiments, the memory macro 602 further includes a write driver (WD) 606, a multiplexer (MUX) 608, a sense amplifier (SA) 610, and a control circuit 612. In some embodiments, the WD 606 is configured to provide the necessary voltage and / or current required to program the memory cell array 604. In some embodiments, the MUX 608 is configured to select a path for forwarding an input signal to an output. In some embodiments, the SA 610 is configured to compare a voltage or current generated during a read operation with a predefined threshold.

[0157] In some embodiments, the control circuit 612 is a representative device and may include a processor, a memory, an input / output interface, a communication interface, and a system bus. The processor may include any processing circuit system that can operate to control the operation and performance of the control circuit 612 of the memory macro 602. In various aspects, the processor may be implemented as a general-purpose processor, a chip multiprocessor (CMP), a special-purpose processor, an embedded processor, a digital signal processor (DSP), a network processor, an input / output (I / O) processor, a media access control (MAC) processor, a radio baseband processor, a coprocessor, a microprocessor (e.g., a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, and / or a very long instruction word (VLIW) microprocessor) or other processing device. The processor may also be implemented by a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), etc.

[0158] In various aspects, the processor can be arranged to run an operating system (OS) and various applications. Examples of OS include operating systems generally named by the trademark names of Apple OS, Microsoft Windows OS, Android OS, and any other proprietary or open source OS, for example.

[0159] In some embodiments, at least one non-transitory computer-readable storage medium containing computer-executable instructions thereon is provided, wherein the computer-executable instructions, when executed by at least one processor, cause the at least one processor to perform an embodiment of the method described herein. Such a computer-readable storage medium may be contained in a memory.

[0160] In some embodiments, the memory may include any machine-readable or computer-readable medium capable of storing data (including both volatile / non-volatile memory and removable / non-removable memory). The memory may include at least one non-volatile storage unit. The non-volatile storage unit is capable of storing one or more software programs. To name just a few examples, the software program may include, for example, an application, user data, device data, and / or configuration data, or a combination thereof. The software program may include instructions that can be executed by various components of the control circuit 612 of the memory macro 602.

[0161] For example, the memory may include read-only memory (ROM), random access memory (RAM), dynamic random access memory (DRAM), double data rate dynamic random access memory (DDR-DRAM), synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory (e.g., NOR flash memory or NAND flash memory), content addressable memory (CAM), polymer memory (e.g., ferroelectric polymer memory), phase change memory (e.g., bidirectional memory), ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, disk storage (e.g., floppy disk, hard drive, optical disk, magnetic disk) or card (e.g., magnetic card, optical card), or any other type of medium suitable for storing information.

[0162] In one embodiment, the memory may include an instruction set in the form of a file for performing the method of generating one or more timing libraries described herein. The instruction set can be stored in any acceptable form of machine-readable instructions (including source code or various appropriate programming languages). Some examples of programming languages ​​that can be used to store instruction sets include, but are not limited to, Java, C, C++, C#, Python, Objective-C, Visual Basic, or .NET programming. In some embodiments, a compiler or interpreter is included to convert the instruction set into a machine executable code for execution by a processor.

[0163] In some embodiments, the I / O interface may include any suitable mechanisms or components to at least enable a user to provide input (i.e., test / request and / or test / normal mode, etc.) to the control circuit 612 of the memory macro 602 and enable the control circuit 612 of the memory macro 602 to provide output control to other components of the memory macro 602 (e.g., the memory cell array 604, the WD 606, the MUX 608, and the SA 610).

[0164] In some embodiments, the neural network macro 650 further includes two selectors 614 / 616. In some embodiments, the selector 614 is configured to Figure 5A and Figure 5B The inputs are swapped according to the swap decision discussed in , to form the mapping inputs of the storage cell array 604, and the selector 616 is configured according to Figure 5A and Figure 5B The outputs of storage cell array 604 are swapped using the swap decisions discussed in .

[0165] In some embodiments, the neural network macro 650 also includes a memory 618. In some embodiments, the memory may include any machine-readable or computer-readable medium capable of storing data (including both volatile / non-volatile memory and removable / non-removable memory). The memory may include at least one non-volatile storage unit. For example, the memory may include a read-only memory (ROM), a random access memory (RAM), a dynamic random access memory (DRAM), a double data rate dynamic random access memory (DDR-DRAM), a synchronous dynamic random access memory (SDRAM), a static random access memory (SRAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (e.g., NOR flash or NAND flash), a content addressable memory (CAM), a polymer memory (e.g., a ferroelectric polymer memory), a phase change memory (e.g., a bidirectional memory), a ferroelectric memory, a silicon-oxide-nitride-oxide-silicon (SONOS) memory, a disk memory (e.g., a floppy disk, a hard drive, an optical disk, a magnetic disk) or a card (e.g., a magnetic card, an optical card) or any other type of medium suitable for storing information.

[0166] In one embodiment, memory 618 includes FIG. 3A to FIG. 3B Defect pattern in any acceptable form as discussed in [D1], in the form of a file or machine-readable instructions N×M In some embodiments, the memory 618 includes addresses of corresponding defective memory cells in the memory cell array 604. In some embodiments, the defect patterns pre-stored in the memory 618 are determined by measuring the memory cell array 604 during the manufacturing process.

[0167] In some embodiments, the neural network macro 650 further includes a controller 620. In some embodiments, the controller 620 is configured to receive the defect pattern from the memory 618 and receive the weight pattern sensitivity (WPS) 624. In some embodiments, the controller 620 is further configured to determine a swap decision based on the defect pattern 300 and the WPS 624 to instruct the selector 614 / 616 to perform an I / O swap.

[0168] In some embodiments, the neural network macro 650 further includes a buffer 802 and a processor 804. In some embodiments, the buffer 802 stores a plurality of weights used by the processor 804 to determine the WPS 624. In some embodiments, the processor 804 is enabled by the EN signal 806 to determine the WPS 624 according to the plurality of weights stored in the buffer 802. In some embodiments, the system interface 650 further includes at least one of the following outside: a processing unit, a sensing unit, and a power regulation unit, all of which are not shown.

[0169] Fig. 9 A flowchart of a method 900 is shown according to some embodiments of the present disclosure, which performs calculations on values ​​of each of the neurons 108 on the hidden layer 114 of the network 100. In some embodiments, the operations of the method 900 are performed by Figure 1 To Figure 4, Figure 5, Figure 7B and Figure 8 For the convenience of discussion, the corresponding components shown in Figure 1 To Figure 4, Figure 5, Figure 7B and Figure 8 The following embodiments of method 900 are described. The illustrated embodiments of method 900 are merely examples of performing calculations on values ​​on each of neurons 108 on hidden layer 114 of network 100. Therefore, it should be understood that any of the various operations may be omitted, reordered, and / or added while remaining within the scope of the present disclosure. It should also be noted that network 100 may include multiple hidden layers and each of the multiple hidden layers may include a different number of neurons, more than 2 I / Os may be determined to be exchanged, and different algorithms may be used to determine the values ​​on each of the neurons, all of which are within the scope of the present application.

[0170] Method 900 begins with operation 902, in which a defect pattern [D1] of cell array 604 is stored according to some embodiments. N×M 300 is loaded into the memory 618 of the neural network macro 650. In some embodiments, the defect pattern [D1] N×M 300 includes the address of the defective memory cell in the memory cell array 604. In some embodiments, a defect pattern indicator (DPI) 306 may be loaded into the controller 620. In some embodiments, the DPI 306 includes 1 row and m columns, where m=log2M, and M is the corresponding defect pattern [D1] N×M 300. In some embodiments, when the defect pattern [D] N×MWhen the number of defective memory cells in the column 302-j of 300 is equal to or greater than a predefined threshold, the DPI 306 is determined as the address of the column 302-j. In some other embodiments, for a corresponding defect pattern [D1] including N rows and M columns, N×M 300, DPI 306 may also include N rows and 1 column. In some embodiments, when the defect pattern [D1] N×M When the number of defective memory cells in column 302-j of 300 is equal to or greater than a predefined threshold, the d in DPI 306 is j is determined to be "0"; and when the defect pattern [D1] N×M When the number of defective memory cells in column 302-j of 300 is less than a predefined threshold, the corresponding d in DPI 306 is j is determined as "1". In some embodiments, the defect pattern [D1] N×M 300 or DPI 306 may be stored in memory 618 .

[0171] In some embodiments, the defect pattern [D1] may be determined by measuring the memory cell array 604. N×M 300. In some embodiments, operation 902 also includes writing a preconfigured logic state (e.g., "1") to each of a plurality of storage cells in the storage cell array 604 and measuring the stored logic state. When the stored logic state in the storage cell is consistent with the preconfigured logic state (e.g., both are "1"), the storage cell is stable and non-defective. When the stored logic state in the storage cell is different from the preconfigured logic state (e.g., the stored logic state is "0"), the storage cell is determined to be defective and the storage cell is a defect in the storage cell array 604. In some embodiments, operation 902 may be performed by a neural network system or by a memory manufacturer during a manufacturing process.

[0172] Method 900 proceeds to operation 904, where the weight pattern [W] is set according to some embodiments. N×M 118 is loaded as input 622 into the neural network macro 650. In some embodiments, the weight pattern [W] N×M 118 is determined by a training process using software without considering the memory cell array 604 and potential defects of the memory cell array 604 introduced during the corresponding manufacturing process. In some embodiments, the weight pattern [W] N×M 118 is loaded into the neural network macro 650 as input 622 and arrives at the buffer 802 of the neural network macro 650.

[0173] The method 900 continues with operation 906, where a weight pattern sensitivity (WPS) 206 is determined according to some embodiments. In some embodiments, the WPS 206 is determined by the processor 804 of the neural network macro 650 based on the weight pattern [W] stored in the buffer 802. N×M In the illustrated embodiment, WPS 206 includes 1 row and M columns. In some embodiments, the corresponding weight pattern [W] may be determined based on the number of "0"s or the number of "1"s in column 202. N×M For example, when the number of "1"s in column 202-j is equal to or greater than a predefined threshold, the S in WPS 206 is j is determined to be 1, where j≤N and j is a positive integer. Similarly, when the number of "1"s in column 202-j is less than a predefined threshold, S in WPS 206 j is determined to be "0". In some embodiments, for the corresponding weight pattern 118 [W] N×M , there is one WPS 206. In some embodiments, the WPS 206 may vary according to different thresholds, which may be predefined or specified by a user.

[0174] In some embodiments, the value in WPS 206 is determined by comparing the number of positive weights in a column of the weight pattern to a multi-level threshold. For example, when the number of positive weights in a column of the weight pattern is equal to or greater than 0 and less than 5, the WPS value for this column is 0; when the number of positive weights in a column of the weight pattern is equal to or greater than 5 and less than 10, the WPS value for this column is 1; when the number of positive weights in a column of the weight pattern is equal to or greater than 10 and less than 15, the WPS value for this column is 2; and when the number of positive weights in a column of the weight pattern is equal to or greater than 15 and less than the size of the column (e.g., Figure 2 When N is 0, the WPS value of this column is 3.

[0175] Method 900 continues with operation 908, where the controller 620 performs a pairing operation between the WPS 206 and the corresponding weight pattern [W] according to some embodiments. N×M Defect pattern of 118 [D1] N×M 300. In some other embodiments, the WPS 206 is compared to the DPI 306 by the controller 620. In some other embodiments, the WPS 206 is determined to be consistent with the defect pattern [D1] N×M The product of the number of defects in each column of 300. In some embodiments, controller 620 receives WPS 624 from processor 804 and defect pattern 300 from memory 618 to determine a switching decision.

[0176] The method 900 continues with operation 910, where a swap decision is determined by the controller 620 according to some embodiments. In some embodiments, the column in the memory cell array 604 having the highest number of defects and the highest number of ones in the corresponding weight pattern is determined to receive the weights and input data originally stored on the column in the memory cell array 604 having the lowest number of defects and the lowest number of ones in the corresponding weight pattern. In some other embodiments, the swap decision is determined according to the WPS 206 and the defect pattern [D1]. N×M 300 to determine the statistical severity (SS) 514. In some embodiments, the column with the highest number of SS 514 in the storage cell array 604 of the storage cell array is determined to receive the weights and input data originally stored on the column with the lowest number of SS 514 in the storage cell array 604.

[0177] Method 900 proceeds to operation 912, where the weight pattern [W] is set according to some embodiments. N×M 118 is loaded into selector 614. In some embodiments, the weight pattern [W] N×M 118 is loaded from buffer 802 to selector 614.

[0178] Method 900 proceeds to operation 914, where the weight pattern [W] is adjusted according to some embodiments. N×M 118 is rearranged to determine the mapping weight pattern [W]' N×M In some embodiments, the mapping weight pattern [W]' N×M is determined according to the swap decision determined in operation 910. For example, the weight pattern [W] at the input N×M 118 and the corresponding weight pattern [W] in the storage cell array 604 N×M The column 202-a corresponding to the column with the highest number of defects and the highest number of 1s in 118 and the weight pattern [W] at the input N×M 118 and the storage cell array 604 in the corresponding weight pattern [W] N×M The column 202 - b corresponding to the column with the lowest number of defects and the lowest number of 1s in 118 is switched, where a and b are positive integers and both are less than M.

[0179] Method 900 proceeds to operation 916, where the mapping weight pattern [W]′ is mapped according to some embodiments. N×M The mapping weight pattern [W] is loaded into the storage cell array 604. In some embodiments, the mapping weight pattern [W] is written by storing a "0" or a "1" in a corresponding storage cell of the storage cell array 604. N×MIn some embodiments, the columns in the storage cell array 604 having the highest number of defects and the highest number of ones in the corresponding weight pattern receive the weights originally stored in the columns in the storage cell array 604 having the lowest number of defects and the lowest number of ones in the corresponding weight pattern. Similarly, the columns in the storage cell array 604 having the lowest number of defects and the lowest number of ones in the corresponding weight pattern receive the weights originally stored in the columns in the storage cell array 604 having the highest number of defects and the highest number of ones in the corresponding weight pattern. All other columns receive their corresponding weights without further modification.

[0180] Method 900 continues with operation 912, where the values ​​on the neurons 106 of the input layer 112 are loaded into the neural network macro 650 according to some embodiments. In some embodiments, the values ​​on the neurons 106 of the input layer 112 are input data [A] M×1 In some embodiments, the input data may be loaded from the output of the previous network [A] M×1 .

[0181] Method 900 proceeds to operation 914, where, according to some embodiments, input data [A] M×1 Rearrange to determine the mapping input data [A]' M×1 In some embodiments, the mapping input data [A]' M×1 is determined based on the swap decision determined in operation 910. In some embodiments, the mapping input data [A]' M×1 Then transpose from columns to rows ([A]') before loading into the storage cell array 604. 1×M ). In some embodiments, according to Figure 7B The method 730 shown in FIG. 7 obtains the mapping input data [A]' M×1 .

[0182] Method 900 continues with operation 916, where the mapped and transposed input data [A]′ is converted into 1×M Loaded into storage cell array 604.

[0183] Method 900 proceeds to operation 918, where mapping output data [B]′ is determined according to some embodiments. N×M In some embodiments, the mapping output data [B]' N×M is determined according to a predetermined algorithm. In some embodiments, the mapped and transposed input data [A]' 1×M and mapping weight pattern [W]' N×MThe processing is performed in the corresponding storage cell through in-bit multiplication.

[0184] Method 900 continues with operation 920, where output data [B] is determined according to some embodiments. N×M In some embodiments, the output data [B] N×M The output data is mapped according to the exchange decision [B]' N×M Continue to refer to Figure 7B , then outputting the output data on the column 202-a of the storage cell array on the output I / O of the corresponding column 202-b, and then outputting the output data on the column 202-b of the storage cell array on the output I / O of the corresponding column 202-b. In some embodiments, the swap decision is received by the selector 616 from the controller 620. In some embodiments, operation 920 is performed by the selector 616 at Figure 8 The neural network macro 650 is shown to be implemented at the output.

[0185] In one embodiment, a method for calculating a value on a first neuron of a first layer in a neural network includes: receiving a first pattern of a storage cell array, wherein the storage cell array includes a plurality of storage cells, the plurality of storage cells being configured into a plurality of columns and a plurality of rows; determining a second pattern of the storage cell array using a third pattern; determining at least one pair of columns of the storage cell array according to the first pattern and the second pattern; switching input data of two columns in each of the at least one pair of columns of the storage cell array; performing bit-by-bit calculation using the input data stored in the plurality of storage cells; and switching output data of the two columns in each of the at least one pair of columns of the storage cell array to determine the value on the first neuron of the first layer. In one embodiment, the first pattern is a defect pattern, wherein the defect pattern maps at least one defective storage cell in the storage cell array. In one embodiment, the method further includes, before receiving the first pattern, writing a preconfigured logic state to each of the plurality of storage cells; measuring the stored logic state in each of the plurality of storage cells; and comparing the preconfigured logic state with the stored logic state in each of the plurality of storage cells to determine at least one defective storage cell. In one embodiment, the second pattern includes a plurality of weight pattern sensitivity values, wherein each of the plurality of weight pattern sensitivity values ​​is determined by comparing at least one predetermined threshold with one of the following numbers in a corresponding column in the third pattern: a first number of logical "1" values, and a second number of logical "0" values. In one embodiment, the third pattern is a weight pattern including a plurality of weights, wherein each of the plurality of weights has a value of "0" or a value of "1". In one embodiment, the third pattern is determined by an off-chip training process. In one embodiment, the determining of at least one pair of columns further comprises determining the number of defective memory cells in each of the plurality of columns of the memory cell array according to the first pattern; determining a statistical severity value for each of the plurality of columns, wherein the statistical severity value for the corresponding column is determined as the product of the number of defective memory cells and the value of the corresponding column in the second pattern; and determining the at least one pair of columns according to the statistical severity value. In one embodiment, the input data comprises one of the following: the third pattern, and output data of a second neuron of the second layer, wherein the second neuron of the second layer is coupled to the first neuron of the first layer.

[0186] In another embodiment, a system for calculating a value on a first neuron of a first layer in a neural network includes: a storage cell array including a plurality of storage cells, the plurality of storage cells being arranged into a plurality of columns and a plurality of rows; a storage unit configured to store a first pattern; a processor unit configured to determine a second pattern using a third pattern; a controller unit configured to determine at least one pair of columns of the storage cell array according to the first pattern received from the storage unit and the second pattern received from the processor unit; a first selector configured to switch input data of two columns in each of the at least one pair of columns of the storage cell array; and a second selector configured to switch output data of the two columns in each of the at least one pair of columns of the storage cell array to determine the value on the respective neuron. In one embodiment, the first pattern is a defect pattern, wherein the defect pattern maps at least one defective storage cell in the storage cell array. In one embodiment, the first pattern is determined by: writing a preconfigured logic state to each of the plurality of storage cells; measuring the stored logic state in each of the plurality of storage cells; and comparing the preconfigured logic state with the stored logic state in each of the plurality of storage cells. In one embodiment, the second pattern includes a plurality of weight pattern sensitivity values, wherein each of the plurality of weight pattern sensitivity values ​​is determined by comparing at least one predetermined threshold with one of the following numbers in the corresponding column in the third pattern: a first number of logic "1" values, and a second number of logic "0" values. In one embodiment, the third pattern is a weight pattern including a plurality of weights, wherein each of the plurality of weights has a value "0" or a value "1". In one embodiment, the input data includes one of the following: the third pattern, and output data of a second neuron of a second layer, wherein the second neuron of the second layer is coupled to the first neuron of the first layer. In one embodiment, the first selector and the second selector are controlled by the controller. In one embodiment, the third pattern is determined by an off-chip training process. In one embodiment, the at least one pair of columns is determined based on statistical severity values ​​of the plurality of columns, wherein each of the statistical severity values ​​of a corresponding column is determined as a product of the number of defective storage cells of the corresponding column and a value of the corresponding column in the second pattern.

[0187] In yet another embodiment, a system for performing calculations on a value on a first neuron of a first layer in a neural network includes: a storage cell array including a plurality of storage cells, the plurality of storage cells being configured into a plurality of columns and a plurality of rows; a storage unit configured to store a first pattern; a processor unit configured to determine a second pattern using a third pattern; a controller unit configured to determine at least one pair of columns of the storage cell array based on the first pattern received from the storage unit and the second pattern received from the processor unit; a first selector configured to switch input data of two columns in each pair of the at least one pair of columns of the storage cell array; and a second selector configured to select the at least one pair of columns of the storage cell array. The output data of the two columns in each pair of at least one pair of columns are switched to determine the values ​​on the respective neurons, wherein the first pattern is a defect pattern, wherein the defect pattern maps at least one defective storage cell in the storage cell array, wherein the second pattern includes a plurality of weight pattern sensitivity values, wherein each of the plurality of weight pattern sensitivity values ​​is determined by comparing at least one predetermined threshold with one of the following numbers in the corresponding column in the third pattern: a [first] number of logical "1" values, and a second number of logical "0" values, and wherein the third pattern is a weight pattern including a plurality of weights, wherein each of the plurality of weights has a value of "0" or a value of "1". In one embodiment, the input data includes one of the following: the third pattern, and output data of a second neuron of a second layer, wherein the second neuron of the second layer is coupled to the first neuron of the first layer. In one embodiment, the third pattern is determined by an off-chip training process.

[0188] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

Claims

1. A method for calculating a value on a first neuron of a first layer in a neural network, comprising: Receiving a first pattern of a memory cell array, wherein the memory cell array includes a plurality of memory cells, and the plurality of memory cells are arranged into a plurality of columns and a plurality of rows; determining a second pattern of the memory cell array using a third pattern; Determine at least one pair of columns of the memory cell array according to the first pattern and the second pattern; Switching input data of two columns in each of the at least one pair of columns of the memory cell array; Performing bit-by-bit calculations using the input data stored in the plurality of memory cells; and The output data of the two columns in each of the at least one pair of columns of the storage cell array are switched to determine the value of the first neuron of the first layer, wherein The first pattern is a defect pattern that maps at least one defective memory cell in the memory cell array, the second pattern includes a plurality of weight pattern sensitivity values, each of the plurality of weight pattern sensitivity values ​​is determined by comparing at least one predetermined threshold with one of the following numbers in a corresponding column in the third pattern: a first number of logical "1" values, and a second number of logical "0" values, the third pattern is a weight pattern including a plurality of weights, each of the plurality of weights having a value of "0" or a value of "1", wherein The determining of at least one pair of columns further comprises: determining a number of defective memory cells in each of the plurality of columns of the memory cell array according to the first pattern; determining a statistical severity value for each of the plurality of columns, wherein the statistical severity value for a corresponding column is determined as a product of the number of defective memory cells and a value of the corresponding column in the second pattern; and The at least one pair of columns is determined based on the statistical severity value.

2. The method according to claim 1, wherein: Also includes: before receiving the first pattern, writing a preconfigured logic state to each of the plurality of memory cells; measuring a stored logic state in each of the plurality of memory cells; as well as The preconfigured logic state is compared to the stored logic state in each of the plurality of memory cells to determine at least one defective memory cell.

3. The method according to claim 1, wherein the input data comprises one of the following: the third pattern, and output data of a second neuron of a second layer, wherein the second neuron of the second layer is coupled to the first neuron of the first layer.

4. A system for calculating a value on a first neuron of a first layer in a neural network, wherein: include: A memory cell array includes a plurality of memory cells, wherein the plurality of memory cells are arranged into a plurality of columns and a plurality of rows; a storage unit configured to store a first pattern; a processor unit configured to determine the second pattern using the third pattern; a controller unit configured to determine at least one pair of columns of the memory cell array according to the first pattern received from the memory unit and the second pattern received from the processor unit; a first selector configured to switch input data of two columns in each of the at least one pair of columns of the memory cell array; as well as a second selector configured to switch output data of the two columns in each of the at least one pair of columns of the storage cell array to determine the values ​​on the respective neurons, wherein the first pattern is a defect pattern that maps at least one defective storage cell in the storage cell array, the second pattern includes a plurality of weight pattern sensitivity values, each of the plurality of weight pattern sensitivity values ​​is determined by comparing at least one predetermined threshold with one of the following numbers in the corresponding column in the third pattern: a first number of logical "1" values, and a second number of logical "0" values, the third pattern is a weight pattern including a plurality of weights, wherein each of the plurality of weights has a value of "0" or a value of "1", wherein The at least one pair of columns is determined based on statistical severity values ​​of the plurality of columns, wherein each of the statistical severity values ​​of a corresponding column is determined as a product of a number of defective memory cells of the corresponding column and a value of the corresponding column in the second pattern.

5. The system of claim 4, wherein the first pattern is determined by: writing a preconfigured logic state to each of the plurality of memory cells; measuring a stored logic state in each of the plurality of memory cells; and The preconfigured logic state is compared to the stored logic state in each of the plurality of memory cells.

6. The system of claim 4, wherein the input data comprises one of: the third pattern, and output data of a second neuron of a second layer, wherein the second neuron of the second layer is coupled to the first neuron of the first layer.

7. The system of claim 4, wherein the first selector and the second selector are controlled by the controller.

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