Semiconductor device

Abstract

A semiconductor device can include a conductive structure on a substrate, a contact plug on the conductive structure, and a magnetic tunnel junction structure on the contact plug. A lower surface of the contact plug can have an area greater than an area of an upper surface thereof, and the contact plug can include a cover pattern at least partially covering an upper surface of the conductive structure, a conductive pattern on the cover pattern, and an amorphous metal-containing pattern on the conductive pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0124849, entitled “Semiconductor Devices,” filed on October 19, 2018, in the Korean Intellectual Property Office (KIPO) is hereby incorporated by reference in its entirety. Technical Field

[0003] Example embodiments relate to semiconductor devices. Background Art

[0004] In a semiconductor device, a contact plug may be formed on a conductive line. Summary of the Invention

[0005] Embodiments relate to a semiconductor device comprising a conductive structure on a substrate, a contact plug on the conductive structure, and a magnetic tunnel junction structure on the contact plug. The area of ​​a lower surface of the contact plug may be greater than the area of ​​an upper surface thereof, and the contact plug may include a covering pattern at least partially covering the upper surface of the conductive structure, a conductive pattern on the covering pattern, and an amorphous metal-containing pattern on the conductive pattern.

[0006] Embodiments further relate to a semiconductor device comprising a first conductive structure and a second conductive structure respectively disposed on a cell region and a peripheral circuit region of a substrate, a contact plug disposed on the conductive structure, a magnetic tunnel junction structure disposed on the contact plug, and a second covering pattern at least partially covering an upper surface of the second conductive structure. The area of ​​the lower surface of the contact plug may be greater than the area of ​​its upper surface, and the contact plug may include a first covering pattern at least partially covering an upper surface of the first conductive structure, a first conductive pattern disposed on the first covering pattern, and an amorphous metal-containing pattern disposed on the first conductive pattern.

[0007] Embodiments also relate to a semiconductor device comprising a gate structure on a substrate, a source / drain layer on a portion of the substrate adjacent to the gate structure, a conductive structure electrically connected to the source / drain layer, a contact plug on the conductive structure, and a magnetic tunnel junction structure on the contact plug. The area of ​​a lower surface of the contact plug may be greater than the area of ​​an upper surface thereof, and the contact plug may include a covering pattern at least partially covering the upper surface of the conductive structure, a conductive pattern on the covering pattern, and an amorphous metal-containing pattern on the conductive pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figures 1 to 8 A cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments is shown.

[0010] Figures 9 to 12 A cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments is shown. DETAILED DESCRIPTION

[0011] Hereinafter, two directions substantially parallel to the upper surface of the substrate and crossing each other are defined as a first direction and a second direction, respectively. In example embodiments, the first direction and the second direction may be substantially orthogonal to each other.

[0012] Figures 1 to 8 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0013] Reference Figure 1 , an active fin 105 may be formed on the substrate 100 , and a dummy gate structure 140 may be formed on the active fin 105 .

[0014] In example embodiments, the substrate 100 may include a semiconductor material (e.g., silicon, germanium, silicon germanium, etc.) or a III-V semiconductor compound (e.g., GaP, GaAs, GaSb, etc.). In example embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0015] The active fin 105 may be formed by partially etching an upper portion of the substrate 100, and a lower sidewall of the active fin 105 may be covered by an isolation pattern. The isolation pattern may include oxide, such as silicon oxide.

[0016] The active fin 105 may include a lower active pattern 105b whose sidewall may be covered by an isolation pattern and an upper active pattern 105a protruding upward from the isolation pattern. In example embodiments, the active fin 105 may extend in a first direction, and a plurality of active fins 105 may be formed along a second direction.

[0017] The dummy gate structure 140 may be formed by sequentially forming a dummy gate insulation layer, a dummy gate electrode layer, and a dummy gate mask layer on the active fins 105 and the isolation pattern; patterning the dummy gate mask layer to form a dummy gate mask 130; and sequentially etching the dummy gate electrode layer and the dummy gate insulation layer below the dummy gate electrode layer using the dummy gate mask 130 as an etching mask. Thus, the dummy gate structure 140 may include a dummy gate insulation pattern 110, a dummy gate electrode 120, and a dummy gate mask 130 sequentially stacked on the active fins 105 and the isolation pattern. In an exemplary embodiment, the dummy gate structure 140 may extend in the second direction, and multiple dummy gate structures 140 may be formed along the first direction.

[0018] The dummy gate insulating layer, the dummy gate electrode layer, and the dummy gate mask layer may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc. In one implementation, the dummy gate insulating layer may be formed by performing a thermal oxidation process on an upper portion of the substrate 100, and in this case, the dummy gate insulating layer may be formed only on the upper surface of the active fin 105.

[0019] The dummy gate insulating layer may include oxide (eg, silicon oxide), the dummy gate electrode layer may include, for example, polysilicon, and the dummy gate mask layer may include nitride (eg, silicon nitride).

[0020] Reference Figure 2 , the gate spacer 150 can be formed to cover the sidewalls of the dummy gate structure 140, the source / drain layer 160 can be formed on the active fin 105 adjacent to the gate spacer 150, and the first insulating interlayer 170 covering the sidewalls of the source / drain layer 160 and the gate spacer 150 can be formed on the active fin 105 and the isolation pattern.

[0021] The gate spacers 150 may be formed by forming a gate spacer layer on the active fins 105 and the isolation pattern to cover the dummy gate structure 140 and anisotropically etching the gate spacer layer. The gate spacers 150 may include nitride, such as silicon nitride.

[0022] The source / drain layer 160 may be formed by: using the dummy gate structure 140 and the gate spacers 150 on the sidewalls of the dummy gate structure 140 as an etching mask, removing the upper portion of the active fin 105 through a dry etching process to form a first recess; and filling the first recess. In an exemplary embodiment, the source / drain layer 160 may be formed by performing a selective epitaxial growth (SEG) process using the upper surface of the active fin 105 exposed by the first recess as a seed.

[0023] In example embodiments, an SEG process may be performed and a single crystal silicon germanium layer may be formed to serve as the source / drain layer 160. A p-type impurity source gas may also be used in the SEG process, and a single crystal silicon germanium layer doped with p-type impurities may be formed to serve as the source / drain layer 160. Thus, the source / drain layer 160 may serve as a source / drain region of a positive channel metal oxide semiconductor (PMOS) transistor.

[0024] The source / drain layer 160 may be grown in vertical and horizontal directions to fill the first groove, and an upper portion of the source / drain layer 160 may be grown to contact a sidewall of the gate spacer 150 .

[0025] In example embodiments, a plurality of source / drain layers 160 may be formed along the second direction, and the source / drain layers 160 grown on respective active fins 105 adjacent to each other in the second direction may be connected and merged.

[0026] The source / drain layer 160 is described above as functioning as the source / drain of a PMOS transistor. In another example embodiment, the source / drain layer 160 may be formed to function as the source / drain of an NMOS transistor.

[0027] A single crystal silicon carbide layer or a single crystal silicon layer may be formed as the source / drain layer 160. The SEG process may be performed with an n-type impurity source gas, thereby forming a single crystal silicon carbide layer or a single crystal silicon layer doped with n-type impurities.

[0028] A first insulating interlayer 170 may be formed on the substrate 100 to cover the dummy gate structure 140, the gate spacer 150, and the source / drain layer 160. The upper portion of the first insulating interlayer 170 may be planarized until the upper surface of the dummy gate electrode 120 in the dummy gate structure 140 is exposed. The first insulating interlayer 170 may include an oxide, such as silicon oxide. The dummy gate mask 130 in the dummy gate structure 140 may be removed by a planarization process.

[0029] The exposed dummy gate electrode 120 and the underlying dummy gate insulation pattern 110 may be removed to form a first opening exposing inner sidewalls of the gate spacers 150 and upper surfaces of the active fins 105 , and a gate structure 220 may be formed to fill the first opening.

[0030] The gate structure 220 may be formed by, for example, the following process. First, after performing a thermal oxidation process on the upper surface of the active fin 105 exposed through the first opening to form the interface pattern 180, a gate insulating layer and a work function control layer may be sequentially formed on the interface pattern 180, the isolation pattern, the gate spacer 150, and the first insulating interlayer 170, and a gate electrode sufficiently filling the remaining portion of the first opening may be formed on the work function control layer.

[0031] The gate electrode layer, the work function control layer, and the gate insulating layer may be planarized until the upper surface of the first insulating interlayer 170 is exposed, so that a gate insulating pattern 190 and a work function control pattern 200 stacked in sequence may be formed on the upper surface of the interface pattern 180, the upper surface of the isolation pattern, and the inner sidewalls of the gate partition 150. Furthermore, a gate electrode 210 may be formed on the work function control pattern 200 to fill the remaining portion of the first opening. Thus, the lower surface and sidewalls of the gate electrode 210 may be covered by the work function control pattern 200.

[0032] The sequentially stacked interface pattern 180, the gate insulating pattern 190, the work function control pattern 200, and the gate electrode 210 may form a gate structure 220. The gate structure 220 may form a transistor together with the source / drain layer 160.

[0033] The interface pattern 180 may include an oxide (e.g., silicon oxide), the gate insulation pattern 190 may include a metal oxide (e.g., hafnium oxide, tantalum oxide, zirconium oxide, etc.), the work function control pattern 200 may include a metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.), and the gate electrode 210 may include a low-resistance metal (e.g., aluminum, copper, titanium, tantalum, etc., their nitrides, or their alloys).

[0034] Depending on the conductivity type of the source / drain layer 160 , the transistor may form an NMOS transistor or a PMOS transistor.

[0035] Reference Figure 3 An insulating layer 230 and a second insulating interlayer 240 may be sequentially formed on the first insulating interlayer 170, the gate structure 220 and the gate partition wall 150, and a source line 260 may be formed to pass through the first insulating interlayer 170, the insulating layer 230 and the second insulating interlayer 240 to contact the upper surface of one or more source / drain layers 160 (hereinafter referred to as the first source / drain layer).

[0036] The insulating layer 230 may include a nitride, such as silicon nitride. Figure 3 In contrast, the insulating layer 230 may be formed by removing an upper portion of the gate structure 220 to form a trench and filling the trench.

[0037] Before forming the source line 260, a first metal silicide pattern 250 may be further formed on the first source / drain layer. Thus, a second opening may be formed through the first insulating interlayer 170, the insulating layer 230, and the second insulating interlayer 240 to expose the upper surface of the first source / drain layer. A first metal layer may be formed on the upper surface of the first source / drain layer, the sidewalls of the second opening, and the upper surface of the second insulating interlayer 240. A thermal treatment process may be performed to form the first metal silicide pattern 250 on the first source / drain layer. The first metal silicide pattern 250 may include, for example, nickel silicide, cobalt silicide, titanium silicide, or the like.

[0038] The source line 260 may include metal, metal nitride, and / or polysilicon doped with impurities, and may further include a barrier layer pattern covering a lower surface and sidewalls of the source line 260. In example embodiments, the source line 260 may extend to a given length in the second direction, and a plurality of source lines 260 may be formed along the first direction.

[0039] After forming a third insulating interlayer 270 on the second insulating interlayer 240 and the source line 260, a first contact plug 290 can be formed to pass through the first insulating interlayer 170, the insulating layer 230, the second insulating interlayer 240 and the third insulating interlayer 270 to contact the upper surface of one or more source / drain layers 160 (hereinafter referred to as the second source / drain layer).

[0040] A second metal silicide pattern 280 may be further formed between the first contact plug 290 and the second source / drain layer, and the first contact plug 290 may further include a barrier layer pattern covering a lower surface and sidewalls of the first contact plug 290 .

[0041] Reference Figure 4 After forming the fourth insulating interlayer 300 on the third insulating interlayer 270 and the first contact plug 290, sequentially stacked vias 310 and conductive lines 320 may be formed through the fourth insulating interlayer 300 to contact the upper surface of the first contact plug 290. The sequentially stacked vias 310 and conductive lines 320 may be referred to as a conductive structure.

[0042] In example embodiments, the conductive line 320 and the via 310 may be simultaneously formed by a dual damascene process. In one implementation, the conductive line 320 and the via 310 may be independently formed by a single damascene process.

[0043] In example embodiments, each of the conductive line 320 and the via 310 may include a low-resistance metal such as copper (Cu), aluminum (Al), or the like.

[0044] Reference Figure 5 , a capping layer 330 , a conductive layer 340 , and an amorphous metal-containing layer 350 may be sequentially formed on the fourth insulating interlayer 300 and the conductive line 320 .

[0045] In example embodiments, the capping layer 330 may include a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), tantalum boride (TaB), etc.), the conductive layer 340 may include a metal (e.g., tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), etc.), and the amorphous metal-containing layer 350 may include a metal nitride (e.g., tantalum nitride (TaN), titanium nitride (TiN), etc.).

[0046] Reference Figure 6 The capping layer 330 , the conductive layer 340 , and the amorphous metal-containing layer 350 may be patterned by an etching process using a photoresist pattern to form a second contact plug 390 including a capping pattern 360 , a conductive pattern 370 , and an amorphous metal-containing pattern 380 stacked sequentially.

[0047] In example embodiments, the second contact plug 390 may have a sidewall that is not vertical but inclined relative to the upper surface of the substrate 100, and may have an area that gradually increases from the upper portion toward the lower portion of the second contact plug, and may be formed using, for example, characteristics of an etching process. Therefore, the area of ​​the lower surface of the second contact plug 390 may be greater than the area of ​​the upper surface of the second contact plug 390.

[0048] In an example embodiment, the second contact plug 390 may be formed by a patterning process rather than a damascene process. If the second contact plug 390 is to be formed by a damascene process, the groove on the insulating interlayer may not be completely filled, thereby forming a void, and thus the second contact plug 390 may not be well connected to the conductive line 320 thereunder. For example, when the conductive line 320 includes, for example, copper, and the second contact plug 390 includes a material different from the conductive line 320 (e.g., tungsten), poor bonding between the different materials may occur. In addition, the copper included in the conductive line 320 may be eluted to the adjacent layer structure through the void. However, in this example embodiment, the second contact plug 390 may be formed by a patterning process so that a void may not be formed, and the covering pattern 360 included in the second contact plug 390 may cover the upper surface of the conductive line 320 to reduce or prevent copper elution of the conductive line 320 in subsequent processes.

[0049] In example embodiments, the second contact plug 390 may have a small height, eg, approximately As described above, no gap may be formed between the second contact plug 390 and the conductive line 320 thereunder, and thus, even if the second contact plug 390 has a small height, copper may be prevented from being eluted from the conductive line 320.

[0050] Reference Figure 7 , a partition wall layer 400 covering the second contact plug 390 may be formed on the fourth insulating interlayer 300, a fifth insulating interlayer 410 may be formed on the partition wall layer 400, and the fifth insulating interlayer 410 and the partition wall layer 400 may be planarized until the upper surface of the second contact plug 390 is exposed.

[0051] In example embodiments, the spacer layer 400 may be conformally formed, and an upper portion of the spacer layer 400 may be removed by a planarization process, so that the spacer layer 400 may be formed to cover the sidewalls of the second contact plug 390 and the upper surface of the fourth insulating interlayer 300. The spacer layer 400 may include a nitride, such as silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or the like.

[0052] Reference Figure 8 , a memory cell may be formed on the second contact plug 390 .

[0053] A lower electrode layer, a barrier layer, an adhesion layer, a seed layer, an MTJ (magnetic tunnel junction) structure layer, and an upper electrode layer may be formed on the fifth insulating interlayer 410, the second contact plug 390, and the partition layer 400. The lower electrode layer, the barrier layer, the adhesion layer, the seed layer, the MTJ structure layer, and the upper electrode layer may be etched by an etching process to form a memory cell. Thus, the memory cell may include a lower electrode 420, a barrier pattern 430, an adhesion pattern 440, a seed pattern 450, an MTJ structure 500, and an upper electrode 490 sequentially stacked on the second contact plug 390. The MTJ structure 500 may include a fixed layer pattern 460, a tunnel barrier layer pattern 470, and a free layer pattern 480.

[0054] The lower electrode 420 may include a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), the barrier pattern 430 may include a metal boride (e.g., tantalum boride (TaB), titanium boride (TiB), etc.), a metal boronitride (e.g., tantalum boronitride (TaBN), titanium boronitride (TiBN), etc.), or a metal compound (e.g., tantalum carbon fluoroborate (CFBTa)), the adhesion pattern 440 may include a metal (e.g., tantalum (Ta), titanium (Ti), etc.), and the seed crystal may include a plurality of metals. Figure 4 The pattern 50 may include a metal (eg, ruthenium (Ru), rhenium (Re), etc.).

[0055] The fixed layer pattern 460 may include a ferromagnetic material such as cobalt (Co), platinum (Pt), iron (Fe), nickel (Ni), etc. In example embodiments, the fixed layer pattern 460 may include an alloy of cobalt and platinum (i.e., CoPt) or a multilayer structure including alternating cobalt and platinum layers. The tunnel barrier layer pattern 470 may include, for example, magnesium oxide (MgO) or aluminum oxide (Al2O3), and the free layer pattern 480 may include a ferromagnetic material such as cobalt (Co), platinum (Pt), iron (Fe), nickel (Ni), etc.

[0056] In example embodiments, the MTJ structure 500 may include a free layer pattern 480 , a tunnel barrier layer pattern 470 , and a fixed layer pattern 460 that are sequentially stacked, at least one of which may be formed to include a plurality of layers that are sequentially stacked.

[0057] The upper electrode layer 490 may include metal (eg, titanium, tantalum, tungsten, etc.) and / or metal nitride (eg, titanium nitride, tantalum nitride, tungsten nitride, etc.).

[0058] The second contact plug 390 may include an amorphous metal-containing pattern 380 at an upper portion thereof. Therefore, when the MTJ structure 500 is formed, the crystallinity of the lower structure (eg, the conductive pattern 370) may not be transferred thereto.

[0059] During the etching process for forming the memory cells, the fifth insulating interlayer 410 and the spacer layer 400 may also be partially etched, and the upper portion of the fourth insulating interlayer 300 may also be partially etched. The spacer layer 400 may be transformed into a first spacer 405 covering the sidewall of the second contact plug 390. In example embodiments, the first spacer 405 may have a width that gradually increases from an upper portion toward a lower portion thereof.

[0060] A sixth insulating interlayer covering the memory cells and the first partition walls 405 may be formed on the fourth insulating interlayer 300 and the fifth insulating interlayer 410 , which may complete the fabrication of the semiconductor device.

[0061] As described above, second contact plug 390 can be formed using a patterning process rather than a damascene process. Therefore, second contact plug 390 can be formed to be well connected to conductive line 320 without a gap therebetween. Therefore, copper included in conductive line 320 can be prevented from being eluted into adjacent layer structures. Second contact plug 390 can include a capping pattern 360 covering the upper surface of conductive line 320, which can further reduce the elution of copper included in conductive line 320 in subsequent processes.

[0062] Figures 9 to 12 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment. In addition to further including a peripheral circuit region, this example embodiment of the semiconductor device may be similar to Figures 1 to 8 The semiconductor devices described in the accompanying drawings are substantially the same or similar. Therefore, the same reference numerals denote the same elements, and detailed descriptions thereof will not be repeated here.

[0063] Reference Figure 9 , can be executed with Figures 1 to 5 The process described in is basically the same or similar process.

[0064] The substrate 100 may include a first region I and a second region II, and the gate structure 220, the first contact plug 290, the via 310, the conductive line 320, etc. may be formed on each of the first region I and the second region II. In this example embodiment, the source line 260 may be formed only on the first region I of the substrate 100.

[0065] In example embodiments, the first region I of the substrate 100 may be a memory cell region where memory cells may be formed, and the second region II of the substrate 100 may be a peripheral circuit region where peripheral circuits may be formed.

[0066] The vias 310 and the conductive lines 320 on the first region I of the substrate 100 may be collectively referred to as a first conductive structure, and the vias 310 and the conductive lines 320 on the second region II of the substrate 100 may be collectively referred to as a second conductive structure.

[0067] Reference Figure 10 , can be executed with Figure 6 The process described in is basically the same or similar process.

[0068] Therefore, a third contact plug 390a including a first covering pattern 360a, a first conductive pattern 370a and a first amorphous metal-containing pattern 380a stacked sequentially can be formed on the first conductive structure on the first region I of the substrate 100, and a fourth contact plug 390b including a second covering pattern 360b, a second conductive pattern 370b and a second amorphous metal-containing pattern 380b stacked sequentially can be formed on the second conductive structure on the second region II of the substrate 100.

[0069] Reference Figure 11 , can be executed with Figure 7 The process described in is basically the same or similar process.

[0070] Therefore, a partition wall layer 400 covering the third contact plug 390a and the fourth contact plug 390b can be formed on the fourth insulating interlayer 300, a fifth insulating interlayer 410 can be formed on the partition wall layer 400, and the fifth insulating interlayer 410 and the partition wall layer 400 can be planarized until the upper surfaces of the third contact plug 390a and the fourth contact plug 390b are exposed.

[0071] Reference Figure 12 , can be executed with Figure 8 The process described in is basically the same or similar process.

[0072] Therefore, a memory cell may be formed on the third contact plug 390 a on the first region I of the substrate 100 to complete the manufacture of the semiconductor device.

[0073] During the etching process for forming the memory cells, the fifth insulating interlayer 410 and the partition wall layer 400 may also be partially etched, and the upper portion of the fourth insulating interlayer 300 may also be partially etched. In addition, the fourth contact plug 390b on the second region II of the substrate 100 may be partially removed.

[0074] Thus, the second partition wall 405a may be formed to cover the sidewall of the third contact plug 390a on the first region I of the substrate 100, and the third partition wall 405b may be formed to cover the sidewall of the fourth contact plug 390b on the second region II of the substrate 100. In example embodiments, each of the second partition wall 405a and the third partition wall 405b may have a width gradually increasing from an upper portion toward a lower portion.

[0075] During the etching process, the second amorphous metal-containing pattern 380b of the fourth contact plug 390b may be removed, the second conductive pattern 370b may be partially or completely removed, and the second capping pattern 360b may remain to cover the second conductive structure. The lower surface of the fourth contact plug 390b remaining on the second region II of the substrate 100 may be lower than the lower surface of the third contact plug 390a on the first region I of the substrate 100, and the lower surface of the third partition wall 405b may also be lower than the lower surface of the second partition wall 405a.

[0076] By way of summary and review, the conductive line may include, for example, copper. If a gap is formed between the contact plug and the conductive line, there may be no electrical connection between them, and in subsequent processes, the copper included in the conductive line may be washed away, which may cause an electrical short circuit with an adjacent conductive structure.

[0077] As described above, embodiments relate to semiconductor devices including contact plugs. Embodiments can provide semiconductor devices with improved electrical characteristics. In semiconductor devices according to example embodiments, the contact plugs can be formed using a positive patterning process rather than a damascene process, and can be formed into a multilayer structure that includes a cover pattern at least partially covering the upper surface of a conductive structure, a conductive pattern on the cover pattern, and an amorphous metal-containing pattern on the conductive pattern. Therefore, the contact plug and the conductive structure below it can be formed to be well connected to each other without a gap therebetween, and copper included in the conductive structure can be prevented from being eluted into adjacent layer structures.

[0078] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a general, descriptive sense only and not for purposes of limitation. In some cases, as will be appreciated by those skilled in the art submitting this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in other embodiments, unless expressly stated otherwise. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device comprising: a first contact plug on the substrate; a conductive structure on the first contact plug; a second contact plug on the conductive structure, wherein an area of ​​a lower surface of the second contact plug is greater than an area of ​​an upper surface of the second contact plug, the lower surface is closer to the substrate than the upper surface, and the second contact plug comprises: a covering pattern, at least partially covering the upper surface of the conductive structure; A conductive pattern on the cover pattern; and an amorphous metal-containing pattern on the conductive pattern; a partition wall covering a sidewall of the second contact plug; and The magnetic tunnel junction structure on the second contact plug, Wherein, the width of the partition wall gradually increases from the top toward the bottom.

2. The semiconductor device according to claim 1, wherein: The capping pattern comprises titanium nitride, tantalum nitride or tantalum boride, and The conductive structure includes copper.

3. The semiconductor device according to claim 1, wherein: The conductive pattern includes tungsten, aluminum, copper or tantalum, and The amorphous metal-containing pattern includes tantalum nitride or titanium nitride.

4. The semiconductor device according to claim 1, wherein The second contact plug has a sidewall that is inclined and not perpendicular to the upper surface of the substrate.

5. The semiconductor device according to claim 1, wherein The partition wall comprises silicon nitride, silicon carbonitride or silicon oxynitride. The semiconductor device according to claim 1 , wherein: The height of the second contact plug is 600 Å or less.

7. The semiconductor device according to claim 1, wherein The magnetic tunnel junction structure includes a fixed layer pattern, a tunnel barrier layer pattern, and a free layer pattern that are sequentially stacked.

8. The semiconductor device according to claim 1, further comprising: a lower electrode between the second contact plug and the magnetic tunnel junction structure; as well as An upper electrode on the magnetic tunnel junction structure.

9. A semiconductor device comprising: A first contact plug and a second contact plug are respectively on the cell region and the peripheral circuit region of the substrate; a first conductive structure and a second conductive structure respectively on the first contact plug and the second contact plug; A third contact plug on the first conductive structure, wherein an area of ​​a lower surface of the third contact plug is greater than an area of ​​an upper surface of the third contact plug, the lower surface is closer to the substrate than the upper surface, and the third contact plug comprises: a first covering pattern, at least partially covering an upper surface of the first conductive structure; a first conductive pattern on the first covering pattern; and an amorphous metal-containing pattern on the first conductive pattern; a first partition wall covering a sidewall of the third contact plug; a magnetic tunnel junction structure on the third contact plug; a second covering pattern, at least partially covering an upper surface of the second conductive structure; and a second partition wall on a sidewall of the second covering pattern; The width of each of the first partition wall and the second partition wall gradually increases from the top toward the bottom thereof.

10. The semiconductor device according to claim 9, wherein Each of the first partition wall and the second partition wall includes silicon nitride, silicon carbonitride, or silicon oxynitride. 11 . The semiconductor device according to claim 9 , further comprising a second conductive pattern on the second capping pattern.

12. The semiconductor device according to claim 11, wherein An upper surface of the second conductive pattern is lower than an upper surface of the first conductive pattern.

13. The semiconductor device according to claim 9, wherein: The first capping pattern comprises titanium nitride, tantalum nitride or tantalum boride, and The first conductive structure includes copper.

14. A semiconductor device comprising: a gate structure on a substrate; a source / drain layer on a portion of the substrate adjacent to the gate structure; a first contact plug on the source / drain layer; a conductive structure on the first contact plug; a second contact plug on the conductive structure, wherein an area of ​​a lower surface of the second contact plug is greater than an area of ​​an upper surface of the second contact plug, the lower surface is closer to the substrate than the upper surface, and the second contact plug comprises: a covering pattern, at least partially covering the upper surface of the conductive structure; A conductive pattern on the cover pattern; and an amorphous metal-containing pattern on the conductive pattern; a partition wall covering a sidewall of the second contact plug; and The magnetic tunnel junction structure on the second contact plug, Wherein, the width of the partition wall gradually increases from the top toward the bottom.

15. The semiconductor device according to claim 14, further comprising: a lower electrode between the second contact plug and the magnetic tunnel junction structure; as well as An upper electrode on the magnetic tunnel junction structure.

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