Gallium nitride transistor and method of manufacturing the same

Abstract

The application discloses a gallium nitride transistor and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a gate stack on a first region above a barrier layer, the gate stack comprising a gate structure layer and a first insertion layer between the gate structure layer and the barrier layer; and forming a first hole injection layer on a second region above the barrier layer, the first region and the second region being separated from each other, wherein the step of forming the gate stack comprises the following steps: patterning a hard mask layer by using a first resist mask, patterning a doped layer by using the first resist mask to form the gate structure layer, and patterning the insertion layer by using the hard mask layer to form the first insertion layer. The manufacturing method uses the hard mask layer for subsequent patterning processes, which can avoid misalignment of multiple photolithography processes, thereby simplifying the manufacturing process of the gallium nitride transistor and improving product yield. The gallium nitride transistor injects charges into a channel layer by using the first hole injection layer to release electrons trapped by trap energy levels, so that stable on-resistance can be obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and more particularly, to a gallium nitride transistor and a manufacturing method thereof. BACKGROUND

[0002] Compared with semiconductor materials such as silicon and gallium arsenide, wide bandgap semiconductor material gallium nitride (GaN) has a larger bandgap (3.4 eV), a stronger critical breakdown field, and a higher electron migration rate, and has been widely concerned by researchers at home and abroad, and has great advantages and potential in power electronic power devices and high-frequency power devices. As a typical representative of the third generation of wide bandgap semiconductors, gallium nitride material not only has the characteristics of large bandgap, high critical breakdown field, large electron saturation drift speed, high temperature resistance, radiation resistance, and good chemical stability, but also due to the polarization effect of gallium nitride material, it can form a two-dimensional electron gas (2DEG) with high concentration (greater than 10 13 cm -2 ) and high mobility (greater than 2000 cm 2 / V·s), which is very suitable for preparing power switch devices, and has become a research hotspot in the field of power devices.

[0003] At present, it is difficult to obtain gallium nitride single crystal substrate, and most of the gallium nitride thin films are realized by heteroepitaxy on other substrates. Commonly used substrates include silicon, sapphire, and silicon carbide. Due to the large lattice mismatch and thermal strain between gallium nitride and the substrate, the defect density of the gallium nitride epitaxial material can be 3 to 4 orders of magnitude higher than that of silicon material. In addition, in order to achieve high breakdown voltage, carbon, iron or magnesium doping is performed in the high resistance nitride layer. The defects and impurities in the gallium nitride channel layer can form trap energy levels. Under a high reverse voltage, the trap energy levels can capture electrons. As a result, when the gallium nitride transistor is re-conducted, the on-resistance increases, and the stability and reliability of the device deteriorate.

[0004] As a further improved device structure, a composite stack is formed in the gate region and the drain region of the gallium nitride transistor. In the reverse blocking state, the hole injection layer in the drain region injects holes into the channel layer, so that the electrons captured by the trap energy level can be released. Therefore, when the gallium nitride transistor is re-conducted, a substantially constant on-resistance can be obtained.

[0005] However, the manufacturing method of the gallium nitride transistor is complex, including secondary lithography and additional epitaxial growth after the patterning step of the insertion layer, thereby there is a problem of secondary lithography misalignment. As a result, in the composite stack in the gate region, the gate structure layer and the insertion layer are misaligned with each other, resulting in that the gallium nitride transistor cannot work normally. SUMMARY

[0006] Therefore, the application provides a gallium nitride transistor and a manufacturing method thereof, wherein a hard mask layer is patterned when forming the gate structure layer, and the hard mask layer is used in subsequent patterning processes, so that the manufacturing process of the gallium nitride transistor can be simplified and the product yield can be improved.

[0007] According to an aspect of the application, a manufacturing method of a gallium nitride transistor is provided, comprising: forming a barrier layer on a substrate; forming a gate stack on a first region above the barrier layer, the gate stack comprising a gate structure layer and a first interlayer between the gate structure layer and the barrier layer; and forming a first hole injection layer on a second region above the barrier layer, the first region and the second region being separated from each other, wherein the step of forming the gate stack comprises patterning a hard mask layer using a first resist mask, patterning a doped layer using the first resist mask to form the gate structure layer, and patterning an interlayer using the hard mask layer to form the first interlayer.

[0008] Preferably, the interlayer is patterned using a second resist mask to form the first hole injection layer at the same time when the interlayer is patterned using the hard mask layer to form the first interlayer.

[0009] Preferably, the gate stack is formed by one-time photolithography etching.

[0010] Preferably, the hard mask layer is removed after the interlayer is patterned.

[0011] Preferably, the doped layer is formed by an epitaxial growth method.

[0012] Preferably, the gate structure layer, the first interlayer and the first hole injection layer are respectively composed of a doped nitride.

[0013] Preferably, the dopant in the gate structure layer, the first interlayer and the first hole injection layer is distributed in any one of a composition fixed, a composition gradually changed and a composition abruptly changed.

[0014] Preferably, the gate structure layer comprises a p-type dopant.

[0015] Preferably, the dopant doped in the gate structure layer comprises any one selected from magnesium, calcium, beryllium, zinc or a combination thereof.

[0016] Preferably, before the step of forming the barrier layer on the substrate, the method further comprises: forming a nucleation layer on the substrate; forming a buffer layer on the nucleation layer; forming a gallium nitride channel layer on the buffer layer, and the barrier layer is located on the gallium nitride channel layer.

[0017] Preferably, the doping concentration of the gate structure layer is selected such that the two-dimensional electron gas between the gallium nitride channel layer and the barrier layer below the gate stack is in an off state at zero bias.

[0018] Preferably, the first insertion layer and the first hole injection layer comprise a p-type dopant.

[0019] Preferably, the dopant incorporated in the first hole injection layer comprises any one selected from magnesium, calcium, beryllium, zinc or a combination thereof.

[0020] Preferably, the doping concentration of the first hole injection layer is selected such that the two-dimensional electron gas between the gallium nitride channel layer and the barrier layer below the first hole injection layer is in an on state at zero bias, the first hole injection layer injects holes into the barrier layer in a reverse off state.

[0021] Preferably, the thickness of the first hole injection layer is etched down such that the channel in the gallium nitride channel layer below the first hole injection layer is in an on state at zero bias, the first hole injection layer injects holes into the channel in the gallium nitride channel layer in a reverse off state.

[0022] Preferably, after the step of forming the gate stack and the first hole injection layer, further comprising: forming a source electrode, a drain electrode, and a gate electrode between the source electrode and the drain electrode above the barrier layer, respectively, wherein the gate electrode and the gate structure layer contact each other, the source electrode and the barrier layer contact each other, a first portion of the drain electrode and the first hole injection layer contact each other, and a second portion of the drain electrode and the barrier layer contact each other.

[0023] Preferably, the gate electrode forms a Schottky contact with the gate structure layer.

[0024] Preferably, the source electrode and the drain electrode form an ohmic contact with the barrier layer.

[0025] Preferably, a two-dimensional electron gas is formed between the channel layer and the barrier layer.

[0026] Preferably, further comprising forming a second insertion layer between the first insertion layer and the gate structure layer, the second insertion layer acts as a stop layer in the step of patterning the doping layer using the first resist mask.

[0027] Preferably, the gate structure layer is a p-type doped gallium nitride layer, the first insertion layer is a p-type doped gallium nitride layer, and the second insertion layer is a p-type doped aluminum gallium nitride layer.

[0028] Preferably, the second insertion layer has a thickness of one fifth to one twentieth of the thickness of the gate structure layer.

[0029] Preferably, a second hole injection layer is further included between the drain electrode and the first hole injection layer, and the second hole injection layer acts as a stop layer in the step of patterning the doped layer using the first resist mask.

[0030] Preferably, the first hole injection layer is a p-doped gallium nitride layer, and the second hole injection layer is a p-doped aluminum gallium nitride layer.

[0031] According to another aspect of the present application, there is provided a gallium nitride transistor, comprising: a barrier layer on a substrate; a gate stack in a first region above the barrier layer, the gate stack comprising a gate structure layer and a first insertion layer between the gate structure layer and the barrier layer; and a first hole injection layer in a second region above the barrier layer, the first region and the second region being separated from each other, wherein a drain electrode of the gallium nitride transistor is in contact with both the first hole injection layer and the barrier layer.

[0032] Preferably, the gate structure layer, the first insertion layer and the first hole injection layer are each composed of a doped nitride.

[0033] Preferably, the dopant distribution in the gate structure layer, the first insertion layer and the first hole injection layer is any one of a compositionally fixed, a compositionally graded and a compositionally abrupt.

[0034] Preferably, the gate structure layer comprises a p-type dopant.

[0035] Preferably, the dopant incorporated in the gate structure layer comprises any one selected from magnesium, calcium, beryllium zincate or a combination thereof.

[0036] Preferably, further comprising: a nucleation layer on the substrate; a buffer layer on the nucleation layer; a gallium nitride channel layer on the buffer layer; and the barrier layer on the gallium nitride channel layer, between the substrate and the barrier layer.

[0037] Preferably, the doping concentration of the gate structure layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer below the gate stack is in a cut-off state at zero bias.

[0038] Preferably, the first insertion layer and the first hole injection layer comprise a p-type dopant.

[0039] Preferably, the dopant incorporated in the first hole injection layer comprises any one selected from magnesium, calcium, beryllium zincate or a combination thereof.

[0040] Preferably, the doping concentration of the first hole injection layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer below the first hole injection layer is in an on state at zero bias, and the first hole injection layer injects holes into the barrier layer in a reverse blocking state.

[0041] Preferably, a gate electrode of the gallium nitride transistor and the gate structure layer are in contact with each other, and a source electrode and a drain electrode of the gallium nitride transistor and the barrier layer are in contact with each other.

[0042] Preferably, the gate electrode and the gate structure layer form a Schottky contact.

[0043] Preferably, the source electrode and the drain electrode and the barrier layer form an ohmic contact.

[0044] Preferably, a two-dimensional electron gas is formed between the gallium nitride channel layer and the barrier layer.

[0045] Preferably, a second insertion layer is further included between the first insertion layer and the gate structure layer.

[0046] Preferably, the gate structure layer is a p-doped gallium nitride layer, the first insertion layer is a p-doped gallium nitride layer, and the second insertion layer is a p-doped aluminum gallium nitride layer.

[0047] Preferably, the thickness of the second insertion layer is one fifth to one twentieth of the thickness of the gate structure layer.

[0048] Preferably, a second hole injection layer is further included between the drain electrode and the first hole injection layer.

[0049] Preferably, the first hole injection layer is a p-doped gallium nitride layer, and the second hole injection layer is a p-doped aluminum gallium nitride layer.

[0050] The manufacturing method of the gallium nitride transistor according to the embodiment of the present application, when forming the gate structure layer, patterns a hard mask layer, and uses the hard mask layer for a subsequent patterning process of forming the first insertion layer. The manufacturing method uses one-time photolithography to form a pattern of the gate stack, and uses the hard mask layer to retain the mask pattern, so that the gate structure layer and the first insertion layer in the gate stack can be formed in different etching steps, respectively. The manufacturing method avoids alignment deviation of the second photolithography pattern by using the hard mask layer for the subsequent patterning process of forming the first insertion layer, so that the gate design size can be reduced, the misalignment problem of the second photolithography can be avoided, and the second epitaxy process can be avoided, so as to simplify the manufacturing process of the gallium nitride transistor and improve the product yield.

[0051] In the preferred embodiment, the manufacturing method comprises sequentially forming an insertion layer, a doped layer and a hard mask layer on the barrier layer before the steps of forming the first insertion layer and the first hole injection layer, wherein the doped layer is an epitaxially grown nitride layer. Since the epitaxial growth is performed before the patterning step, the manufacturing process of the gallium nitride transistor can be further simplified and the product yield can be improved.

[0052] The gallium nitride transistor formed by the manufacturing method has a gate stack layer sandwiched between the gate electrode and the barrier layer, and the gate stack layer comprises a stacked gate structure layer and the first insertion layer. The first insertion layer, for example, is composed of P-type doped nitride, which can serve as an etching stop layer for the gate structure layer and effectively reduce the gate leakage current.

[0053] The gallium nitride transistor further comprises a first hole injection layer on the barrier layer. The first hole injection layer, for example, is composed of P-type doped nitride. The drain electrode and the first hole injection layer are in contact with each other. By modulating the doping concentration of the first hole injection layer or the method of etching thinning, the first hole injection layer can make the channel layer in the on state under zero bias and inject holes into the channel layer in the reverse blocking state to release trapped electrons, inhibit the increase of dynamic on-resistance of the gallium nitride transistor, increase the stability of dynamic resistance, and improve the stability and reliability of the gallium nitride transistor.

[0054] In the preferred embodiment, a second insertion layer is further included between the first insertion layer and the gate structure layer, which can be used as an etching stop layer to make the etching process stop precisely on the second insertion layer, so as to avoid under-etching of the gate structure layer or over-etching of the first insertion layer, and increase the stability of the process.

[0055] In the preferred embodiment, the first hole injection layer further comprises a second hole injection layer, which can be used as an etching stop layer to make the etching process stop precisely on the second hole injection layer, ensure the consistency of the thickness of the hole injection layer, and increase the stability of the process. BRIEF DESCRIPTION OF DRAWINGS

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present application, but not limit the present application.

[0057] Figure 1 A structural schematic diagram of a gallium nitride transistor according to a first embodiment of the present application is shown.

[0058] Figure 2 A flowchart of a manufacturing method of a gallium nitride transistor according to the first embodiment of the present application is shown.

[0059] Figures 3a to 3eCross-sectional views showing different stages of a gallium nitride transistor manufacturing method according to the first embodiment of the present application are shown.

[0060] Figure 4 A structural schematic diagram of a gallium nitride transistor according to the second embodiment of the present application is shown.

[0061] Figures 5a to 5e Cross-sectional views showing different stages of a gallium nitride transistor manufacturing method according to the second embodiment of the present application are shown. DETAILED DESCRIPTION

[0062] In order to make the above objectives, features and advantages of the present application more clear and comprehensible, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. In the description, a lot of specific details are set forth in order to fully understand the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the spirit of the present application, so the present application is not limited to the specific embodiments disclosed below. Secondly, the present application is described in detail with reference to the schematic diagrams, and when the embodiments of the present application are described in detail, in order to facilitate the description, the cross-sectional diagrams showing the device structure will be partially enlarged without the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application herein. In addition, the three-dimensional spatial dimensions including length, width and depth should be included in the actual manufacturing.

[0063] <First Embodiment>

[0064] Figure 1 A structural schematic diagram of a gallium nitride transistor according to the first embodiment of the present application is shown.

[0065] As shown in Figure 1 , the gallium nitride transistor 100 according to the first embodiment of the present application includes a substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, a gate stack layer 210, a first hole injection layer 221, a gate electrode 301, a source electrode 302 and a drain electrode 303. The gate stack layer 210 includes a first insertion layer 211 and a gate structure layer 212 stacked.

[0066] A nucleation layer 102, a buffer layer 103, a channel layer 104, and a barrier layer 105 are sequentially formed on a substrate 101. The substrate 101 is composed of, for example, any one of silicon, sapphire, and silicon carbide. The nucleation layer 102 is composed of, for example, gallium nitride or aluminum nitride. The buffer layer 103 is composed of, for example, any one of aluminum gallium nitride with different aluminum components or carbon self-doped semi-insulating high-resistance gallium nitride. The channel layer 104 is, for example, an epitaxially grown gallium nitride layer, and the barrier layer 105 is, for example, a nitride including aluminum gallium nitride with an aluminum component of 5% to 30%, indium aluminum gallium nitride, aluminum nitride, or the like. The channel layer 104 and the barrier layer 105 form a heterojunction, and a two-dimensional electron gas is formed between the channel layer 104 and the barrier layer 105.

[0067] A gate stack 210 is located on the barrier layer 105. In this embodiment, a first insertion layer 211 is located between the gate structure layer 212 and the barrier layer 105, and the gate structure layer 212 and the first insertion layer 211 are both p-type doped nitride, composed of, for example, any one of aluminum nitride, aluminum gallium nitride, or gallium nitride, and further, the dopant distribution is any one of a component fixed distribution, a component gradual distribution, and a component abrupt distribution, including any one of p-type dopants selected from magnesium, calcium, beryllium, zinc, or a combination thereof.

[0068] A first hole injection layer 221 is located on the barrier layer 105 and is laterally separated from the gate stack 210. In this embodiment, the first hole injection layer 221 is p-type doped nitride, and further, the dopant distribution in the first hole injection layer 221 is any one of a component fixed distribution, a component gradual distribution, and a component abrupt distribution. The first hole injection layer 221 includes any one of p-type dopants selected from magnesium, calcium, beryllium, zinc, or a combination thereof. The doping type and the doping concentration of the first hole injection layer 221 are selected such that the two-dimensional electron gas between the channel layer 104 and the barrier layer 105 located below the first hole injection layer 221 is in an on state at zero bias, and the first hole injection layer 221 injects holes into the two-dimensional electron gas between the channel layer 104 and the barrier layer 105 in a reverse blocking state.

[0069] A gate electrode 301 is located between a source electrode 302 and a drain electrode 303. The gate electrode 301 is located on the gate stack 210. The gate electrode 301 and the gate structure layer 212 in the gate stack 210 are in contact with each other, thereby forming a Schottky contact. The source electrode 302 is located on the barrier layer 105. A first portion of the drain electrode 303 is located on the first hole injection layer 221, and a second portion of the drain electrode 303 is located on the barrier layer 105. The source electrode 302 and the drain electrode 303 form an ohmic contact with the barrier layer 105 by rapid thermal annealing (RTA), and the first portion of the drain electrode 303 and the first hole injection layer 221 are in contact with each other, thereby forming a Schottky contact.

[0070] Any one of the gate electrode 301, the source electrode 302, and the drain electrode 303 is composed of, for example, titanium, aluminum, nickel, gold, silver, platinum, tungsten, copper, tantalum, molybdenum, titanium tungsten, titanium nitride, or any one of an alloy combination thereof.

[0071] In this embodiment, the first hole injection layer 221 is p-type doped by adjusting the doping concentration thereof, for example, by doping with magnesium, calcium, beryllium, zinc, or a combination thereof, so that a two-dimensional electron gas formed between the channel layer 104 and the barrier layer 105 under the first hole injection layer 221 is in an on state at zero bias and in an off state in a reverse bias state. The first hole injection layer 221 can inject holes into the channel layer 104 so that trapped electrons are released. When the gallium nitride transistor is reactivated, the on resistance of the transistor is substantially maintained, thereby increasing the stability of the dynamic on resistance of the device. The gate stack 210 is composed of the gate structure layer 212 and the first insertion layer 211. By adjusting the doping concentration of the gate structure layer 212, a two-dimensional electron gas formed between the channel layer 104 and the barrier layer 105 under the gate stack 210 is in an off state at zero bias.

[0072] In an alternative embodiment, the thickness of the first hole injection layer 221 can be etched to thin the first hole injection layer 221 in order to achieve a two-dimensional electron gas in an on state at zero bias and in an off state in a reverse bias state.

[0073] Figure 2 A flowchart of a gallium nitride transistor manufacturing method according to a first embodiment of the present application is shown. The various steps of the manufacturing method are explained in detail below with reference to the cross-sectional view shown in Figures 3a to 3e

[0074] In step S01, a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, an insertion layer 201, and a doping layer 202 are formed in order on a substrate 101, as shown in Figure 3a and Figure 3b

[0075] In this step, the nucleation layer 102, the buffer layer 103, the channel layer 104, the barrier layer 105, the insertion layer 201, and the doping layer 202 are formed, for example, using a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or other methods. The processes for forming the various material layers are known in the art and are not described in detail here.

[0076] The substrate 101 is cleaned and the nucleation layer 102 is grown on the substrate 101. The material of the substrate 101 can include silicon, silicon carbide, sapphire, or the like, and the material of the nucleation layer 102 can include gallium nitride, aluminum nitride, or the like. ​​

[0077] Further, a buffer layer 103 is grown on the nucleation layer 102, wherein the material of the buffer layer 103 can include carbon self-doped semi-insulating high-resistance gallium nitride, aluminum gallium nitride.

[0078] Further, a channel layer 104 is grown on the buffer layer 103, wherein the material of the channel layer 104 can be unintentionally doped gallium nitride, aluminum gallium nitride, etc.

[0079] Further, a barrier layer 105 is grown on the channel layer 104, wherein a two-dimensional electron gas is formed at the interface between the channel layer 104 and the barrier layer 105, and the material of the barrier layer 105 can include aluminum components of 5% to 30% of aluminum gallium nitride, indium aluminum gallium nitride, aluminum nitride, etc.

[0080] Further, an insertion layer 201 is grown on the barrier layer 105. The insertion layer 201 is composed of, for example, any one or more of p-type doped aluminum nitride, aluminum gallium nitride or gallium nitride.

[0081] Further, a doped nitride layer is epitaxially grown on the insertion layer 201, thereby forming a p-type doped layer 202. The doped layer 202 is composed of, for example, a nitride, such as a binary or multi-nitride containing In, Ga, Al, etc., such as any one or more of aluminum nitride, aluminum gallium nitride or gallium nitride, wherein the dopant includes, for example, any one of a p-type dopant selected from magnesium, calcium, beryllium, zinc or a combination. The dopant distribution in the doped layer 202 is any one of a fixed composition, a gradual composition and a sudden composition.

[0082] Then, in step S02, a hard mask layer 203 is formed on the doped layer 202, as shown in Figure 3b .

[0083] In this step, the hard mask layer 203 is formed by, for example, sputtering, PECVD, etc. The processes for forming various material layers are known in the art and will not be described in detail here.

[0084] The hard mask layer 203 is composed of, for example, any one of silicon oxide, silicon nitride or other materials.

[0085] Then, in step S03, the hard mask layer 203 and the doped layer 202 are patterned by using a resist mask PR1 to form a gate structure layer 212 in the gate stack 210, as shown in Figure 3c .

[0086] In this step, a resist layer is formed on the hard mask layer 203, and an opening pattern is formed in the resist layer by a photolithography method to obtain a resist mask PR1. The resist mask PR1 shields the gate region of the gallium nitride transistor. Then, the exposed portions of the hard mask layer 203 and the doped layer 202 are removed via the openings in the resist mask PR1 by a dry or wet etching method. By controlling the etching time, or using a selective etchant, the etching is stopped at the surface of the insertion layer 201. After the etching step, the resist mask PR1 is removed by an ashing or solvent dissolving method.

[0087] Then, in step S04, the insertion layer 201 is patterned using the resist mask PR2 and the mask layer 203 to form the first insertion layer 211 of the gate stack 210, and the first hole injection layer 221, as shown in FIG. 2B. Figure 3d

[0088] In this step, a resist layer is formed on the insertion layer 201, and an opening pattern is formed in the resist layer by a photolithography method to obtain a resist mask PR2. The mask layer 203 and the resist mask PR2 shield the gate region and the drain region of the gallium nitride transistor, respectively. Then, the exposed portions of the insertion layer 201 are removed via the openings defined by the hard mask layer 203 and the resist mask PR2 together by a dry or wet etching method. By controlling the etching time, or using a selective etchant, the etching is stopped at the surface of the barrier layer 105. After the etching step, the resist mask PR2 is removed by an ashing or solvent dissolving method.

[0089] In the semiconductor structure obtained in this step, in the gate region above the barrier layer 105, the gate stack 210 has been formed, which includes the first insertion layer 211 and the gate structure layer 212. In this embodiment, the first insertion layer 211 is, for example, a p-type doped gallium nitride layer, and the gate structure layer 212 is, for example, a p-type doped gallium nitride layer

[0090] Then, in step S05, the hard mask layer 203 is removed. For example, the hard mask layer 203 is removed by a selective etching or a corrosive liquid method.

[0091] Then, in step S06, the gate electrode 301, the source electrode 302 and the drain electrode 303 are formed, as shown in FIG. 2C. Figure 3e

[0092] ​​A gate electrode is formed on the gate stack 210. Gate metal is deposited on the gate stack 210, and the gate metal contact area is opened by coating and photolithography. The gate electrode 301 is formed on the gate structure layer 212 by electron beam evaporation or sputtering. The gate electrode 301 is in contact with the gate structure layer 212. The gate metal material includes titanium, aluminum, nickel, gold, silver, platinum, tungsten, copper, tantalum, molybdenum, titanium tungstenide, titanium nitride, or alloys thereof. The gate electrode 301 and the gate structure layer 212 form a Schottky contact through high-temperature annealing.

[0093] Furthermore, source and drain metals are deposited on the barrier layer 105 using processes such as electron beam evaporation and sputtering to form source electrode 302 and drain electrode 303 on the barrier layer 105. The source metal material includes titanium, aluminum, nickel, gold, silver, platinum, tungsten, copper, tantalum, molybdenum, titanium tungstenide, titanium nitride, or alloys thereof, and annealing is used to form an ohmic contact between the source electrode 302 and the barrier layer 105.

[0094] <Second Embodiment>

[0095] Figure 4 A schematic diagram of a gallium nitride transistor according to a second embodiment of the present invention is shown.

[0096] like Figure 4 As shown, a gallium nitride transistor 200 according to a first embodiment of the present invention includes: a substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, a gate stack 310, a drain stack 320, a gate electrode 301, a source electrode 302, and a drain electrode 303. The gate stack 310 includes: a stacked first insertion layer 211, a second insertion layer 231, and a gate structure layer 212. The drain stack 320 includes: a stacked first hole injection layer 221 and a second hole injection layer 232.

[0097] The gate stack 310 and drain stack 320 are located on the barrier layer 105 and are laterally spaced from each other. In this embodiment, the first insertion layer 211, the second insertion layer 231, and the gate structure layer 212 in the gate stack 310 are all p-type doped nitrides, such as any one of aluminum nitride, aluminum gallium nitride, or gallium nitride. Further, the dopant distribution is any one of fixed composition, gradual composition, and abrupt composition, including any p-type dopant selected from magnesium, calcium, zinc beryllium, or combinations thereof. For example, the first insertion layer 211 is, for example, a p-type doped gallium nitride layer, the second insertion layer 231 is a p-type doped aluminum gallium nitride layer, and the gate structure layer 212 is, for example, a p-type doped gallium nitride layer. For example, the thickness of the second insertion layer 231 is one-fifth to one-twentieth of the thickness of the gate structure layer 212.

[0098] The first hole injection layer 221 and the second hole injection layer 232 in the leakage stack 320 are both p-type doped nitrides, for example, composed of any one of aluminum nitride, aluminum gallium nitride or gallium nitride, further, the dopant distribution is any one of a composition fixed, a composition graded and a composition abrupt, including any one of p-type dopants selected from magnesium, calcium, beryllium, zinc or a combination thereof. For example, the first hole injection layer 221 is a p-type doped gallium nitride layer, and the second hole injection layer 232 is a p-type doped aluminum gallium nitride layer.

[0099] The gallium nitride transistor 200 according to the second embodiment is the same as the first embodiment in other aspects, and will not be described in detail here. The following describes the gallium nitride transistor manufacturing method according to the second embodiment in combination with Figures 5a to 5e Briefly describe each step of the gallium nitride transistor manufacturing method according to the second embodiment.

[0100] The nucleation layer 102, the buffer layer 103, the channel layer 104, the barrier layer 105, the insertion layers 2011 and 2012, the doped layer 202 and the hard mask layer 203 are sequentially formed on the substrate 101, as shown in Figure 5a .

[0101] In this step, the nucleation layer 102, the buffer layer 103, the channel layer 104, the barrier layer 105, the insertion layers 2011 and 2012, the doped layer 202 and the hard mask layer 203 are formed by, for example, a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method or other methods. The processes for forming each material layer are known in the art and will not be described in detail here.

[0102] The insertion layer 2011 and the insertion layer 2012 are, for example, composed of any one of p-type doped aluminum nitride, aluminum gallium nitride or gallium nitride. Specifically, for example, the insertion layer 2011 is a p-type doped gallium nitride layer, and the insertion layer 2012 is a p-type doped aluminum gallium nitride layer.

[0103] In this embodiment, the steps of the nucleation layer 102, the buffer layer 103, the channel layer 104, the barrier layer 105, the doped layer 202 and the hard mask layer 203 are the same as those of the first embodiment and will not be described in detail here.

[0104] Further, the hard mask layer 203 and the doped layer 202 are patterned by using a resist mask PR1 to form the gate structure layer 212 in the gate stack 310, as shown in Figure 5b .

[0105] Further, the first and second insertion layers 211 and 231 in the gate stack 310 and the first and second hole injection layers 221 and 232 in the drain stack 320 are patterned by using the resist mask PR2 and the hard mask layer 203, as shown in FIG. 3D. Figure 5c

[0106] In this embodiment, the gate stack 310 includes the first insertion layer 211, the second insertion layer 231 and the gate structure layer 212 stacked together. The drain stack 320 includes the first hole injection layer 221 and the second hole injection layer 232 stacked together. Specifically, the first insertion layer 211, the second insertion layer 231 in the gate stack 310 and the first hole injection layer 221 and the second hole injection layer 232 in the drain stack 320 are formed in this step.

[0107] Further, the hard mask layer 203 and the resist mask PR2 are removed, as shown in FIG. 3E. Figure 5d

[0108] Further, the gate electrode 301, the source electrode 302 and the drain electrode 303 are formed, as shown in FIG. 3F. Figure 5e

[0109] In this embodiment, the gate structure layer 212 and the second insertion layer 231 are composed of different materials, respectively. For example, the gate structure layer 212 and the second insertion layer 231 are gallium nitride layer and aluminum gallium nitride layer, respectively. A selective etching gas, for example, etching gas of CL2 / BCl3 / O2 or SF6, can be used to etch gallium nitride and aluminum gallium nitride, and AR, N2, HE and other auxiliary gases can be added to make the etching rate ratio of gallium nitride to aluminum gallium nitride about 30:1 or even higher. Thus, in the patterning step of the gate structure layer 212 shown in FIG. 3D, the insertion layer 2012 as the etching stop layer can avoid under-etching of the gate structure layer 212 or over-etching of the insertion layer 2011, and solve the problem of poor consistency of the hole injection region caused by the influence of epitaxial uniformity and etching uniformity in the conventional process, thereby ensuring the repeatability and stability of the manufacturing process. Figure 5b

[0110] The gallium nitride transistor according to the embodiment of the present application has a gate stack between the gate electrode and the barrier layer, and the gate stack includes a gate structure layer and a first insertion layer. The first insertion layer is composed of P-type doped nitride, for example, which can act as the etching stop layer of the gate structure layer and effectively reduce the gate leakage current.

[0111] ​​​​The gallium nitride transistor further comprises a first hole injection layer on the barrier layer. The first hole injection layer is composed of, for example, P-type doped nitride. The drain electrode and the first hole injection layer are in contact with each other. By modulating the doping concentration of the first hole injection layer or by etching thinning, the first hole injection layer makes the two-dimensional electron gas between the channel layer and the barrier layer in an on state under zero bias, and injects holes into the two-dimensional electron gas between the channel layer and the barrier layer in a reverse blocking state to release trapped electrons, inhibit the increase of dynamic on-resistance of the gallium nitride transistor, increase the stability of dynamic resistance, and improve the stability and reliability of the gallium nitride transistor.

[0112] In further embodiments, a second insertion layer is further included between the first insertion layer and the gate structure layer, which can be used as an etching stop layer, so that the etching process can be accurately stopped on the second insertion layer, and under-etching of the gate structure layer or over-etching of the first insertion layer can be avoided, thereby increasing the stability of the process.

[0113] In further embodiments, a second hole injection layer is further included between the first hole injection layer and the drain electrode, which can be used as an etching stop layer, so that the etching process can be accurately stopped on the second hole injection layer, and the consistency of the thickness of the first hole injection layer is ensured, thereby increasing the stability of the process.

[0114] It should be noted that, in the present text, relational terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between such entities or operations. Moreover, the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a list of elements not only includes those elements, but also includes other elements not expressly listed or inherent to such process, method, article or apparatus. Without more limitations, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0115] The embodiments according to the present application are described above as described in the foregoing, and these embodiments do not exhaustively describe all the details, nor limit the disclosure to only the specific embodiments described. It is obvious that, according to the above description, many modifications and changes can be made. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A method of fabricating a gallium nitride transistor, comprising: forming a barrier layer on a substrate; forming a gate stack on a first region above the barrier layer, the gate stack comprising a gate structure layer and a first interposition layer between the gate structure layer and the barrier layer; and forming a first hole injection layer on a second region above the barrier layer, the first region and the second region being separated from each other, wherein the forming a gate stack comprises patterning a hard mask layer using a first resist mask, patterning a doping layer using the first resist mask to form the gate structure layer, and patterning an interposition layer using the hard mask layer to form the first interposition layer; patterning the interposition layer using a second resist mask to form the first hole injection layer simultaneously with patterning the interposition layer using the hard mask layer to form the first interposition layer. forming the gate stack by one lithography etching.

2. The manufacturing method according to claim 1, wherein, removing the hard mask layer after patterning the interposition layer.

3. The production method according to claim 1 or 2, wherein forming the doping layer using an epitaxial growth method.

4. The manufacturing method according to claim 1, wherein, the gate structure layer, the first interposition layer, and the first hole injection layer each comprise a doped nitride.

5. The manufacturing method according to claim 1, wherein, the dopant distribution in the gate structure layer, the first interposition layer, and the first hole injection layer is any one of a fixed composition, a graded composition, and a sudden composition change.

6. The manufacturing method according to claim 5, wherein, the gate structure layer comprises a p-type dopant.

7. The manufacturing method according to claim 5, wherein, the dopant incorporated in the gate structure layer comprises any one selected from the group consisting of magnesium, calcium, beryllium, zinc, or a combination thereof.

8. The manufacturing method according to claim 7, wherein, the method further comprises, before the forming a barrier layer on a substrate:

9. The production method according to claim 1, wherein forming a nucleation layer on a substrate; forming a buffer layer on the nucleation layer; forming a gallium nitride channel layer on the buffer layer, the barrier layer being on the gallium nitride channel layer. the doping concentration of the gate structure layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer below the gate stack is in an off state at zero bias.

10. The manufacturing method according to claim 9, wherein, the first interposition layer and the first hole injection layer comprise a p-type dopant.

11. The manufacturing method according to claim 5, wherein, the dopant incorporated in the first hole injection layer comprises any one selected from the group consisting of magnesium, calcium, beryllium, zinc, or a combination thereof.

12. The manufacturing method according to claim 11, wherein, the doping concentration of the first hole injection layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer below the first hole injection layer is in an on state at zero bias, the first hole injection layer injecting holes into the barrier layer in a reverse off state.

13. The manufacturing method of claim 10, wherein, the thickness of the first hole injection layer is etched down such that a channel in the gallium nitride channel layer below the first hole injection layer is in an on state at zero bias, the first hole injection layer injecting holes into the channel in the gallium nitride channel layer in a reverse off state.

14. The manufacturing method of claim 11, wherein, 15. The method of claim 1, further comprising, after the forming a gate stack and the forming a first hole injection layer: forming a source electrode, a drain electrode, and a gate electrode between the source electrode and the drain electrode on the barrier layer, respectively, ​ The gate electrode and the gate structure layer form a Schottky contact.

16. The manufacturing method of claim 15, wherein, The source electrode and the drain electrode form an ohmic contact with the barrier layer.

17. The manufacturing method of claim 15, wherein, The gallium nitride channel layer and the barrier layer form a two-dimensional electron gas.

18. The manufacturing method of claim 9, wherein, 19. The manufacturing method of claim 1, further comprising forming a second interposition layer between the first interposition layer and the gate structure layer, the second interposition layer serving as a stop layer in the step of patterning the doped layer using the first resist mask. The gate structure layer is a p-doped gallium nitride layer, the first interposition layer is a p-doped gallium nitride layer, and the second interposition layer is a p-doped aluminum gallium nitride layer.

20. The manufacturing method of claim 19, wherein, The second interposition layer has a thickness that is one fifth to one twentieth of the thickness of the gate structure layer.

21. The manufacturing method of claim 20, wherein, The first interposition layer and the first hole injection layer comprise a p-type dopant.

22. The manufacturing method of claim 15, wherein, 24. A gallium nitride transistor, comprising:

23. The manufacturing method of claim 22, wherein, a barrier layer on a substrate; a gate stack in a first region above the barrier layer, the gate stack comprising a gate structure layer and a first interposition layer between the gate structure layer and the barrier layer; and a first hole injection layer in a second region above the barrier layer, the first region and the second region being separated from each other, wherein further comprising a gate electrode on the gate stack, a source electrode on the barrier layer, and a drain electrode, a first portion of the drain electrode of the gallium nitride transistor being on the first hole injection layer and a second portion being on the barrier layer, the first hole injection layer being in direct contact with the barrier layer, the first hole injection layer and the first interposition layer are patterned simultaneously. The gate structure layer, the first interposition layer, and the first hole injection layer each comprise a doped nitride. The dopant distribution in the gate structure layer, the first interposition layer, and the first hole injection layer is any one of a fixed composition, a graded composition, and a sudden composition change.

25. The gallium nitride transistor of claim 24, wherein, The gate structure layer comprises a p-type dopant.

26. The gallium nitride transistor of claim 25, wherein, The dopant incorporated in the gate structure layer comprises any one selected from magnesium, calcium, beryllium, zinc, or a combination thereof.

27. The gallium nitride transistor of claim 25, wherein, Further comprising, between the substrate and the barrier layer:

28. The gallium nitride transistor of claim 27, wherein, a nucleation layer on a substrate; 29. The gallium nitride transistor of claim 24, wherein, a buffer layer on the nucleation layer; a gallium nitride channel layer on the buffer layer, the barrier layer being on the gallium nitride channel layer. The doping concentration of the gate structure layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer below the gate stack is in a cutoff state at zero bias. The first interposition layer and the first hole injection layer comprise a p-type dopant.

30. The gallium nitride transistor of claim 29, wherein, ​ 31. The gallium nitride transistor of claim 30, wherein, ​ 32. The gallium nitride transistor of claim 31, wherein, The dopant incorporated in the first hole injection layer includes any one selected from magnesium, calcium, beryllium, zinc, or a combination thereof.

33. The gallium nitride transistor of claim 31, wherein, The doping concentration of the first hole injection layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer below the first hole injection layer is in an on state at zero bias, and the first hole injection layer injects holes into the barrier layer in a reverse blocking state.

34. The gallium nitride transistor of claim 24, wherein, The gate electrode of the gallium nitride transistor and the gate structure layer are in contact with each other, and the source electrode and the drain electrode of the gallium nitride transistor are in contact with each other.

35. The gallium nitride transistor of claim 34, wherein, The gate electrode and the gate structure layer form a Schottky contact.

36. The gallium nitride transistor of claim 34, wherein, The source electrode and the drain electrode and the barrier layer form an ohmic contact.

37. The gallium nitride transistor of claim 29, wherein, A two-dimensional electron gas is formed between the gallium nitride channel layer and the barrier layer.

38. The gallium nitride transistor of Claim 24 wherein, A second insertion layer is further included between the first insertion layer and the gate structure layer.

39. The gallium nitride transistor of claim 38, wherein, The gate structure layer is a p-doped gallium nitride layer, the first insertion layer is a p-doped gallium nitride layer, and the second insertion layer is a p-doped aluminum gallium nitride layer.

40. The gallium nitride transistor of claim 38, wherein, The thickness of the second insertion layer is one fifth to one twentieth of the thickness of the gate structure layer.

41. The gallium nitride transistor of claim 39, wherein, A second hole injection layer is further included between the drain electrode and the first hole injection layer.

42. The gallium nitride transistor of claim 41 wherein, The first hole injection layer is a p-doped gallium nitride layer, and the second hole injection layer is a p-doped aluminum gallium nitride layer.

Images