A bridge damage information acquisition device based on piezoelectric effect

Abstract

A bridge damage information collection device based on piezoelectric effect comprises a shock wave receiving sensor, wherein the signal output end of the shock wave receiving sensor is connected to the signal input end of a front-end conditioning circuit, the signal output end of the front-end conditioning circuit is connected to the signal input end of a data acquisition module, and the signal output end of the data acquisition module is connected to the signal input end of a host computer; the shock wave receiving sensor collects internal reflection waves of the bridge under external excitation through the bridge; the shock wave receiving sensor collects the internal reflection waves of the bridge under external excitation and converts them into electrical signals, then amplifies, filters, and performs over-current and over-voltage protection on the electrical signals through the front-end conditioning circuit, and then converts the analog signals into digital signals through a digital-to-analog conversion module in the data acquisition module and sends them to the host computer; the present invention can complete the flaw detection inside the bridge without damaging the bridge structure, and has the characteristics of safety and convenience.

Description

Technical Field

[0001] The invention belongs to the technical field of non-destructive flaw detection, and in particular relates to a bridge damage information acquisition device based on piezoelectric effect. Background Art

[0002] Due to floods, earthquakes, impacts and years of use, bridge structures will suffer varying degrees of damage. Timely discovery of these hidden damage problems is crucial to ensuring bridge safety. Existing bridge flaw detection devices mostly use electromagnetic waves for flaw detection operations, and their equipment structures are complex, and their manufacturing and use costs are high. Therefore, a flaw detection device with a relatively simple structure, relatively convenient use and low cost is needed to achieve low-cost non-destructive flaw detection operations, so as to better grasp the safety status of the bridge and avoid the occurrence of major traffic safety accidents due to untimely discovery, which will cause significant losses to the country and the people. Summary of the invention

[0003] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a bridge damage information collection device based on the piezoelectric effect, which can detect the waveform emitted by the seismic source through a seismic wave receiving sensor to determine whether there is damage inside the bridge, and can complete the flaw detection inside the bridge without damaging the bridge structure, and is safe and convenient.

[0004] In order to achieve the above object, the present invention adopts the following technical solution:

[0005] A bridge damage information collection device based on piezoelectric effect includes a shock wave receiving sensor 1, wherein the signal output end of the shock wave receiving sensor 1 is connected to the signal input end of a front-end conditioning circuit 2, and the signal output end of the front-end conditioning circuit 2 is connected to the signal input end of a data acquisition module 3.

[0006] The seismic wave receiving sensor 1 includes a metal shell 5, which is connected to a movement cover 6. A piezoelectric detection core 8 is provided inside the metal shell 5, and an inertia block 9 is provided on one side of the piezoelectric detection core 8; the insulating layer 7 separates the piezoelectric detection core 8 from the metal shell 5 and the inertia block 9.

[0007] The piezoelectric detection core 8 includes a first electrode 10, a first piezoelectric stack 11, a second electrode 12, a second piezoelectric stack 13 and a third electrode 14; the first piezoelectric stack 11 is sandwiched between the first electrode 10 and the second electrode 12, and the second piezoelectric stack 13 is sandwiched between the second electrode 12 and the third electrode 14; the second electrode 12 is connected to the first signal input terminal of the front-end conditioning circuit 2, and the third electrode 14 is connected to the second signal input terminal of the front-end conditioning circuit 2.

[0008] The data acquisition module 3 includes an analog-to-digital conversion circuit 15, a clock circuit 16, a reference voltage generating circuit 17, a main control chip 18, a memory 19 and a communication serial port 20; the first signal input terminal and the second signal input terminal of the analog-to-digital conversion circuit 15 are connected to the first signal output terminal and the second signal output terminal of the front-end conditioning circuit 2; the third signal input terminal of the analog-to-digital conversion circuit 15 is connected to the signal output terminal of the clock circuit 16; the fourth signal input terminal of the analog-to-digital conversion circuit 15 is connected to the signal output terminal of the reference voltage generating circuit 17; the signal output terminal of the analog-to-digital conversion circuit 15 is connected to the first signal input terminal of the main control chip 18; the main control chip 18 is signal-connected to the memory 19; the main control chip 18 is signal-connected to the communication serial port 20.

[0009] The front-end conditioning circuit 2 includes a first operational amplifier A1 and a third operational amplifier A3; the first pin of the first operational amplifier A1 is connected to one end of a resistor R106; the second pin of the first operational amplifier A1 is connected to one end of a resistor R101 and a resistor R102; the other end of the resistor R101 is grounded; the other end of the resistor R102 is connected to the first pin of the first operational amplifier A1; the third pin of the first operational amplifier A1 is connected to the first signal output end of the shock wave receiving sensor 1 and one end of a resistor R103, and the other end of the resistor R103 is grounded; the fourth pin of the first operational amplifier A1 is connected to one end of a capacitor C101, one end of a resistor R105 and one end of a first power supply; the other end of the capacitor C101 and the other end of the resistor R105 are grounded; the other end of the resistor R106 is respectively connected to one end of a resistor R107 and a capacitor C103; the other end of the capacitor C103 is grounded; the other end of the resistor R107 is respectively connected to one end of a capacitor C104 and the fifth pin of the second operational amplifier A2; the other end of the capacitor C104 is grounded;

[0010] The sixth pin of the second operational amplifier A2 is connected to one end of the resistor R108 and the resistor R109 respectively; the other end of the resistor R108 is grounded; the other end of the resistor R109 is connected to the seventh pin of the second operational amplifier A2; the seventh pin of the second operational amplifier A2 is connected to one end of the capacitor C105; the other end of the capacitor C105 is connected to one end of the resistor R111; the eighth pin of the second operational amplifier A2 is connected to one end of the capacitor C102, one end of the resistor R110 and the other end of the first power supply; the other end of the resistor R110 and the other end of the capacitor C102 are grounded;

[0011] The first pin of the third operational amplifier A3 is connected to one end of the resistor R206; the second pin of the third operational amplifier A3 is connected to one end of the resistor R201 and the resistor R202; the other end of the resistor R201 is grounded; the other end of the resistor R202 is connected to the first pin of the third operational amplifier A3; the third pin of the third operational amplifier A3 is connected to the second signal output end of the shock wave receiving sensor 1 and one end of the resistor R203; the other end of the resistor R203 is grounded; the fourth pin of the second operational amplifier A2 is connected to one end of the capacitor C201, one end of the resistor R205 and one end of the second power supply; the other end of the capacitor C201 and the other end of the resistor R205 are grounded;

[0012] The other end of the resistor R206 is connected to the resistor R207 and one end of the capacitor C203 respectively; the other end of the capacitor C203 is grounded; the other end of the resistor R207 is connected to one end of the capacitor C204 and the fifth pin of the fourth operational amplifier A4 respectively; the other end of the capacitor C204 is grounded;

[0013] The sixth pin of the fourth operational amplifier A4 is connected to one end of the resistor R208 and the resistor R209 respectively; the other end of the resistor R208 is grounded; the other end of the resistor R209 is connected to the seventh pin of the fourth operational amplifier A4; the seventh pin of the fourth operational amplifier A4 is connected to one end of the capacitor C205; the other end of the capacitor C205 is connected to one end of the resistor R211; the eighth pin of the fourth operational amplifier A4 is connected to one end of the capacitor C202, one end of the resistor R210 and the other end of the second power supply; the other end of the resistor R210 is grounded to the other end of the capacitor C202; the other end of the resistor R210 is grounded;

[0014] The other end of the resistor R111 is connected to the first pin of the fifth operational amplifier A5; the other end of the resistor R211 is connected to the second pin of the fifth operational amplifier A5;

[0015] The third pin of the fifth operational amplifier A5 is grounded; the fourth pin of the fifth operational amplifier A5 is suspended; the fifth pin of the fifth operational amplifier A5 is connected to one end of the third power supply; the sixth pin of the fifth operational amplifier A5 is connected to the other end of the third power supply; the seventh pin of the fifth operational amplifier A5 is connected to one end of the resistor R112 and the resistor R113, and the other end of the resistor R112 is connected to the first pin of the fifth operational amplifier A5; the eighth pin of the fifth operational amplifier A5 is connected to one end of the resistor R212 and the resistor R213; the other end of the resistor R212 is connected to the second pin of the fifth operational amplifier A5;

[0016] The other end of the resistor R113 is connected to one end of the resistor R114 and the resistor R115 respectively, one end of the resistor R114 is grounded, the other end of the resistor R115 is connected to one end of the resistor R116 and the capacitor C106, the other end of the capacitor C106 is grounded, the other end of the resistor R116 is connected to one end of the capacitor C301, and the other end of the resistor R116 is also connected to the common connection point of the diode D2 and the diode D3;

[0017] The other end of the resistor R213 is connected to one end of the resistor R214 and the resistor R215 respectively, one end of the resistor R214 is grounded, the other end of the resistor R215 is connected to one end of the resistor R216 and the capacitor C206, the other end of the capacitor C206 is grounded, the other end of the resistor R216 is connected to the other end of the capacitor C301, and the other end of the resistor R216 is also connected to the common connection point of the diode D1 and the diode D4;

[0018] One end of the diode D1 is connected to one end of the diode D2, the other end of the diode D2 is connected to one end of the diode D3, the other end of the diode D3 is connected to the other end of the diode D4, and one end of the diode D4 is connected to the other end of the diode D2;

[0019] The common connection point of the diode D3 and the diode D4 is connected to one end of the fourth power supply; the common connection point of the diode D1 and the diode D2 is connected to the other end of the fourth power supply;

[0020] The common connection point between the diode D2 and the diode D3 is connected to the first signal input terminal of the analog-to-digital conversion circuit 15 ; the common connection point between the diode D1 and the diode D4 is connected to the second signal input terminal of the analog-to-digital conversion circuit 15 .

[0021] The beneficial effects of the present invention are as follows: the shock wave receiving sensor 1 of the present invention adopts a metal shell 5 to shield external interference signals; the front-end conditioning module 2 adopts capacitor filtering and multi-stage signal amplification to obtain a clear reflected wave signal reflecting the internal information of the bridge. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural schematic diagram of the present invention.

[0023] Figure 2 It is a schematic structural diagram of the seismic wave receiving sensor 1 of the present invention.

[0024] Figure 3 It is a schematic diagram of the structure of the insulating layer 7 and the piezoelectric detection core 8 of the present invention.

[0025] Figure 4 It is a schematic diagram of the module structure of the present invention.

[0026] Figure 5 It is a circuit schematic diagram of the front-end conditioning circuit 2 of the present invention.

[0027] 1. Shock wave receiving sensor; 2. Front-end conditioning circuit; 3. Data acquisition module; 4. Host computer; 5. Metal shell; 6. Movement cover; 7. Insulation layer; 7a. First insulation pad; 7b. Second insulation pad; 7c. Insulation ring; 8. Piezoelectric detection core; 9. Inertia block; 10. First electrode; 11. First piezoelectric stack; 12. Second electrode; 13. Second piezoelectric stack; 14. Third electrode; 15. Analog-to-digital conversion circuit; 16. Clock circuit; 17. Reference voltage generation circuit; 18. Main control chip; 19. Memory; 20. Communication serial port;

[0028] 21. Power module. DETAILED DESCRIPTION

[0029] The present invention will be further described below in conjunction with the accompanying drawings.

[0030] See also Figure 1 A bridge damage information collection device based on piezoelectric effect includes a shock wave receiving sensor 1, a signal output end of the shock wave receiving sensor 1 is connected to a signal input end of a front-end conditioning circuit 2, and a signal output end of the front-end conditioning circuit 2 is connected to a signal input end of a data acquisition module 3.

[0031] See also Figure 2 The shock wave receiving sensor 1 includes a metal shell 5, which is connected to a movement cover 6. A piezoelectric detection core 8 is provided inside the metal shell 5, and an inertia block 9 is provided on one side of the piezoelectric detection core 8; the insulating layer 7 separates the piezoelectric detection core 8 from the metal shell 5 and the inertia block 9.

[0032] See also Figure 3 The insulating layer 7 includes a first insulating pad 7a, a second insulating pad 7b and an insulating ring 7c; the first insulating pad 7a is arranged between one side of the piezoelectric detection core 8 and the metal shell 5; the second insulating pad 7b is arranged between the other side of the piezoelectric detection core 8 and the metal shell 5; the insulating ring 7c is arranged between the side of the piezoelectric detection core 8 and the metal shell 5.

[0033] The piezoelectric detection core 8 includes a first electrode 10, a first piezoelectric stack 11, a second electrode 12, a second piezoelectric stack 13 and a third electrode 14; the first piezoelectric stack 11 is sandwiched between the first electrode 10 and the second electrode 12, and the second piezoelectric stack 13 is sandwiched between the second electrode 12 and the third electrode 14; the second electrode 12 is connected to the first signal input terminal of the front-end conditioning circuit 2, and the third electrode 14 is connected to the second signal input terminal of the front-end conditioning circuit 2.

[0034] See also Figure 4 , the data acquisition module 3 includes an analog-to-digital conversion circuit 15, a clock circuit 16, a reference voltage generating circuit 17, a main control chip 18, a memory 19 and a communication serial port 20;

[0035] The first signal input terminal and the second signal input terminal of the analog-to-digital conversion circuit 15 are connected to the first signal output terminal and the second signal output terminal of the front-end conditioning circuit 2; the third signal input terminal of the analog-to-digital conversion circuit 15 is connected to the signal output terminal of the clock circuit 16; the fourth signal input terminal of the analog-to-digital conversion circuit 15 is connected to the signal output of the reference voltage generating circuit 17; the signal output terminal of the analog-to-digital conversion circuit 15 is connected to the first signal input terminal of the main control chip 18;

[0036] The main control chip 18 is connected to the memory 19 by signal; the main control chip 18 is connected to the communication serial port 20 by signal.

[0037] See also Figure 5 , the front-end conditioning circuit 2 includes a first operational amplifier A1 and a third operational amplifier A3;

[0038] The first pin of the first operational amplifier A1 is connected to one end of the resistor R106; the second pin of the first operational amplifier A1 is connected to one end of the resistor R101 and the resistor R102; the other end of the resistor R101 is grounded; the other end of the resistor R102 is connected to the first pin of the first operational amplifier A1; the third pin of the first operational amplifier A1 is connected to the first signal output end of the shock wave receiving sensor 1 and one end of the resistor R103, and the other end of the resistor R103 is grounded; the fourth pin of the first operational amplifier A1 is connected to one end of the capacitor C101, one end of the resistor R105 and one end of the first power supply; the other end of the capacitor C101 and the other end of the resistor R105 are grounded;

[0039] The other end of the resistor R106 is connected to the resistor R107 and one end of the capacitor C103 respectively; the other end of the capacitor C103 is grounded; the other end of the resistor R107 is connected to one end of the capacitor C104 and the fifth pin of the second operational amplifier A2 respectively; the other end of the capacitor C104 is grounded;

[0040] The sixth pin of the second operational amplifier A2 is connected to one end of the resistor R108 and the resistor R109 respectively; the other end of the resistor R108 is grounded; the other end of the resistor R109 is connected to the seventh pin of the second operational amplifier A2; the seventh pin of the second operational amplifier A2 is connected to one end of the capacitor C105; the other end of the capacitor C105 is connected to one end of the resistor R111; the eighth pin of the second operational amplifier A2 is connected to one end of the capacitor C102, one end of the resistor R110 and the other end of the first power supply; the other end of the resistor R110 and the other end of the capacitor C102 are grounded;

[0041] The first pin of the third operational amplifier A3 is connected to one end of the resistor R206; the second pin of the third operational amplifier A3 is connected to one end of the resistor R201 and the resistor R202; the other end of the resistor R201 is grounded; the other end of the resistor R202 is connected to the first pin of the third operational amplifier A3; the third pin of the third operational amplifier A3 is connected to the second signal output end of the shock wave receiving sensor 1 and one end of the resistor R203; the other end of the resistor R203 is grounded; the fourth pin of the second operational amplifier A2 is connected to one end of the capacitor C201, one end of the resistor R205 and one end of the second power supply; the other end of the capacitor C201 and the other end of the resistor R205 are grounded;

[0042] The other end of the resistor R206 is connected to the resistor R207 and one end of the capacitor C203 respectively; the other end of the capacitor C203 is grounded; the other end of the resistor R207 is connected to one end of the capacitor C204 and the fifth pin of the fourth operational amplifier A4 respectively; the other end of the capacitor C204 is grounded;

[0043] The sixth pin of the fourth operational amplifier A4 is connected to one end of the resistor R208 and the resistor R209 respectively; the other end of the resistor R208 is grounded; the other end of the resistor R209 is connected to the seventh pin of the fourth operational amplifier A4; the seventh pin of the fourth operational amplifier A4 is connected to one end of the capacitor C205; the other end of the capacitor C205 is connected to one end of the resistor R211; the eighth pin of the fourth operational amplifier A4 is connected to one end of the capacitor C202, one end of the resistor R210 and the other end of the second power supply; the other end of the resistor R210 is grounded to the other end of the capacitor C202; the other end of the resistor R210 is grounded;

[0044] The other end of the resistor R111 is connected to the first pin of the fifth operational amplifier A5; the other end of the resistor R211 is connected to the second pin of the fifth operational amplifier A5.

[0045] The third pin of the fifth operational amplifier A5 is grounded; the fourth pin of the fifth operational amplifier A5 is suspended; the fifth pin of the fifth operational amplifier A5 is connected to one end of the third power supply; the sixth pin of the fifth operational amplifier A5 is connected to the other end of the third power supply; the seventh pin of the fifth operational amplifier A5 is connected to one end of the resistor R112 and the resistor R113, and the other end of the resistor R112 is connected to the first pin of the fifth operational amplifier A5; the eighth pin of the fifth operational amplifier A5 is connected to one end of the resistor R212 and the resistor R213; the other end of the resistor R212 is connected to the second pin of the fifth operational amplifier A5;

[0046] The other end of the resistor R113 is connected to one end of the resistor R114 and the resistor R115 respectively, one end of the resistor R114 is grounded, the other end of the resistor R115 is connected to one end of the resistor R116 and the capacitor C106, the other end of the capacitor C106 is grounded, the other end of the resistor R116 is connected to one end of the capacitor C301, and the other end of the resistor R116 is also connected to the common connection point of the diode D2 and the diode D3;

[0047] The other end of the resistor R213 is connected to one end of the resistor R214 and the resistor R215 respectively, one end of the resistor R214 is grounded, the other end of the resistor R215 is connected to one end of the resistor R216 and the capacitor C206, the other end of the capacitor C206 is grounded, the other end of the resistor R216 is connected to the other end of the capacitor C301, and the other end of the resistor R216 is also connected to the common connection point of the diode D1 and the diode D4;

[0048] One end of the diode D1 is connected to one end of the diode D2, the other end of the diode D2 is connected to one end of the diode D3, the other end of the diode D3 is connected to the other end of the diode D4, and one end of the diode D4 is connected to the other end of the diode D2;

[0049] The common connection point of the diode D3 and the diode D4 is connected to one end of the fourth power supply; the common connection point of the diode D1 and the diode D2 is connected to the other end of the fourth power supply;

[0050] The common connection point between the diode D2 and the diode D3 is connected to the first signal input terminal of the analog-to-digital conversion circuit 15 ; the common connection point between the diode D1 and the diode D4 is connected to the second signal input terminal of the analog-to-digital conversion circuit 15 .

[0051] The data acquisition module 3 is connected to the host computer 4 by signal.

[0052] The front-end conditioning circuit 2 and the data acquisition module 3 are both electrically connected to the power supply module 21 .

[0053] The working principle of the present invention is as follows: the device first uses a seismic wave receiving sensor 1 to collect the internal reflection wave of the bridge under external excitation and converts it into an electrical signal, then amplifies, filters, and performs overcurrent and overvoltage protection on the electrical signal through a front-end conditioning circuit 2, and then converts the analog signal into a digital signal through an analog-to-digital conversion circuit 15 in a data acquisition module 3 and sends it to a host computer 4; the safety assessment system in the host computer 4 evaluates the damage state of the bridge structure;

[0054] In the process that the shock wave receiving sensor 1 receives the shock wave reflected wave and converts it into an electrical signal, the inertial block 9 plays the following role: when the shock wave reflected wave propagates to the shock wave receiving sensor 1, the shock wave receiving sensor 1 is forced to vibrate, but since the inertial block 9 inside the shock wave receiving sensor 1 has a large mass and a strong tendency to maintain its original position, while the metal shell 5 and the piezoelectric detection core 8 have a weak tendency to maintain their original positions, the metal shell 5 and the inertial block 9 will generate a force to squeeze the piezoelectric detection core 8, causing the piezoelectric detection core 8 to emit an electrical signal.

Claims

1. A bridge damage information collection device based on piezoelectric effect, characterized in that: It comprises a shock wave receiving sensor (1), wherein the signal output end of the shock wave receiving sensor (1) is connected to the signal input end of the front-end conditioning circuit (2), and the signal output end of the front-end conditioning circuit (2) is connected to the signal input end of the data acquisition module (3); The shock wave receiving sensor (1) comprises a metal shell (5), the metal shell (5) being connected to a movement cover (6), a piezoelectric detection core (8) being provided inside the metal shell (5), and an inertia block (9) being provided on one side of the piezoelectric detection core (8); an insulating layer (7) is used to separate the piezoelectric detection core (8) from the metal shell (5) and the inertia block (9); The data acquisition module (3) comprises an analog-to-digital conversion circuit (15), a clock circuit (16), a reference voltage generation circuit (17), a main control chip (18), a memory (19) and a communication serial port (20); The first signal input terminal and the second signal input terminal of the analog-to-digital conversion circuit (15) are connected to the first signal output terminal and the second signal output terminal of the front-end conditioning circuit (2); the third signal input terminal of the analog-to-digital conversion circuit (15) is connected to the signal output terminal of the clock circuit (16); the fourth signal input terminal of the analog-to-digital conversion circuit (15) is connected to the signal output of the reference voltage generating circuit (17); the signal output terminal of the analog-to-digital conversion circuit (15) is connected to the first signal input terminal of the main control chip (18); the main control chip (18) is signal-connected to the memory (19); the main control chip (18) is signal-connected to the communication serial port (20); The front-end conditioning circuit (2) comprises a first operational amplifier A1 and a third operational amplifier A3; the first pin of the first operational amplifier A1 is connected to one end of a resistor R106; the second pin of the first operational amplifier A1 is connected to one end of a resistor R101 and a resistor R102; the other end of the resistor R101 is grounded; the other end of the resistor R102 is connected to the first pin of the first operational amplifier A1; the third pin of the first operational amplifier A1 is connected to the first signal output end of the shock wave receiving sensor (1) and one end of a resistor R103, and the other end of the resistor R103 is grounded; the fourth pin of the first operational amplifier A1 is connected to one end of a capacitor C101, one end of a resistor R105 and one end of a first power supply; the other end of the capacitor C101 and the other end of the resistor R105 are grounded; The other end of the resistor R106 is connected to the resistor R107 and one end of the capacitor C103 respectively; the other end of the capacitor C103 is grounded; the other end of the resistor R107 is connected to one end of the capacitor C104 and the fifth pin of the second operational amplifier A2 respectively; the other end of the capacitor C104 is grounded; The sixth pin of the second operational amplifier A2 is connected to one end of the resistor R108 and the resistor R109 respectively; the other end of the resistor R108 is grounded; the other end of the resistor R109 is connected to the seventh pin of the second operational amplifier A2; the seventh pin of the second operational amplifier A2 is connected to one end of the capacitor C105; the other end of the capacitor C105 is connected to one end of the resistor R111; the eighth pin of the second operational amplifier A2 is connected to one end of the capacitor C102, one end of the resistor R110 and the other end of the first power supply; the other end of the resistor R110 and the other end of the capacitor C102 are grounded; The first pin of the third operational amplifier A3 is connected to one end of the resistor R206; the second pin of the third operational amplifier A3 is connected to one end of the resistor R201 and the resistor R202; the other end of the resistor R201 is grounded; the other end of the resistor R202 is connected to the first pin of the third operational amplifier A3; the third pin of the third operational amplifier A3 is connected to the second signal output end of the shock wave receiving sensor (1) and one end of the resistor R203; the other end of the resistor R203 is grounded; the fourth pin of the second operational amplifier A2 is connected to one end of the capacitor C201, one end of the resistor R205 and one end of the second power supply; the other end of the capacitor C201 and the other end of the resistor R205 are grounded; The other end of the resistor R206 is connected to the resistor R207 and one end of the capacitor C203 respectively; the other end of the capacitor C203 is grounded; the other end of the resistor R207 is connected to one end of the capacitor C204 and the fifth pin of the fourth operational amplifier A4 respectively; the other end of the capacitor C204 is grounded; The sixth pin of the fourth operational amplifier A4 is connected to one end of the resistor R208 and the resistor R209 respectively; the other end of the resistor R208 is grounded; the other end of the resistor R209 is connected to the seventh pin of the fourth operational amplifier A4; the seventh pin of the fourth operational amplifier A4 is connected to one end of the capacitor C205; the other end of the capacitor C205 is connected to one end of the resistor R211; the eighth pin of the fourth operational amplifier A4 is connected to one end of the capacitor C202, one end of the resistor R210 and the other end of the second power supply; the other end of the resistor R210 is grounded to the other end of the capacitor C202; the other end of the resistor R210 is grounded; The other end of the resistor R111 is connected to the first pin of the fifth operational amplifier A5; the other end of the resistor R211 is connected to the second pin of the fifth operational amplifier A5; The third pin of the fifth operational amplifier A5 is grounded; the fourth pin of the fifth operational amplifier A5 is suspended; the fifth pin of the fifth operational amplifier A5 is connected to one end of the third power supply; the sixth pin of the fifth operational amplifier A5 is connected to the other end of the third power supply; the seventh pin of the fifth operational amplifier A5 is connected to one end of the resistor R112 and the resistor R113, and the other end of the resistor R112 is connected to the first pin of the fifth operational amplifier A5; the eighth pin of the fifth operational amplifier A5 is connected to one end of the resistor R212 and the resistor R213; the other end of the resistor R212 is connected to the second pin of the fifth operational amplifier A5; The other end of the resistor R113 is connected to one end of the resistor R114 and the resistor R115 respectively, one end of the resistor R114 is grounded, the other end of the resistor R115 is connected to one end of the resistor R116 and the capacitor C106, the other end of the capacitor C106 is grounded, the other end of the resistor R116 is connected to one end of the capacitor C301, and the other end of the resistor R116 is also connected to the common connection point of the diode D2 and the diode D3; The other end of the resistor R213 is connected to one end of the resistor R214 and the resistor R215 respectively, one end of the resistor R214 is grounded, the other end of the resistor R215 is connected to one end of the resistor R216 and the capacitor C206, the other end of the capacitor C206 is grounded, the other end of the resistor R216 is connected to the other end of the capacitor C301, and the other end of the resistor R216 is also connected to the common connection point of the diode D1 and the diode D4; One end of the diode D1 is connected to one end of the diode D2, the other end of the diode D2 is connected to one end of the diode D3, the other end of the diode D3 is connected to the other end of the diode D4, and one end of the diode D4 is connected to the other end of the diode D2; The common connection point of the diode D3 and the diode D4 is connected to one end of the fourth power supply; the common connection point of the diode D1 and the diode D2 is connected to the other end of the fourth power supply; The common connection point between the diode D2 and the diode D3 is connected to the first signal input terminal of the analog-to-digital conversion circuit (15); and the common connection point between the diode D1 and the diode D4 is connected to the second signal input terminal of the analog-to-digital conversion circuit (15).

2. The bridge damage information collection device based on piezoelectric effect according to claim 1 is characterized in that: The piezoelectric detection core (8) comprises a first electrode (10), a first piezoelectric stack (11), a second electrode (12), a second piezoelectric stack (13) and a third electrode (14); the first piezoelectric stack (11) is sandwiched between the first electrode (10) and the second electrode (12), and the second piezoelectric stack (13) is sandwiched between the second electrode (12) and the third electrode (14); the second electrode (12) is connected to a first signal input terminal of a front-end conditioning circuit (2), and the third electrode (14) is connected to a second signal input terminal of the front-end conditioning circuit (2).

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