Lateral superjunction transistor device and method for manufacturing the same

Abstract

The invention discloses a transistor arrangement and method. The transistor arrangement comprises: a plurality of first semiconductor regions (11) of a first doping type and a plurality of second semiconductor regions (12) of a second doping type, wherein the first semiconductor regions (11) and the second semiconductor regions (12) are alternately arranged along a vertical direction (z) of a semiconductor body (100); a source region (13) adjacent to the plurality of first semiconductor regions (11); a drain region (15) adjacent to the plurality of second semiconductor regions (120) and arranged to be separated from the source region (13) along a first lateral direction (x); and a plurality of gate regions (14), wherein each of the plurality of gate regions (14) is adjacent to at least one of the plurality of second semiconductor regions (12) and is arranged between the source region (13) and the drain region (15). At least one of the first semiconductor region and the second semiconductor region (11, 12) (but not each of the first semiconductor region and the second semiconductor region (11, 12)) has a doping amount that varies along the first lateral direction (x).

Description

Technical Field

[0001] The present disclosure relates generally to transistor arrangements and, more particularly, to lateral superjunction transistor devices. Background Art

[0002] The lateral superjunction transistor device includes a plurality of first semiconductor regions of a first doping type and a plurality of second semiconductor regions of a second doping type, wherein each of the first semiconductor region and the second semiconductor region is arranged between a source region and a drain region. The first semiconductor region is often referred to as a drift region, and the second semiconductor region is often referred to as a compensation region. The switching state (on or off) of the transistor device can be controlled by one or more gate regions.

[0003] In the off state of the transistor device, when the drain-source voltage is applied between the drain region and the source region, a space charge region (depletion region) expands in the first and second semiconductor regions. The space charge region is associated with an electric field, wherein avalanche breakdown may occur when the voltage is increased so that the field strength of the electric field reaches a critical value (which is often referred to as the critical electric field). In the case of avalanche breakdown, a current (which is often referred to as an avalanche current) flows through the transistor device.

[0004] In a superjunction transistor device, the voltage blocking capability, which is the maximum voltage that the transistor device can withstand in the off state, depends in particular on the ratio of the total number of dopant atoms in the first semiconductor region to the total number of dopant atoms in the second semiconductor region, and on the distribution of these dopant atoms between the source region and the drain region. At a given on-resistance, which is the resistance between the source region and the drain region in the on-state of the transistor device, the maximum voltage blocking capability can be obtained by implementing the first semiconductor region and the second semiconductor region so that the total number of dopant atoms in the first semiconductor region and the total number of dopant atoms in the second semiconductor region are substantially equal and the dopant atoms in the first semiconductor region and the second semiconductor region are distributed in the same manner. However, this type of transistor device has low avalanche robustness. That is, avalanche breakdown can damage or destroy the transistor device.

[0005] Therefore, there is a need for a lateral superjunction transistor device with avalanche robustness, ie, a device that can repeatedly withstand avalanche breakdown. Summary of the invention

[0006] An example relates to a transistor arrangement. The transistor arrangement includes a plurality of first semiconductor regions of a first doping type and a plurality of second semiconductor regions of a second doping type, a source region adjacent to the plurality of first semiconductor regions, a drain region adjacent to the plurality of second semiconductor regions (120) and arranged to be separated from the source region along a first lateral direction of the semiconductor body, and a plurality of gate regions. The first semiconductor regions and the second semiconductor regions are alternately arranged along a vertical direction of the semiconductor body. Each of the plurality of gate regions is adjacent to at least one of the plurality of second semiconductor regions and is arranged between the source region and the drain region. In addition, at least one of the first semiconductor region and the second semiconductor region has a doping amount that varies along the first lateral direction and the remaining first semiconductor regions and the second semiconductor regions have a substantially uniform doping amount.

[0007] Another example relates to a method. The method includes: forming a plurality of first semiconductor regions of a first doping type and a plurality of second semiconductor regions of a second doping type, so that the first semiconductor regions and the second semiconductor regions are arranged alternately along a vertical direction of a semiconductor body; forming a source region adjacent to the plurality of first semiconductor regions; forming a drain region adjacent to the plurality of first and second semiconductor regions and arranged to be separated from the source region along a first lateral direction of the semiconductor body; and forming a plurality of gate regions, so that each of the plurality of gate regions is adjacent to at least one of the plurality of second semiconductor regions and is arranged between the source region and the drain region. Forming at least one of the first and second semiconductor regions includes: forming at least one of the first and second semiconductor regions so that it has a varying doping amount along a first lateral direction; and forming the remaining first and second semiconductor regions so that they all have a substantially uniform doping amount.

[0008] The following examples will be explained with reference to the accompanying drawings. The accompanying drawings serve to illustrate certain principles and thus only show aspects necessary for understanding these principles. The accompanying drawings are not drawn to scale. In the accompanying drawings, the same reference numerals represent similar features. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A-Figure 1C Schematically shows a perspective cross-sectional view of a lateral superjunction transistor device ( Figure 1A )、Vertical Section( Figure 1B ) and horizontal cross-section ( Figure 1C );

[0010] Figure 2 An example of the behavior of an electric field in a lateral superjunction transistor device having first and second semiconductor regions with uniform doping doses is shown;

[0011] Figure 3Shows that when avalanche breakdown occurs Figure 2 the drain-source voltage of a transistor device of the type shown;

[0012] Figure 4 An example of the behavior of an electric field in a lateral superjunction transistor device having at least one first or second semiconductor region with varying doping doses is shown;

[0013] Figure 5-Figure 7 Different examples of uniform doping levels and varying doping levels are shown;

[0014] Figure 8A-8D Different examples are shown in which a first or second semiconductor region having a varying doping dose may be located in a lateral superjunction transistor device;

[0015] Fig.9A and Fig. 9B One example of a method for forming a lateral superjunction transistor device is shown;

[0016] Figures 10A-10D One example of a method for forming first and second semiconductor layers having uniform doping doses is shown;

[0017] Fig.11A and Fig. 11B Shows the Figures 10A-10D Modifications of the methods shown;

[0018] Figure 12-Figure 15 Various examples for forming a first or second semiconductor layer having a varying doping amount are shown;

[0019] Fig.16 The substrate additionally includes a diode below the first and second semiconductor regions. Figure 1A-Figure 1C A transistor device of the type shown; and

[0020] Fig.17 Shows that there is Figure 1A-Figure 1C A transistor arrangement of a transistor device of the type shown and another transistor device. DETAILED DESCRIPTION

[0021] Reference will be made to the accompanying drawings in the detailed description below. The accompanying drawings form part of the specification and show examples of how the invention may be used and implemented for illustrative purposes. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically indicated.

[0022] Figure 1A-Figure 1C A perspective cross-sectional view of a transistor arrangement including a lateral superjunction transistor device 10 is shown ( Figure 1A )、Vertical Section( Figure 1B) and horizontal cross-section ( Figure 1C ). The transistor device 10 includes a plurality of first semiconductor regions 11 of a first doping type and a plurality of second semiconductor regions 12 of a second doping type. The first semiconductor regions and the second semiconductor regions are arranged alternately, and the second doping type is complementary to the first doping type. Each of the source region 13 and the drain region 15 is adjacent to each of the plurality of first semiconductor regions 11, wherein the drain region 15 is positioned to be separated from the source region 13 along a first lateral direction x of the semiconductor body 100, and the first semiconductor regions 11 and the second semiconductor regions 12, the source region 13, and the drain region 15 are arranged in the semiconductor body 100. In addition, each of the plurality of gate regions 14 is (a) adjacent to at least one of the plurality of second semiconductor regions 12, (b) arranged between the source region 13 and the drain region 15, and (c) separated from the first source region 13 and the first drain region 15.

[0023] As used herein, a region or layer of a first doping type is a layer or region that is effectively doped with the first doping type. Such a region or layer of the first doping type may include a dopant of a second doping type in addition to a dopant of the first doping type, but the dopant of the first doping type is dominant. Similarly, a region or layer of the second doping type is a layer or region that is effectively doped with the second doping type and may contain a dopant of the first doping type.

[0024] Each of the first semiconductor region 11 and the second semiconductor region 12 has a length along a first lateral direction x of the semiconductor body 100 and a thickness along a vertical direction of the semiconductor body 100, and further extends along a second lateral direction y. The “vertical direction z” is a direction perpendicular to the first surface 101 of the semiconductor body 100, and the “first lateral direction x and the second lateral direction y” are directions parallel to the first surface 101. The first semiconductor region 11 and the second semiconductor region 12 may also be referred to as semiconductor layers, and an arrangement having a plurality of first semiconductor regions (layers) 11 and a plurality of second semiconductor regions (layers) 12 may also be referred to as a layer stack or simply a stack.

[0025] The stack may extend to the first surface 101 such that one of the first semiconductor region 11 and the second semiconductor region 12 forms the first surface 101. Alternatively, the third semiconductor region (layer) 131 is arranged between the stack and the first surface such that the third semiconductor region 131 forms the first surface 101.

[0026] The semiconductor body 100 may include conventional semiconductor materials, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN) or gallium arsenide (GaAs), etc. The semiconductor body 100 may be arranged on any kind of carrier 200 (on Figure 1A and Figure 1B An example of the carrier 200 will be further explained below.

[0027] According to one example, the total number of first semiconductor regions 11 in the stack is equal to the total number of second semiconductor regions 12. Figure 1A and Figure 1B In the example shown, the uppermost semiconductor region of the stack is the second semiconductor region 12, and the lowermost semiconductor region is the first semiconductor region 11. The "uppermost semiconductor region of the stack" is the region of the stack that is closest to the first surface 101, and the lowermost semiconductor region is the region of the stack that is farthest from the uppermost layer. However, implementing the uppermost region as the second semiconductor region 12 and the lowermost region as the first semiconductor region 11 is only an example. According to another example (not shown), the uppermost region is the first semiconductor region 11, and the lowermost region is the second semiconductor region 12. For illustrative purposes only, in Figure 1A-Figure 1C In the example shown, the stack having the first semiconductor region 11 and the second semiconductor region 12 includes four first regions 11 and four second regions 12, so that the stack includes a total of eight regions. However, this is only an example. According to an example, the total number of complementary regions 11 and 12 in the stack is between 4 and 60, between 4 and 30, or between 6 and 20.

[0028] exist Figure 1A-Figure 1C In the example shown, each of the source region 13 and the drain region 15 extends along the vertical direction z of the semiconductor body 100, so that each of the source region 13 and the drain region 15 is adjacent to each of the first region 11 (and the second region 12). In addition, in this example, the gate region 14 extends along the vertical direction z of the semiconductor body 100, so that each of the plurality of gate regions 14 is adjacent to each of the second semiconductor regions 12. The gate regions 14 are spaced apart from each other along a second lateral direction y. The second lateral direction y is different from the first lateral direction x and may be perpendicular to the first lateral direction x.

[0029] Figure 1A-Figure 1C The lateral super junction transistor device 10 shown is a depletion mode device, more specifically a JFET (junction field effect transistor). In the transistor device 10, each of the source region 13 and the drain region 15 is a region of a first doping type, and each of the gate region 14 is a region of a second doping type. In addition, the first semiconductor region 11 forms a drift region of the super junction device, and the second semiconductor region 12 forms a compensation region of the super junction device. The functions of these drift regions 11 and compensation regions 12 will be further explained below.

[0030] The transistor device can be implemented as an n-type transistor device or a p-type transistor device, wherein the specific type is defined by the type of the first doping type. When the first doping type is n-type and the second doping type is p-type, the first transistor device 10 is an n-type JFET. Similarly, when the first doping type is p-type and the second doping type is n-type, the first transistor device 10 is a p-type JFET.

[0031] According to one example, the source region 13, the drain region 15, the plurality of gate regions 14, the first and second regions 11, 12 forming the drift region and the compensation region, and the optional third region 131 are single crystalline semiconductor regions. According to one example, these regions include single crystalline silicon (Si), and the doping concentration of the source region 13 and the drain region 15 is selected from the range of 1E17 cm -3 (=1·10 17 cm -3 ) and 1E21 cm -3 and the doping concentration of the gate region 14 is selected from 1E17 cm -3 and 1E21 cm -3 Examples of doping details of the first semiconductor region 11 and the second semiconductor region 12 will be discussed in further detail below.

[0032] refer to Figure 1A and Figure 1B , the source region 13 is connected to the source node S, the gate region 14 is connected to the gate node G, and the drain region 15 is connected to the drain node D. Figure 1A and Figure 1B The source node S, the gate node G, and the drain node D are only schematically shown in FIG. These nodes S, G, D may include metallization (not shown) on the top of the semiconductor body 100 or on the sidewalls of the trench. Optionally, as Figure 1B As shown by the dotted lines in , the first electrode 33 may be embedded in the source region 13, the second electrode 34 may be embedded in the gate region 14, and the third electrode 35 may be embedded in the drain region 15. The first electrode 33 is connected to the source node S, and provides a low-ohmic connection between each segment of the source region 13 and the source node S. The second electrode 34 is connected to the gate node G, and provides a low-ohmic connection between each segment of the gate region 14 and the gate node G. The third electrode 35 is connected to the drain node D, and provides a low-ohmic connection between each segment of the drain region 15 and the drain node D. Reference Figure 1B, each of the first electrode 33, the second electrode 34, and the third electrode 35 may extend along the entire length of the corresponding semiconductor region 14, 15, 13 in the vertical direction z. Alternatively, one or more of these electrodes 33, 34, 35 extend into the corresponding semiconductor region 13, 14, 15, but do not extend completely along the corresponding semiconductor region 13, 14, 15 in the vertical direction. Each of these electrodes 34, 35, 33 includes a conductive material. Examples of such conductive materials include, but are not limited to: metals such as copper (Cu), aluminum (Al), tantalum (Ta), titanium (Ti), cobalt (Co), nickel (Ni), or tungsten (W); highly doped polycrystalline semiconductor materials such as polysilicon; or metal silicides such as tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), or nickel silicide (NiSi).

[0033] The following will explain Figure 1A-Figure 1C The function of the lateral superjunction transistor device shown. For the purpose of explanation only, it is assumed that the transistor device is an n-type JFET. In this case, when the gate-source voltage V received between the gate node G and the source node S is GS The voltage level is higher than the predefined threshold level V th When V GS >V th When the transistor device 10 is in the on state, the threshold voltage V th In an n-type JFET, it is negative (V th1 <0). In the on state, when an appropriate voltage is applied between the drain node D and the source node S, current can flow between the source region 13 and the drain region 15 via the first region (drift region) 11.

[0034] When the transistor device 10 is in the on state and the gate-source voltage V GS Towards the threshold voltage V th When V is reduced, the pn junction between the first source region 13 and the compensation region 12 and the pn junction between the gate region 14 and the drift region 11 become reverse biased. In addition, the pn junction between the drift region 11 and the compensation region 12 also becomes reverse biased. Reverse biasing these pn junctions will cause the drift region 11 to be depleted of charge carriers. Once the section of the drift region 11 between at least two gate regions 14 and / or between the gate region 14 and the source region 13 is completely depleted of charge carriers, the transistor device 10 is turned off. The threshold voltage V th is the voltage that turns transistor device 10 off.

[0035] Figure 1C1 shows a horizontal cross-sectional view of a cross section of the transistor device 10 in a horizontal cross-sectional plane AA passing through one of the drift regions 11. The threshold voltage V th is required to be applied between the gate region 14 and the first source region 13 so that the first drift region section 11 between the source region 13 and the gate region 14 1 or the second drift region section 11 between the gate regions 14 2 fully depleted voltage. Figure 1C In FIG. 5 , d1 represents the distance between two gate regions 14 along the second direction y.

[0036] Threshold voltage V th The magnitude (level) of depends on several design parameters and can be adjusted by appropriately designing these parameters. These design parameters include, for example, the (shortest) distance d1 between the two gate regions 14, the first drift region segment 11 1 The doping concentration of the second drift region segment 11 2 The doping concentration of the gate region 14 and the compensation region 12 ( Figure 1C The doping concentration is not visible in the figure.

[0037] Figure 1A-Figure 1C A transistor device of the type shown can be manufactured so that each of the first semiconductor region 11 and the second semiconductor region 12 has a substantially uniform doping dose. "Doping dose" is the integral of the doping concentration of the corresponding semiconductor region along the vertical direction z. The first semiconductor region 11 or the second semiconductor region 12 having a uniform doping dose can be manufactured by (for example) the following methods: (1) epitaxially growing a semiconductor layer and in-situ doping the semiconductor layer during an epitaxial growth process; or (2) epitaxially growing an intrinsic semiconductor layer and implanting dopant atoms into the semiconductor layer by a blanket (maskless) implantation process. In the latter case, the implantation dose used in the implantation process for forming one of the first semiconductor region and the second semiconductor region is equal to the doping dose of the corresponding semiconductor region.

[0038] The first semiconductor region 11 and the second semiconductor region 12 can be manufactured at the wafer level, that is, a semiconductor wafer including a plurality of first semiconductor layers of a first doping type and a plurality of second semiconductor layers of a second doping type can be manufactured, wherein the first semiconductor layers and the second semiconductor layers are arranged alternately, and wherein each of the first semiconductor layers and the second semiconductor layers has a substantially uniform doping amount. Based on such a wafer, a plurality of transistor devices can be manufactured by forming a source region, a gate region, and a drain region. The voltage blocking capability of each transistor device can be adjusted by appropriately selecting the distance between the source region 13 and the drain region 15.

[0039] The first semiconductor region 11 and the second semiconductor region 12 can be manufactured so that the first semiconductor region 11 and the second semiconductor region 12 are substantially balanced in terms of their doping doses. That is, the first semiconductor region 11 has substantially the same doping dose as the second semiconductor region 12. "Substantially balanced" means that there can be an imbalance of up to + / - 10%. That is, the dopant atoms in the drift region 11 can be 10% more or 10% less than the dopant atoms in the compensation region 12. Figure 2 shows the voltage V when the transistor device is in the off state and the drain-source voltage V DS (refer to Figure 1B ) is applied between the drain node D and the source node S, and generates an electric field |E| between the gate region 14 and the drain region 15. Figure 2 The illustration is based on the assumptions that (1) the transistor device is an n-type transistor device, that is, the drift region 11 is an n-type region and the compensation region 12 is a p-type region; (2) each of the drift region 11 and the compensation region 12 has a substantially uniform doping dose, that is, the doping dose is substantially the same at each horizontal position of the corresponding region; and (3) the doping is substantially balanced, that is, the total number of n-type dopants in the drift region 11 is substantially equal to the total number of p-type dopants in the compensation region 12.

[0040] exist Figure 2 , curve 301 represents the situation where the doping is exactly balanced, that is, the total number of n-type dopant atoms in the drift region 11 is exactly equal to the total number of p-type dopant atoms in the compensation region 12. In this case, the amplitude of the electric field is substantially constant between the gate region 14 and the drain region 15. Curve 302 represents the situation where the total number of p-type dopant atoms in the compensation region 12 is higher than the total number of n-type dopant atoms in the drift region 13. In this case, the amplitude of the electric field increases toward the drain region 15 and has a maximum value at the boundary of the drain region 15. Curve 303 shows the situation where the total number of n-type dopant atoms in the drift region 11 is higher than the total number of p-type dopant atoms in the compensation region 12. In this case, the electric field has a maximum value close to the gate region 14 and decreases toward the drain region 15.

[0041] Figure 2 The curves 301, 302 and 303 shown in FIG. 3 show the curves 301, 302 and 303 for three different doping situations but for the same drain-source voltage V DS The drain-source voltage V DS Basically it is given by the integral of the electric field (which is equal to Figure 2The voltage blocking capability is given by the integral of the magnitude of the electric field when the magnitude of the electric field reaches the critical value (the area under curve 301-curve 303). The voltage blocking capability of the transistor device implemented according to the doping details below curve 301 is higher than the voltage blocking capability of the transistor device implemented according to the doping details below curve 302 and curve 303. This can be seen from curve 301-curve 303, because when the maximum value of the electric field magnitude is equal to the critical value, the area under curve 301 is larger than the area under curve 302 or curve 303. (Or in other words, at a given drain-source voltage V DS , the maximum value of the electric field according to the curve 301 is lower than the maximum value of the electric field according to each of the curve 302 and the curve 303. )

[0042] Considering the avalanche robustness of transistor devices, Figure 2 Each of the situations shown in is undesirable. When avalanche breakdown occurs, the lateral superjunction transistor device according to one of the curves 301-303 tends to produce a snapback. Figure 3 An example of this is given in .

[0043] Figure 3 shows the drain-source current I DS , which is the voltage between the drain region 15 and the source region 14 depending on the drain-source voltage V DS In this example, when the drain-source voltage V DS Reaching the breakdown voltage V DS_BR (which defines the voltage blocking capability), the drain-source current I DS In addition, the drain-source current I DS Increases and falls below the snapback value I DS_SNAP When the drain-source voltage V DS However, when the drain-source current I DS When the snapback value is reached, the drain-source voltage V DS With the current I DS The drain-source voltage V DS With the current I DS Further increasing the reduced operating state is highly unstable and may cause destruction of the transistor device.

[0044] When avalanche breakdown occurs, charge carrier pairs are generated at the position where the electric field amplitude reaches a critical value in the transistor device. These charge carriers generate other charge carrier pairs by collision ionization. Each carrier pair includes an electron and a hole, wherein, in an n-type transistor device, the hole flows to the source region 14 and the electron flows to the drain region 15. These charge carriers and the fact that the electric field amplitude is reduced at the position where avalanche breakdown begins to occur may cause a shift in the electric field, so that the maximum value appears at another position and causes avalanche breakdown there. In the context of snapback behavior, avalanche breakdown of a transistor device may occur at multiple positions due to this shift in the electric field.

[0045] Therefore, it is desirable to design the lateral superjunction transistor device to avoid snapback or to reduce the snapback value I DS_SNAP to a value outside the current range that may occur when the transistor device is operated in avalanche mode. "Avalanche mode" is an operating mode in which the operation of the transistor device is such that avalanche breakdown occurs. Avalanche mode is not usually designed specifically for the application, but may occur in special circumstances during operation, such as commutation of an inductive load in series with the transistor device, where the avalanche current, i.e., the drain-source current flowing in avalanche mode, is limited by the load.

[0046] Figure 4 The figure shows the magnitude of the electric field in a lateral superjunction transistor device with high avalanche robustness. In the transistor device, in the off state of the transistor device, the maximum value of the magnitude |E| of the electric field appears at a lateral position located between the gate region 14 and the drain region 15 and separated from the gate region 14 and the drain region 15. Figure 4 , x0 represents the lateral position of the boundary between the gate region 14 and the drift region 11 and the compensation region 12, x2 represents the lateral position of the boundary between the drain region 15 and the drift region 11 and the compensation region 12, and x1 represents the lateral position where the maximum value of the electric field occurs. This position x1 is hereinafter referred to as the "maximum position".

[0047] from Figure 4 It can be seen from FIG. 1 that the maximum position x1 is separated from the gate region 14 and the drift region 15. Figure 4 , which can be obtained by implementing the drift region 11 and the compensation region 12 so that the compensation degree C(x) varies along the first lateral direction x so that the compensation degree C(x) changes its sign at the maximum position x1. For illustrative purposes only, it is assumed that the transistor device is an n-type transistor device. In this case, the drift region 11 and the compensation region 12 are implemented so that the compensation degree C(x) is positive between the gate region 14 and the maximum position x with the maximum value, and is negative between the position x1 with the maximum value and the drain region 15. The compensation degree C(x) is given by the following formula:

[0048]

[0049] The compensation areas 12 may be numbered from 1 to n, where D12 i (x) represents the doping amount of the i-th compensation region, and the drift regions 11 can be numbered from 1 to m, where D11 j (x) represents the doping dose of the jth drift region. More specifically, D12 i (x) represents the doping amount of the i-th compensation region 12 at the lateral position x, D11 j (x) represents the doping amount of the j-th drift region 11 at the lateral position x. In addition, n represents the total number of compensation regions 12, and m represents the total number of drift regions 11. Referring to the above, the doping amount of one of the drift region 11 and the compensation region 12 at a specific lateral position x represents the number of dopant atoms included in the corresponding drift region 11 or the corresponding compensation region 12 at the corresponding lateral position x. Thus, the term represents the total number of dopant atoms in the plurality of compensation regions 12 at a given position x, and represents the total number of dopant atoms in the plurality of drift regions 11 at the corresponding lateral position x.

[0050] Figure 4 1 shows a vertical cross-sectional view of the transistor device in a cross-sectional plane parallel to the vertical direction z and the first lateral direction x. i (x) and D12 j (x) represents any one of the drift regions 11 i The doping dose at position x and any one of the compensation regions 12 j Doping dose at position x. The "dopant dose" of one of the drift region and the compensation region is given by the number of dopant atoms per unit area of ​​the respective drift region or compensation region. For illustration purposes, it is assumed that the doping dose at a specific first lateral position x is the same at every point of the device having this first lateral position x, i.e. there is no variation of the doping dose along the second lateral direction y.

[0051] It can be seen from equation (1) that when the total number of dopant atoms in the compensation region 12 at a given lateral position x is equal to the total number of dopant atoms in the drift region 11, the compensation degree C(x) is zero. When the total number of dopant atoms in the compensation region 12 is higher than the total number of dopant atoms in the drift region 11, the compensation degree C(x) is positive. In addition, when the total number of dopant atoms in the compensation region 12 is lower than the total number of dopant atoms in the drift region 11, the compensation degree C(x) is negative.

[0052] refer to Figure 4, the compensation degree C(x) may be substantially constant between the gate region 14 and the maximum position x1, and may be substantially constant between the maximum position x1 and the drain region 15. Figure 4 In the example shown, C1 represents the degree of compensation between the gate region 14 and the maximum position x1, and C2 represents the degree of compensation between the maximum position x1 and the drain region 15. According to one example, C1*(x1-x0) and C2*(x2-x1) have the same amplitude, |C1*(x1-x0)|=|C2*(x2-x1)|. In this case, the transistor device is exactly balanced. That is, the total number of dopant atoms of the first type in the drift region 11 is equal to the total number of dopant atoms of the second type in the compensation region. According to another example, the amplitude of one of C1*(x1-x0) and C2*(x2-x1) is greater than the amplitude of the other of C1*(x1-x0) and C2*(x2-x1), wherein, according to one example, the amplitude of the difference C1*(x1-x0)-C2*(x2-x1) is less than 30%.

[0053] According to one example, the maximum position x1 is closer to the gate region 14 than to the drain region 15. This is equivalent to d3<0.5d2, where d2 is the (shortest) distance between the gate region 14 and the drain region 15, and d3 is the (shortest) distance between the gate region 15 and the maximum position. According to one example, 0.1*d2 <d3<0.4*d2。

[0054] According to an example, Figure 4 The compensation behavior shown is obtained by implementing at least one of the drift region 11 and the compensation region 12 (but not each of the drift regions 11 nor each of the compensation regions 12) such that the doping dose varies along the first lateral direction x. The remaining drift regions 11 and each of the compensation regions 12 may be implemented such that the doping dose is substantially uniform, i.e., substantially unchanged along the first lateral direction x. Figure 5-Figure 7 Explain how to obtain Figure 4 Various examples of compensation behavior are shown. According to one example, "substantially uniform" means that the minimum and maximum doping levels deviate from the average doping level by less than 10%, less than 5%, or even less than 1%.

[0055] According to one example, at least one of the compensation regions has a varying doping dose D12 V (x), so that the doping amount has a first value D12 between the gate region 14 and the maximum position x1 1 , and has a second value D12 between the maximum position x1 and the drain region 15 2 , where the first value D12 1 Higher than D12 2In this example, the remaining compensation region has a uniform doping dose D12 C (x), so that the doping amount is substantially the same at each horizontal position. Figure 5 Medium, D12 C (x) represents the doping dose distribution profile of one of the compensation regions 12 having a uniform doping dose, where D12 3 Indicates a constant doping dose value of uniform doping dose. This constant value D12 3 The constant doping amount D12 is the same for each compensation zone with a uniform doping amount. However, this is only an example. Different compensation zones with a uniform doping amount may also have different constant doping amount values ​​D12. 3 .

[0056] In addition, Figure 5 In the example shown, the drift region 11 has Figure 5 Doping dose profile D11 shown C (x) represents the uniform doping amount. Figure 5 Medium, D11 3 represents a constant doping dose of one of the drift regions with a uniform doping dose. The constant value D11 3 It may be the same for each of the drift regions 11. According to another example, different drift regions have different constant values ​​D11 of the doping dose. 3 .

[0057] according to Figure 6 In another example shown, at least one of the drift regions has a varying doping dose distribution profile D11 V (x), so that the doping amount has a first value D11 between the maximum position x1 and the drain region 15 1 , and has a value lower than the first value D11 between the maximum position x1 and the gate region 14. 1 The second value D11 2 , where the first value D11 1 Higher than the second value D11 2 The remaining drift region 11 has the same Figure 5 Explained uniform doping profile D11 C (x). In addition, in this example, the compensation area 12 has the same Figure 5 Explained uniform doping profile D11 C (x).

[0058] according to Figure 7 In another example shown, at least one of the compensation zones (but not every compensation zone 12) has a Figure 5 Explained changes in doping dose profile D12 V(x), at least one of the drift regions 11 (but not every drift region 11) has a Figure 6 Explanation of the changes in doping dose profile D11 V (x), while the remaining compensation region 12 has a uniform doping dose distribution profile D11 C (x) and the remaining compensation region 12 has a uniform doping dose distribution profile D12 C (x).

[0059] According to an example, in Figures 5 to 7 In the method shown, D12 1 At D12 2 Between 1.1 and 2 times (1.1*D12 2 ≤D12 1 ≤2*D12 2 ), and D11 1 Located at D11 2 Between 1.2 and 2 times (1.1*D11 2 ≤D11 1 ≤2*D11 2 ). According to one example, D11 1 and / or D12 1 At 2E12 cm -2 and 5E12 cm -2 between.

[0060] Furthermore, according to one example, the first semiconductor region and the second semiconductor region having the substantially uniform doping dose distribution profile have substantially the same doping dose, ie, D12 3 =D11 3 According to one example, D12 3 and D11 3 At 1E12 cm -2 and 4E12 cm -2 between.

[0061] With reference to the above, in a transistor device, one or more compensation regions 11 may be implemented with a varying doping dose and the drift region may be implemented with a uniform doping dose, one or more drift regions 12 may be implemented with a varying doping dose and the compensation region may be implemented with a uniform doping dose, or one or more compensation regions 12 and one or more drift regions 11 may be implemented with a varying doping dose. In each case, according to an example, less than 50% of the drift region 11 and less than 50% of the compensation region 12 are implemented with a varying doping dose.

[0062] The following will refer to Figures 8A-8DVarious examples are explained in which at least one drift region 11 or compensation region 12 with a varying doping dose distribution profile is located in a layer stack. Each of these figures schematically shows a layer stack with a plurality of drift regions 11 and a plurality of compensation regions 12, and shows which semiconductor region in the layer stack is implemented with a varying doping dose distribution profile. In these figures, D11 is used V (x) or D12 V (x) indicates a semiconductor region with a varying doping dose distribution profile. The remaining semiconductor regions have a uniform doping dose distribution profile. According to one example, at least one semiconductor region with a varying doping dose is separated from the lowermost semiconductor region and the uppermost semiconductor region of the layer stack. Figures 8A-8D Middle, 11 L represents the lowermost semiconductor region in the layer stack, and 12 U Represents the uppermost semiconductor region in the layer stack.

[0063] Lowermost semiconductor region 11 L is the first semiconductor region, and the uppermost semiconductor region 12 U is the second semiconductor region. However, this is only an example. It is also possible to implement the uppermost semiconductor region as the first semiconductor region and the lowermost semiconductor region as the second semiconductor region.

[0064] exist Fig. 8A In the example shown, one of the compensation regions 12 has a varying doping dose profile and Figure 8B In the examples shown, one of the drift regions has a varying doping dose distribution profile. In each of these examples, there is only one semiconductor region with a varying doping dose distribution profile. However, this is only an example. Fig. 8A In the example shown, more than one compensation region may be implemented with varying doping dose profiles and in Figure 8B In the examples shown, more than one drift region 11 can be implemented with a varying doping dose profile. In each of these examples, the semiconductor region with the varying doping dose is different from the lowermost semiconductor region 11 in the layer stack. L and the uppermost semiconductor region 12 U .

[0065] exist Figure 8C In the example shown, one of the drift regions 11 is implemented with a varying doping dose profile D11 V (x), and one of the compensation regions 12 is implemented with a varying doping dose profile D12 V (x). In this example, the drift region 11 having a varying doping dose distribution profile is adjacent to the compensation region having a varying doping dose distribution profile. However, this is only an example. Fig.8D In another example shown, one or more semiconductor regions having a uniform doping dose distribution profile are located between two regions having a varying doping dose distribution profile. According to one example, the semiconductor region having a varying doping dose distribution profile is different from the uppermost semiconductor region 12 in the layer stack. U and the lower semiconductor region 11 L .

[0066] exist FIG. 8A to FIG. 8C In the example shown, the remaining first semiconductor region and the second semiconductor region, that is, the region not marked with D11 V (x) or D12 V (x) have a substantially uniform doping dose, wherein the doping doses of these regions having the uniform doping dose may be substantially equal. According to one example, each of the remaining first semiconductor regions and second semiconductor regions (except the lowermost region 11 L and the top area 12 U The uppermost region 12 has a uniform doping dose distribution profile and has substantially the same doping dose value. U and the lowest area 11 L It can have a uniform doping dose distribution profile, and its doping dose value is about 50% of the doping dose value of other semiconductor regions with uniform doping dose distribution profile. Optionally or in addition, the semiconductor region adjacent to at least one semiconductor region with a variable doping dose distribution profile can have a uniform doping dose distribution profile, and its doping dose value is lower than the doping dose value of other semiconductor regions (except the uppermost region and the lowermost region) with a uniform doping dose distribution profile. This will be further explained below.

[0067] Figure 4 The compensation degree distribution profile of the entire transistor device is shown. Figures 5 to 7 The transistor device of one of the examples shown has the effect that the compensation degree distribution profile of a particular drift region and compensation region pair has Figure 4 The overall compensation degree distribution profile C(x) is shown in FIG. The particular drift region and compensation region pair includes (a) a variable doping dose distribution profile D12 V Compensation area and uniform doping dose distribution profile D11 C (b) with a variable doping dose profile D11 V Drift region and profile D12 with uniform doping dose distribution C or (c) having a variable doping dose distribution profile D12 V Compensation zone and profile D11 with varying doping dose distribution VThe adjacent drift region includes a uniform doping dose profile D11. C Drift region and profile D12 with uniform doping dose distribution C The other drift regions and compensation region pairs of the compensation regions have a substantially constant compensation degree distribution profile, wherein when the adjacent drift regions and compensation regions have the same doping dose (D11 C =D12 C ), the compensation degree is zero.

[0068] also, Figure 4 The average value of the amplitude of the electric field in each pair of drift region 11 and compensation region 12 is shown. More specifically, at a specific lateral position x, the electric field may vary along the vertical direction z. For example, assume that there is a specific pair of drift region and compensation region in which the drift region and / or the compensation region has a varying doping concentration, and assume that in other pairs of drift region and compensation region the doping dose profile is uniform. In this case, in this specific pair of drift region and compensation region, the electric field has a value such as Figure 4 The form of the overall electric field shown, wherein the electric field in the other pairs is substantially constant. This has the effect that the avalanche breakdown first occurs at the maximum position x1 in this particular pair of drift and compensation regions. Furthermore, by implementing the drift and compensation regions of this particular pair with a step in the compensation distribution profile, the lateral position of the avalanche breakdown is substantially pinned to the maximum position x1. In other words, the maximum value of the electric field is substantially pinned to the maximum position x1 along the first lateral direction. However, at the maximum position x1, the electric field may vary along the vertical direction z.

[0069] Refer to the above, Figure 4 The compensation degree distribution profile shown can be obtained by implementing one of the drift region and the compensation region with a variable doping dose and implementing the other of the drift region and the compensation region with a uniform doping dose in a pair of adjacent drift and compensation regions. The doping dose of the drift region or the compensation region with the uniform doping dose can be the same as the doping dose of the remaining drift and compensation regions, or can be lower, for example, 10% to 50% lower.

[0070] Fig.9A and Fig. 9B One example of a method for manufacturing a transistor device of the type previously explained in this document is basically shown. Fig.9A The method includes forming a plurality of first semiconductor layers 110 and second semiconductor layers 120 such that the first semiconductor layers 110 and second semiconductor layers 120 are alternately arranged on top of the carrier 200 . Fig.9AA layer stack with a plurality of first semiconductor layers 110 and second semiconductor layers 120 is shown after forming these semiconductor layers on top of a carrier 200. Examples for forming these semiconductor layers will be further explained below.

[0071] The method further includes forming a source region 13 , a gate region 14 and a drain region 15 in the layer stack. Fig. 9B A vertical cross-sectional view of the layer stack after forming the source region 13, the gate region 14, and the drain region 15 is shown. Forming each of these regions may include forming trenches extending from the first surface 101 through the layer stack downward to the carrier 200, and introducing dopant atoms into the layer stack via the sidewalls of these trenches to form the corresponding regions, namely the source region 13, the gate region 14, and the drain region 15. In the transistor device, those sections of the first semiconductor layer 110 arranged between the source region 12 and the drain region 15 form the drift region 11, and those sections of the second semiconductor layer 120 arranged between the source region 12 and the drain region 15 form the compensation region 12. Thus, the doping doses of the first semiconductor region 11 and the second semiconductor region 12 are defined by the doping doses of the first semiconductor layer and the second semiconductor layer in the corresponding sections.

[0072] refer to Fig.9A and Fig. 9B An optional third layer 131 may be formed on top of the layer stack. The details of this optional layer will be outlined below.

[0073] Referring to the above, at least some of the drift region 11 and at least some of the compensation region 12 have a uniform doping dose. Thus, at least some of the first semiconductor layer 110 and at least some of the second semiconductor layer 120 are formed to have a uniform doping dose. An example for forming one or more semiconductor layers having a uniform doping dose will be explained below.

[0074] according to Figures 10A-10D In one example shown, the method includes epitaxially growing a semiconductor layer 100 i This semiconductor layer is hereinafter referred to as an epitaxial layer. Fig. 10A The epitaxial layer 100 is shown in i A vertical cross-section of Fig. 10A The epitaxial layer 100 is not shown thereon. i The vector may be Figure 1A and Figure 1B A carrier of the type shown in the figure carries the layer stack with the first region 11 and the second region 12 in the finished device, or the carrier can be a carrier on which the epitaxial layer 100 is grown. i Another epitaxial layer grown previously. Epitaxial layer 100 iIt may be intrinsic or may have a substantial doping concentration of one of the first doping type and the second doping type.

[0075] refer to Fig. 10B and Fig. 10C The method further comprises implanting a first doping type dopant atom into the semiconductor layer 100 i Surface 101 i In the epitaxial layer 100 i The first implantation region 110' is formed at a predefined vertical position of the epitaxial layer 100. i Surface 101 i The implantation region 110' is substantially parallel to the surface 101. i The vertical position of the implanted region 110' depends on the implantation energy, wherein the higher the implantation energy, the closer the surface 101 is to the implanted region 110'. i According to one example, the first type dopant atoms are n-type atoms, and the semiconductor layer 100 i Including single crystal silicon. For example, the n-type dopant atom is a phosphorus (P) atom.

[0076] refer to Fig. 10C The method further comprises applying to the surface 101 i The second implantation region 120' is formed by implanting dopant atoms of the second doping type uniformly in the implantation process. The implantation energy in the implantation process can make the second implantation region 120' be formed at a vertical position different from the vertical position of the first implantation region 110'. Fig. 10B and Fig. 10C In the example shown, the second implant region 120' is formed closer to the surface 101 than the first implant region 110'. i .

[0077] The first implantation region 110' includes first type dopant atoms, and the second implantation region 120' includes second type dopant atoms. In order to activate these dopant atoms, a thermal process is performed. In the thermal process, dopant atoms are incorporated into the epitaxial layer 100. i The implanted dopant atoms are activated in the crystal lattice of the first semiconductor layer 110 so that the first semiconductor layer 110 of the first doping type is formed by the first implantation region 110', and the second semiconductor layer 120 of the second doping type is formed by the second implantation region 120'. The doping amount of the first semiconductor layer 110 is determined by Fig. 10B The implantation dose used in the implantation process for forming the first implantation region 110' is given by . Similarly, the doping dose of the second semiconductor layer 120 is given by Fig. 10C The implantation dose used in the implantation process for forming the second implantation region 120 ′ shown in is given by .

[0078] Figures 10A-10D The method shown can be performed several times to form a plurality of first semiconductor layers 110 and a plurality of second semiconductor layers 120 one above the other. That is, after the second implantation process, the surface 101 can be implanted with a plurality of first semiconductor layers 110 and a plurality of second semiconductor layers 120. i Another epitaxial layer (not shown) is formed on the Fig. 10B and Fig. 10C The method shown forms a first implantation region and a second implantation region in the other semiconductor layer. According to one example, a thermal process is used to activate dopant atoms in each of the implantation regions. That is, several epitaxial layers can be formed one on top of another, the first implantation region and the second implantation region can be formed in each of these epitaxial layers before forming the next one of these epitaxial layers, and a thermal process is performed after forming each of these epitaxial semiconductor layers and after the implantation regions are formed in each of these epitaxial layers. In addition, growing the epitaxial layer can include a thermal process so that growing the epitaxial layer can activate dopant atoms implanted in the previously grown epitaxial layer.

[0079] For illustrative purposes only, Figure 10A-10C In the example shown, in an epitaxial layer 100 i However, this is only an example. According to another example (not shown), only one implantation region is formed in one epitaxial semiconductor layer, and then the next intrinsic semiconductor layer in the intrinsic semiconductor layer is formed. According to another example, in one epitaxial layer 100 i Two or more implantation regions are formed.

[0080] FIG. 11 shows an example of an epitaxial layer in which four implantation regions (two first implantation regions 110' and two second implantation regions 120') are formed. Each of these implantation regions 110', 120' includes Fig. 10B The first implant regions 110' and the second implant regions 120' are formed alternately, so that after the thermal process, two first semiconductor layers 110 and two second semiconductor layers 120 arranged alternately are formed. Fig. 11B The semiconductor 100 is shown after the thermal process. i layer.

[0081] According to another example (not shown), the first semiconductor layer 110 or the second semiconductor layer 120 having a uniform doping dose may be formed by epitaxially growing the semiconductor layer and in-situ doping the semiconductor layer during the epitaxial growth process.

[0082] The following will refer to Figure 12 to Figure 15An example for forming the first semiconductor layer 110 or the second semiconductor layer 120 with a varying dopant dose is explained. Basically, forming the first semiconductor layer 110 or the second semiconductor layer 120 with a varying dopant dose includes an implantation process that selectively implants dopant atoms into the epitaxial layer. "Selective implantation" includes forming an implantation mask atop the epitaxial layer, and implanting dopant atoms into sections of the surface that are not covered by the implantation mask, wherein the implantation mask prevents dopant atoms from being implanted into those sections of the surface that are covered by the implantation mask.

[0083] Fig.12 An example of a mask implantation process for forming a second semiconductor layer with a varying doping dose is shown. Fig. 10C The method of explaining the epitaxial layer 100 i After forming the second implantation region 120' in the embodiment of the present invention, a mask implantation process is performed. However, this is only an example. The mask implantation process may also be performed after performing a blanket implantation to generate the second implantation region 120'.

[0084] refer to Fig.12 , in the intrinsic semiconductor layer 100 i Surface 101 i An implantation mask 400 is formed on the surface, and dopant atoms of the second doping type are implanted into the surface 101 i Injected into the surface 101 i In those sections of the surface 101 that are not covered by the implantation mask 400. According to one example, the implantation mask 400 is placed on the surface 101 i on, so that the dopant atoms are implanted into the segment between the gate region 14 and the expected maximum position x1 in the completed semiconductor device. Implanting the second type of dopant atoms forms another implantation region 120", wherein the dopant atoms of the other implantation region 120" are added to the dopant atoms included in the second implantation region 120'. After a thermal process (not shown), in those segments obtained from the first implantation region 120' and the other implantation region 120", the second semiconductor region 120 has a doping dose given by the implantation dose used to form the implantation region 120' and the implantation dose used to form the other implantation region 120". The second implantation region 120' and the other implantation region 120" can be formed using the same type of dopant atoms, and in addition, the implantation energy can be the same in each of these implantation processes.

[0085] Can be referenced by Fig.12 The first semiconductor layer 110 having a varying doping amount is formed by a method equivalent to the method explained. Fig.13, forming the first semiconductor layer 110 having a varying dopant dose may include forming a first implantation region 110' including dopant atoms of the first doping type by a blanket implantation process and forming another implantation region 110' including dopant atoms of the first doping type by a mask implantation process using an implantation mask 400. The first implantation region 110' may be formed before or after the other implantation region 110'. Reference Fig.13 In this process, the implantation mask 400 is placed on the surface 101 i on, so that the dopant atoms are implanted into those sections which are located between the maximum position and the drain region 15 in the finished device.

[0086] exist Fig.12 and Fig.13 In each of the examples shown, the semiconductor layer with a varying doping dose is formed by a first implantation region 110' or a second implantation region 120' formed by a blanket implantation process. The first semiconductor region 11 or the second semiconductor region 12 formed by the semiconductor layer has a reference Figures 5 to 7 Explanation of doping dose profile D12 V (x) or D11 V (x) The implantation dose of the first implantation region 110' for forming the first semiconductor layer 110 having a varying doping dose and the implantation dose for forming the first semiconductor layer 110 having a uniform doping dose may be equal. In this case, Figure 6 and Figure 7 D11 2 and D11 3 According to another example, the implantation dose for forming the first implantation region 110' of the first semiconductor layer 110 with a varying doping dose is lower than the implantation dose for forming the first implantation region 110' of the first semiconductor layer 110 with a uniform doping dose. In this case, Figure 6 and Figure 7 D11 2 Lower than D11 3 .

[0087] Likewise, the implantation dose of the second implantation region 120' for forming the second semiconductor layer 120 having a varying doping dose may be equal to the implantation dose for forming the second semiconductor layer 120 having a uniform doping dose. In this case, Figure 6 and Figure 7 D12 2 and D12 3 According to another example, the implantation dose of the second implantation region 120' for forming the second semiconductor layer 120 with a varying doping dose is lower than the implantation dose of the second implantation region 120' for forming the second semiconductor layer 120 with a uniform doping dose. In this case, Figure 5 and Figure 7 D12 2 Below D12 3 .

[0088] Fig.14 Another example of a method for forming a second semiconductor layer 120 having a varying doping dose is shown. In this example, a second semiconductor layer 120 having a uniform doping dose has been formed by an epitaxial growth process. H In addition, by referring to Fig.12 Explain the type of implantation process in the second semiconductor layer 120 H The corresponding reference Fig.12 The implantation region 120'' is explained as an implantation region 120''. After forming the implantation region 120'', a thermal process is performed to activate the implanted dopant atoms. The result of the thermal process is the second semiconductor layer 120 having a varying dopant dose.

[0089] Fig.15 Another example of a method for forming a first semiconductor layer 110 having a varying doping dose is shown. In this example, the first semiconductor layer 110 having a uniform doping dose is produced by an epitaxial growth process. H , and in the semiconductor layer 110 through a mask implantation process H The corresponding reference Fig.13 Another implantation region 110 ″ is explained.

[0090] Referring to the above, a layer stack having the first semiconductor region 11 and the second semiconductor region 12 may be formed on top of the carrier 200. According to an example, the carrier 200 includes an electrically insulating material such as glass or oxide.

[0091] according to Fig.16In another example shown, the carrier 200 is a semiconductor substrate having a basic doping of one of a first doping type and a second doping type. According to one example, the carrier 200 has a basic doping of the second doping type, and the gate region 14 and the drain region 15 extend downward to the carrier 200 through the layer stack. In order to prevent a short circuit between the gate region 14 and the drain region 15, a pn junction between the drain region 15 and the gate region 14 is formed in the carrier 200. More specifically, a diode having a first emitter region 42 adjacent to the gate region 14 and a second emitter region 43 adjacent to the drain region 15 is formed in the substrate 200. In addition, the base region 41 of the diode is formed by a section of the carrier 200 having the basic doping concentration of the carrier 200. The first emitter region 42 has the same doping type as the gate region 14, and the second emitter region 43 has the same doping type as the drain region 15. According to one example, the base region has the same doping type as the first emitter region 42. In this case, a pn junction is formed between the base region 41 and the second emitter region 43. According to one example, the doping concentration of the basic doping of the carrier 200 and the doping concentrations of the first and second emitter regions 42, 43 are selected such that the voltage blocking capability of the diode formed between the drain region 15 and the gate region 14 in the carrier 200 is higher than the voltage blocking capability of the transistor device. In this way, avalanche breakdown occurs first in the layer stack separated from the carrier 200.

[0092] according to Fig.17 In one example shown, another transistor device M2 is integrated in the third semiconductor layer 131. According to one example, the other transistor device is an enhancement MOSFET, wherein the drain D2 of the MOSFET is connected to the source region 13 of the lateral super junction transistor device, and the source S2 of the other transistor device M2 is connected to the gate region 14 of the lateral super junction transistor device. The lateral super junction transistor device as a depletion-mode device and the other transistor device M2 as an enhancement-mode device form a common source and common gate circuit, which can be controlled (turned on or off) by applying a driving voltage (gate-source voltage) between the gate node G2 and the source node S2 of the other transistor device M2. The common source and common gate circuit can be operated like a single transistor. The operating state of the common source and common gate circuit is defined by the operating state of the enhancement MOSFET M2, wherein the common source and common gate circuit is based on the driving voltage V received between the second gate node G2 and the second source node S2. GS2 This type of cascode circuit is known and no further explanation is needed in this regard. In addition, another transistor device M2 may be integrated in the third semiconductor layer 131 in a conventional manner.

[0093] According to an example, the third semiconductor layer 131 has a doping of a second doping type (the same doping type as the gate region 14) in a section between the source region 13 and the drain region 15, so that a first pn junction is formed between the drain region 15 and the third layer 131, and a second pn junction is formed between the source region 13 and the third layer 131. These pn junctions are part of two bipolar diodes, a first bipolar diode formed by the gate region 14, the third layer 131 and the first drain region 15, and a second bipolar transistor formed by the gate region 14, the third layer 131 and the first source region 13. In each of these bipolar transistors, the third layer 131 forms a base region. According to an example, the doping concentration of the third layer 131 is such that the voltage blocking capability of the first bipolar diode is equal to or higher than the voltage blocking capability of the transistor device 10.

Claims

1. A transistor arrangement, comprising: a plurality of first semiconductor regions of a first doping type and a plurality of second semiconductor regions of a second doping type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged along the vertical direction of the semiconductor body; a source region adjacent to the plurality of first semiconductor regions; a drain region adjacent to the plurality of second semiconductor regions and arranged to be spaced apart from the source region along a first lateral direction; and a plurality of gate regions, each of the plurality of gate regions being adjacent to at least one of the plurality of second semiconductor regions and arranged between the source region and the drain region, wherein at least one of the first semiconductor regions and the second semiconductor regions has a doping dose that varies along the first lateral direction, and wherein the remaining first semiconductor regions and second semiconductor regions each have a substantially uniform doping dose, wherein the doping dose of at least one of the first semiconductor regions and the second semiconductor regions is such that the doping dose has a substantially constant first value between the gate region and a first position, and a substantially constant second value different from the first value between the first position and the drain region, wherein the first position is closer to the gate region than to the drain region.

2. The transistor arrangement according to claim 1, wherein more than 50% of the first semiconductor regions and more than 50% of the second semiconductor regions have a substantially uniform doping dose.

3. The transistor arrangement according to claim 1, wherein 0.1·d2 < d3 < 0.4·d2, where d2 is the distance between the gate region and the drain region, and d3 is the distance between the gate region and the first position.

4. The transistor arrangement according to claim 1, wherein the maximum value of the first value and the second value is between 1.2 times and 2 times the minimum value of the first value and the second value.

5. The transistor arrangement according to claim 1, wherein the plurality of first semiconductor regions and the plurality of second semiconductor regions include an uppermost semiconductor region and a lowermost semiconductor region, and wherein at least one of the first semiconductor regions and the second semiconductor regions is spaced apart from the uppermost semiconductor region and the lowermost semiconductor region.

6. The transistor arrangement according to claim 1, wherein the plurality of first semiconductor regions and the plurality of second semiconductor regions include contiguous semiconductor regions adjacent to at least one of the first semiconductor regions and the second semiconductor regions, wherein the contiguous semiconductor regions have a uniform doping dose, and the uniform doping dose of the contiguous semiconductor regions is lower than the uniform doping dose of at least another of the first semiconductor regions and the second semiconductor regions spaced apart from at least one of the first semiconductor regions and the second semiconductor regions.

7. The transistor arrangement according to claim 1, wherein the number of first semiconductor regions is equal to the number of second semiconductor regions, and Therein, the number is between 3 and 60.

8. The transistor arrangement according to claim 1, in, A dimension of each of the first semiconductor region and the second semiconductor region along the vertical direction is between 0.5 micrometers and 2 micrometers.

9. The transistor arrangement according to claim 1 , further comprising: include: A transistor device is integrated in the semiconductor body and connected between the source region and the plurality of gate regions.

10. A transistor arrangement, include: A plurality of first semiconductor regions of a first doping type and a plurality of second semiconductor regions of a second doping type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged along a vertical direction of the semiconductor body; a source region adjacent to the plurality of first semiconductor regions; a drain region adjacent to the plurality of second semiconductor regions and arranged to be spaced apart from the source region along a first lateral direction; and a plurality of gate regions, each of the plurality of gate regions being adjacent to at least one of the plurality of second semiconductor regions and being arranged between the source region and the drain region, wherein at least one of the first semiconductor region and the second semiconductor region has a doping amount that varies along the first lateral direction, and The remaining first semiconductor regions and the remaining second semiconductor regions have substantially uniform doping amounts. wherein the doping amount of the at least one of the first semiconductor region and the second semiconductor region is such that the doping amount has a substantially constant first value between the gate region and a first location, and has a substantially constant second value different from the first value between the first location and the drain region, The maximum value of the first value and the second value is between 1.2 times and 2 times the minimum value of the first value and the second value.

11. A transistor arrangement, include: A plurality of first semiconductor regions of a first doping type and a plurality of second semiconductor regions of a second doping type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged along a vertical direction of the semiconductor body; a source region adjacent to the plurality of first semiconductor regions; a drain region adjacent to the plurality of second semiconductor regions and arranged to be spaced apart from the source region along a first lateral direction; and a plurality of gate regions, each of the plurality of gate regions being adjacent to at least one of the plurality of second semiconductor regions and being arranged between the source region and the drain region, wherein at least one of the first semiconductor region and the second semiconductor region has a doping amount that varies along the first lateral direction, and The remaining first semiconductor regions and the remaining second semiconductor regions have substantially uniform doping amounts. wherein the plurality of first semiconductor regions and the plurality of second semiconductor regions include an uppermost semiconductor region and a lowermost semiconductor region, wherein the at least one of the first semiconductor region and the second semiconductor region is separated from the uppermost semiconductor region and the lowermost semiconductor region.

12. A transistor arrangement, include: A plurality of first semiconductor regions of a first doping type and a plurality of second semiconductor regions of a second doping type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged along a vertical direction of the semiconductor body; a source region adjacent to the plurality of first semiconductor regions; a drain region adjacent to the plurality of second semiconductor regions and arranged to be spaced apart from the source region along a first lateral direction; and a plurality of gate regions, each of the plurality of gate regions being adjacent to at least one of the plurality of second semiconductor regions and being arranged between the source region and the drain region, wherein at least one of the first semiconductor region and the second semiconductor region has a doping amount that varies along the first lateral direction, and The remaining first semiconductor regions and the remaining second semiconductor regions have substantially uniform doping amounts. wherein the plurality of first semiconductor regions and the plurality of second semiconductor regions include an adjacent semiconductor region adjacent to the at least one of the first semiconductor region and the second semiconductor region, The adjacent semiconductor region has a uniform doping dose that is lower than a uniform doping dose of at least one other of the first semiconductor region and the second semiconductor region that is separated from the at least one of the first semiconductor region and the second semiconductor region.

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