A limiting amplifier and TIA circuit

Abstract

A limiting amplifier (10) has a first input terminal (11), a second input terminal (12), a first output terminal (13) and a second output terminal (14). The limiting amplifier (10) includes a first inductor L1, a second inductor (L2), a first load (R1), a second load (R2), a first transistor (T1) and a second transistor (T2). The collectors of the first transistor (T1) and the second transistor (T2) are grounded via a current source (15). The first inductor L1 and the second inductor L2 are a pair of differential coupling inductors connected in series with the loads (R1, R2). Thus, the limiting amplifier (10) of this structure has the function of converting a single-ended input signal into a double-ended differential output signal. Moreover, the addition of the differential coupling inductor can reduce the phase difference between the two output signals, so that the swing of the total output signal is closer to the output of a true differential amplifier.

Description

Technical Field

[0001] The present application belongs to the field of optoelectronic communication technology, and in particular relates to a limiting amplifier and a TIA circuit. Background Art

[0002] In optical sensors and fiber-optic communication systems, TIAs (Trans-Impedance Amplifiers) are part of the optical receiver. TIAs are typically used in conjunction with photodiodes, which receive optical signals and convert them into electrical signals. Most electrical signals directly converted from optical signals are relatively weak, so a TIA is needed to amplify the electrical signals converted by the photodiode. Generally speaking, photodiodes convert optical signals into single-ended electrical signals, and TIAs only need to amplify the single-ended electrical signals. However, in fiber-optic communication systems, for very high-speed signals, TIAs must convert the single-ended electrical signals into two-ended differential signals. This increases the signal transmission bandwidth, reduces noise, and facilitates further signal processing.

[0003] The TIA circuit in a typical digital fiber-optic communication system receiver generally includes modules such as a pre-transimpedance amplifier (TIA) circuit and a limiting amplifier circuit. Incident light is converted into photocurrent by a photodiode. The photocurrent then passes through the pre-TIA, converting the single-ended current signal into a single-ended voltage signal. The limiting amplifier's task is to further amplify the small voltage signal output by the pre-TIA to a sufficiently large amplitude, enabling the subsequent data decision circuit to function effectively and reduce bit error rates. Furthermore, the CML (Current-Mode Logic) limiting amplifier also serves as a single-ended to dual-ended differential signal converter. Through a DC feedback loop, the single-ended voltage signal is converted into a dual-ended differential voltage signal by the CML limiting amplifier. The schematic diagram of a traditional CML limiting amplifier is shown in Figure 1(a). A CML limiting amplifier has two input terminals, one of which is driven by a single-ended RF signal, while the other is fixed to a reference voltage DC. For low- and intermediate-frequency signals, the two output terminals produce a pair of well-defined differential output signals, Vp and Vn. However, as frequency increases, the phase and amplitude differences between the two differential output signals, Vp and Vn, become increasingly significant for high-frequency signals. As shown in Figure 1(b), this results in a smaller swing, Vtotal, of the differential output (Vtotal is the vector difference between Vp and Vn), which in turn reduces the output eye opening and increases jitter. This phenomenon is caused by the signal paths of the two differential signals: one signal, RF, runs from the base of transistor T1 to its collector, while the other, DC, runs from the base of transistor T2 to its collector. Transistor T1 operates in a common-emitter circuit, while transistor T2 operates in a common-base circuit.

[0004] Therefore, when a traditional CML limiting amplifier is connected to a high-frequency signal, the phase and amplitude differences between the two differential output signals are obvious, the eye opening is reduced, and the jitter is increased. Summary of the Invention

[0005] In view of this, an embodiment of the present application provides a TIA circuit with an improved limiting amplifier structure, which aims to solve the problem that when a traditional CML limiting amplifier is connected to a high-frequency signal, the phase and amplitude differences between the two differential output signals output are obvious, resulting in a reduced eye opening and increased jitter.

[0006] A first aspect of an embodiment of the present application provides a limiting amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, including:

[0007] a first inductor, wherein a first terminal of the first inductor is connected to a power supply;

[0008] a second inductor, wherein a first end of the second inductor is connected to the power supply, and the second inductor and the first inductor are differentially coupled to each other;

[0009] a first transistor, wherein the base of the first transistor serves as the first input terminal, the collector of the first transistor is connected to the second terminal of the first inductor via a first load, and the collector of the first transistor also serves as the first output terminal; and

[0010] a second transistor, wherein the base of the second transistor serves as the second input terminal, the collector of the second transistor is connected to the second end of the second inductor via a second load, the collector of the second transistor also serves as the second output terminal, and the emitter of the second transistor and the emitter of the first transistor are both grounded via a current source.

[0011] A second aspect of an embodiment of the present application provides a TIA circuit, including:

[0012] Preamplifier;

[0013] The limiting amplifier as described above, wherein the first input terminal of the limiting amplifier is connected to the output terminal of the pre-transimpedance amplifier;

[0014] an output buffer, wherein two input terminals of the output buffer are connected to two output terminals of the limiting amplifier, and two output terminals of the output buffer serve as output terminals of the TIA circuit; and

[0015] A feedback loop, wherein two input terminals of the feedback loop are connected to the two output terminals of the output buffer, and the output terminal of the feedback loop is connected to the second input terminal of the limiting amplifier.

[0016] To improve the imbalance between the two output signals, the aforementioned limiting amplifier incorporates a pair of differential coupled inductors, each connected in series with the load. This reduces the phase difference between the two output signals, bringing the total output signal swing closer to that of a true differential amplifier. This increases the output eye opening and reduces jitter. By properly selecting the time constant, the addition of the differential inductors can also increase the limiting amplifier's -3dB bandwidth. Furthermore, because the two output signals more closely resemble true differential signals, the addition of the inductors improves the limiting amplifier's common-mode rejection ratio (CMRR), suppressing AC current noise superimposed on the power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] FIG1( a ) is a schematic diagram of the circuit structure of a conventional limiting amplifier;

[0019] Figure 1(b) is a vector diagram of two differential output signals of a conventional limiting amplifier;

[0020] FIG2( a ) is a schematic diagram of the circuit structure of a limiting amplifier provided in an embodiment of the present application;

[0021] FIG2( b ) is a vector diagram of two differential output signals of the limiting amplifier shown in FIG2( a );

[0022] Figure 3 A schematic diagram of the structure of a TIA circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0024] 2( a ), the limiting amplifier 10 provided in the embodiment of the present application has a first input terminal 11, a second input terminal 12, a first output terminal 13, and a second output terminal 14. The limiting amplifier 10 includes a first inductor L1, a second inductor L2, a first load R1, a second load R2, a first transistor T1, and a second transistor T2.

[0025] A first terminal of the first inductor L1 is connected to a power supply Vcc; a first terminal of the second inductor L2 is connected to the power supply Vcc, and the second inductor L2 and the first inductor L1 are differentially coupled to each other; the base of the first transistor T1 serves as a first input terminal 11 of the limiting amplifier 10, the collector of the first transistor T1 is connected to the second terminal of the first inductor L1 via a first load R1, and the collector of the first transistor T1 also serves as a first output terminal 13 of the limiting amplifier 10; the base of the second transistor T2 serves as a second input terminal 12 of the limiting amplifier 10, the collector of the second transistor T2 is connected to the second terminal of the second inductor L2 via a second load R2, and the collector of the second transistor T2 also serves as a second output terminal 14 of the limiting amplifier 10, and the emitter of the second transistor T2 and the emitter of the first transistor T1 are both grounded via a current source 15.

[0026] In some embodiments, the second end of the first inductor L1 is a terminal with the same name; the first end of the second inductor L2 is a terminal with the same name; in other embodiments, the first end of the first inductor L1 may be a terminal with the same name; the second end of the second inductor L2 may be a terminal with the same name. Optionally, the first load R1 and the second load R2 are circuits composed of at least one of a resistor, a capacitor, and an inductor. In this embodiment, the first load R1 and the second load R2 are one or more resistors connected in series and in parallel. In other embodiments, the first load R1 and the second load R2 may be inductors / capacitors connected in series and in parallel, etc. The first input terminal 11 of the limiting amplifier 10 is a non-inverting input terminal, the second input terminal 12 is a reverse input terminal, the first output terminal 13 is a non-inverting (positive) output terminal, and the second output terminal 14 is a reverse (negative) input terminal.

[0027] Optionally, the first transistor T1 and the second transistor T2 are both NPN transistors. In other embodiments, the first transistor T1 and the second transistor T2 may be PNP transistors or N-channel MOS transistors.

[0028] The limiting amplifier 10 described above is generally a CML limiting amplifier, which incorporates a pair of differentially coupled inductors L1 and L2 connected in series with a first load R1 and a second load R2, respectively. The addition of the differentially coupled inductors can reduce the phase difference between the two differential output signals Vp and Vn, so that the total output signal swing Vtotal (Vtotal is the vector difference between Vp and Vn) is closer to the output of a true differential amplifier (as shown in FIG2(b)). This increases the opening of the output eye diagram and reduces jitter. Furthermore, by appropriately selecting the time constant τ = L / R, the addition of the differentially coupled inductors can also increase the 3-dB bandwidth of the limiting amplifier 10. Furthermore, after adding the differentially coupled inductors, because the two differential output signals Vp and Vn are closer to true differential signals, the common mode rejection ratio (CMRR) of the limiting amplifier 10 is improved, and the AC current noise superimposed on the power supply Vcc is also suppressed.

[0029] Please refer to Figure 2(a) and Figure 3 The embodiment of the present application further provides a TIA circuit, which includes a pre-transimpedance amplifier 20, the above-mentioned limiting amplifier 10, an output buffer 30 and a feedback loop 40.

[0030] The input end of the pre-transimpedance amplifier 20 serves as the input end of the TIA circuit, and the first input end 11 of the limiting amplifier 10 is connected to the output end of the pre-transimpedance amplifier 20; the two input ends of the output buffer 30 are connected to the two output ends of the limiting amplifier 10, and the two output ends of the output buffer 30 serve as the output ends of the TIA circuit; the two input ends of the feedback loop 40 are connected to the two output ends of the output buffer 30, and the output end of the feedback loop 40 is connected to the second input end 12 of the limiting amplifier 10.

[0031] In optical sensors and fiber-optic communication systems, the input of the pre-transimpedance amplifier 20 is generally connected to the anode of the photodiode D1, and the cathode of the photodiode D1 is connected to the supply voltage VPD. Incident light is converted into a photocurrent by the photodiode D1. The photocurrent then passes through the pre-transimpedance amplifier 20, converting the single-ended current signal into a single-ended voltage signal. The limiting amplifier 10 then converts the single-ended voltage signal into a two-terminal voltage differential signal, which is then input into the output buffer 30. Optionally, both the limiting amplifier 10 and the output buffer 30 are CML limiting amplifiers and output buffers.

[0032] In some embodiments, the TIA circuit further includes a first differential load resistor R3 and a second differential load resistor R4, which are respectively connected between the two output terminals of the output buffer 30 and the power supply Vcc1. The first differential load resistor R3 and the second differential load resistor R4 also serve as load resistors at the output terminal of the entire circuit.

[0033] In some embodiments, the feedback loop 40 includes an operational amplifier 41, wherein the two input terminals of the operational amplifier 41 are respectively connected to the two output terminals of the output buffer 30, and the output terminal of the operational amplifier 41 is connected to the second input terminal 12 of the limiting amplifier 10. Optionally, the two input terminals of the operational amplifier 41 are respectively connected to the two output terminals of the output buffer 30 via current-limiting resistors R5 and R6, and the two input terminals of the operational amplifier 41 are directly connected to a filter capacitor C1.

[0034] Optionally, the inverting input of the pre-transimpedance amplifier 20 is connected to the anode of the photodiode D1 , the non-inverting input of the operational amplifier 41 is connected to the non-inverting output of the output buffer 30 , and the inverting input of the operational amplifier 41 is connected to the inverting output of the output buffer 30 .

[0035] Various embodiments are described herein for various devices, systems and / or methods. Many specific details are set forth to provide a thorough understanding of the overall structure, function, manufacture, and use of the embodiments as described in the specification and shown in the drawings. However, those skilled in the art will understand that the embodiments may be implemented without such specific details. In other examples, well-known operations, parts, and elements are described in detail so as not to obscure the embodiments in the specification. Those skilled in the art will understand that the embodiments described herein and shown are non-limiting examples, and therefore it will be appreciated that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the embodiments.

[0036] References throughout this specification to "various embodiments," "in an embodiment," "one embodiment," or "an embodiment," etc., mean that a particular feature, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Thus, the appearance of the phrases "in various embodiments," "in some embodiments," "in one embodiment," or "in an embodiment," etc., in appropriate places throughout this specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any appropriate manner in one or more embodiments. Thus, particular features, structures, or characteristics shown or described with respect to one embodiment may be combined in whole or in part with features, structures, or characteristics of one or more other embodiments without assuming that such a combination is not illogical or non-functionally limiting. Any directional references (e.g., plus, minus, upper, lower, upward, downward, left, right, leftward, rightward, top, bottom, above, below, vertical, horizontal, clockwise, and counterclockwise) are used for identification purposes to assist the reader in understanding the present disclosure and do not create limitations, particularly with respect to the location, orientation, or use of the embodiments.

[0037] Although certain embodiments have been described above in a certain degree of detail, those skilled in the art may make many changes to the disclosed embodiments without departing from the scope of the present disclosure. Connection references (e.g., attachment, coupling, connection, etc.) should be interpreted broadly and may include intermediate members between the connections of elements and relative motion between elements. Therefore, a connection reference does not necessarily imply that two elements are directly connected / coupled and are in a fixed relationship with each other. The use of "e.g." throughout the specification should be interpreted broadly and for providing non-limiting examples of embodiments of the present disclosure, and the present disclosure is not limited to such examples. It is intended that all matters included in the above description or shown in the accompanying drawings should be interpreted as being merely illustrative and not restrictive. Changes in details or structure may be made without departing from the present disclosure.

Claims

1. A TIA circuit, characterized in that: include: Preamplifier; a limiting amplifier, wherein a first input terminal of the limiting amplifier is connected to an output terminal of the pre-transimpedance amplifier; an output buffer, wherein two input terminals of the output buffer are connected to two output terminals of the limiting amplifier, and two output terminals of the output buffer serve as output terminals of the TIA circuit; and a feedback loop, wherein two input terminals of the feedback loop are connected to the two output terminals of the output buffer, and an output terminal of the feedback loop is connected to the second input terminal of the limiting amplifier; The limiting amplifier has a first input terminal, a second input terminal, a first output terminal and a second output terminal, and the limiting amplifier includes: a first inductor, wherein a first terminal of the first inductor is connected to a power supply; a second inductor, wherein a first end of the second inductor is connected to the power supply, the second inductor and the first inductor are differentially coupled to each other, the second end of the first inductor being a common-name terminal and the first end of the second inductor being a common-name terminal; or the first end of the first inductor being a common-name terminal and the second end of the second inductor being a common-name terminal; and the second inductor is used to reduce the phase difference between the two output signals so that the swing of the total output signal approaches that of a true differential amplifier. The differentially coupled inductor increases the -3dB bandwidth of the limiting amplifier and improves the common-mode rejection ratio, thereby suppressing AC current noise superimposed on the power supply. a first transistor, wherein the base of the first transistor serves as the first input terminal, the collector of the first transistor is connected to the second terminal of the first inductor via a first load, and the collector of the first transistor also serves as the first output terminal; and a second transistor, wherein the base of the second transistor serves as the second input terminal, the collector of the second transistor is connected to the second end of the second inductor via a second load, the collector of the second transistor also serves as the second output terminal, and the emitter of the second transistor and the emitter of the first transistor are both grounded via a current source.

2. The TIA circuit according to claim 1, wherein: The first load and the second load are circuits composed of at least one of a resistor, a capacitor, and an inductor.

3. The TIA circuit according to claim 1, wherein: The first input terminal is a non-inverting input terminal, and the second input terminal is an inverting input terminal.

4. The TIA circuit according to claim 1, wherein: The first transistor and the second transistor are both NPN type.

5. The TIA circuit according to any one of claims 1 to 4, wherein: The device further comprises a first differential load resistor and a second differential load resistor, wherein the first differential load resistor and the second differential load resistor are respectively connected between the two output terminals of the output buffer and a power supply.

6. The TIA circuit according to claim 5, wherein: The feedback loop includes an operational amplifier, wherein two input terminals of the operational amplifier are respectively connected to two output terminals of the output buffer, and the output terminal of the operational amplifier is connected to the second input terminal of the limiting amplifier.

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