Inter-cluster communication of real-time register values

Abstract

Embodiments of apparatuses, methods, and systems for inter-cluster communication of real-time register values are described. In one embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which values generated by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters are stored. The cache memory is separate from the system memory hierarchy and the register file of the processor.

Description

[0001] The field of the invention generally relates to computer architectures. Background Art

[0002] Processors in a computer or other information processing system may be implemented with a cluster microarchitecture, in which resources used in one or more stages of a pipeline are partitioned into separate clusters. In such a microarchitecture, an instruction executed by one cluster may depend on a register value produced by another instruction to be executed by another cluster. In this case, the former instruction may be referred to as a consumer, the latter instruction may be referred to as a producer, and the register value may be referred to as a live register value, as it is used or alive in the processor and affects the result of subsequent operations (arithmetic and memory). In contrast, an invalid register value does not affect any subsequent operations. Communication between clusters, such as communication of a live register value from a producer in one cluster to a consumer in a different cluster, may be referred to as inter-cluster communication. Brief Description of the Drawings

[0003] In the drawings, the invention is illustrated by way of example and not limitation, where like reference numerals indicate like elements and in which:

[0004] Figure 1 is a block diagram of a processor showing a microarchitecture with clusters;

[0005] Figure 2 is a block diagram of a processor showing a microarchitecture with clusters and a live cache according to an embodiment of the invention;

[0006] Figure 3 is a flowchart of a method for using a live cache according to an embodiment of the invention;

[0007] Figure 4A is a block diagram of an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the invention;

[0008] Figure 4B is an exemplary block diagram of an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core included in a processor according to an embodiment of the invention;

[0009] Figure 5 is a block diagram of a processor according to an embodiment of the invention, which may have multiple cores, may have an integrated memory controller, and may have integrated graphics;

[0010] Figure 6 is a block diagram of a system according to an embodiment of the invention;

[0011] Figure 7 is a block diagram of a first more specific exemplary system according to an embodiment of the present invention;

[0012] Figure 8 is a block diagram of a second more specific exemplary system according to an embodiment of the present invention; and

[0013] Figure 9 is a block diagram of a SoC according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] In the following description, numerous specific details such as component and system configurations may be set forth in order to provide a more thorough understanding of the present invention. However, those skilled in the art will understand that the present invention may be practiced without such specific details. Additionally, some well-known structures, circuits, and other features are not shown in detail to avoid unnecessarily obscuring the present invention.

[0015] References to "one embodiment", "an embodiment", "example embodiment", "various embodiments", etc. indicate that embodiments of the present invention so described may include a particular feature, structure, or characteristic, but more than one embodiment may and not every embodiment must include the feature, structure, or characteristic. Some embodiments may have some or all of the features described in other embodiments or may not have the features described in other embodiments. Additionally, such phrases do not necessarily refer to the same embodiment. When a particular feature, structure, or characteristic is described in connection with an embodiment, it is considered that such feature, structure, or characteristic may be implemented in connection with other embodiments whether or not explicitly described, within the knowledge of those skilled in the art.

[0016] As used in this specification and the claims, unless otherwise specified, the use of the ordinal adjectives "first", "second", "third", etc. to describe an element only indicates a particular instance of the element or different instances of similar elements referred to, and does not imply that the elements so described must be in a particular order in time, space, rank, or any other manner.

[0017] In addition, terms such as "bit", "flag", "field", "entry", "indicator", etc. can be used to describe any type or content of a storage location in a register, table, database, or other data structure implemented either in hardware or software, but do not imply limiting embodiments of the present invention to any particular type of storage location or the number of bits or other elements within any particular storage location. The term "clear" can be used to indicate storing or otherwise causing a logical value of 0 to be stored in a storage location, and the term "set" can be used to indicate storing or otherwise causing a logical value of 1, all 1s, or some other specified value to be stored in a storage location; however, these terms do not imply limiting embodiments of the present invention to any particular logical convention, as any logical convention can be used within embodiments of the present invention.

[0018] In addition, as used in the description of embodiments of the present invention, the " / " character between terms can indicate that an embodiment can include the first term and / or the second term, or be implemented using, leveraging, and / or in accordance with the first term and / or the second term (and / or any other additional terms).

[0019] Embodiments of the present invention provide techniques for inter-cluster communication of real-time register values. Based on the complexity, capabilities, and / or performance of other inter-cluster communication techniques, such as register renaming, broadcast of producer values, and insertion of register copy operations, the use of embodiments may desirably and / or preferably reduce the latency of inter-cluster communication. The use of embodiments can provide a smaller physical register file size and a lower complexity of register renaming.

[0020] Figure 1 is a block diagram showing a processor 100 having a cluster microarchitecture that includes a front end 101 and execution clusters 102, 103, 104, 105, and 106. Each of the execution clusters 102, 103, 104, and 105 can be configured to execute integer instructions, and the execution cluster 106 can be configured to execute floating-point and / or vector (VEX) instructions. As Figure 1 shown, the processor 100 depicts one possible configuration of a cluster microarchitecture having four clusters. Many other configurations of cluster microarchitectures having any number of clusters and any number of elements within each cluster are possible. A real-time cache according to embodiments of the present invention can be included in any one of these different cluster microarchitectures.

[0021] The front end 101 includes a Next Instruction Pointer (NIP) 110, which is coupled to a Branch Prediction Unit (BPU) 112, and the Branch Prediction Unit is coupled to fetch pipelines 122 and 124. The fetch pipeline 122 includes a Decoded Stream Buffer (DSB) 122A and a Micro Instruction Translation Engine (MITE) 122B, the fetch pipeline 124 includes a DSB 124A and a MITE 124B, and both the fetch pipeline 122 and the fetch pipeline 124 are coupled to a Microsequencer (MS) 120. The fetch pipeline 122 is also coupled to a scan unit 132 for real-time detection of instructions from the fetch pipeline 122 and instruction block formation, and the fetch pipeline 124 is further coupled to a scan unit 134 for real-time detection of instructions from the fetch pipeline 124 and instruction block formation. The scan unit 122 is coupled to Instruction Decode Queues (IDQ) 142 and 143, and the scan unit 124 is coupled to IDQ 144 and IDQ 145.

[0022] The front end 101 can fetch, scan, and decode instructions and generate as output one or more micro-operations, microcode entry points, micro-instructions, other instructions, or other control signals decoded from the original instructions, or otherwise reflecting or derived from the original instructions. Various different mechanisms can be used to implement the decoding. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, Programmable Logic Arrays (PLAs), Microcode Read-Only Memories (ROMs), etc.

[0023] The IDQs 142, 143, 144, and 145 are respectively coupled to dispatchers 152, 153, 154, and 155, and each of the dispatchers 152, 153, 154, and 155 can include a Register Alias Table (RAT) and / or a Reorder Buffer (ROB). The dispatcher 152 is coupled to a Reservation Station (RS) / Physical Register File (PRF) 162, the dispatcher 153 is coupled to an RS / PRF 163 and a VEX RS / PRF 166, the dispatcher 154 is coupled to an RS / PRF 164 and a VEX RS / PRF 166, and the dispatcher 155 is coupled to an RS / PRF 165. The RS / PRF 162 is coupled to an execution stack 172, the RS / PRF 163 is coupled to an execution stack 173, the RS / PRF 164 is coupled to an execution stack 174, the RS / PRF 165 is coupled to an execution stack 175, and the VEX RS / PRF 166 is coupled to an execution stack 176. Each of the execution stacks 172, 173, 174, 175, and 176 is coupled to a memory hierarchy 180, and the memory hierarchy can include one or more levels of cache memory on the same chip as the processor 100.

[0024] In processor 100, known methods for inter-cluster communication of real-time register values can include an allocator 152, 153, 154, or 155 that generates an inter-cluster register request 150, which is implemented by the transfer of an inter-cluster register value 160 from an RS / PRF 162, 163, 164, 165, or 166 to another RS / PRF 162, 163, 164, 165, or 166. According to this method, physical register file entries in a cluster are assigned to real-time values generated in different clusters.

[0025] Figure 2 is a block diagram showing a processor 200 having a cluster microarchitecture and a real-time cache according to an embodiment of the present invention. Figure 3 is a flowchart showing a method 300 for using a real-time cache such as Figure 2 shown. Figures 4 to Figure 9 also show a processor and a system including an embodiment of the present invention, wherein the processors 490, 500, 610, 615, 770, 780, and 910 and the systems 600, 700, 800, and 900 can include Figure 1 any or all of the blocks and / or elements shown in the processor 200 of Figure 2 and 3 operate the blocks and / or elements according to the techniques and / or methods described therein.

[0026] Processor 200 can represent all or a part of a hardware component. The processor includes one or more processors integrated on a single substrate or packaged in a single package. Each processor can include multiple execution threads and / or multiple execution cores in any combination. Each processor represented as processor 200 or represented in processor 200 can be any type of processor, including a general microprocessor (e.g., Core TM processors in the processor family or processors in other processor families of

[0027] In Figure 2 processor 200 has a cluster microarchitecture including a front end 201 and execution clusters 202, 203, 204, 205, and 206. As Figure 2As shown, the processor 200 depicts one possible configuration of a clustered microarchitecture. Many other configurations of a clustered microarchitecture with any number of clusters and any number of elements within each cluster are possible. The real-time cache according to an embodiment of the present invention can be included in any one of these different clustered microarchitectures.

[0028] The front end 201 includes a NIP 210, which is coupled to a BPU 212, and the BPU 212 is coupled to fetch pipelines 222 and 224. The fetch pipeline 222 includes a DSB 222A and a MITE 222B, the fetch pipeline 224 includes a DSB 224A and a MITE 224B, and both the fetch pipeline 222 and the fetch pipeline 224 are coupled to an MS 220. The fetch pipeline 222 is also coupled to a scan unit 232 for real-time detection of instructions from the fetch pipeline 222 and instruction block formation, and the fetch pipeline 224 is also coupled to a scan unit 234 for real-time detection of instructions from the fetch pipeline 224 and instruction block formation. The scan unit 222 is coupled to IDQs 242 and 243, and the scan unit 224 is connected to IDQs 244 and 245.

[0029] The front end 101 can fetch, scan, and decode instructions and generate, as output, one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals decoded from the original instructions, or otherwise reflecting or derived from the original instructions. Various different mechanisms can be used to implement the decoding. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc.

[0030] The IDQs 242, 243, 244, and 245 are respectively coupled to distributors 252, 253, 254, and 255, and each of the distributors 252, 253, 254, and 255 can include a RAT and / or a ROB. The distributor 252 is coupled to an RS / PRF 262, the distributor 253 is coupled to an RS / PRF 263 and a VEX RS / PRF 266, the distributor 254 is coupled to an RS / PRF 264 and a VEX RS / PRF 266, and the distributor 255 is coupled to an RS / PRF 265. The RS / PRF 262 is coupled to an execution stack 272, the RS / PRF 263 is coupled to an execution stack 273, the RS / PRF 264 is coupled to an execution stack 274, the RS / PRF 265 is coupled to an execution stack 275, and the VEX RS / PRF 266 is coupled to an execution stack 276. Each of the execution stacks 272, 273, 274, 275, and 276 is coupled to a memory hierarchy 280, which can include one or more levels of cache memory on the same chip as the processor 200.

[0031] In processor 200, a new method for inter-cluster communication of real-time register values according to an embodiment of the present invention may include generating a scan unit 222 or 224 for an inter-cluster register request 250 implemented by an execution stack 272, 273, 273, 274, or 275 that reads real-time values from a local inter-cache (LINC) 290.

[0032] The LINC 290 may be any type of cache memory that provides a separate namespace (e.g., a container for register values that is different from various levels of a physical register file and / or system memory and can be addressed and accessed independently of various levels of the physical register file and / or system memory), and is used to store real-time register values in the namespace. Each LINC entry also stores a ready bit (or other indicator) to indicate that a real-time register value has been generated and stored in the LINC 290. The ready bit may be used as described below. One or more storage structures for real-time register values and ready bits may be physically located in the execution unit of the processor.

[0033] Each LINC may also include a corresponding entry and / or be associated with a corresponding entry, in which a real-time identification (ID) value and one or more semaphore (or other indicator) bits for locking the entry are stored. The real-time ID value may be a unique value formed by a combination of an identifier of an instruction block that generates a real-time register value and an identifier of a logical register in which the real-time register value (in other words, the real-time register) is stored or will be stored. One or more storage structures for real-time register values and ready bits may be physically located in the front-end unit of the processor: for example, a lock bit may be physically located in a lock manager 230 to provide locking of LINC entries during the decode stage of the processor pipeline.

[0034] The real-time values stored in LINC 290 can be locked by the lock manager 230 to avoid premature eviction (before being used by the consumers). Once the producer cluster of the real-time values is known (after the decoding and cluster assignment phases), the consumer instructions will find the LINC entry (if it exists) and lock it. The lock counter is incremented on an inter-cluster register request and decremented when the corresponding consumer instruction is executed. When the lock bit becomes zero, its LINC entry is unlocked and can be replaced at will according to the replacement policy (e.g., least recently used). As an optimization, the inter-cluster request is sent only when the LINC entry for the required real-time register has not yet been allocated in the cache. If the previous instruction has already allocated the LINC entry for the real-time register, the lock counter is incremented but no request is sent. Since the lock is established (speculatively) at decoding, the lock counter is reset in response to a pipeline flush. The pipeline flush also flushes the LINC to maintain the consistency of the register values.

[0035] After locking the LINC entry, an instruction carries the LINC_ID and the instruction execution is blocked until the real-time value is received. When the real-time value is received, the data is written into the cache entry locked for the request and the LINC_ID is used to unblock all the consumers waiting for the input value. Each instruction that reads and executes the value decrements the lock counter of the LINC entry it depends on. The locking mechanism ensures that a valid LINC entry is not evicted until all the consumer instructions for that entry have read the value from the cache.

[0036] The dependency tracker 292 tracks the dependencies of instructions on real-time values and wakes up the instructions when their real-time values have been produced and are ready in the real-time cache. The dependency tracker 292 can be implemented with additional entries in the out-of-order scheduler to track the dependencies on the values stored in LINC by simply extending the scheduler matrix to utilize the existing instruction unblocking mechanism. Thus, it does not add additional hardware for tracking instruction dependencies.

[0037] Figure 3 is a flowchart showing a method 300 for using a real-time cache according to an embodiment of the present invention. For illustrative purposes, the description of method 300 may refer to the elements of the processor 200; however, the method embodiments of the present invention are not limited to these illustrative details.

[0038] In block 310 of method 300, the instruction is decoded. In block 312, it is determined that the source value of the instruction is a real-time value. In block 320, it is determined whether there is an available and unlocked entry in the LINC. If not, method 300 stays at block 320 until an unlocked LINC entry becomes available. If so, method 300 continues in block 322.

[0039] In block 322, the LINC entry is identified. In block 330, it is determined whether the identified LINC entry has been locked. If so, the lock counter is incremented in block 334, and method 300 continues in block 340. If not, in block 332, the LINC entry is locked (e.g., by setting the lock counter), and a real-time request is sent, then method 300 continues in block 340.

[0040] Each of blocks 310 to 334 can be executed during the instruction decoding stage 301 of the processor pipeline.

[0041] In block 340, the instruction scheduler is blocked from scheduling the consumer instruction corresponding to the LINC_ID. In block 342, it is determined (e.g., based on the ready bit corresponding to the LINC_ID) whether the source value has been generated and stored in the LINC entry corresponding to the LINC_ID. If not, method 300 stays at block 342 until the LINC entry until the source value has been generated and stored in the LINC entry corresponding to the LINC_ID. If so, method 300 continues in block 344.

[0042] In block 344, the block on the instruction scheduler for the consumer instruction corresponding to the LINC_ID is removed. In block 350, it is determined whether all other source values of the instruction are ready. If not, method 300 stays at block 350 until all other source values of the instruction are ready. If so, method 300 continues in block 352.

[0043] Each of blocks 340 to 350 can be executed during the instruction scheduling stage 302 of the processor pipeline.

[0044] In block 352, the instruction is issued. In block 360, it is determined whether the execution of the instruction is ready to write back. If not, method 300 stays at block 360 until the execution of the instruction is ready to write back. If so, method 300 continues in block 362. In block 362, the lock counter is decremented, and if decrementing the lock counter causes the lock counter to equal zero, the LINC entry will be unlocked.

[0045] Each of boxes 352 through 362 may execute during the instruction execution stage 303 of the processor pipeline.

[0046] In box 370, the instruction is cancelled.

[0047] Accordingly, embodiments of the present invention allow for earlier generation of inter-cluster register requests in the pipeline (once the consumer instruction has been decoded and the instruction block has been formed such that information about the cluster of the source of the generating instruction is known, rather than after register renaming and allocation), because the instruction does not need to wait for logical-to-physical register renaming. In one embodiment, the live source may be predicted before decoding.

[0048] Furthermore, since no inter-cluster live source registers are allocated in the physical register file, the size of the physical register file does not increase and no additional hardware is added to the renamer to handle additional physical registers. Accordingly, LINC according to embodiments of the present invention may be required because without it, additional physical registers may be required to allocate live sources without increasing register pressure, which complicates the renamer hardware because the renamer must handle more physical registers.

[0049] Exemplary Core Architectures, Processors, and Computer Architectures

[0050] The following figures detail exemplary architectures and systems for implementing the above embodiments.

[0051] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, the implementation of such cores can include: 1) general-purpose in-order cores designed for general computing; 2) high-performance general-purpose out-of-order cores designed for general computing; 3) specialized cores mainly used for graphics and / or scientific (throughput) computing. The implementation of different processors can include: 1) a CPU that includes one or more general-purpose in-order cores for general computing and / or one or more general-purpose out-of-order cores for general computing; 2) a coprocessor that includes one or more specialized cores mainly used for graphics and / or scientific (throughput). Such different processors result in different computer system architectures, which can include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor on a separate die located in the same package as the CPU; 3) a coprocessor on the same die as the CPU (in this case, such a coprocessor is sometimes referred to as specialized logic, such as integrated graphics and / or scientific (throughput) logic, or a specialized core); and 4) a system-on-a-chip that can include the described CPU (sometimes referred to as an application core or application processor), the above coprocessor, and additional functions on the same die. Exemplary core architectures are described next, followed by exemplary processor and computer architectures.

[0052] Exemplary core architectures

[0053] Block diagrams of in-order and out-of-order cores

[0054] Figure 4A is a block diagram showing an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present invention. Figure 4B is a block diagram showing an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core included in a processor according to an embodiment of the present invention. Figure 4A - Figure 4B The solid boxes in show the in-order pipeline and in-order core, while the optionally added dashed boxes show the register renaming, out-of-order issue / execution pipeline and core. Assuming that the in-order aspects are a subset of the out-of-order aspects, the out-of-order aspects will be described.

[0055] In Figure 4A the processor pipeline 400 includes a fetch stage 402, a length decoding stage 404, a decoding stage 406, an allocation stage 408, a renaming stage 410, a scheduling (also referred to as issue or dispatch) stage 412, a register read / memory read stage 414, an execution stage 416, a write-back / memory write stage 418, an exception handling stage 422, and a commit stage 424.

[0056] Figure 4BA processor core 490 is shown, which includes a front-end unit 430 coupled to an execution engine unit 450, and both are coupled to a memory unit 470. The core 490 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another alternative, the core 490 can be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0057] The front-end unit 430 includes a branch prediction unit 432, which is coupled to an instruction cache unit 434, which is coupled to an instruction translation lookaside buffer (TLB) 436, which is coupled to an instruction fetch unit 438, and the instruction fetch unit 438 is coupled to a decoding unit 440. The decoding unit 440 (or decoder) can decode instructions and produce, as output, one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from or otherwise reflect or are derived from the original instructions. Various different mechanisms can be used to implement the decoding unit 440. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc. In one embodiment, the core 490 includes a microcode ROM or other medium for storing microcode for certain macro instructions (e.g., in the decoding unit 440 or within the front-end unit 430). The decoding unit 440 is coupled to a rename / allocator unit 452 in the execution engine unit 450.

[0058] The execution engine unit 450 includes a rename / allocator unit 452 coupled to an issue unit 454 and a set of one or more scheduler units 456. The scheduler units 456 represent any number of different schedulers, including reservation stations, a central instruction window, and the like. The scheduler units 456 are coupled to a physical register file unit 458. Each physical register file unit 458 represents one or more physical register files, and different physical register files store one or more different data types, such as scalar integer, scalar floating point, compressed integer, compressed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and the like. In one embodiment, the physical register file unit 458 includes a vector register unit, a write mask register unit, and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general-purpose registers. The physical register file unit 458 is overlapped by the issue unit 454 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using a reorder buffer and an issue register file; using a future file, a history buffer, and an issue register file; using a register map and a register pool; and so on). The issue unit 454 and the physical register file unit 458 are coupled to an execution cluster 460. The execution cluster 460 includes a set of one or more execution units 462 and a set of one or more memory access units 464. The execution units 462 may perform various operations (e.g., shift, add, subtract, multiply) on various types of data (e.g., scalar floating point, compressed integer, compressed floating point, vector integer, vector floating point). Although some embodiments may include multiple execution units dedicated to specific functions or a set of functions, other embodiments may include only one execution unit or multiple execution units that perform all functions. The scheduler units 456, the physical register file unit 458, and the execution cluster 460 are shown as potentially being multiple because certain embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / compressed integer / compressed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline - each having its own scheduler unit, physical register file unit, and / or execution cluster; in the case of a separate memory access pipeline, some embodiments in which only the execution cluster of that pipeline has a memory access unit 464). It should also be understood that in the case of using separate pipelines, one or more of these pipelines may be out-of-order issue / execution while the rest are in-order.

[0059] This set of memory access units 464 is coupled to a memory unit 470 that includes a data TLB unit 472, which is coupled to a data cache unit 474 that is coupled to a level 2 (L2) cache unit 476. In an exemplary embodiment, the memory access units 464 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 472 in the memory unit 470. The instruction cache unit 434 is also coupled to the level 2 (L2) cache unit 476 in the memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of cache and ultimately to main memory.

[0060] For example, an exemplary register renaming, out-of-order issue / execution core architecture may implement pipeline 400 as follows: 1) Instruction fetch 438 performs the fetch and length decoding stages 402 and 404; 2) Decode unit 440 performs the decode stage 406; 3) Rename / allocator unit 452 performs the allocation stage 408 and the rename stage 410; 4) Scheduler unit 456 performs the schedule stage 412; 5) Physical register file unit 458 and memory unit 470 perform the register read / memory read stage 414; Execution cluster 460 implements the execution stage 416; 6) Memory unit 470 and physical register file unit 458 perform the writeback / memory write stage 418; 7) Various units may be involved in the exception handling stage 422; and 8) Retirement unit 454 and physical register file unit 458 perform the commit stage 424.

[0061] Core 490 may support one or more instruction sets including the instructions described herein (e.g., the x86 instruction set (with certain extensions added to more recent versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set of ARM Holdings of Sunnyvale, CA (with optional additional extensions such as NEON)). In one embodiment, core 490 includes logic to support compressed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used in many multimedia applications to be performed using compressed data.

[0062] It should be understood that the core may support multithreading (executing two or more sets of parallel operations or threads) and may be implemented in a variety of ways, including time-sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each thread of the physical core's simultaneous multithreading), or a combination thereof (e.g., such as time-sliced fetching and decoding followed by simultaneous multithreading as in hyperthreading technology).

[0063] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiments of the processor also include separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, alternative embodiments can have a single internal cache for instructions and data, such as a level 1 (L1) internal cache, or multiple levels of internal caches. In some embodiments, the system can include a combination of an internal cache and an external cache outside the core and / or the processor. Alternatively, all caches can be outside the core and / or the processor.

[0064] Figure 5 is a block diagram of a processor 500 according to an embodiment of the present invention, which processor 500 can have more than one core, can have an integrated memory controller, and can have integrated graphics. Figure 5 The solid boxes in show a processor 500 having a single core 502A, a system agent 510, and a group of one or more bus controller units 516, while the optionally added dashed boxes show an alternative processor 500 having multiple cores 502A-N, a group of one or more integrated memory controller units 514 in the system agent unit 510, and dedicated logic 508.

[0065] Thus, different implementations of the processor 500 can include: 1) a CPU with dedicated logic 508 that is integrated graphics and / or scientific (throughput) logic (which can include one or more cores), and the cores 502A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, a combination of both); 2) a coprocessor with cores 502A-N that are a large number of dedicated cores mainly for graphics and / or scientific (throughput); 3) a coprocessor with cores 502A-N that are a large number of general-purpose in-order cores. Thus, the processor 500 can be a general-purpose processor, a coprocessor, or a special-purpose processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor can be implemented on one or more chips. The processor 500 can be part of one or more substrates using any of a variety of processing technologies, such as BiCMOS, CMOS, or NMOS, and / or can be implemented on one or more of such substrates.

[0066] The memory hierarchy includes one or more levels of cache within the core, a group of one or more shared cache units 506, and external memory (not shown) coupled to the group of integrated memory controller units 514. The group of shared cache units 506 may include one or more intermediate levels of cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, last level cache (LLC), and / or combinations thereof. Although in one embodiment, the ring-based interconnect unit 512 interconnects the integrated graphics logic 508 (the integrated graphics logic 508 is exemplary dedicated logic and is also referred to herein as dedicated logic), the group of shared cache units 506, and the system agent unit 510 / integrated memory controller units 514, alternative embodiments may use any number of well-known techniques to interconnect such units. In one embodiment, coherence is maintained between one or more cache units 506 and the cores 502-A-N.

[0067] In some embodiments, one or more of the cores 502A-N are capable of multithreading. The system agent 510 includes those components that coordinate and operate the cores 502A-N. The system agent unit 510 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or include the logic and components required to regulate the power states of the cores 502A-N and the integrated graphics logic 508. The display unit is used to drive one or more externally connected displays.

[0068] In terms of the architecture instruction set, the cores 502A-N may be homogeneous or heterogeneous; that is, two or more of the cores 502A-N may be capable of executing the same instruction set, while others may only be capable of executing a subset of the instruction set or a different instruction set.

[0069] Exemplary computer architecture

[0070] Figures 6 - 9 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art are also applicable to laptop computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cell phones, portable media players, handheld devices, and various other electronic devices. Generally, various systems or electronic devices capable of incorporating the processors and / or other execution logic disclosed herein are generally applicable.

[0071] Now refer to Figure 6, which shows a block diagram of a system 600 according to an embodiment of the present invention. The system 600 may include one or more processors 610, 615, and the processors 610, 615 are coupled to a controller hub 620. In one embodiment, the controller hub 620 includes a Graphics Memory Controller Hub (GMCH) 690 and an Input / Output Hub (IOH) 650 (which may be on separate chips); the GMCH 690 includes a memory and a graphics controller, and the memory 640 and the coprocessor 645 are coupled to the memory and the graphics controller; the IOH 650 couples input / output (I / O) devices 660 to the GMCH 690. Alternatively, one or both of the memory and the graphics controller are integrated within the processor (as described herein), the memory 640 and the coprocessor 645 are directly coupled to the processor 610, and are coupled to the controller hub 620 having the IOH 650 in a single chip.

[0072] In Figure 6 , the optional nature of the additional processor 615 is indicated by a dashed line. Each of the processors 610, 615 may include one or more processing cores described herein and may be a certain version of the processor 500.

[0073] The memory 640 may be, for example, Dynamic Random Access Memory (DRAM), Phase Change Memory (PCM), or a combination of both. For at least one embodiment, the controller hub 620 communicates with the processors 610, 615 via a multi-branch bus such as a Front Side Bus (FSB), a point-to-point interface (such as QuickPath Interconnect (QPI)), or a similar connection 695.

[0074] In one embodiment, the coprocessor 645 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc. In one embodiment, the controller hub 620 may include an integrated graphics accelerator.

[0075] In terms of the value metric spectrum including architecture, microarchitecture, thermal, power consumption characteristics, etc., there can be many differences between the physical resources 610, 615.

[0076] In one embodiment, the processor 610 executes instructions that control general types of data processing operations. Coprocessor instructions may be embedded in the instructions. The processor 610 identifies these coprocessor instructions as being of the type to be executed by the attached coprocessor 645. Therefore, the processor 610 issues these coprocessor instructions (or control signals representing coprocessor instructions) to the coprocessor 645 on a coprocessor bus or other interconnection. The coprocessor 645 accepts and executes the received coprocessor instructions.

[0077] Referring now to Figure 7 , a block diagram of a first more specific exemplary system 700 in accordance with an embodiment of the present invention is shown. As Figure 7 shown, multi-processor system 700 is a point-to-point interconnect system, and includes a first processor 770 and a second processor 780 coupled via a point-to-point interconnect 750. Each of processors 770 and 780 may be some version of processor 500. In one embodiment of the present invention, processors 770 and 780 are processors 610 and 615 respectively, while the coprocessor 738 is coprocessor 645. In another embodiment, processors 770 and 780 are processor 610 and coprocessor 645 respectively.

[0078] Processors 770 and 780 are shown including integrated memory controller (IMC) units 772 and 782 respectively. Processor 770 also includes point-to-point (P-P) interfaces 776 and 778 as part of its bus controller units; similarly, second processor 780 includes P-P interfaces 786 and 788. Processors 770, 780 may exchange information via P-P interface circuits 778, 788 using a point-to-point (P-P) interface 750. As Figure 7 shown, IMCs 772 and 782 couple the processors to corresponding memories, namely memory 732 and memory 734, which may be part of the main memory locally attached to the corresponding processors.

[0079] Each of processors 770, 780 may exchange information with chipset 790 via separate P-P interfaces 752, 754 using point-to-point interface circuits 776, 794, 786, 798. Chipset 790 may optionally exchange information with coprocessor 738 via a high performance interface 792. In one embodiment, coprocessor 738 is a specialized processor, such as for example a high throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like.

[0080] A shared cache (not shown) may be included in either processor or outside of both processors, but is also connected to the processors via the P-P interconnect, such that if the processors are placed in a low power mode, local cache information of one or both of the processors may be stored in the shared cache.

[0081] Chipset 790 may be coupled to a first bus 716 via an interface 796. In one embodiment, first bus 716 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I / O interconnect bus, but the scope of the present invention is not limited thereto.

[0082] As shown Figure 7 in FIG. 1, various I / O devices 714 are coupled to a first bus 716 together with a bus bridge 718 that couples the first bus 716 to a second bus 720. In one embodiment, one or more additional processors 715, such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processor, are coupled to the first bus 716. In one embodiment, the second bus 720 may be a low pin count (LPC) bus. In one embodiment, various devices including, for example, a keyboard and / or mouse 722, a communication device 727, and a storage unit 728 such as a disk drive or other mass storage device may be coupled to the second bus 720, and the storage unit 728 may include instructions / code and data 730. Additionally, audio I / O 724 may be coupled to the second bus 720. It should be noted that other architectures are possible. For example, instead of Figure 7 a point-to-point architecture, the system may implement a multi-branch bus or other such architectures.

[0083] Now referring to Figure 8 FIG. 2, a block diagram of a second more specific exemplary system 800 in accordance with an embodiment of the present invention is shown. Figure 7 And 8 similar elements in FIGS. 1 Figure 8 and Figure 7 have similar reference numerals, and certain aspects of Figure 8 FIG. 1 are omitted to avoid obscuring other aspects of

[0084] Figure 8 FIG. 2. It is shown that processors 770, 780 may respectively include integrated memories 772 and I / O control logic ("CL") 782. Thus, CL 772, 782 includes integrated memory controller units and includes I / O control logic. Figure 8 It is shown that not only memories 732, 734 are coupled to CL 772, 782, but also I / O devices 814 are coupled to control logic 772, 782. Conventional I / O devices 815 are coupled to a chipset 790.

[0085] Now referring to Figure 9 FIG. 3, a block diagram of a SoC 900 in accordance with an embodiment of the present invention is shown. Figure 5 Similar elements in FIGS. 2 Figure 9In [the figure], the interconnect unit 902 is coupled to an application processor 910, which includes a set of one or more cores 502A-N and a shared cache unit 506. The cores 502A-N include cache units 504A-N; the interconnect unit 902 is also coupled to a system agent unit 510; a bus controller unit 516; an integrated memory controller unit 514; a set of one or more coprocessors 920 that may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 930; a direct memory access (DMA) unit 932; and a display unit 940 for coupling to one or more external displays. In one embodiment, the coprocessor 920 includes a dedicated processor, such as a network or communication processor, a compression engine, a GPGPU, a high throughput MIC processor, an embedded processor, etc.

[0086] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation methods. Embodiments of the present invention may be implemented as a computer program or program code executed on a programmable system, the programmable system including at least one processor, a memory system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one input device.

[0087] Such as Figure 7 Program code, such as the code 730 shown in [the figure], may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0088] The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. If desired, the program code may also be implemented in assembly or machine language. In fact, the scope of the mechanisms described herein is not limited to any particular programming language. In any case, the language may be a compiled language or an interpreted language.

[0089] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium, the instructions representing various logics within a processor, which, when read by the machine, cause the machine to fabricate the logics to perform the techniques described herein. Such a representation, referred to as an "IP core", may be stored on a tangible machine-readable medium and provided to various customers or manufacturing facilities to be loaded into a manufacturing machine or processor for actual fabrication of the logic.

[0090] Such a machine-readable storage medium may include, but is not limited to, non-transitory tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disc read-only memory (CD-ROM), rewritable compact disc (CD-RW), and magneto-optical disks, semiconductor devices such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), magnetic or optical cards, or any other medium suitable for storing electronic instructions.

[0091] Accordingly, embodiments of the present invention also include non-transitory tangible machine-readable media that contain instructions or contain design data, such as a hardware description language (HDL), which defines the structures, circuits, devices, processors, and / or system features described herein. Such embodiments may also be referred to as program products.

[0092] In one embodiment, the processor may include a plurality of execution clusters. The processor also includes a cache memory in which values generated by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters are stored. The cache memory is separated from the system memory hierarchy and the register file of the processor.

[0093] The processor may also include a scan unit to detect that the value will be generated by a first instruction and consumed by a second instruction; allocate an entry in the cache memory for storing the value; and assign an identifier of the entry to the second instruction. The entry may include a first field in which an identifier of a register to which the value will be assigned is stored. The entry may also include a second field in which a ready indicator is stored to indicate that the value has been generated by the first instruction and stored in the entry. The entry may also include a third field in which a lock indicator is stored to indicate that the entry is locked. The processor may also include a lock manager for managing the lock indicator to prevent the entry from being evicted before the value is consumed by the second instruction. The scan unit may also detect that the value will be consumed by a third instruction. Find the entry in the cache memory; and assign an identifier of the entry to the third instruction. The lock manager may also manage the lock indicator to prevent the entry from being evicted before the value is consumed by the third instruction. The processor may also include a dependency tracker to block the scheduling of the second instruction until the ready indicator is set.

[0094] In one embodiment, a method may include: detecting, by a scan unit of a processor, that a first instruction produces a value consumed by a second instruction; allocating an entry in a cache memory of the processor for storing the value, the cache memory being separate from a system memory hierarchy and a register file of the processor; and assigning an identifier of the entry to the second instruction.

[0095] The method may further include incrementing a lock counter in response to assigning the identifier of the entry to the second instruction. The method may further include: detecting, by the scan unit, that a third instruction will also consume the value; looking up the entry in the cache memory; and assigning the identifier of the entry to the third instruction. The method may further include incrementing the lock counter in response to assigning the identifier of the entry to the third instruction. The method may further include preventing the second instruction from being scheduled by a dependency tracker until the value has been produced by the first instruction and stored in the entry. The method may further include executing the first instruction by a first execution cluster of the processor; storing the value in the entry; and setting a ready indicator in the entry. The method may further include: in response to setting the ready indicator, unblocking the second instruction by the dependency tracker; executing the second instruction by a second execution cluster of the processor; and decrementing the lock indicator. The method may further include executing the third instruction; and decrementing the lock indicator. The method may further include determining that the lock counter is equal to zero; and evicting the entry from the cache.

[0096] In one embodiment, an apparatus may include means for performing any of the methods above. In one embodiment, a machine-readable tangible medium may store instructions that, when executed by a machine, cause the machine to perform any of the methods above.

[0097] In one embodiment, a system may include a system memory having a hierarchical memory hierarchy and a processor including a plurality of execution clusters; a first cache memory in the hierarchical memory hierarchy of the system memory; and a second cache memory storing a value produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters, the second cache memory being separate from the first cache memory and the hierarchical memory hierarchy of the system memory.

[0098] The system may further include a physical register file separate from the second cache memory.

Claims

1. A processor for inter-cluster communication of real-time register values, comprising: a plurality of execution clusters; and a cache memory that stores values generated by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters, the cache memory being separated from other memories in the system memory hierarchy and the register file of the processor; the processor further includes a scan unit for: detecting that the value will be generated by a first instruction and consumed by a second instruction; allocating an entry in the cache memory for storing the value; assigning an identifier of the entry to the second instruction; detecting that the value is also consumed by a third instruction; finding the entry in the cache memory; and assigning the identifier of the entry to the third instruction.

2. The processor according to claim 1, wherein the entry includes a first field in which an identifier of a register to which the value will be assigned is stored.

3. The processor according to claim 2, wherein the entry includes a second field in which a ready indicator is stored to indicate that the value has been generated by the first instruction and stored in the entry.

4. The processor according to claim 3, wherein the entry includes a third field in which a lock indicator is stored to indicate that the entry is locked.

5. The processor according to claim 4, further comprising a lock manager that manages the lock indicator to prevent eviction of the entry before the value is consumed by the second instruction.

6. The processor according to claim 5, wherein the lock manager is further configured to manage the lock indicator to prevent eviction of the entry before the value is consumed by the third instruction.

7. The processor according to claim 6, further comprising a dependency tracker to block scheduling of the second instruction until the ready indicator is set.

8. A method for inter-cluster communication of real-time register values, comprising: detecting, by a scan unit of a processor, that a first instruction generates a value consumed by a second instruction; allocating an entry in the cache memory of the processor for storing the value, the cache memory being separated from other memories in the system memory hierarchy and the register file of the processor; and assigning an identifier of the entry to the second instruction; incrementing a lock counter in response to assigning the identifier of the entry to the second instruction; detecting, by the scan unit, that a third instruction also consumes the value; looking up the entry in the cache memory; and assigning the identifier of the entry to the third instruction.

9. The method according to claim 8, further comprising incrementing the lock counter in response to assigning the identifier of the entry to the third instruction.

10. The method according to claim 9, further comprising blocking scheduling of the second instruction by a dependency tracker until the value has been generated by the first instruction and stored in the entry.

11. The method according to claim 10, further Comprising: Executing a first instruction by a first execution cluster of the processor; Storing the value in the entry; And Setting a ready indicator in the entry.

12. The method according to claim 11, further Comprising: Unblocking a second instruction by a dependency tracker in response to setting the ready indicator; Executing the second instruction by a second execution cluster of the processor; And Decrementing a lock indicator that is used to indicate that the entry is locked.

13. The method according to claim 12, further Comprising: Executing the third instruction; and Decrementing the lock indicator.

14. The method according to claim 13, further Comprising: Determining that the lock counter is zero; And Evicting the entry from the cache.

15. A system for inter-cluster communication of real-time register values, Comprising: A system memory having a hierarchical structure; A processor, comprising: A plurality of execution clusters; A first cache in the hierarchical structure of the system memory hierarchy; and A second cache that stores values generated by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters, the second cache being separated from the first cache and other memories in the hierarchical structure of the system memory hierarchy; and A scan unit for: Detecting that the value will be generated by a first instruction and consumed by a second instruction; Allocating an entry in the cache for storing the value; Assigning an identifier of the entry to the second instruction; Detecting that the value is also consumed by a third instruction; Finding the entry in the cache; and Assigning an identifier of the entry to the third instruction.

16. The system according to claim 15, Wherein, The processor further includes a physical register file separated from the second cache.

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