A simulated intelligent lock load test circuit

Abstract

The present invention discloses a simulated smart lock load test circuit, which relates to the field of electronic circuits. The test circuit includes a control signal output port, a simulation circuit, a switch circuit, a charging circuit and a discharging circuit, wherein the control signal output port is respectively connected to the charging circuit and the discharging circuit, wherein the charging circuit and the discharging circuit are connected to the switch circuit, wherein the switch circuit is connected to the simulation circuit, and wherein the simulation circuit is connected to a power supply; wherein the simulation circuit is used to simulate the load of a smart lock. The present invention simulates the same electrical characteristics as the door lock motor load through circuit elements, thereby miniaturizing and reproducible the motor load, and facilitating batch stability testing of smart locks.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to a simulated intelligent lock load test circuit. Background Art

[0002] Nowadays, smart locks are entering more and more households. Smart locks control the opening and closing of doors by driving the motor installed inside the door. Since smart locks need to have the characteristics of safety and stability, manufacturers need to conduct strict stability tests before leaving the factory, and usually need to conduct actual opening and closing tests with door lock motor loads on the market. Different door brands usually use different motors, and after being installed in the door, they cannot be easily disassembled because they are connected to the mechanical transmission device. It is not easy for smart lock manufacturers to obtain these motor loads in batches. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a simulated smart lock load test circuit, which simulates the same electrical characteristics as the door lock motor load through circuit elements, miniaturizes and reproducible the motor load, and makes batch stability testing of smart locks easier.

[0004] An embodiment of the present invention provides a simulated smart lock load test circuit, comprising a control signal output port, a simulation circuit, a switch circuit, a charging circuit and a discharging circuit, wherein the control signal output port is connected to the charging circuit and the discharging circuit respectively, the charging circuit and the discharging circuit are connected to the switch circuit, the switch circuit is connected to the simulation circuit, and the simulation circuit is connected to a power supply;

[0005] The simulation circuit is used to simulate the smart lock load.

[0006] The simulated smart lock load test circuit of the embodiment of the present invention has at least the following beneficial effects: the same electrical characteristics as the door lock motor load are simulated through circuit elements, the motor load is miniaturized and reproducible, and batch stability testing of smart locks becomes easy.

[0007] According to some other embodiments of the simulated smart lock load test circuit of the present invention, the simulated circuit includes a first inductor, a first resistor and a third resistor, one end of the first inductor is connected to a power supply, the other end of the first inductor is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the third resistor, and the other end of the third resistor is grounded.

[0008] According to some other embodiments of the simulated smart lock load test circuit of the present invention, the switching circuit includes a first MOS tube and a fourth resistor, the gate of the first MOS tube is connected to one end of the fourth resistor, the source of the first MOS tube and the other end of the fourth resistor are both grounded, and the drain of the first MOS tube is connected to the other end of the first resistor.

[0009] According to some other embodiments of the simulated smart lock load test circuit of the present invention, the charging circuit includes a third diode, a second resistor and a first capacitor, the negative electrode of the first capacitor is connected to the gate of the first MOS tube, the positive electrode of the first capacitor is connected to one end of the second resistor, the other end of the second resistor is connected to the negative electrode of the third diode, and the positive electrode of the third diode is connected to the control signal output port.

[0010] According to some other embodiments of the simulated smart lock load test circuit of the present invention, the discharge circuit includes a second diode and a first transistor, the anode of the second diode is connected to the positive electrode of the first capacitor, the cathode of the second diode is respectively connected to the collector of the first transistor and the other end of the second resistor, the emitter of the first transistor is grounded, and the base of the first transistor is connected to the control signal output port.

[0011] According to some other embodiments of the simulated smart lock load test circuit of the present invention, it also includes a fifth resistor, one end of the fifth resistor is connected to the control signal output port, and the other end of the fifth resistor is connected to the emitter of the first transistor.

[0012] According to some other embodiments of the simulated smart lock load test circuit of the present invention, the smart lock load is a motor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a circuit block diagram of a specific embodiment of a simulated smart lock load test circuit in an embodiment of the present invention;

[0014] Figure 2 It is a circuit schematic diagram of a specific embodiment of a simulated smart lock load test circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the embodiments to clearly and completely describe the concept of the present invention and the technical effects produced, so as to fully understand the purpose, characteristics and effects of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without creative work are all within the scope of protection of the present invention.

[0016] In the description of the present invention, if it involves a description of orientation, for example, the orientation or position relationship indicated by "upper", "lower", "front", "back", "left", "right", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. If a feature is referred to as being "set", "fixed", "connected", or "installed" on another feature, it can be directly set, fixed, or connected to the other feature, or it can be indirectly set, fixed, connected, or installed on the other feature.

[0017] In the description of the embodiments of the present invention, if "several" is involved, it means more than one, if "multiple" is involved, it means more than two, if "greater than", "less than" or "exceed" is involved, it should be understood as not including the number itself, if "above", "below" or "within" is involved, it should be understood as including the number itself. If "first" or "second" is involved, it should be understood as being used to distinguish technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0018] Embodiment 1

[0019] Reference Figure 1 , shows a circuit block diagram of a simulated smart lock load test circuit in an embodiment of the present invention, specifically including: a control signal output port, an analog circuit, a switching circuit, a charging circuit and a discharging circuit, the control signal output port is respectively connected to the charging circuit and the discharging circuit, the charging circuit and the discharging circuit are connected to the switching circuit, the switching circuit is connected to the analog circuit, and the analog circuit is connected to a power supply.

[0020] Among them, the analog circuit is used to simulate the smart lock load, and its electrical performance is similar to that of the smart lock load.

[0021] In this embodiment, the smart lock load is a motor load.

[0022] Embodiment 2

[0023] Reference Figure 2 , shows a circuit schematic diagram of a simulated smart lock load test circuit in an embodiment of the present invention.

[0024] like Figure 2 As shown, P1 is the control signal output port, that is, the gate-opening logic level signal port output by the main control chip.

[0025] The analog circuit includes a first inductor L1, a first resistor R1 and a third resistor R3. One end of the first inductor L1 is connected to a 24V power supply, the other end of the first inductor L1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is grounded.

[0026] In this embodiment, the third resistor R3 needs to control the time of connecting to the circuit. Since different door lock motors are loaded with different structural components, the motor load size is different, and the current generated after unlocking is also different. The load current can be adjusted by adjusting the resistance value of the third resistor R3.

[0027] The switch circuit includes a first MOS tube Q1 and a fourth resistor R4, the gate of the first MOS tube Q1 is connected to one end of the fourth resistor R4, the source of the first MOS tube Q1 and the other end of the fourth resistor R4 are grounded, and the drain of the first MOS tube Q1 is connected to the other end of the first resistor R1.

[0028] In this embodiment, the switch circuit is used to control the connection of the third resistor R3.

[0029] The charging circuit includes a third diode D3, a second resistor R2 and a first capacitor C1, the cathode of the first capacitor C1 is connected to the gate of the first MOS tube Q1, the anode of the first capacitor C1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the cathode of the third diode D3, and the anode of the third diode D3 is connected to the control signal output port P1.

[0030] In this embodiment, the charging circuit is used to achieve delayed turning on of the first MOS transistor Q1.

[0031] The discharge circuit includes a second diode D2 and a first transistor Q2, the anode of the second diode D2 is connected to the anode of the first capacitor C1, the cathode of the second diode D2 is respectively connected to the collector of the first transistor Q2 and the other end of the second resistor R2, the emitter of the first transistor Q2 is grounded, and the base of the first transistor Q2 is connected to the control signal output port.

[0032] In this embodiment, the discharge circuit is used to discharge the first capacitor C1 quickly so as to achieve the next continuous and effective turn-on of the first MOS transistor Q1.

[0033] The load test circuit further includes a fifth resistor R5 (bias resistor), one end of the fifth resistor R5 is connected to the control signal output port, and the other end of the fifth resistor R5 is connected to the emitter of the first transistor Q2.

[0034] In this embodiment, when the control signal output port P1 outputs a high-level signal, it is equivalent to stopping the door lock motor, and the first capacitor C1 is charged via the third diode D3 and the second resistor R2. When the voltage is charged to a voltage higher than the threshold voltage of the first MOS tube Q1, the first MOS tube Q1 is turned on; when the control signal output port P1 outputs a low-level signal, it is equivalent to opening the door lock motor, and the first capacitor C1 is discharged via the second diode D2 and the first transistor Q2. When the voltage is discharged to a voltage lower than the threshold voltage of the first MOS tube Q1, the first MOS tube Q1 is turned off.

[0035] The control signal is output in a high-low level alternating manner, which can simulate the continuous opening and closing state of the motor to achieve the purpose of cyclic testing.

[0036] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the technical field without departing from the purpose of the present invention. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

Claims

1. A simulated smart lock load test circuit, characterized in that: It includes a control signal output port, an analog circuit, a switch circuit, a charging circuit and a discharging circuit, wherein the control signal output port is connected to the charging circuit and the discharging circuit respectively, the charging circuit and the discharging circuit are connected to the switch circuit, the switch circuit is connected to the analog circuit, and the analog circuit is connected to a power supply; The simulation circuit is used to simulate the load of the smart lock; wherein the simulation circuit includes a first inductor, a first resistor and a third resistor, one end of the first inductor is connected to a power supply, the other end of the first inductor is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the third resistor, and the other end of the third resistor is grounded; the third resistor controls the time of accessing the circuit, and adjusts the load current by adjusting the resistance value of the third resistor, thereby simulating different motor load sizes; the switch circuit is used to control the access of the third resistor R3, and the switch circuit includes a first MOS tube and a fourth resistor, the gate of the first MOS tube is connected to one end of the fourth resistor, the source of the first MOS tube and the other end of the fourth resistor are grounded, and the drain of the first MOS tube is connected to the other end of the first resistor; Among them, the discharge circuit includes a first transistor, and the simulated smart lock load test circuit also includes a fifth resistor, one end of the fifth resistor is connected to the control signal output port, and the other end of the fifth resistor is connected to the collector of the first transistor, the collector of the first transistor is grounded, the base of the first transistor is connected to the control signal output port, and the collector of the first transistor is connected to the gate of the first MOS tube.

2. A simulated smart lock load test circuit according to claim 1, characterized in that: The charging circuit includes a third diode, a second resistor and a first capacitor, the cathode of the first capacitor is connected to the gate of the first MOS tube, the anode of the first capacitor is connected to one end of the second resistor, the other end of the second resistor is connected to the cathode of the third diode, and the anode of the third diode is connected to the control signal output port.

3. A simulated smart lock load test circuit according to claim 2, characterized in that: The discharge loop also includes a second diode, the anode of the second diode is connected to the anode of the first capacitor, and the cathode of the second diode is respectively connected to the emitter of the first transistor and the other end of the second resistor.

4. A simulated smart lock load test circuit according to any one of claims 1 to 3, characterized in that: The smart lock load is a motor.

Images