Array substrate, display panel and display device

Abstract

On one hand, the present invention provides an array substrate. The array substrate defines a display area and a camera hole area surrounded by the display area, and the camera hole area includes a light-transmitting area and a wiring area surrounding the light-transmitting area. The array substrate includes a substrate, a first conductive layer, and a second conductive layer. The first conductive layer includes a plurality of first conductive lines arranged around the light-transmitting area. The second conductive layer includes a plurality of second conductive lines arranged around the light-transmitting area. The first conductive layer also includes a plurality of first capacitor compensation patterns, each of which is located between two adjacent first conductive lines. Along the thickness direction of the array substrate, the projection of each first capacitor compensation pattern on the substrate overlaps with the projection of at least one second conductive line. A display panel and a display device are also provided.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel using the array substrate, and a display device using the display panel. Background Art

[0002] As users' demands for diversified functions of display devices such as mobile phones and tablet computers increase, they often need to be combined with components having other functions. Among them, display devices combined with camera modules have been widely produced and used.

[0003] Taking an array substrate including multiple wires in a display device as an example, the array substrate needs to be provided with a camera hole area exposing the camera module. However, the camera hole area will affect the arrangement of the wires on the array substrate and even affect the performance of the electronic device. Summary of the Invention

[0004] In one aspect, the present invention provides an array substrate, wherein the array substrate defines a display area and a camera hole area surrounded by the display area, wherein the camera hole area includes a light-transmitting area and a wiring area surrounding the light-transmitting area, and the array substrate includes:

[0005] substrate;

[0006] a first conductive layer located on the substrate, the first conductive layer comprising a plurality of first conductive wires, each of the first conductive wires being arranged around the light-transmitting area;

[0007] a second conductive layer located on a side of the first conductive layer away from the substrate, the second conductive layer comprising a plurality of second conductive wires, each of the second conductive wires being arranged around the light-transmitting area;

[0008] The first conductive layer further includes a plurality of first capacitance compensation patterns insulated and spaced apart from the first conductive wires, and each of the first capacitance compensation patterns is located between two adjacent first conductive wires;

[0009] Along the thickness direction of the array substrate, a projection of each first capacitance compensation pattern on the base overlaps with a projection of at least one second conductive line.

[0010] In the above-mentioned array substrate, due to the setting of the first capacitance compensation pattern, the capacitive coupling amount of the second wire overlapping with the first capacitance compensation pattern increases and the coupling voltage decreases, thereby weakening the influence of the coupling voltage on the original voltage of the second wire, thereby improving the phenomenon that the parasitic capacitance between adjacent wires is large due to the close arrangement of the wires in the camera hole area of ​​the array substrate, which affects the display effect.

[0011] Another aspect of the present invention provides a display panel, including a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is sandwiched between the color filter substrate and the array substrate, and the array substrate is the array substrate described above.

[0012] The display panel uses the above-mentioned array substrate, which also improves the phenomenon that the parasitic capacitance between adjacent wirings is large and affects the display due to the tight arrangement of wirings in the camera hole area.

[0013] Another aspect of the present invention provides a display device, comprising:

[0014] The above-mentioned display panel;

[0015] a backlight module, the backlight module being located on a side of the display panel away from the display surface thereof, the backlight module being defined with a mounting hole penetrating the backlight module, the mounting hole being aligned with the light-transmitting area; and

[0016] A camera module is installed in the installation hole and collects image information through the light-transmitting area.

[0017] The display device uses the above-mentioned display panel, which also improves the phenomenon that the parasitic capacitance between adjacent wirings is large and affects the display due to the tight arrangement of wirings in the camera hole area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 FIG. 1 is a schematic top view of an array substrate according to an embodiment of the present invention.

[0019] Figure 2 for Figure 1 Schematic diagram of the wiring layout of the array substrate.

[0020] Figure 3 for Figure 2 A cross-sectional diagram of the auxiliary data line and the data line lead at the connection position.

[0021] Figure 4 for Figure 2 Enlarged schematic diagram of IV in the middle.

[0022] Figure 5 for Figure 2 Schematic diagram of the projection of the first conductive layer of the array substrate on the base.

[0023] Figure 6 for Figure 2 Schematic diagram of the projection of the second conductive layer of the array substrate on the base.

[0024] Figure 7 for Figure 2 Enlarged schematic diagram of point VII in the middle.

[0025] Figure 8 FIG. 4 is an equivalent circuit diagram of a second compensation capacitor pattern and four first conductive lines stacked one on top of the other in one embodiment of the present invention.

[0026] Figure 9 FIG. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention.

[0027] Figure 10 FIG. 1 is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention.

[0028] Description of main component symbols

[0029] Array substrate 10

[0030] Display Area A

[0031] Camera hole area B

[0032] Light-transmitting area B1

[0033] Routing area B2

[0034] First direction X

[0035] Second direction Y

[0036] First axis of symmetry L1

[0037] Second symmetry axis L2

[0038] Left area AL

[0039] Right Area AR

[0040] Upper AT

[0041] Lower area AB

[0042] Scan line 12

[0043] First scan line 122

[0044] Second scanning line 124

[0045] Data cable 14

[0046] First data line 142

[0047] Second data line 144

[0048] Auxiliary data line 144a

[0049] Data line lead 144b

[0050] The third data line 146

[0051] Fourth data line 148

[0052] Sub-pixel 16

[0053] Thin film transistor 162

[0054] Gate GE

[0055] Source SE

[0056] Drain DE

[0057] pixel electrode 164

[0058] Base 11

[0059] First conductive layer 13

[0060] First wire 120

[0061] First capacitance compensation pattern 110

[0062] Second conductive layer 15

[0063] Second wire 140

[0064] The second capacitance compensation pattern 130

[0065] Insulation layer 17

[0066] Via 19

[0067] Color filter substrate 20

[0068] Liquid crystal layer 30

[0069] Display panel 40

[0070] Display surface 40a

[0071] Camera module 50

[0072] Backlight module 60

[0073] Light exit side 60a

[0074] Mounting holes 62

[0075] Display device 100

[0076] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0077] like Figure 1As shown, the array substrate 10 of this embodiment of the present invention defines a display area A and a camera aperture area B surrounded by the display area A. The camera aperture area B is defined by a light-transmitting area B1 and a wiring area B2 surrounding the light-transmitting area B1. The camera aperture area B is a light-transmitting area. In this embodiment, the camera aperture area B and the light-transmitting area B1 are roughly circular, and the wiring area B2 is a ring.

[0078] In other embodiments, the camera hole area B may also be in other shapes, such as an ellipse, a polygon, etc.

[0079] like Figure 2 As shown, the routing area B2 has a first symmetry axis L1 and a second symmetry axis L2. Along the first direction X, the routing area B2 is axially symmetrical about the second symmetry axis L2. Along the second direction Y, the routing area B2 is axially symmetrical about the first symmetry axis L1. The second direction Y intersects the first direction X.

[0080] like Figure 2 As shown, along the first direction X, the display area A is divided by the second axis of symmetry L2 into a left area AL and a right area AR, located on opposite sides of the second axis of symmetry L2. Along the second direction Y, the display area A is divided by the first axis of symmetry L1 into an upper area AT and a lower area AB, located on opposite sides of the first axis of symmetry L1. That is, the left area AL and the right area AR constitute the entire display area A. The upper area AT and the lower area AB also constitute the entire display area A. The left area AL overlaps with both the upper area AT and the lower area AB, and the right area AR overlaps with both the upper area AT and the lower area AB. In one embodiment, the second direction Y is perpendicular to the first direction X.

[0081] like Figure 2 As shown, the array substrate 10 includes a substrate 11 and scan lines 12 and data lines 14 located on the substrate 11 .

[0082] like Figure 2As shown, the scan lines 12 include multiple first scan lines 122. The multiple first scan lines 122 extend across the routing area B2 and are spaced apart in sequence along the second direction Y. Some of the first scan lines 122 extend within the upper area AT and the routing area B2, while other portions of the first scan lines 122 extend within the lower area AB and the routing area B2. The multiple first scan lines 122 are axially symmetrically distributed about the first axis of symmetry L1. The portion of each first scan line 122 within the routing area B2 is axially symmetrically distributed about the second axis of symmetry L2. Each first scan line 122 extends along the first direction X to the routing area B2 in the left area AL, bends and extends around the outer contour of the light-transmitting area B1 within the routing area B2, and then continues to extend along the first direction X in the right area AR. In other words, each first scan line 122 is arranged to bypass the light-transmitting area B1, cross the routing area B2, and extend along the first direction X within the display area A. The first scan line 122 in the upper area AT and the wiring area B2 bends and extends along the upper half of the transparent area B1 , and the first scan line 122 in the lower area AB and the wiring area B2 bends and extends along the lower half of the transparent area B1 .

[0083] Each first scan line 122 includes a straight line portion extending along the first direction X in the left area AL, a curved portion extending around the outer contour of the light-transmitting area B1 in the routing area B2 ( Figure 2 The first scan line 122 is a curved portion (arc in the middle) and a straight portion extending along the first direction X within the right area AR. The length of the curved portion of the first scan line 122 varies with its distance from the first axis of symmetry L1. The closer the first scan line 122 is to the first axis of symmetry L1, the longer its curved portion; the farther the first scan line 122 is from the first axis of symmetry L1, the shorter its curved portion. In one embodiment, multiple first scan lines 122 are arranged at equal intervals.

[0084] like Figure 2 As shown, the data lines 14 include a plurality of first data lines 142 extending across the routing area B2. The plurality of first data lines 142 are spaced apart in sequence along the first direction X. Some of the first data lines 142 extend within the left area AL and the routing area B2, while others extend within the right area AR and the routing area B2. The plurality of first data lines 142 are axially symmetrically distributed about the second symmetry axis L2.

[0085] The portion of each first data line 142 within the routing area B2 is axially symmetrical about the first axis of symmetry L1. Each first data line 142 extends along the second direction Y in the upper area AT to the routing area B2, then curves and extends around the outer contour of the light-transmitting area B1 within the routing area B2 before continuing along the second direction Y within the lower area AB. In other words, each first data line 142 is arranged to bypass the light-transmitting area B1, cross the routing area B2, and extend along the second direction Y within the display area A. Specifically, the first data line 142 located in the left area AL and the routing area B2 curves and extends along the left half of the light-transmitting area B1, while the first data line 142 located in the right area AR and the routing area B2 curves and extends along the right half of the light-transmitting area B1.

[0086] Each first data line 142 includes a straight segment portion extending along the second direction Y in the upper area AT, and a curved segment portion extending around the outer contour of the light-transmitting area B1 in the routing area B2 ( Figure 2 The first data lines 142 are arranged as a curved portion (arc in the middle) and as a straight line segment extending along the second direction Y within the lower area AB. The length of the curved portion of the first data line 142 varies with its distance from the second axis of symmetry L2. First data lines 142 closer to the second axis of symmetry L2 have longer curved portions; first data lines 142 farther from the first axis of symmetry L1 have shorter curved portions. In one embodiment, multiple first data lines 142 are arranged at equal intervals.

[0087] like Figure 2 As shown, the data lines 14 also include a plurality of second data lines 144. The plurality of second data lines 144 extend across the routing area B2. Some second data lines 144 extend within the left area AL and the routing area B2, while others extend within the right area AR and the routing area B2. The plurality of second data lines 144 are axially symmetrically distributed about the second axis of symmetry L2. The plurality of first data lines 142 and the plurality of second data lines 144 are arranged alternately along the first direction X, with one first data line 142 and one second data line 144.

[0088] Each second data line 144 extends along the second direction Y in the upper area AT to the routing area B2, then bends and extends around the outer contour of the light-transmitting area B1 within the routing area B2, and then continues to extend along the second direction Y within the lower area AB. In other words, each second data line 144 is arranged to bypass the light-transmitting area B1, cross the routing area B2, and extend along the second direction Y within the display area A. The second data line 144 located in the left area AL and the routing area B2 bends and extends along the left half of the light-transmitting area B1, and the second data line 144 located in the right area AR and the routing area B2 bends and extends along the right half of the light-transmitting area B1.

[0089] Each second data line 144 includes a straight line portion extending along the second direction Y in the upper area AT, and a curved portion extending around the outer contour of the light-transmitting area B1 in the routing area B2 ( Figure 2 An arc in the middle) and a straight line segment extending along the second direction Y in the lower area AB.

[0090] The curved portion of each second data line 144 is defined as an auxiliary data line 144a. Each auxiliary data line 144a is symmetrically distributed about the first axis of symmetry L1. Each first data line 142 is located between two adjacent auxiliary data lines 144a, with one auxiliary data line 144a located between two adjacent first data lines 142. The curved portions of the auxiliary data lines 144a and the first data lines 142 are arranged alternately in the first direction X, forming one auxiliary data line 144a and one first data line 142. The length of the auxiliary data lines 144a varies with their distance from the second axis of symmetry L2. The closer the auxiliary data lines 144a are to the second axis of symmetry L2, the longer they are; the farther the auxiliary data lines 144a are from the first axis of symmetry L1, the shorter they are.

[0091] The straight segments of each second data line 144 are defined as data line leads 144b. The plurality of data line leads 144b and the straight segments of the plurality of first data lines 142 are arranged alternately in the first direction X. In the second direction Y, the first scan lines 122 are located on the side of the auxiliary data lines 144a away from the light-transmitting area B1. The projection of each data line lead 144b on the substrate 11 overlaps with all of the first scan lines 122.

[0092] like Figure 3 As shown, the array substrate 10 includes a substrate 11, a first conductive layer 13 located on one surface of the substrate 11, a second conductive layer 15 located on a side of the first conductive layer 13 away from the substrate 11, and an insulating layer 17 located between the first conductive layer 13 and the second conductive layer 15. The insulating layer 17 can be one or more layers. The first scan line 122 and the auxiliary data line 144a are defined by the first conductive layer 13. The first data line 142 and the data line lead 144b are defined by the second conductive layer 15. The auxiliary data line 144a and the data line lead 144b are electrically connected through a via 19. That is, the auxiliary data line 144a and the first data line 142 are located on different conductive layers.

[0093] Please refer again Figure 2The projection of each first data line 142 on the substrate 11 is located between two adjacent auxiliary data lines 144a, and there is an auxiliary data line 144a between two adjacent first data lines 142. Compared to an arrangement in which adjacent conductive lines (for example, the first data line 142 and the second data line 144) are located on the same conductive layer, adjacent conductive lines in the routing area B2 (for example, the auxiliary data lines 144a between the first data line 142 and the second data line 144) are located on different conductive layers. This allows for a tighter arrangement of the conductive lines without short circuits, thereby reducing the wiring area of ​​the routing area B2.

[0094] Please continue reading Figure 2 The data lines 14 also include a plurality of third data lines 146. The plurality of third data lines 146 extend across the routing area B2 and are located on the side of the first data lines 142 and the second data lines 144 away from the light-transmitting area B1. The plurality of third data lines 146 are sequentially spaced along the first direction X. Some third data lines 146 extend within the left area AL and the routing area B2, while others extend within the right area AR and the routing area B2. The plurality of third data lines 146 are symmetrically distributed about the second axis of symmetry L2.

[0095] The portion of each third data line 146 within the routing area B2 is axially symmetrical about the first axis of symmetry L1. Each third data line 146 extends along the second direction Y from the upper area AT to the routing area B2, then curves and extends around the outer contour of the light-transmitting area B1 within the routing area B2 before continuing along the second direction Y within the lower area AB. In other words, each third data line 146 is arranged to bypass the light-transmitting area B1, cross the routing area B2, and extend along the second direction Y within the display area A. Specifically, the first data line 142 located in the left area AL and the routing area B2 curves and extends along the left half of the light-transmitting area B1, while the first data line 142 located in the right area AR and the routing area B2 curves and extends along the right half of the light-transmitting area B1.

[0096] Each third data line 146 includes a straight segment portion extending along the second direction Y in the upper area AT, a curved segment portion extending around the outer contour of the light-transmitting area B1 in the routing area B2 ( Figure 2 The third data lines 146 are arcs in the center and straight line segments extending along the second direction Y within the lower area AB. The length of the curved portion of the third data line 146 varies with its distance from the second axis of symmetry L2. The closer the third data line 146 is to the second axis of symmetry L2, the longer its curved portion; the farther the third data line 146 is from the first axis of symmetry L1, the shorter its curved portion. In one embodiment, multiple third data lines 146 are arranged at equal intervals.

[0097] like Figure 2As shown, the data lines 14 extending across the routing area B2 include a first data line 142, a second data line 144, and a third data line 146. Along the first direction X, the data lines 14 within the routing area B2 are arranged in the following order: a plurality of third data lines 146 (near the left area AL), alternating second data lines 144 and first data lines 142, and a plurality of third data lines 146 (near the right area AR). The data line 14 closest to the light-transmitting area B1 can be either the first data line 142 or the second data line 144.

[0098] In one embodiment, the third data line 146 is defined by the second conductive layer 15. That is, the first data line 142, the data line lead 144b of the second data line 144, and the third data line 146 are all defined by the same conductive layer. The auxiliary data line 144a of the second data line 144 is formed from a first conductive layer 13 that is different from the second conductive layer 15. Preferably, the second data line 144 is immediately adjacent to the third data line 146. In this way, among the data lines 14 extending across the routing area B2, different conductive layers are used at the intersections of different types of data lines 14. This allows for a tighter arrangement of the wires, preventing short circuits and further minimizing the difference between the inner and outer diameters of the routing area B2.

[0099] Please continue reading Figure 2 The data lines 14 also include a plurality of fourth data lines 148. The fourth data lines 148 extend within the display area A and do not extend into the routing area B2. Some of the fourth data lines 148 are located in the left area AL, and some are located in the right area AR. Within the left area AL, the plurality of fourth data lines 148 are spaced apart, each extending along the second direction Y. Within the right area AR, the plurality of fourth data lines 148 are spaced apart, each extending along the second direction Y. Within the lower area AB (or upper area AT), along the first direction X, the first data lines 142, the second data lines 144, the third data lines 146, and the fourth data lines 148 are arranged in the following order: a plurality of fourth data lines 148, a plurality of third data lines 146, an alternating arrangement of the first and second data lines 142, 144, the plurality of third data lines 146, and the plurality of fourth data lines 148.

[0100] Please continue reading Figure 2, the scan line 12 also includes a plurality of second scan lines 124 that are arranged only corresponding to the display area A. The second scan lines 124 extend only within the display area A and do not extend to the routing area B2. Some of the second scan lines 124 are located in the upper area AT, and some of the second scan lines 124 are located in the lower area AB. In the upper area AT, the plurality of second scan lines 124 are arranged in sequence at intervals, and each second scan line 124 extends along the first direction X. In the lower area AB, the plurality of second scan lines 124 are arranged in sequence at intervals, and each second scan line 124 extends along the first direction X. Along the second direction Y, the first scan lines 122 and the second scan lines 124 are arranged in the following order: the plurality of second scan lines 124 located in the upper area AT, the plurality of first scan lines 122 located in the upper area AT, the plurality of first scan lines 122 located in the lower area AB, and the plurality of second scan lines 124 located in the lower area AB.

[0101] In one embodiment, the plurality of first scan lines 122, the plurality of second scan lines 124, and the auxiliary data lines 144a of the plurality of second data lines 144 are defined by the first conductive layer 13. The plurality of first data lines 142, the data line leads 144b of the plurality of second data lines 144, the plurality of third data lines 146, and the plurality of fourth data lines 148 are defined by the second conductive layer 15. In other words, all scan lines 12 are formed by the first conductive layer 13. All data lines 14, excluding the auxiliary data lines 144a of the second data lines 144, are formed by the second conductive layer 15. The traces formed by the first conductive layer 13 (the first scan lines 122, the second scan lines 124, and the auxiliary data lines 144a) are defined as first conductive lines 120. The traces formed by the second conductive layer 15 (the first data lines 142, the data line leads 144b, the third data lines 146, and the fourth data lines 148) are defined as second conductive lines 140.

[0102] Because adjacent conductive lines (e.g., the auxiliary data lines 144a of the first and second data lines 142 and 144, and the auxiliary data lines 144a of the third and second data lines 146 and 144) are made of different conductive layers, adjacent conductive lines can be arranged more densely without short circuits, facilitating the narrowing of the routing area B2. Furthermore, the auxiliary data lines 144a are closer to the light-transmitting area B1 than the first scan lines 122, which are made of the same conductive layer, without interfering with the routing of the first scan lines 122.

[0103] Please refer again Figure 2All scan lines 12 and all data lines 14 are arranged away from the camera aperture area B, allowing light to pass through the camera aperture area B. At least a portion of the first scan lines 122, first data lines 142, second data lines 144, and third data lines 146 form a ring around the light-transmitting area B1. The portions of all scan lines 12 within the display area A extend along the first direction X, and the portions of all data lines 14 within the display area A extend along the second direction Y. The projection of each data line 14 on the substrate 11 vertically overlaps with all scan lines 12.

[0104] In one embodiment, the camera aperture area B is not used for displaying images. Any two adjacent pairs of the plurality of first scan lines 122 and the plurality of second scan lines 124 intersect with any two adjacent pairs of the plurality of first data lines 142, the plurality of second data lines 144, the plurality of third data lines 146, and the plurality of fourth data lines 148 within the display area A to define a sub-pixel 16.

[0105] like Figure 4 As shown, each sub-pixel 16 includes a thin film transistor 162 and a pixel electrode 164. The thin film transistor 162 includes a gate electrode GE, a source electrode SE, and a drain electrode DE. The gate electrode GE is electrically connected to one of the first scan line 122 and the second scan line 124. The source electrode SE is electrically connected to one of the first data line 142, the second data line 144, the third data line 146, and the fourth data line 148. The drain electrode DE is electrically connected to the pixel electrode 164.

[0106] It can be understood that although the arrangement of the scan lines 12 and the data lines 14 on the array substrate 10 is described as an example in this embodiment, it is not limited to the scan lines 12 and the data lines 14. In other embodiments, it can also be the arrangement of other wires on the array substrate 10 that defines the camera hole area B. For example, the touch lines on the array substrate 10 that serves as a touch panel can avoid the camera hole area B.

[0107] In one embodiment, the substrate 11 is made of a transparent hard material, such as glass, quartz, or plastic. In other embodiments, the substrate 11 can be made of a flexible material, such as one or more of polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), and polyethylene terephthalate (PET). The material of the first conductive layer 13 and the second conductive layer 15 can be selected from at least one of aluminum, silver, gold, chromium, copper, indium, manganese, molybdenum, nickel, neodymium, palladium, platinum, titanium, tungsten, and zinc. The material of the insulating layer 17 can be selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), etc.

[0108] Figure 5 for Figure 2Schematic diagram of the projection of the first conductive layer 13 of the array substrate 10 on the substrate 11. Figure 5 As shown, the first conductive layer 13 further includes a plurality of first capacitance compensation patterns 110 insulated and spaced apart from the first conductive lines 120. Each first capacitance compensation pattern 110 is located between two adjacent first conductive lines 120. Some first capacitance compensation patterns 110 are located between two adjacent first scan lines 122 and in the routing area B2 near the display area A. Some first capacitance compensation patterns 110 are located between two adjacent auxiliary data lines 144a and in the routing area B2 near the light-transmitting area B1. Figure 5 In the embodiment, the shape of the first capacitance compensation pattern 110 is substantially a hollow rectangle. In other embodiments, the shape of the first capacitance compensation pattern 110 is not limited.

[0109] Figure 6 for Figure 2 Schematic diagram of the projection of the second conductive layer 15 of the array substrate 10 on the substrate 11. Figure 6 As shown, the second conductive layer 15 further includes a plurality of second capacitance compensation patterns 130 spaced apart from the second conductive lines 140. Each second capacitance compensation pattern 130 is located between two adjacent second conductive lines 140. Within the alignment routing area B2, one or more second capacitance compensation patterns 130 can be disposed between any two adjacent first data lines 142, the plurality of auxiliary data lines 144a, the plurality of third data lines 146, and the plurality of fourth data lines 148. That is, within the alignment routing area B2, one or more second capacitance compensation patterns 130 can be disposed between any two adjacent second conductive lines 140 (e.g., between two adjacent first data lines 142, between an auxiliary data line 144a and its adjacent first data line 142 or third data line 146, between two adjacent third data lines 146, and between a third data line 146 and its adjacent fourth data line 148). The plurality of second capacitance compensation patterns 130 are located on the side of the alignment routing area B2 near the display area A, substantially surrounding the light-transmitting area B1.

[0110] Figure 6 In the embodiment, the second capacitance compensation pattern 130 is generally shaped like a hollow rectangle. In other embodiments, the second capacitance compensation pattern 130 may have other shapes, and the second capacitance compensation pattern 130 may be disposed between some adjacent second conductive lines 140, while no second capacitance compensation pattern 130 may be disposed between other adjacent second conductive lines 140.

[0111] Figure 7 for Figure 2 The enlarged schematic diagram of VII in FIG. Figure 7As shown, along the thickness direction of the array substrate 10, the projection of each first capacitance compensation pattern 110 on the substrate 11 overlaps with the projection of at least one second conductive line 140, thereby achieving signal compensation between adjacent first conductive lines 120. Along the thickness direction of the array substrate 10, the projection of each second capacitance compensation pattern 130 on the substrate 11 overlaps with the projection of at least one first conductive line 120, thereby achieving signal compensation between adjacent second conductive lines 140.

[0112] Figure 8 FIG. 1 is an equivalent circuit diagram of a second compensation capacitor pattern and four first conductive lines 120 stacked one above the other in one embodiment of the present invention. Figure 8 As shown, the parasitic capacitance between adjacent first conductive lines 120 is C1, the original capacitance of the first conductive line 120 is Cs, and the capacitive coupling amounts of the four first conductive lines 120 increased by the provision of the second capacitance compensation pattern 130 are Cp1, Cp2, Cp3, and Cp4, respectively. The coupling voltage Vc1 of the first conductive line 120 is:

[0113] Vc1=dV*(C1+Cp1*Cp2 / (Cp1+Cp2)) / (C1+Cs+Cp1(Cp2+Cp3+Cp4) / (Cp1+Cp2+Cp3+Cp4)).

[0114] If the array substrate 10 is not provided with the second capacitance compensation pattern 130 , the coupling voltage Vc2 of the first conductive line 120 is:

[0115] Vc2 = dV*C1 / (C1+Cs).

[0116] It can be seen that when the first conductor 120 and the second capacitor compensation pattern 130 overlap, the coupling voltage Vc1 is less than the coupling voltage Vc2 when the second capacitor compensation pattern 130 is not set. When the coupling voltage of the first conductor 120 decreases, the influence of the coupling voltage on the original voltage of the first conductor 120 is weakened, thereby improving the phenomenon that the parasitic capacitance between adjacent conductors is large due to the close arrangement of the conductors (the first conductor 120 and the second conductor 140) on the array substrate 10, which affects the display effect.

[0117] As can be seen from the above formula, the effect of the second capacitance compensation pattern 130 on the original voltage of the first conductive line 120 is related to the number of first conductive lines 120 that it overlaps. In one embodiment, the projection of each second capacitance compensation pattern 130 on the substrate 11 overlaps with the projections of at least three first conductive lines 120 to further reduce the effect of parasitic capacitance on the original voltage of the first conductive line 120.

[0118] The capacitance compensation principle when the first capacitance compensation pattern 110 and the second conductive line 140 are stacked one above the other is similar and will not be further described here. Similarly, in one embodiment, the projection of each first capacitance compensation pattern 110 on the substrate 11 overlaps with the projections of at least three second conductive lines 140 to further reduce the effect of parasitic capacitance on the original voltage on the second conductive line 140, thereby avoiding the phenomenon of large parasitic capacitance between adjacent conductive lines due to the close arrangement of the conductive lines (first conductive lines 120 and second conductive lines 140) on the array substrate 10, which affects the display effect.

[0119] Figure 9 FIG. 4 is a cross-sectional view of a display panel 40 provided in one embodiment of the present invention. Figure 9 As shown, the display panel 40 includes an array substrate 10 and a color filter substrate 20 that are oppositely arranged, and a liquid crystal layer 30 sandwiched between the array substrate 10 and the color filter substrate 20 .

[0120] The color filter substrate 20 includes a transparent base (not shown), a black matrix (not shown) disposed on the side of the base near the liquid crystal layer 30, a filter layer (not shown), and a protective layer (not shown). The black matrix and filter layer are removed from the light-transmitting area B1 corresponding to the camera aperture area B. The liquid crystal layer 30 is disposed corresponding to the display area A and the camera aperture area B.

[0121] The array substrate 10 further includes a common electrode (not shown) disposed corresponding to the display area A. An electric field is generated between the pixel electrode 164 and the common electrode to drive the liquid crystal molecules in the liquid crystal layer 30 to rotate, causing the display area A to display images while the camera aperture area B does not display images.

[0122] Figure 10 FIG. 1 is a cross-sectional view of a display device 100 provided in one embodiment of the present invention. Figure 10 As shown, the display device 100 includes a display panel 40, a backlight module 60, and a camera module 50. The display panel 40 defines a display surface 40a. The backlight module 60 and the camera module 50 are located on a side of the display panel 40 facing away from the display surface 40a. The backlight module 60 defines a light-emitting side 60a. The display panel 40 is located on the light-emitting side 60a of the backlight module 60. The camera module 50 is positioned corresponding to the camera aperture area B to capture image information through the camera aperture area B.

[0123] The backlight module 60 is a direct-type backlight source. The backlight module 60 includes a light source (not shown), an optical film group (not shown) and a back plate (not shown), etc. The backlight module 60 is defined with a mounting hole 62 that passes through the backlight module 60 corresponding to the camera hole area B. The size of the mounting hole 62 is greater than or approximately equal to the size of the camera hole area B. The camera module 50 is arranged in the mounting hole 62. Since the camera module 50 is arranged corresponding to the camera hole area B surrounded by the display area A, the screen-to-body ratio of the display device 100 is improved compared to the method of setting the camera module 50 in the border area surrounding the display area A. The display device 100 can be a mobile phone, a tablet computer, etc.

[0124] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate is defined with a display area and a camera hole area surrounded by the display area, the camera hole area includes a light-transmitting area and a wiring area surrounding the light-transmitting area, and the array substrate includes: substrate; a first conductive layer located on the substrate, the first conductive layer comprising a plurality of first conductive lines arranged around the light-transmitting area; a second conductive layer located on a side of the first conductive layer away from the substrate, the second conductive layer comprising a plurality of second conductive wires disposed around the light-transmitting area; and an insulating layer, located between the first conductive layer and the second conductive layer; The first conductive layer further includes a plurality of first capacitance compensation patterns insulated and spaced apart from the first conductive wires, and each of the first capacitance compensation patterns is located between two adjacent first conductive wires; Along the thickness direction of the array substrate, a projection of each first capacitance compensation pattern on the base overlaps with a projection of at least one second conductive line; The second conductive layer further includes a plurality of second capacitance compensation patterns insulated and spaced apart from the second conductive wires, each of the second capacitance compensation patterns being located between two adjacent second conductive wires; Along the thickness direction of the array substrate, a projection of each of the second capacitance compensation patterns on the base overlaps with a projection of at least one of the first conductive lines.

2. The array substrate according to claim 1, wherein: The first conductive line includes a plurality of first scanning lines, each of the first scanning lines bypasses the light-transmitting area, crosses the routing area, and extends along a first direction in the display area; The first capacitance compensation pattern is disposed between two adjacent first scan lines.

3. The array substrate according to claim 2, wherein: The second conductive line includes a plurality of first data lines, each of the first data lines bypasses the light-transmitting area, crosses the routing area, and extends along the second direction in the display area; The second direction intersects the first direction; The second capacitance compensation pattern is disposed between two adjacent first data lines.

4. The array substrate according to claim 3, wherein: The array substrate further includes a plurality of second data lines, each of the second data lines bypassing the light-transmitting area, crossing the routing area, and extending along the second direction in the display area; In the first direction, the second data lines and the first data lines are arranged alternately in sequence; The first conductive line further includes a plurality of auxiliary data lines, and the second conductive line further includes a plurality of data line leads, each of the auxiliary data lines is located in the routing area, and each of the data line leads is electrically connected to one of the auxiliary data lines and extends along the second direction within the routing area and the display area; Each of the second data lines includes one auxiliary data line and one data line lead line.

5. The array substrate according to claim 4, wherein: The first capacitance compensation pattern is disposed between two adjacent auxiliary data lines.

6. The array substrate according to claim 5, wherein: The second capacitance compensation pattern is disposed between the adjacent first data lines and the second data lines.

7. The array substrate according to claim 6, wherein: The second conductive line further includes a plurality of third data lines; Each of the third data lines bypasses the light-transmitting area, crosses the routing area, and extends along the second direction in the display area; In the first direction, the third data line is located on a side of the first data line and the second data line away from the light-transmitting area; The second capacitance compensation pattern is disposed between two adjacent third data lines.

8. A display panel comprising a color filter substrate, a liquid crystal layer, and an array substrate, wherein the liquid crystal layer is sandwiched between the color filter substrate and the array substrate, characterized in that: The array substrate is the array substrate according to any one of claims 1 to 7.

9. A display device, characterized in that: include: The display panel according to claim 8; a backlight module, the backlight module being located on a side of the display panel away from the display surface thereof, the backlight module being defined with a mounting hole penetrating the backlight module, the mounting hole being aligned with the light-transmitting area; as well as A camera module is installed in the installation hole and collects image information through the light-transmitting area.

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