Single-ended phase change memory device and reading method

Abstract

The present disclosure relates to a single-ended phase change memory device and a reading method. A phase change memory device includes: a memory array of PCM cells, a variable current generator, and a sense amplifier. The current generator includes a reference array of PCM cells programmed to be in a set resistance state. The phase change memory device also includes a decoder and a controller, the decoder is used to address each cell of the reference array so as to generate a corresponding plurality of setting current signals through a plurality of reference cells; the controller is configured to receive the setting current signal at an input, select a certain number of setting current signals with the lowest current value from a plurality of setting current signals, calculate an average value of the lowest current value, and adjust the reference current to be lower than the average value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Italian Patent Application No. 102018000009922, filed on October 30, 2018, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present invention relates to a phase change memory device and a method for reading a phase change memory device. Background Art

[0004] Non-volatile phase change memories (PCM) are known, which store information by exploiting the properties of a material that has the property of switching between multiple solid phases to display different electrical properties. For example, the material can switch between a disordered amorphous phase and a crystalline or polycrystalline phase, which displays a higher level of order relative to the amorphous phase. The two phases of the material are associated with resistivities having quite different values, and therefore with different values ​​of logical data stored in the material, making the material interesting for memory applications. For example, tellurium (Te), selenium (Se) or antimony (Sb), known as chalcogenide materials, can be advantageously used to produce phase change memory cells. Furthermore, Ge can also be used. x Sb y Te z Alloy (also called GST), which has the advantage that the phase change material obtained after the welding process can guarantee the integrity of the code (i.e. the integrity of the stored data), and can maintain the data over an extended temperature range. In particular, the following conclusions have been shown in the known art: for temperatures at the unit level above 150°C, the data can be maintained for 10 years.

[0005] The phase change is obtained by locally increasing the temperature of the phase change material by a resistive electrode (commonly referred to as a heater) arranged in contact with the corresponding area of ​​the phase change material. A selection device (e.g., a MOSFET) is connected to the heater, and the selection device enables a programming current to pass through the corresponding heater. This current generates the temperature required to cause the phase change through the Joule effect.

[0006] To program the cell to its low resistance state, in which the phase change material is in a crystalline state (referred to as the "SET" state), an electrical pulse is applied to heat the phase change material above its crystallization temperature. Alternatively, the material may be first heated to a temperature above the crystallization temperature and then slowly cooled to normal operating temperature. To set the cell to its high resistance state, in which the phase change material is in an amorphous phase (referred to as the "RESET" state), a current pulse is applied to heat the phase change material to melt the phase change material. By suddenly cutting off the current pulse, the phase change material rapidly cools to the amorphous phase of the phase change material, thereby generating a high resistance state.

[0007] During reading, the state of the chalcogenide material is detected by applying a voltage low enough not to cause overheating of the material, and then reading the value of the current flowing in the cell (so-called "current mode reading"). Considering that the current is proportional to the conductivity of the chalcogenide material, the state of the material can be determined, and therefore the data stored in the memory cell can be traced back.

[0008] As described in more detail below, reading is performed in a differential manner (i.e., the so-called "dual-ended" mode) or with a reference current provided by a reference current generator (the so-called "single-ended" mode). To perform the single-ended read mode, one input of the sense amplifier receives the current of the memory cell to be read, while the other input of the sense amplifier receives the reference current provided by the reference current generator.

[0009] It has been noted that GST phase change cells suffer from resistance drift. This effect results in resistance variations during the operating life of the cell. Therefore, it is not feasible to select a constant reference current throughout the operating life of the cell.

[0010] One possible solution to this problem relies on the use of a dual-end read mode, to perform a dual-end mode read, any data ("0" or "1") is stored in a memory cell in its direct form ("0" or "1" respectively) and in an associated memory cell in its complementary form ("1" or "0" respectively). When reading, one input of the sense amplifier receives the current of the "direct" memory cell that needs to be read, while the other input of the sense amplifier receives the current of the associated "complementary" memory cell.

[0011] However, because two memory cells are required to store a single data, ie, a single information bit, the required device area increases significantly relative to the single-ended read mode.

[0012] There is a need in the art to provide a phase change memory device and a method for reading a phase change memory device to overcome the above problems. Summary of the invention

[0013] A phase change memory device and a method for reading a phase change memory device are provided.

[0014] In one embodiment, a phase change memory device includes: a current generator configured to output a reference current; a memory array including a plurality of memory cells of a phase change material, the plurality of memory cells being programmable to be in a set resistance state and a reset resistance state, and the memory array being configured to: during a read operation of a memory cell among the plurality of memory cells, output a read current indicating the set resistance state or the reset resistance state of the memory cell being read; and a read stage coupled to the current generator and the memory array.

[0015] The read stage is configured to receive at inputs a reference current and a read current, compare the read current to the reference current, and output a result of such comparison indicative of logic data stored in the memory cell being read.

[0016] The current generator includes a reference array including a plurality of reference cells of a phase change material, wherein each reference cell is programmed to be in a set resistance state.

[0017] The phase change memory device also includes: a decoder for addressing each reference cell of the reference array so as to generate a corresponding plurality of setting current signals through the plurality of reference cells; and a controller configured to: receive the setting current signals at an input, select a certain number of setting current signals having the lowest current values ​​from the plurality of setting current signals, calculate an average value of the lowest current values, and adjust the reference current to be lower than the average value.

[0018] In one embodiment, a method for reading a phase change memory device is provided, the phase change memory device including a memory array including a plurality of memory cells of a phase change material programmable to be in a set resistance state and a reset resistance state. The method includes: controlling a current generator to output a reference current; during a read operation of a memory cell belonging to the plurality of memory cells, outputting a read current from the memory array indicating the set resistance state or the reset resistance state of the memory cell being read; supplying the reference current and the read current to a read stage coupled to the current generator and the memory array; comparing the read current with the reference current by the read stage; and outputting a result of the comparison by the read stage, the result indicating the logical data stored in the memory cell being read.

[0019] The current generator includes a reference array including a plurality of reference cells of a phase change material, wherein each reference cell is programmed to be in a set resistance state.

[0020] The method also includes: programming a reference cell to be in a set resistance state; addressing each reference cell of a reference array so as to generate a corresponding plurality of set current signals through a plurality of reference cells; inputting the set current signals into a controller; selecting, by the controller, a certain number of set current signals having the lowest current value from the plurality of set current signals; calculating, by the controller, an average value of the lowest current values; and adjusting the reference current to be lower than the average value.

[0021] In one embodiment, a phase change memory device includes: a current generator configured to output a reference current; a memory array including a plurality of memory cells of a phase change material, the plurality of memory cells being programmable to be in a set resistance state and a reset resistance state, and the memory array being configured to: during a read operation of a memory cell among the plurality of memory cells, output a read current indicating the set resistance state or the reset resistance state of the memory cell being read; and a comparison circuit configured to compare the read current with the reference current to output a result indicating logic data stored in the memory cell being read; wherein the reference current output by the current generator is generated in response to a plurality of first current signals generated by the reference cells of the phase change material being programmed to be in the set resistance state. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] For a better understanding of the present invention, preferred embodiments of the present invention will now be described, by way of non-limiting example only, and with reference to the accompanying drawings, in which:

[0023] Figure 1 schematically illustrates a portion of a memory device including a memory array and a reference array of PCM cells coupled to a sense amplifier for reading a selected cell;

[0024] Figure 2 The flowchart shows the Figure 1 The step of programming the PCM cells of the reference array of the memory device to be in a set state;

[0025] Figure 3 The flow chart shows Figure 1 A method for reading a memory device;

[0026] Figure 4 The flowchart shows the Figure 1 Method for drifting resistance of a PCM cell of a memory device;

[0027] Figure 5A-Figure 5C shows a scatter curve of memory cells programmed to be in a set state as a function of read current at successive moments;

[0028] Figure 6A-6C shows the distribution curves of memory cells programmed in set and reset states as a function of read current at successive moments;

[0029] Figure 7 Shown in Figure 3 A lookup table used in the method of

[0030] Figure 8A-8C Shows Figure 1 An alternative embodiment of a memory device. DETAILED DESCRIPTION

[0031] Figure 1 shows a portion of a non-volatile memory device 1, in particular, the non-volatile memory device 1 is of the phase change memory (PCM) type, Figure 1 Elements useful for understanding the present disclosure are shown limitedly.

[0032] In particular, the nonvolatile memory device 1 comprises: a memory array 2, which comprises a plurality of memory cells of a known type (not shown here), in particular, the known type is a GST alloy; a variable current generator 4, which comprises an array 4a of reference cells, and the variable current generator 4 is configured to generate a reference current i ref and a sense amplifier 6 having a first input port 6a and a second input port 6b, the first input port 6a being coupled to the memory array 2 to receive a read current i associated with a logic bit stored in a cell being read; read The second input port 6b is coupled to the variable current generator 4 to receive the reference current i ref .

[0033] The sense amplifier 6 is configured to perform a read operation on the current i read and the reference current i ref Comparison between.

[0034] The array of reference cells 4a includes a plurality (e.g., 33) of PCM cells (hereinafter referred to as "reference cells"), each of which is of the same type as the memory cells belonging to the memory array 2. Therefore, as long as the two groups of cells undergo the same (or similar) write operations, the memory cells belonging to the memory array 2 and the reference cells will experience comparable (ideally, the same) resistance drift during use. In this way, the current through the reference cells can be used to effectively track the resistance drift of the memory cells. This aspect will be better discussed later.

[0035] The memory cells are programmed (to a set (SET) state or a reset (RESET) state) using known techniques that are not discussed here and are not a part of the present invention.

[0036] Note that the resistance of cells in both the set and reset states tends to increase over time. According to one embodiment herein, the reference cell is programmed to be in the set state, since such an effect is more pronounced for cells in the set state when current mode reading is employed.

[0037] according to Figure 2 , each reference cell of array 4a is programmed to be in a set state. In particular, at step S1, the reference cell to be programmed is initialized to a reset state using conventional techniques. A set current pulse (e.g., about 300 μA) is used to heat the reference cell to above its crystallization temperature. To verify that the set current pulse positively causes a phase change in the reference cell, at step S3, a current i is generated through the reference cell by applying a constant voltage (e.g., in the range of 0.4 V-0.8 V) across the reference cell. v Then, in step S4, the current i v With the threshold current value i th For comparison, the threshold current value i th Indicates the current value used as a fixed threshold for Figure 2 During the cell programming step represented in , it is determined whether the reference cell is in a high logic value (set state) or a low logic value (reset state). th Usually in the range of tens of μA, for example 30 μA. If it is found that the current through the reference cell is less than the threshold current value i th (from Figure 2 If the “No” in step S4 is exited), a weak pulse (e.g., about 200 μA) lower than the previous setting current pulse is applied to the reference cell to further heat the reference cell. Then step S3 is repeated. If the current i v Above the threshold current value i th (Exit from "YES" of step S4), the reference cell has been successfully programmed to be in the set state, and the programming process for the reference cell is terminated.

[0038] After programming all reference cells belonging to the array of reference cells 4a, it is possible to program the reference cells 4a by using Figure 3 The information stored in the memory cell is read by the read process shown in FIG.

[0039] refer to Figure 3At step S10, the reference cells are read one by one by applying a constant voltage (eg, in the range of 0.4V-0.8V) across the reference cells, thereby generating a current indicative of the resistance value of the read cell, and thus the current indicative of the phase of the phase change material.

[0040] As is known, the programming process of any PCM cell (and therefore also of the reference cell) is such that, immediately after programming, the resistance value of the cell may not be the same; in other words, the resistance value may differ slightly from one cell to another. Therefore, the currents generated in step S10 may differ from one another. In fact, there are two main reasons for the variability of the currents generated by the cells in step S10; one is the spread of the programming results and the other is the resistance drift. The latter effect is due to the structural rearrangement of the crystalline material immediately after step S10, which may ultimately lead to an increase in the resistance of the phase change material. In particular, some of the reference cells being programmed may show current values ​​generated in step S10 that are lower than those of the reference cells. Figure 2 The threshold current value i described th .

[0041] In step S11, the corresponding currents of one or more (e.g., 3) reference cells (usually, those reference cells that experience higher resistance drift) showing the lowest current values ​​are obtained in the array 4a of reference cells. It should be noted that the current drift of the reference cells is related to the resistance drift of the memory cells (this assumption is particularly correct when all cells are manufactured in the same die using the same manufacturing process). Therefore, an indication of the resistance drift of the memory cells can be obtained from the analysis of the resistance drift of the reference cells.

[0042] In step S12, the average value of the lowest current values ​​acquired in step S11 is calculated. Figure 8A-8C The controller 12 schematically shown in FIG. 1 performs each step involving calculation. Then, in step S13, for example, according to the later reference Figure 7 In one embodiment described, the average value is used to obtain a reference current value.

[0043] Then, in step S14, the reference current value of step S13 is used to generate Figure 1 The variable current generator outputs Figure 1 The reference current i ref .

[0044] Considering that resistance drift is a continuous process, the reference current i ref is updated, in particular periodically. For example, a timer may be used to set (step S15) a time period T Read(e.g., several hundred milliseconds, such as 100ms-300ms), during which time period the reference current i ref Remain unchanged. In time period T Read After that, the reference current i ref Updates.

[0045] Then, in step S16, Figure 1 The sense amplifier 6 will read the current i read With the reference current i ref The comparison is made and the memory array 2 is read in a manner known per se. The reading process can continue until all relevant memory cells have been read (step S17) and / or during the entire time period T Read If no unit needs to be read, then Figure 3 The process detailed in will remain in "standby" mode until a new read is requested; when a new read is requested, block S17 is activated again.

[0046] When the time period T read When it expires, exit from "Yes" in step S18 and then execute step S19, which includes repeating the operations of steps S10-S12; therefore, during step S19, a new average value is obtained.

[0047] In step S20, the new average value is compared with the last calculated average value.

[0048] If the new average is comparable to the previous average (e.g., they have the same value, or they have values ​​that differ by an amount below a predefined threshold (e.g., less than 1%-10%), then the timer is again set to the time period T. Read (Exit from "Yes" in step S20), discard the new average value, and repeat the process from step S15.

[0049] Otherwise, the process exits from step S20 with a “No”, stores the new average value, and sets the reference current i ref Needs to be updated.

[0050] In order to update the reference current i ref , step S13 ( Figure 3 The dashed line in the figure), or in step S21, the previous reference current i ref According to another embodiment, step S21 may include reducing the previous reference current i ref Decrease by an amount proportional to the difference between the new average and the previous (previous) average.

[0051] Then, the process continues from step S14.

[0052] When all relevant memory cells have been read, the reading process ends, exiting from "No" in step S17.

[0053] exist Figure 4 The analysis that may be performed in step S13 to determine and calculate an appropriate value for the reference current is shown in FIG. 1 and may be performed on the array 2 of memory cells or on a test array that is similar in structure to the array 2. Reference will be made to the array 2 for description without loss of generality. Figure 4 The steps are not performed during the use of the memory (reading / programming steps), Figure 4 The steps refer only to possible steps that may be implemented to calculate the reference current to be actually used during reading of the relevant memory.

[0054] in a manner known per se or by an equivalent reference Figure 2 (Refer to the reference cell of array 4a) The step in question initializes the memory cell to the set state, ie, the state of S30.

[0055] In step S32, the memory cell is exposed to a high temperature (e.g., 180° C.) for a period of time (e.g., 1 hour) long enough to cause a change in resistance in the phase change material due to resistance drift. As long as the high temperature is below the crystallization temperature, heating the memory cell to the high temperature accelerates the resistance drift, and thus, a resistance drift that occurs in the order of years can be simulated in a short period of time (typically, on the order of several hours) at the high temperature.

[0056] Then, at step S34, a constant voltage is applied across the phase change material of each memory cell, or alternatively across a statistically significant number of memory cells, e.g., 50% of the memory cells belonging to array 2. The current associated with each cell generated in step S34 is then collected.

[0057] Figure 5A It is shown that at the first time t1, as the reading current i read The scatter curve of the memory cell as a function of Figure 5A As can be seen in , different memory cells may exhibit different read currents, thus resulting in a broadening of the curve along the read current axis.

[0058] At successive moments t2…t N repeat Figure 4 Steps S32-S34.

[0059] Figure 5B and Figure 5C It means that when t2>t1 and tN > At different moments of t2, Figure 5A The scatter curves of the memory cells shown in FIG. 5 are used to show the effect of resistance drift, which shifts the distribution toward lower current values ​​over time.

[0060] When at the Nth iteration (time t N ) and the lowest measured read current at the (N+1)th iteration (time t N+1 ) when the difference between the lowest measured reading currents falls below a predefined threshold ε, Figure 4 The process ends, from Figure 4 The "yes" of step S36 exits. Those skilled in the art can freely choose this threshold, for example, it is equal to a fraction of 1μA (for example, 0.1μA-0.5μA). The term "lowest read current value" can also be interpreted as the average value of the lowest read currents of multiple (for example, 10% of the total number of memory cells considered) cells in the set state.

[0061] The process performed to generate a scatter curve for memory cells programmed to the set state can be repeated to generate a corresponding scatter curve for memory cells programmed to the reset state. In this case, Figure 4 Step S30 requires programming the memory cells to be in a reset state in a manner known per se. Figure 6A-6C shows the "N" time intervals t1-t N During the scatter plots of the set state and the reset state. It can be appreciated that cells in the reset state show lower read current values ​​than cells in the set state, and the resistance drift of cells in the reset state is similar to the resistance drift of cells in the set state (but typically by different amounts).

[0062] Reference current i ref The value of is set between the lowest read current value of the cell in the set state and the highest read current value of the cell in the reset state (for example, set to the average value between the lowest read current value of the cell in the set state and the highest read current value of the cell in the reset state). The terms "lowest read current value" and "highest read current value" may also be interpreted as the average value of the lowest read currents of multiple (for example, 10% of the total number of memory cells considered) of the cells in the set state, and the average value of the highest read currents of multiple (for example, 10% of the total number of memory cells considered) of the cells in the reset state, respectively.

[0063] According to the above, it is obvious that the reference current i ref More specifically, the reference current i refAs a function of the resistance drift of the phase change material of the memory cell, this is advantageous for the purpose of reading the memory cell.

[0064] One embodiment of the present invention contemplates implementation via a lookup table Figure 3 In step S13, for example, the lookup table is stored in a storage device, for example, Figure 8A-8C The lookup table receives the average value obtained from step S12 at the input and outputs the reference current i ref The actual value of is used as the output from step S13. Since the average value of the current obtained from step S12 varies with the resistance drift of the memory cell, the reference current i can be effectively mapped using a predefined lookup table. ref More specifically, according to one embodiment, the reference current i ref The corresponding values ​​of are associated with the corresponding ranges of the average values ​​of the current.

[0065] Figure 7 An exemplary lookup table 10 is shown in graphical form for the sole purpose of improving understanding of the present disclosure and not for limiting the present invention. In this particular embodiment, a reference current i equal to 5 μA ref The value corresponds to an average current between 0 μA and 10 μA. The reference current i of 8 μA ref The value corresponds to an average current between 10 μA and 20 μA. The 12 μA reference current i ref The values ​​correspond to current average values ​​between 20 μA and 30 μA.

[0066] By understanding Figure 6A-6C At each time interval t1-t N The reference current i output by the lookup table 10 can be adjusted during the design phase. ref As discussed above, for each time interval t1-t N , reference current i ref is set between the lowest read current value for a cell in a set state and the highest read current value for a cell in a reset state.

[0067] Alternative embodiments contemplate reference currents i that do not require a lookup table ref , that is, by understanding the scatter curves of the set state and the reset state during the use of the non-volatile memory device 1 and according to Figure 3 To this end, some of the reference cells are programmed to be in a set state, and the remaining reference cells are programmed to be in a reset state.

[0068] Obtain the corresponding currents of one or more (e.g., three) reference cells (i.e., those that experience higher resistance drift) in the array 4a of reference cells programmed to be in the set state that show the lowest current values. Calculate the average value i of the lowest current values ​​thus obtained m_SET .

[0069] The corresponding currents of one or more (eg, three) reference cells showing the highest current values ​​in the array 4a of reference cells programmed to be in the reset state are also acquired. The average value i of the highest current values ​​thus acquired is calculated. m_RESET .

[0070] Reference current i ref is set at the mean value i m_SET and the average value i m_RESET For example, it is set to (i m_SET +i m_RESET ) / 2.

[0071] As a further embodiment, the dependency of the temperature to which the memory cell is subjected during use and / or the leakage current may also be taken into account. The contribution of temperature and leakage is obtained in a manner known per se. The temperature and / or leakage contribution may then be taken into account in the reference current value of step S13 by adding the temperature and / or leakage contribution. Figure 3 The reference current i in step S14 ref is being generated.

[0072] like Fig. 8A As shown in , the non-volatile memory device 1 can be organized into multiple arrays 2 of memory cells and corresponding multiple arrays 4a of reference cells. Each array 2 of memory cells and corresponding array 4a of reference cells is accessed by the same column decoder 15. The row decoder 16 is shared by all arrays 2, 4a.

[0073] like Figure 8B As shown in an alternative embodiment of , the array of reference cells 4a is shared between all multiple arrays 2. In one embodiment, array 4a shares row decoders 16 with multiple arrays 2 and column decoders 15 with one array 2. Other embodiments are possible.

[0074] However, according to Fig. 8A and Figure 8B In an embodiment, if one of array 2 and array 4a is accessed, the other of array 2 or 4a cannot be read / written (e.g., because array(s) 4a may share one or more decoders with array(s) 2).

[0075] exist Figure 8C An alternative embodiment is shown in Figure 8A-B The problem of implementation of the invention. Figure 8C Represents a non-volatile memory device 1 organized as a plurality of arrays 2 of memory cells, which are addressed by a single row decoder 16 and a column decoder 15 for each array. The array 4a of reference cells is external and physically and / or electrically decoupled from the memory itself. The array 4a is accessed by its own row decoder 16a and its own column decoder 15a. Thus, the array 2 can be read / written in parallel with the array 4a.

[0076] From what has been described and illustrated above, the advantages of the described embodiments are apparent.

[0077] In particular, by avoiding differential reading, each memory cell can store one bit resulting in an advantage in optimizing the device area.

[0078] Furthermore, embodiments allow tracking of the distribution of memory cells in the set and reset states that are subject to resistance drift, thus taking into account time-dependent and related effects that would modify the current read across the memory cells during a read process.

[0079] Furthermore, performing digital reading of the memory cells at predefined time intervals will result in reduced power consumption and implementation of a simple system.

[0080] According to one embodiment (in Figure 8C If the array 4a of reference cells is located in an electrically and physically independent region relative to the array 2 of memory cells, the reading process of the reference cells can be performed in parallel with the reading process of the memory cells. This possibility helps to further reduce the time consumption.

[0081] Finally, it is evident that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present invention as defined in the appended claims.

Claims

1. A phase change memory device, comprising: a current generator configured to output a reference current; a memory array comprising a plurality of memory cells of a phase change material, the plurality of memory cells being programmable to be in a set resistance state and a reset resistance state, and the memory array being configured to: during a read operation of a memory cell among the plurality of memory cells, output a read current indicative of the set resistance state or the reset resistance state of the memory cell being read; as well as a read stage coupled to the current generator and the memory array, the read stage configured to: receive the reference current and the read current, and compare the read current with the reference current to output a result indicative of logic data stored in the memory cell being read; wherein the current generator comprises a reference array, the reference array comprising a plurality of reference cells of the phase change material, the plurality of reference cells being programmed to be in the set resistance state; a decoder configured to address the reference cells of the reference array so that a corresponding plurality of set current signals are generated; as well as The controller is configured to receive the plurality of setting current signals, select a certain number of the setting current signals having the lowest current values, calculate an average value of the lowest current values, and adjust the reference current to be lower than the average value. 2 . The phase change memory device of claim 1 , wherein the controller adjusts the reference current by using the average value to access a lookup table to retrieve a corresponding value of the reference current.

3. The phase change memory device of claim 2, wherein the lookup table is pre-computed and stored in a memory device coupled to the controller. 4 . The phase change memory device of claim 1 , wherein the controller is further configured to maintain the adjusted reference current unchanged during a time interval. 5 . The phase change memory device of claim 4 , wherein the controller is further configured to reduce a value of the reference current when the time interval expires.

6. The phase change memory device of claim 4 , wherein the controller is further configured to perform the following operations when the time interval expires: receiving a plurality of updated setting current signals, selecting a certain number of the updated setting current signals having the lowest current values, calculating an updated average value of the lowest current values, and if a difference between the updated average value and the average value is greater than a threshold, adjusting the reference current to be lower than the updated average value.

7. The phase change memory device of claim 1 , wherein the reference array further comprises a plurality of additional reference cells of phase change material, wherein each additional reference cell is programmed to be in the reset resistance state, wherein the decoder is further configured to address the further reference cells so that a corresponding plurality of reset current signals are generated, and The controller is further configured to: receive the reset current signal, select a certain number of reset current signals with the highest current values, and calculate an average value of the highest current values, The controller adjusts the reference current by setting the reference current between the average value of the highest current value and the average value of the lowest current value.

8. A method for reading a phase change memory device, the phase change memory device comprising a phase change memory array, the method comprising: outputting a read current indicating a set resistance state or a reset resistance state of the memory cell being read during a read of a memory cell of the phase change memory array, the phase change memory array comprising a plurality of memory cells of a phase change material, the plurality of memory cells being programmable to be in the set resistance state and the reset resistance state; generating a reference current using a current generator; comparing the read current with the reference current; as well as outputting a result of the comparison, the result indicating logic data stored in the memory cell being read; The generating of the reference current comprises: programming a plurality of reference cells of the phase change material to be in a set resistance state; addressing the reference cell so that a corresponding plurality of setting current signals are generated; selecting a certain number of the set current signals having the lowest current values; calculating an average of the lowest current values; and The reference current is adjusted to be lower than the average value.

9. The method of claim 8, wherein adjusting the reference current comprises: The average value is used to access a lookup table to retrieve a corresponding value for the reference current.

10. The method of claim 9, comprising the step of pre-calculating the look-up table and storing the look-up table in a storage device. The method of claim 8 , further comprising maintaining the adjusted reference current constant over a time interval.

12. The method according to claim 11, further comprising: When the predefined time interval expires, the value of the reference current is reduced.

13. The method according to claim 12, further comprising: When the pre-defined time interval expires: obtaining a plurality of updated setting current signals; selecting a certain number of updated set current signals having the lowest current values; calculating an updated average of the lowest current values ​​of the updated set current signal; determining whether a difference between the updated average value and the average value is greater than a threshold; as well as If so, the reference current is adjusted to be lower than the updated average value.

14. The method according to claim 8, further comprising: programming a plurality of additional reference cells of the phase change material to be in a reset resistance state; addressing the further reference cells so that a corresponding plurality of reset current signals are generated; selecting a certain number of the reset current signals having the highest current values; Calculating an average value of the highest current values; as well as The reference current is adjusted to be between the average value of the highest current value and the average value of the lowest current value.

15. A phase change memory device, comprising: a current generator configured to output a reference current; a memory array comprising a plurality of memory cells of a phase change material, the plurality of memory cells being programmable to be in a set resistance state and a reset resistance state, and the memory array being configured to: during a read operation of a memory cell among the plurality of memory cells, output a read current indicative of the set resistance state or the reset resistance state of the memory cell being read; as well as a comparison circuit configured to compare the read current with the reference current to output a result indicative of logic data stored in the memory cell being read; A controller configured to receive a plurality of first current signals, select a certain number of the first current signals having the lowest current values, calculate an average of the lowest current values, and adjust the reference current to be lower than the average, wherein the plurality of first current signals are generated by reference cells of the phase change material programmed to be in the set resistance state.

16. A phase change memory device, comprising: a current generator configured to output a reference current; a memory array comprising a plurality of memory cells of a phase change material, the plurality of memory cells being programmable to be in a set resistance state and a reset resistance state, and the memory array being configured to: during a read operation of a memory cell among the plurality of memory cells, output a read current indicative of the set resistance state or the reset resistance state of the memory cell being read; as well as a comparison circuit configured to compare the read current with the reference current and output a result indicative of logic data stored in the memory cell being read; A controller configured to: receive a plurality of first current signals, and a plurality of second current signals, select a certain number of the first current signals having the lowest current value, calculate a first average value of the lowest current value, receive the plurality of second current signals, select a certain number of the second current signals having the highest current value, calculate a second average value of the highest current value, and adjust the reference current to be between the first average value and the second average value, wherein the first current signal is generated by a reference cell of the phase change material programmed to be in the set resistance state, and the second current signal is generated by a reference cell of the phase change material programmed to be in the reset resistance state.

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