Method for forming semiconductor devices

Abstract

This document describes a semiconductor device comprising a finned field-effect transistor with a diced metal gate and a method for forming the semiconductor device. The method includes forming a diced metal gate protective cap structure on top of a diced metal gate dummy gate plug in a semiconductor substrate. The diced metal gate protective cap structure prevents the consumption and damage of dummy filler material in the diced metal gate region, and also prevents the formation of unwanted polymers and / or residual byproducts on the upper surface of the epitaxial region of the finned field-effect transistor during the etching process.

Description

Technical Field

[0001] This application relates to semiconductor devices and methods of forming thereof, and more particularly to semiconductor devices and methods of forming thereof having fin field-effect transistors with diced metal gates. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the multiple material layers to form circuit components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to shrink the minimum structural size to improve integrated circuits containing various electronic components such as transistors, diodes, resistors, capacitors, or the like, allowing more components to be integrated into a given area. However, as the minimum structural size shrinks, additional problems arise that need to be addressed. Summary of the Invention

[0004] An embodiment of this application provides a method for forming a semiconductor device, comprising: forming an opening in a diced metal gate region of the semiconductor device; depositing a first refill material in the opening to form a diced metal gate plug; performing chemical mechanical polishing to expose a metal gate structure; etching the first refill material to form a recess in the diced metal gate plug; filling the recess with a second refill material to form a cap structure on the first refill material of the diced metal gate plug; and forming a plurality of contacts to a plurality of source / drain regions of a plurality of adjacent devices separated by the diced metal gate plug.

[0005] An embodiment of this application provides a method for forming a semiconductor device, comprising: forming a first metal gate on a first semiconductor fin; forming a first opening through the first metal gate; filling the first opening with a first dielectric material; planarizing the first dielectric material and the first metal gate; recessing the first dielectric material to form a second opening; filling the second opening with a second dielectric material; and planarizing the second dielectric material and the first metal gate.

[0006] An embodiment of this application provides a semiconductor device comprising: a plurality of metal gate structures located in an interlayer dielectric layer on a substrate; and an isolation structure located between the metal gate structures, wherein the isolation structure includes a dielectric cap portion located on a dielectric plug portion, wherein the isolation structure is at least partially buried in the interlayer dielectric layer and electrically isolates and physically separates the source / drain of a first device and the source / drain of a second device in the interlayer dielectric layer. Attached Figure Description

[0007] Figure 1In some embodiments, some initial fabrication steps form a semiconductor fin in a substrate and form a metal gate on the channel region of the semiconductor fin.

[0008] Figure 2 These are deposition processes in some embodiments.

[0009] Figure 3 These are deposition and patterning processes in some embodiments.

[0010] Figure 4 This refers to the groove patterning process in some embodiments.

[0011] Figure 5 These are deposition processes in some embodiments.

[0012] Figure 6 These are removal processes in some embodiments.

[0013] Figure 7 In some embodiments, a process is used to form multiple cut metal gate openings that pass through multiple metal gates.

[0014] Figure 8 In some embodiments, the removal of polymeric byproducts is achieved through a wet cleaning process.

[0015] Figure 9 This is a refilling process in some embodiments.

[0016] Figure 10 These are some examples of planarization processes.

[0017] Figure 11 These are recessed processes in some embodiments.

[0018] Figure 12 This is a refilling process in some embodiments.

[0019] Figure 13 This is a planarization process in some embodiments.

[0020] Figure 14 These are deposition processes in some embodiments.

[0021] Figure 15A and 15B These are photolithography processes in some embodiments.

[0022] Figure 16 In some embodiments, this is the removal process that forms the contact opening.

[0023] Figure 17 In some embodiments, the removal process that forms the contact opening on the source / drain region follows... Figure 16 Detailed view of the Y-section shown.

[0024] Explanation of reference numerals in the attached figures:

[0025] Tangents A-A', B-B', and C-C'

[0026] D1 First Depth

[0027] D2 Second Depth

[0028] HH Final Cover Height

[0029] H1 First Height

[0030] H2 Second Height

[0031] H3 Third Height

[0032] ILDH Final Height

[0033] RD1 First Depression Depth

[0034] RD2 Second Depression Depth

[0035] Th1 First Thickness

[0036] Th2 Second Thickness

[0037] W401 X W401 Y W501 X W501 Y width

[0038] W701 X1 First width

[0039] W701 X2 Second width

[0040] 101 substrate

[0041] 103 Fins

[0042] 105 Spacers

[0043] Quarantine Zones 107 and 1303

[0044] 108 interlayer dielectric layer

[0045] 109 Metal Gate

[0046] Part 1 of 109a and 113a

[0047] Part 2 of 109b and 113b

[0048] 111 Source / Drain Region

[0049] 111a First source / drain region

[0050] 111b Second source / drain region

[0051] 113 Interlayer Dielectric Layer

[0052] 201, 1401 contact etching stop layer

[0053] 203, 1403 hard mask layer

[0054] Openings in 301, 401, 1503, and 1603

[0055] 303 photoresist layer

[0056] 501 Narrow opening

[0057] 503 Masking Layer

[0058] 701 Cutting Metal Gate Trench

[0059] 703 Residual by-product materials

[0060] 901 First Cut Metal Gate Refill Material

[0061] 1001 Cut the metal gate and then fill the plug

[0062] 1101 Shallow trench

[0063] 1201 Second Cut Metal Gate Refill Material

[0064] 1301 Cut metal gate cap

[0065] 1501 photoresist layer

[0066] 1605 First contact point

[0067] 1700 and 1800 sections Detailed Implementation

[0068] The various embodiments provided below can implement different structures of this disclosure. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit it. For example, a description of forming a first component on a second component includes situations where the two are in direct contact, or where there are additional components between them that are not in direct contact. Furthermore, reference numerals may be repeated in various examples of this disclosure, but these repetitions are for simplification and clarity only and do not represent a consistent correspondence between units with the same reference numerals in different embodiments and / or arrangements.

[0069] Furthermore, spatial relative terms such as "below," "under," "lower," "above," "above," or similar terms can be used to simplify the description of the relative relationship between one unit (or structure) and another unit (or structure) in the illustration. Spatial relative terms can be extended to devices used in other directions, rather than being limited to the direction shown in the illustration. Devices can also be rotated 90° or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0070] This application relates to semiconductor devices and methods of forming them, and more particularly to semiconductor devices and methods of forming them having fin field-effect transistors with diced metal gates. The embodiments described herein relate to forming a plurality of fin field-effect transistors in a wafer. Figures 1 to 17 Each of these shows the intermediate steps in the fabrication of a fin field-effect transistor. Figures 1 to 16 The diagram shows three cross-sectional views along the intermediate structure, and the method of forming the intermediate structure employs intermediate steps as shown in the individual figures. The first cross-sectional view is an X-section passing through the tangent A-A' shown in the associated second and third cross-sectional views, as shown in the Y-section view. The second cross-section is a Y-section of the gate structures in the region of the cut metal gate of the individual intermediate structure (passing through the tangent B-B' shown in the associated X-section view), its direction perpendicular to the fins to which the fin field-effect transistor will be formed. The third cross-section is a second Y-section of the region of the cut metal gate of the individual intermediate structure related to the zeroth interlayer dielectric layer and epitaxial interface (passing through the tangent C-C' shown in the associated X-section view), its direction perpendicular to the fins to which the fin field-effect transistor will be formed. The first cross-section is an X-section of the series of gate structures formed in the individual intermediate structure, its direction parallel to the fins to which the fin field-effect transistor will be formed.

[0071] Figure 1 The display substrate 101 and some initial steps for forming fin field-effect transistors include patterning a plurality of fins 103 from the substrate 101. The substrate 101 may be a silicon substrate, but other substrates such as a semiconductor-on-insulator (SBI) substrate, a strained SBI substrate, or a silicon-germanium-on-insulator (SIG) substrate may also be used. The substrate 101 may be a p-type semiconductor, but in other embodiments, the substrate 101 may be an n-type semiconductor. The fins 103 may be formed using any suitable method to form trenches. For example, the fins may be patterned using one or more photolithography processes, such as double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography with self-alignment processes, resulting in a smaller pattern spacing than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate, and the sacrificial layer is patterned using a photolithography process. A spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the fins are patterned using the remaining spacers.

[0072] However, those skilled in the art should understand that the above-described process and materials for forming a series of fins are merely one example of the process and not the only embodiment. Any suitable process can be used to form the fins 103, including any number of masking and removal steps. Once the fins 103 are formed, they can be used to form the channel regions and source / drain regions of multiple fin field-effect transistors, as described below. Although Figure 1 Only two pairs of fins 103 formed from the substrate 101 are shown, but any number of fins 103 can be used.

[0073] After the fins 103 are formed in the substrate 101, isolation regions 107, such as shallow trench isolation regions, can be formed to isolate the fins 103 from other regions in the substrate 101. In this way, the trenches can be filled with a dielectric material, and the dielectric material in the first trench can be recessed to form the isolation region 107. The dielectric material can be an oxide material, a high-density plasma oxide, or the like. After cleaning the trench liner layer as appropriate, the dielectric material can be formed using chemical vapor deposition, high-density plasma chemical vapor deposition, or other suitable formation methods.

[0074] The trench filling method can overfill the trench and substrate 101 with dielectric material, and then remove the excess material outside the trench and fin 103 using a suitable process such as chemical mechanical polishing, etching, a combination of the above, or similar processes. In one embodiment, the removal process removes any dielectric material on the fin 103, exposing the surface of the fin 103 for subsequent processing steps.

[0075] Once the dielectric material is filled into the trench, it can then be recessed below the surface of the fin 103. A recessing step can be performed to expose at least a portion of the sidewalls of the fin 103 adjacent to the upper surface of the fin 103. Methods for recessing the dielectric material include wet etching of the upper surface of the fin 103 with an etchant such as hydrofluoric acid (but other etchants such as hydrogen can also be used), or other methods such as reactive ion etching, dry etching with ammonia and / or nitrogen trifluoride as the etchant, chemical oxide removal, or dry chemical cleaning. The distance the dielectric material is recessed from the surface of the fin 103 can be approximately... to approximately Between, for example, about In an additional embodiment, the recessing step may also remove any residual dielectric material on the fin 103, ensuring that the fin 103 is exposed for subsequent processes.

[0076] The above steps are only part of the overall process flow for filling the recess with dielectric material. For example, a padding step, a cleaning step, an annealing step, a gap-filling step, a combination of the above, and similar steps can also be used to form the dielectric material and fill the trench with the dielectric material. All possible process steps are fully included within the scope of this embodiment.

[0077] After forming the isolation region 107, a dummy gate dielectric layer (or interface oxide layer), a dummy gate layer on the dummy gate dielectric layer, and a dummy gate spacer layer may be formed on each fin 103. In one embodiment, the dummy gate dielectric layer is formed by thermal oxidation, chemical vapor deposition, sputtering, or any other suitable method known in the art for forming a gate dielectric layer. The thickness of the dummy gate dielectric layer on the top of the fin 103 may differ from the thickness of the dummy gate dielectric layer on the sidewalls of the fin 103, depending on the technique used to form the dummy gate dielectric layer.

[0078] The material of the dummy gate dielectric layer may include silicon oxide or silicon oxynitride, and its thickness may be between approximately to approximately Between, for example, about The dummy gate dielectric layer can be composed of a material with a high dielectric constant (e.g., a dielectric constant greater than about 5), such as lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, or a combination thereof, and its equivalent oxide thickness is between approximately to approximately Between, for example, less than or equal to approximately In addition, any combination of silicon oxide, silicon oxynitride, and / or materials with high dielectric constant can also be used for the dummy gate dielectric layer.

[0079] The dummy gate layer may comprise a conductive material, such as polysilicon (e.g., dummy polysilicon), tungsten, aluminum, copper, aluminum-copper, titanium, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, combinations thereof, or similar materials. The dummy gate layer may be deposited using chemical vapor deposition, sputtering deposition, or other suitable techniques for depositing conductive materials. The thickness of the dummy gate layer may be approximately [missing information - likely a number]. to approximately Between. The dummy gate layer may have an uneven upper surface and may be planarized before the patterning or etching process of the dummy gate layer. In this case, ions may or may not be introduced into the dummy gate layer. For example, ions may be introduced by ion implantation techniques.

[0080] Once the dummy gate dielectric layer and the dummy gate layer are formed, they can be patterned to form a series of dummy gates on the fin 103. Each dummy gate defines a plurality of channel regions located on each side of the fin 103 beneath the dummy gate dielectric layer. The dummy gates can be formed using any suitable deposition and photolithography technique to deposit and pattern a gate mask on the dummy gate layer. The gate mask can combine any suitable masking and sacrificial material, such as, but not limited to, silicon oxide, silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbonate, and / or silicon nitride, and its deposition thickness can be between approximately to approximately Between them, a dry etching process can be used to etch the dummy gate layer and the dummy gate dielectric layer to form a patterned dummy gate.

[0081] Once the dummy gate is patterned, spacers 105 can be formed. Spacers 105 can be formed on both sides of the dummy gate. For example, spacers 105 can be formed by compliantly depositing a spacer layer onto the previously formed structure. The spacer layer can comprise silicon oxycarbonitrile, silicon nitride, oxide oxynitride, silicon carbide, silicon oxynitride, silicon oxycarbonitrile, oxide, or the like, and can be formed by any suitable method for forming such a layer, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, sputtering, or any other suitable method. The spacer layer and isolation region 107 can comprise different dielectric materials with different etch properties, or the same dielectric material. Spacers 105 can then be patterned, for example, by removing the spacer layer from the horizontal surface of the structure by one or more etch passes to form spacers 105.

[0082] Once spacer 105 is formed, the dummy gate and the portion of fin 103 not protected by spacer 105 can be removed. The removal method can be reactive ion etching using the dummy gate and dummy gate spacer layer as a hard mask, or any other suitable removal process. Removal can continue until fin 103 is flush with or below the upper surface of the shallow trench isolation region.

[0083] Once a portion of fin 103 is removed, a hard mask is placed and patterned to cover a series of dummy gates, and fin 103 is regrowed to form the source / drain regions 111 of the fin field-effect transistor. The method for regrowing fin 103 may involve selectively epitaxially growing the material of fin 103. In an embodiment where fin 103 comprises silicon and the fin field-effect transistor is a p-type device, the material for regrowing the source / drain regions 111 may be silicon, silicon-germanium, or silicon phosphide, and its lattice constant may differ from that of the channel region. The epitaxial growth process may employ precursors such as silane, dichlorosilane, germanane, or the like, and may last from approximately 5 minutes to approximately 120 minutes (e.g., approximately 30 minutes). In other embodiments, the source / drain region 111 may comprise materials such as gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, indium antimonide, gallium arsenide phosphide, aluminum gallium nitride, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, combinations thereof, or the like.

[0084] Once the source / drain regions 111 are formed, suitable dopants can be implanted into them to supplement the dopants in the fins 103. For example, p-type dopants such as boron, gallium, indium, or the like can be implanted to form a p-type metal-oxide-semiconductor device. In other embodiments, n-type dopants such as phosphorus, arsenic, antimony, or the like can be implanted to form an n-type metal-oxide-semiconductor device. These dopant implantation methods can employ a dummy gate and spacer 105 as a mask. However, any other suitable process, step, or similar parameters can be used to implant the dopants. For example, multiple implantation processes can be performed using various combinations of spacers and pads to form source / drain regions with specific shapes or characteristics for a specific purpose. Any of these processes can be used to implant dopants, and the foregoing does not limit the embodiments of this application to the steps described above.

[0085] At this point, the hard mask covering the dummy gate during the formation of the source / drain region 111 can be removed. In one embodiment, the hard mask can be removed using a wet etching process or a dry etching process, which is selective for the material of the hard mask. However, any suitable removal process can be used.

[0086] Once the hard mask is removed, an etch stop layer can be deposited over the source / drain region 111 and between the spacer 105. In one embodiment, the etch stop layer may be a dielectric material such as silicon nitride, silicon carbonitride, or silicon carbonitride, and its deposition in the deposition chamber may employ one or more passes of chemical vapor deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, or similar deposition processes. However, any suitable material and any suitable process can be used to deposit the etch stop layer.

[0087] Next, an interlayer dielectric layer 113, such as the zeroth interlayer dielectric layer, is deposited on the semiconductor substrate 101. In some embodiments, the interlayer dielectric layer 113 may comprise a material such as silicon oxide or borosilicate glass, but any suitable dielectric layer may also be used. The interlayer dielectric layer 113 may be formed using a chemical vapor deposition process such as plasma-assisted chemical vapor deposition, but any other suitable process such as low-pressure chemical vapor deposition may also be used.

[0088] Once the interlayer dielectric layer 113 is formed, it can be annealed using a first annealing process. In one embodiment, the first annealing process can be thermal annealing, which involves heating the substrate 101 and the interlayer dielectric layer 113 in a furnace under an inert gas atmosphere. The temperature of the first annealing process is between about 200°C and about 1000°C (e.g., about 500°C), and it can last from about 60 seconds to about 360 minutes (e.g., about 240 minutes).

[0089] After deposition and annealing, the interlayer dielectric layer 113 can be planarized, exposing the dummy gate on its planarized surface. Once the dummy gate is exposed, it can be removed using a wet etching process and replaced with a metal gate 109. For example, the metal gate may include a high-dielectric-constant gate dielectric layer, one or more conductance barrier layers, one or more work function layers, and a conductive filler material.

[0090] In some embodiments, the high-dielectric-constant gate dielectric layer comprises materials such as hafnium oxide, zirconium oxide, hafnium-zirconium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium silicon oxide, hafnium-zirconium silicon oxide, aluminum oxide, hafnium aluminum oxide, hafnium aluminum nitride, zirconium aluminum oxide, lanthanum oxide, titanium oxide, ytterbium oxide, or the like, and may be a single layer or composite layer formed by deposition processes such as atomic layer deposition. However, any suitable material and any suitable process can be used to form the high-dielectric-constant gate dielectric layer.

[0091] In some embodiments, one or more diffusion barrier layers and one or more work function layers may be formed as stacked layers. For example, the barrier layer may be a titanium nitride layer, which may or may not be doped with silicon. In an example of forming a p-type fin field-effect transistor with individual metal gates 109, the work function layer in the stacked layer of the individual metal gates 109 may comprise titanium, aluminum, titanium aluminum, titanium aluminum nitride, tantalum, tantalum nitride, titanium aluminum carbide, tantalum aluminum carbide silicon, tantalum aluminum carbide, titanium silicon nitride, or the like. In an example of forming an n-type fin field-effect transistor with individual metal gates 109, the work function layer in the stacked layer of the individual metal gates 109 may comprise titanium nitride, tantalum nitride, titanium aluminum, tungsten, tantalum, nickel, platinum, or the like. In these embodiments, a barrier layer such as another titanium nitride layer may be formed after depositing the work function layer.

[0092] In some embodiments, the conductive filler material may be composed of tungsten, cobalt, copper, ruthenium, aluminum, or the like. The conductive filler material is deposited on a stack of high dielectric constant gate dielectric layers, one or more conductive barrier layers, and one or more work functions to fill or overfill the reserved spaces between the individual spacers 105 of the individual metal gates 109.

[0093] Once the metal gate 109 is deposited in layers and the conductive filler material is completely filled (or overfilled) into the reserved space, a chemical mechanical polishing (CMP) process is used to planarize the material. The CMP process can thin the material of the metal gate 109, the individual spacers 105, and the interlayer dielectric layer 113 until the planarized surface of the interlayer dielectric layer 113 exposes the planarized surface of the metal gate 109 and the individual spacers 105.

[0094] Once the interlayer dielectric layer 113 is planarized and the flat surfaces of the metal gate 109 and individual spacers 105 are exposed, the interlayer dielectric layer 113 can be annealed again using a second annealing process. In one embodiment, the second annealing process involves heating the substrate 101 and the interlayer dielectric layer 113 under an inert gas in a furnace. The temperature of the second annealing process can be between about 200°C and about 1000°C (e.g., about 500°C), and the duration can be from about 60 seconds to about 360 minutes (e.g., about 240 minutes).

[0095] Figure 2 It is to form a cut metal gate through Figure 1 Some initial steps of one or more metal gates 109 in the intermediate structure shown. Once the metal gates 109 are planarized, a series of hard masking layers can be formed on the planarized surface of the interlayer dielectric layer 113 and the metal gates 109.

[0096] In some embodiments, the first layer of a series of masking layers may be a contact etch stop layer 201. The contact etch stop layer 201 may be formed on the planarized surface of the metal gate 109 and the interlayer dielectric layer 113, and its formation method may be the deposition of materials such as silicon, titanium nitride, silicon nitride, silicon oxide, combinations thereof, or the like, and the deposition method may be atomic layer deposition, plasma-assisted chemical vapor deposition, chemical vapor deposition, or similar processes. However, any suitable material and any suitable method may be used to form the contact etch stop layer 201.

[0097] A hard mask layer 203 may be deposited on the contact etch stop layer 201 as the second layer in a first series of mask layers. The hard mask layer 203, formed on the contact etch stop layer 201, may be composed of a second hard mask material such as silicon nitride, silicon oxide, a combination thereof, or the like. The second hard mask material used to form the hard mask 203 is different from the first hard mask material used to form the contact etch stop layer 201. In this way, the contact etch stop layer 201 can serve as an etch stop layer for subsequent patterning of the mask layer 203. In some embodiments, the hard mask layer 203 may be placed on the contact etch stop layer 201 using deposition methods such as atomic layer deposition, plasma-assisted chemical vapor deposition, chemical vapor deposition, or similar methods. However, any suitable material and any suitable method may be used to form the hard mask layer 203. However, any suitable material and process may be used to form the hard mask layer 203 in the first series of hard mask layers.

[0098] like Figure 3As shown, a photoresist layer 303 is deposited on the hard mask layer 203, and the photoresist layer 303 is patterned to form an opening 301 through the photoresist layer 303. In an embodiment, the photoresist layer 303 may be deposited on the hard mask layer 203 as the third layer of the first series of mask layers. The photoresist layer 303 can be deposited using any suitable deposition process to have any suitable thickness, and the photoresist layer 303 can be patterned using any suitable photolithography method to form an opening 301 through the photoresist layer 303, exposing the surface of the hard mask layer 203 of the first series of hard mask layers in the region above one or more metal gates 109.

[0099] like Figure 4 As shown, the first etchant is used to... Figure 3 The pattern of the photoresist layer 303 is transferred to the hard mask layer 203 to form a pattern of opening 401 through the hard mask layer 203. In some embodiments, the first etchant may be a reactive gas that has a greater etch selectivity for the second hard mask material used to form the hard mask layer 203 than for the first hard mask material used to form the contact etch stop layer 201. Thus, the contact etch stop layer 201 serves as a contact etch stop layer, and the opening 401 exposes the area of ​​the contact etch stop layer 201 above one or more metal gates 109. In some embodiments, the etching process may use a carbon and fluorine-containing gas such as carbon tetrafluoride, difluoromethane, fluoroform, or the like. However, the first etchant may be any suitable material.

[0100] In some embodiments, the opening 401 in the X-section may have one or more widths W401. X It is between approximately 10 nm and approximately 500 nm (e.g., approximately 100 nm), and the opening 401 in the Y-section may have one or more widths W401. Y The size is between approximately 1 nm and approximately 50 nm (e.g., approximately 30 nm). However, the opening 401 can have any suitable width. Once the opening 401 is formed, the remaining photoresist layer 303 is removed.

[0101] like Figure 5 As shown, redepositing a second hard masking material, such as masking layer 503, can narrow the opening 401 to form a narrow opening 501. The masking layer 503 can be formed using compliant deposition processes such as chemical vapor deposition or atomic layer deposition, such that the masking layer 503 pads the exposed surface of the etch stop layer 201, the exposed surface of the hard masking layer 203, and the sidewalls of the opening 401 through the hard masking layer 203. In some embodiments, the composition of the masking layer 503 can be the same as that of the hard masking layer 203, for example, both being silicon nitride. In an embodiment, the masking layer 503 has a highly uniform thickness, which is approximately... to approximately Between, for example, about In this way, one or more widths W501 of the narrow opening 501 in the X-section X Between approximately 10 nm and approximately 500 nm (e.g., approximately 100 nm), and one or more narrow openings 501 in the Y-section with a width W501. Y It ranges from approximately 1 nm to approximately 50 nm (e.g., approximately 30 nm). However, the narrow aperture 501 can be of any suitable width.

[0102] like Figure 6 As shown, an anisotropic etching process is performed to remove a portion of the masking layer 503 at the bottom of the pad narrow opening 501. During the anisotropic etching process, the contact etch stop layer 201 serves as the contact etch stop layer. This exposes at least a portion of the area of ​​the contact etch stop layer 201 above one or more metal gates 109 in the narrow opening 501. In the anisotropic etching, the horizontal portion of the masking layer 503 at the bottom of the pad narrow opening 501 is removed, while the vertical portion of the masking layer 503 on the sidewall of the narrow opening 501 remains intact. This allows the vertical portion on the sidewall of the narrow opening 501 to form a complete annular structure with dimensions corresponding to… Figure 5 The width W501 shown X With W501 Y and corresponding Figure 1 The tangents A-A', B-B', and C-C' are shown. In some embodiments, an anisotropic etching process can be performed to remove the masking layer 503 at the bottom of the narrow opening 501 of the pad, which may employ a carbon- and fluorine-containing gas (such as carbon tetrafluoride, difluoromethane, fluoroform, or the like). However, any suitable gas may be used for the anisotropic etching process.

[0103] like Figure 7 As shown, an etching process is performed to cut the metal gate to remove the exposed portion of the contact etch stop layer 201, and to remove one or more target portions of the metal gate 109 along with portions of the associated spacers 105 and interlayer dielectric layer 113, thereby forming a cut metal gate trench 701. This cut metal gate etching process separates one or more target portions of the metal gate 109 into a first portion 109a and a second portion 109b of the metal gate, effectively cutting the first portion and the second portion, as shown. Figure 7 The first Y-section is shown. The cutting process for the metal gate also divides one or more target portions of the interlayer dielectric layer 113 of the source / drain region into a first portion 113a and a second portion 113b of the interlayer dielectric layer 113, which can effectively cut the first portion and the second portion, as shown. Figure 7The second Y-section is shown. In some embodiments, the metal gate etching process includes dry etching using a chlorine- or fluorine-containing gas (such as chlorine, nitrogen trifluoride, silicon tetrachloride, or boron trichloride), oxygen, nitrogen, hydrogen, a combination of the above, or the like. However, any suitable dry etching gas can be used for the etching process of cutting the metal gate.

[0104] In some embodiments, a first portion of the cut metal gate trench 701 has a first depth D1, and a second portion of the cut metal gate trench 701 has a second depth D2. The method for forming the first portion of the cut metal gate trench 701 may involve removing material from a target portion of the metal gate 109, removing material from a target portion of the spacer 105, and removing material from a portion of the interlayer dielectric layer 113 beneath the target portion of the metal gate 109 and the target portion of the spacer 105. Thus, the first portion of the cut metal gate trench 701 may have a first width W701. X1 The target gate width corresponds to the metal gate 109, and the thickness corresponds to the target spacer 105 in the interlayer dielectric layer 113.

[0105] The method for forming the second portion of the cut metal gate trench 701 may involve removing the masking layer 503 formed along the vertical sidewalls of the opening 401 (through the hard masking layer 203), and removing a portion of the interlayer dielectric layer 113 beneath the masking layer 503 formed along the vertical sidewalls of the opening 401 (through the hard masking layer 203). In this way, the second width W701 of the cut metal gate trench 701 is... X2 The width W401 of the opening in the hard mask layer 203 can correspond to the opening width. X .

[0106] Figure 7 Also shown is a first Y-section (along a tangent B-B' near or at the center of the cut metal gate trench 701), where the cut metal gate trench 701 has a first depth D1, and the target metal gate 109 is completely separated (e.g., cut) into a first portion 109a and a second portion 109b. Figure 7 As shown in the second Y-section (along the tangent C-C' along the region near or located in the source / drain region 111 of the cut metal gate trench 701), the cut metal gate trench 701 has a second depth D2, a portion of the interlayer dielectric layer 108 is retained on the isolation region 107, and the isolation region 107 separates a portion of the fins 103 of the adjacent device.

[0107] In some embodiments, the first depth D1 of the diced metal gate trench 701 may be between about 50 nm and about 200 nm (e.g., about 100 nm), while the first width W701 X1The second depth D2 of the diced metal gate trench 701 can be between approximately 10 nm and approximately 500 nm (e.g., approximately 100 nm), while the second width W701... X2 It can be between approximately 1 nm and approximately 50 nm (e.g., approximately 30 nm). However, the first depth D1 and the second depth D2 of the cut metal gate trench 701 can be any suitable depth, and the first width W701 of the cut metal gate trench 701... X1 With the second width W701 X2 Any suitable width can be used.

[0108] like Figure 7 As shown, during the etching process for cutting a metal gate, the materials of the mask layer 503, the target metal gate 109, the spacer 105, the interlayer dielectric layer 113, and the reactant gas can produce byproducts such as residual byproduct material 703 (e.g., polymer). Figure 7 For example, residual byproduct material 703 can be formed on the hard mask layer 203 and along the sidewall of the cut metal gate trench 701.

[0109] like Figure 8 As shown, residual byproduct material 703 is removed. Once the diced metal gate trench 701 is formed, a polymer removal process can be performed to remove any residual byproduct material 703. For example, a plasma-free formulation using hydrofluoric acid and / or ammonia can be used to remove the polymer material. The plasma-free formulation with hydrofluoric acid and / or ammonia has low selectivity for metals, and the pressure and temperature can be adjusted during the removal of residual byproduct material 703 to tailor the plasma-free formulation to have different selectivity for silicon nitride.

[0110] Once the residual byproduct material 703 is removed, wet cleaning can be performed to ensure the surface of the cut metal gate trench 701 is clean for subsequent processes. In some embodiments, SC-1 or SC-2 cleaning solutions can be used for the wet cleaning process. However, other solutions such as mixtures of sulfuric acid and hydrogen peroxide (such as known SPM) or hydrofluoric acid solutions can also be used. However, any suitable solution or any suitable process can be used for the wet cleaning process, which is fully encompassed within the scope of the embodiments.

[0111] like Figure 9 As shown, the first diced metal gate refill material 901 is deposited on Figure 8The diced metal gate trench 701 is filled with a first diced metal gate refill material 901. Once the residual byproduct material 703 is removed and a wet cleaning process is performed, any residual material in the hard mask layer 203 can be removed. After removing the hard mask layer 203, the first diced metal gate refill material 901 can be filled into the diced metal gate trench 701. The first diced metal gate refill material 901 can be a dielectric material such as silicon nitride, silicon oxycarbide, and / or silicon carbonitride, wherein the carbon content is between about 1 wt% and 10 wt%, and the nitrogen content is less than about 50 wt%. The aforementioned material can be (Si). (1-y) N y (SiO) (1-x) C x and / or (SiO) (1-x-y) C x N y Where x = 0.01 to 0.1 and y < 0.5. The deposition process of the first diced metal gate refill material 901 can be plasma-assisted chemical vapor deposition, atomic layer deposition, chemical vapor deposition, or similar processes. In one embodiment, the first diced metal gate refill material 901 can be deposited on the contact etch stop layer 201 and overfill the diced metal gate trench 701 to a height above the upper surface of the contact etch stop layer 201.

[0112] like Figure 10 As shown, the first diced metal gate refill material 901 is planarized to remove excess first diced metal gate refill material 901, and the planarization method can employ a chemical mechanical polishing (CMP) process. The CMP planarization process continues until the contact etch stop layer 201 is completely removed, and the surfaces of the first diced metal gate refill material 901, the metal gate 109, and the individual spacers 105 are exposed from the planar surface of the first interlayer dielectric layer 113. In this way, the diced metal gate refill plug 1001 formed from the remaining material of the first diced metal gate refill material 901 can be located in the interlayer dielectric layer 113. In some embodiments, once the height of the metal gate 109 and the height of the diced metal gate refill plug 1001 are reduced, they can be reduced to an overall first height H1, which can be between about 5 nm and about 50 nm (e.g., about 20 nm). However, the metal gate 109 and the diced metal gate refill plug 1001 can adopt any suitable height.

[0113] like Figure 11As shown, the cut metal gate refill plug 1001 and the interlayer dielectric layer 113 are recessed to form a shallow recess 1101. The method for recessing the cut metal gate refill plug 1001 and the interlayer dielectric layer 113 can employ a wet etching process, which can be considered as shallow recess etching. The shallow recess etching can be a time-controlled etching process, which has a first etching rate on the interlayer dielectric layer 113 and a second etching rate on the cut metal gate refill plug 1001, wherein the second etching rate is greater than the first etching rate. Thus, the ratio of the time-controlled etching rates of the interlayer dielectric layer and the cut metal gate material to the shallow recess etching is less than 1 and greater than or equal to 0. In summary, the amount of recess in the cut metal gate refill plug 1001 caused by the shallow recess etching is greater than the amount of recess in the interlayer dielectric layer 113 caused by the shallow recess etching process.

[0114] In some embodiments, the etching rate ratio of the interlayer dielectric layer used for shallow recess etching to the first time-controlled rate of the material dicing the metal gate can be between about 0:1 and about 1:1 (e.g., about 0.5:1), and the etching time can be between about 5 seconds and about 300 seconds (e.g., about 100 seconds). In some embodiments, to form the shallow recess 1101, the interlayer dielectric layer 113 can be recessed to a first recess depth RD1 from a first height H1, and the first recess depth RD1 can be between about 1 nm and about 20 nm (e.g., about 5 nm). The dicing metal gate refill plug 1001 can be recessed to a second recess depth RD2 from a first height H1, and the second recess depth RD2 can be between about 1 nm and about 20 nm (e.g., about 10 nm). However, the first recess depth RD1 of the interlayer dielectric layer 113 and the second recess depth RD2 of the dicing metal gate refill plug 1001 can be any suitable depth.

[0115] In some embodiments, the etching process for cutting shallow recesses in the metal gate includes wet etching by immersing the upper surface of the cut metal gate refill plug 1001 in an etchant such as hydrofluoric acid. However, other etchants such as hydrogen, or other methods such as reactive ion etching, dry etching using etchants such as ammonia and / or nitrogen trifluoride, chemical oxide removal, or dry chemical cleaning processes using chlorine- or fluorine-containing gases (such as chlorine, nitrogen trifluoride, silicon tetrachloride, boron trichloride, oxygen, nitrogen, hydrogen, argon, combinations thereof, or the like) can be used. However, any suitable dry etching gas can be used for the etching process for cutting shallow recesses in the metal gate.

[0116] like Figure 12As shown, a second diced metal gate refill material 1201 is formed. Once a shallow trench 1101 is formed in the interlayer dielectric layer 113 and the diced metal gate refill plug 1001, the second diced metal gate refill material 1201 can be deposited on the interlayer dielectric layer 113 to overfill the shallow trench 1101 to a second overall height H2, and conformally cover the exposed surfaces of the interlayer dielectric layer 113, the exposed surfaces of the diced metal gate refill plug 1001, the exposed surfaces of the spacer 105, and the exposed surfaces of the metal gate 109. The second metal gate refill material 1201 can be a dielectric material such as silicon oxycarbide or silicon carbonitride, wherein the carbon content is between about 1 wt% and 10 wt%, and the nitrogen content is less than about 20 wt%. The above material can be (SiO). (1-x) C x and / or (SiO) (1-x-y) C x N y Where x = 0.01 to 0.1 and y < 0.2. The second diced metal gate refill material 1201 is harder than the first diced metal gate refill material 901 of the diced metal gate refill plug 1001, and the two are different dielectric materials. In one embodiment, the overall second height H2 of the second diced metal gate refill material 1201 is higher than the recessed surface of the diced metal gate refill plug 1001. In some embodiments, the overall second height H2 is between about 11 nm and about 50 nm, for example, about 20 nm.

[0117] like Figure 13As shown, multiple isolation regions 1303 are formed in the interlayer dielectric layer 113. Once the second diced metal gate refill material 1201 is deposited, the second diced metal gate refill material 1201 can be planarized to form multiple isolation regions 1303 by performing a planarization process on the interlayer dielectric layer 113, the spacers 105, and the metal gate 109. In some embodiments, a planarization method such as a chemical mechanical polishing process can be used to remove excess material from the second diced metal gate refill material 1201, the metal gate 109, the spacers 105, and the interlayer dielectric layer 113. A sustainable chemical mechanical polishing process is employed until the surfaces of the second diced metal gate refill material 1201, the spacer 105, the metal gate 109, and the flat surface of the interlayer dielectric layer 113 are reduced from a first height H1 to a third height H3, and until the surfaces of the spacer 105, the metal gate 109, and the second diced metal gate refill material 1201 are exposed from the flat surface of the interlayer dielectric layer 113. This forms a plurality of isolation regions 1303 within the interlayer dielectric layer 113. Each isolation region 1303 includes a diced metal gate refill plug 1001 formed by the first diced metal gate refill material 901, and a diced metal gate cap 1301 formed by the second diced metal gate refill material 1201 located on the diced metal gate refill plug 1001.

[0118] In some embodiments, once the planarization process is performed, the height of the planarized interlayer dielectric layer 113, the height of the metal gate 109, the height of the spacer 105, and the height of the second diced metal gate refill material 1201 are reduced to an overall third height H3, which is between about 5 nm and about 50 nm (e.g., about 30 nm). In some embodiments, a portion of the isolation region 1303, such as the diced metal gate refill plug 1001, is about 50% to about 99% of the overall height of the isolation region 1303. A portion of the isolation region 1303, such as the diced metal gate cap 1301, is about 50% to about 1% of the overall height of the isolation region 1303. For example, the first thickness Th1 of the diced metal gate refill plug 1001 may be between about 5 nm and about 45 nm (e.g., about 30 nm), and the second thickness Th2 of the diced metal gate cap 1301 may be between about 1 nm and about 30 nm (e.g., about 20 nm). However, the overall third height H3, the first thickness Th1, and the second thickness Th2 can be of any suitable height or any suitable thickness.

[0119] Figure 13The diagram also shows multiple isolation regions 1303 formed in the interlayer dielectric layer 113 in relevant X and Y sections. In the X section along tangent A-A', the isolation region 1303 extends between adjacent gates of the metal gate 109 in the interlayer dielectric layer 113, and the cut metal gate cap 1301 is exposed from the flat surface of the interlayer dielectric layer 113 along with the exposed portion of the metal gate 109. In the first Y section, the isolation region 1303 extends through tangent B-B' and separates the first portion 109a and the second portion 109b of the metal gate 109. Furthermore, the surfaces of the first portion 109a and the second portion 109b in the flat surface of the interlayer dielectric layer 113 expose the cut metal gate cap 1301. In the second Y section, the isolation region 1303 extends through tangent C-C' and separates the first source / drain region 111a and the second source / drain region 111b. Furthermore, the surfaces of the first portion 109a and the second portion 109b of the flat surface of the interlayer dielectric layer 113 in the second Y-section expose the cut metal gate cap 1301 of the isolation region 1303.

[0120] like Figure 14 As shown, once the isolation region 1303 is formed and the cut metal gate cap 1301 is exposed from the flat surface of the interlayer dielectric layer 113, a second series of hard masking layers can be formed on the planarized surface of the interlayer dielectric layer 113, the exposed portion of the metal gate 109, the exposed portion of the spacer 105, and the exposed portion of the cut metal gate cap 1301.

[0121] In some embodiments, the first layer in the second series of masking layers may be a contact etch stop layer 1401. The contact etch stop layer 1401 may be a blanket-deposited layer, composed of silicon, titanium nitride, silicon nitride, silicon oxide, combinations thereof, or similar materials, and deposited using atomic layer deposition, plasma-assisted chemical vapor deposition, chemical vapor deposition, or similar methods. However, any suitable material and any suitable method may be used to form the contact etch stop layer 1401. In some embodiments, the thickness of the contact etch stop layer 1401 may be between approximately... to approximately Between, for example, about However, the contact etch stop layer 1401 of the second series hard mask layer can be of any suitable thickness.

[0122] A hard mask layer 1403 may be deposited on the contact etch stop layer 1401 as the second layer of a second series of mask layers. The hard mask layer 1403 formed on the contact etch stop layer 1401 may be composed of a second hard mask material such as silicon, silicon oxide, silicon nitride, the aforementioned compounds, or the like. The second hard mask material used to form the hard mask layer 1403 is different from the first hard mask material used to form the contact etch stop layer 1401. In this way, the contact etch stop layer 1401 can serve as an etch stop layer for the subsequent patterning of the hard mask layer 1403 of the second series of hard mask layers. In some embodiments, the step of placing the hard mask layer 1403 of the second series of hard mask layers on the contact etch stop layer 1401 may be performed using deposition methods such as atomic layer deposition, plasma-assisted chemical vapor deposition, chemical vapor deposition, or similar methods. However, any suitable material and any suitable method may be used to form the hard mask layer 1403. In some embodiments, the thickness of the hard mask layer 1403 is between approximately to approximately Between, for example, about However, the hard mask layer 1403 in the second series of hard mask layers can have any suitable thickness.

[0123] Figure 15 illustrates the photolithography process used to deposit and pattern the photoresist layer 1501, which forms an opening 1503 through the hard mask layer 1403 in the second series of hard mask layers. In an embodiment, the photoresist layer 1501 may be deposited on the hard mask layer 1403 as a third layer in the second series of mask layers. The photoresist layer 1501 can be deposited using any suitable deposition process to form any suitable thickness, and any suitable photolithography method can be used to pattern the photoresist layer 1501 to form an opening 1503 through the photoresist layer 1501 and expose the surface of the hard mask layer 1403 of the second series of hard mask layers in one or more isolation regions 1303. In some embodiments, the photoresist layer 1501 is applied and patterned to cover some isolation regions 1303, while the opening 1503 of the photoresist layer 1501 exposes other isolation regions 1303. Figure 15A Also shown is a detailed view of portion 1700 within the dashed box, which is a portion of the second Y-section beneath the opening 1503 in the photoresist layer 1501. The structure of portion 1700, as highlighted here, will be described in detail below.

[0124] Figure 15B In some embodiments, Figure 15A A detailed view of part 1700 of the second Y-section shown. Figure 15BThe patterned photoresist layer 1501 with an opening 1503 is also shown, with the opening 1503 exposing the surface of the hard mask layer 1403. Furthermore, Figure 15 shows an isolation region 1303 before the formation of the opening 1603 through a second series of hard mask layers (such as hard mask layer 1403 and contact etch stop layer 1401) to the interlayer dielectric layer 113, and other structures buried in the first portion 113a and the second portion 113b of the interlayer dielectric layer. In some embodiments, the isolation region 1303 may have a cut-metal gate refill plug 1001 and a cut-metal gate cap 1301.

[0125] like Figure 16 As shown, a patterned photoresist layer 1501 forms an opening 1603 through a second series of hard masking layers. In some embodiments, the photoresist layer 1501 may be removed before using the second series of hard masking layers as a mask and etching the interlayer dielectric layer 113. In other embodiments, the photoresist layer 1501 is removed after etching the interlayer dielectric layer 113. The patterned second series of hard masking layers and the etching of the interlayer dielectric layer 113 expose the surface of the cut metal gate cap 1301 and the surfaces of the epitaxial portions of the first source / drain region 111a and the second source / drain region 111b in the opening 1603 for subsequent processing and formation of the metal contacts used for the first source / drain region 111a and the second source / drain region 111b. In some embodiments, the etching process for forming the opening 1603 and etching into the interlayer dielectric layer 113 may remove the first and second layers of the second series of hard masking layers (such as the contact etch stop layer 1401 and the hard masking layer 1403), and may employ carbon- and fluorine-containing gases such as carbon tetrafluoride, carbon difluoride, fluoroform, or the like. However, any suitable gas may be used.

[0126] In some embodiments described herein, a time-controlled etching process is used to etch the interlayer dielectric layer 113. In this process, the materials of the first portion 113a and the second portion 113b of the interlayer dielectric layer 113 can be etched simultaneously at a first time-controlled etching rate, and the material of the cut metal gate cap 1301 can be etched at a second time-controlled etching rate. In some embodiments, the second time-controlled etching rate is less than the first time-controlled etching rate. In other words, the etching rate ratio of the time-controlled etching process is the first time-controlled etching rate / the second time-controlled etching rate, which is greater than 1. As a result, the removal rate of the material in the interlayer dielectric layer 113 is greater than the removal rate of the material in the cut metal gate cap 1301.

[0127] In some embodiments, the etching rate ratio of the interlayer dielectric layer 113 to the diced metal gate cap 1301 in the time-controlled etching process is between about 10:8 and about 100:1 (e.g., about 20:1), and the etching time is between about 5 seconds and about 300 seconds (e.g., about 50 seconds). However, the time-controlled etching process can employ any suitable etching rate ratio. In some embodiments, the first time-controlled etching rate of the interlayer dielectric layer 113 can be between about 10:8 and about 100:1 (e.g., about 20:1). to approximately Between (e.g., about) The second time-controlled etching rate for cutting the metal gate cover 1301 can be between approximately to approximately Between (e.g., about) However, the first and second time-controlled etching rates can be any suitable etching rates.

[0128] In some embodiments, the first time-controlled etch rate ratio of the interlayer dielectric layer to the diced metal gate material used for shallow recess etching may be between about 0:1 and about 1:1 (e.g., about 1:1), and the etch time may be between about 5 seconds and about 300 seconds (e.g., about 50 seconds). Some embodiments do not form shallow recesses, allowing the first recess depth of the interlayer dielectric layer 113 to be between about 1 nm and about 20 nm (e.g., about 20 nm), and the second recess depth of the diced metal gate cap 1301 to be between about 1 nm and about 20 nm (e.g., about 3 nm) or less than about 25% of the diced metal gate cap 1301. However, any suitable depth may be used.

[0129] Figure 16 The diagram also shows a detailed view of portion 1800 within the dashed box, including the cut-out metal gate cap 1301 exposed in the first portion 113a and the second portion 113b of the interlayer dielectric layer 113, and the portion of the second Y-section below the opening 1603 on the surfaces of the first source / drain region 111a and the second source / drain region 111b. The portion 1800 and its structure highlighted here will be further detailed below.

[0130] Figure 17 In some embodiments, forming Figure 16 A detailed view of part 1800 of the etching process used for the opening 1603 on the source / drain region of the Y-section shown. Figure 15B It also shows a patterned photoresist layer 1501 with an opening 1503, and the surface of a hard mask layer 1403 exposed by the opening 1053. Furthermore, Figure 17The illustration shows the isolation region 1303 formed after the opening 1603 is formed in the interlayer dielectric layer 113, and other structures buried in the first portion 113a and the second portion 113b of the interlayer dielectric layer 113. During the interlayer dielectric layer etching process, some material of the cut metal gate cap 1301 can be removed. In this way, the height of the cut metal gate cap 1301 can be reduced to a final cap height HH, which is between about 0 nm and about 5 nm (e.g., about 2 nm), and the interlayer dielectric layer 113 adjacent to the cut metal gate refill plug 1001 is reduced to a final height ILDH, which is between about 1 nm and about 50 nm (e.g., about 30 nm).

[0131] When the diced metal gate protective cap structure is formed on top of the diced metal gate dummy gate plug, there is no need to clean the residue after contact etching because the refill material of the dummy diced metal gate contact plug leaves only minimal or no residue. As a result, the final diced metal gate device can have improved AC performance because only a small amount or no residue remains on the epitaxial surface during the contact etching process, providing the surface area for surface contact between the epitaxial surface and the contact structure subsequently formed on the epitaxial layer. Furthermore, the final diced metal gate device can have good capacitive efficiency because the diced metal gate refill layer is not damaged during the contact etching process, and the refill material of the dummy diced metal gate contact plug is not lost, allowing the conductive diced metal gate plug subsequently formed in the region of the dummy diced metal gate contact plug to have the required dimensions.

[0132] In some embodiments, if cleaning of residues is still necessary, a weaker solution may be used to minimize damage to the epitaxial surface. For example, weaker solutions such as deionized water, SC1 / SC2, ozone, or the like can be used to remove any unwanted residues. By using a weaker solution, minimal or no damage to the epitaxial layer is achieved while still obtaining the aforementioned advantages.

[0133] Once the opening 1603 is formed, a first contact 1605 can be formed to electrically connect the source / drain regions 111. Prior to forming the first contact 1605, a silicide contact may be formed, if appropriate. The silicide contact may contain titanium, nickel, cobalt, or erbium to reduce the Schottky barrier of the contact; however, other metals such as platinum, palladium, or the like may also be used. The silicide method may involve blanket deposition of a suitable metal material, followed by an annealing step to react the metal with the exposed silicon underneath. The unreacted metal is then removed, and the removal method may be a selective etching process. The thickness of the silicide contact may be between approximately 5 nm and approximately 50 nm.

[0134] In the described embodiment, the first contact 1605 may comprise a conductive material such as titanium, tungsten, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, silicon tantalum nitride, manganese, zirconium, titanium nitride, tantalum nitride, ruthenium, molybdenum, or tungsten nitride, but may also be any other suitable material such as aluminum, copper, the alloys described above, combinations thereof, or the like. The process of depositing conductive material into the opening to fill and / or overfill the opening may be sputtering, chemical vapor deposition, electroplating, electroless plating, or similar methods. Once the conductive material is filled or overfilled, a planarization process such as chemical mechanical polishing may be used to remove the deposited material outside the opening; however, any suitable process may be used to remove the conductive material.

[0135] In one embodiment, the method includes forming an opening in a diced metal gate region of a semiconductor device; depositing a first refill material in the opening to form a diced metal gate plug; performing chemical mechanical polishing to expose a metal gate structure; etching the first refill material to form a recess in the diced metal gate plug; filling the recess with a second refill material to form a cap structure on the first refill material of the diced metal gate plug; and forming a plurality of contacts to a plurality of source / drain regions of a plurality of adjacent devices separated by the diced metal gate plug. In one embodiment, the step of forming contacts further includes: etching an interlayer dielectric material in the source / drain regions at a first etch rate; and etching the cap structure at a second etch rate such that the contact opening is formed on the source / drain regions of the adjacent devices and exposes the upper surface of the source / drain regions, and the second etch rate is different from the first etch rate. In one embodiment, the etch rate ratio between the etch rate of the interlayer dielectric material and the etch rate of the second refill material of the cap structure is greater than 1:1. In one embodiment, the etch rate ratio is greater than 20:1. In one embodiment, the step of etching the cap structure includes removing less than 25% of the cap structure. In one embodiment, the step of etching the first refill material to form a recess in the diced metal gate plug further includes: etching the interlayer dielectric material to a first depth at a first etch rate; and etching the first refill material to a second depth at a second etch rate greater than the first etch rate, and the second depth greater than the first depth. In one embodiment, the etch rate ratio between the first etch rate of the interlayer dielectric material and the second etch rate of the first refill material is less than 1:1.

[0136] In another embodiment, the method includes: forming a first metal gate on a first semiconductor fin; forming a first opening through the first metal gate; filling the first opening with a first dielectric material; planarizing the first dielectric material and the first metal gate; recessing the first dielectric material to form a second opening; filling the second opening with a second dielectric material; and planarizing the second dielectric material and the first metal gate. In one embodiment, the method further includes growing a first epitaxial source / drain region on the first semiconductor fin; forming a first opening through a first portion of an interlayer dielectric layer surrounding the first epitaxial source / drain region, wherein the step of planarizing the second dielectric material and the first metal gate includes planarizing the first portion of the interlayer dielectric layer and the first metal gate; and etching the first portion of the interlayer dielectric layer to expose the first epitaxial source / drain region, and removing at least a portion of the material of the interlayer dielectric layer between the first epitaxial source / drain region and the second dielectric material in the first portion of the interlayer dielectric layer. In one embodiment, the hardness of the second dielectric material is greater than the hardness of the first dielectric material. In one embodiment, the step of etching a first portion of the interlayer dielectric layer further includes employing a time-controlled etching process, which has a first etching rate for the material of the interlayer dielectric layer and a second etching rate for the second dielectric material, wherein the second etching rate is less than the first etching rate. In one embodiment, the second etching rate is at least twice as small as the first etching rate. In some embodiments, the second etching rate is at least 20 times smaller than the first etching rate. In one embodiment, the step of etching the first portion of the interlayer dielectric layer further includes removing less than 25% of the second dielectric material from the first portion of the interlayer dielectric layer.

[0137] In another embodiment, the semiconductor device includes a plurality of metal gate structures located in an interlayer dielectric layer on a substrate; and an isolation structure located between the metal gate structures, wherein the isolation structure includes a dielectric cap portion located on a dielectric plug portion, wherein the isolation structure is at least partially buried in the interlayer dielectric layer and electrically isolates and physically separates the source / drain of a first device and the source / drain of a second device in the interlayer dielectric layer. In one embodiment, the dielectric cap portion includes a first material, and the dielectric plug portion includes a second material, wherein the first material and the second material are different. In one embodiment, the interface between the dielectric cap portion and the dielectric plug portion of the isolation structure is below the upper surface of the epitaxial region covered by the source / drain contacts of the first device. In one embodiment, the flat surface of the dielectric cap portion is located in the flat surface of the interlayer dielectric layer. In one embodiment, the first material is harder than the second material.

[0138] This application has been disclosed above with several embodiments to facilitate understanding of this application by those skilled in the art. Those skilled in the art can use this application as a basis to design or adjust other processes and structures to achieve the same purpose as the embodiments and / or achieve the same advantages as the embodiments. Those skilled in the art should understand that the above equivalent substitutions do not depart from the concept and scope of this application, and these different changes, substitutions, and adjustments can be made without departing from the concept and scope of this application.

Claims

1. A method for forming a semiconductor device, comprising: An opening is formed in a diced metal gate region of a semiconductor device, wherein the sidewall of the opening after the opening is formed includes a conductive material; A first refill material is deposited in the opening to form a cut metal gate plug; A chemical mechanical polishing process was performed to expose a metal gate structure; The first refill material is etched to form a recess in the cut metal gate plug; A second refill material is filled into the recess to form a cap structure on the first refill material of the cut metal gate plug; as well as Forming multiple contacts to multiple source / drain regions of multiple adjacent devices separated by the diced metal gate plug, wherein the step of forming the contacts includes: Etch an interlayer dielectric material in these source / drain regions at a first etch rate; as well as The cover structure is etched at a second etching rate, such that multiple contact openings are formed on the source / drain regions of the adjacent devices and the upper surfaces of the source / drain regions are exposed, and the second etching rate is different from the first etching rate.

2. The method of forming a semiconductor device as claimed in claim 1, wherein the etching rate ratio between the etching rate of the interlayer dielectric material and the etching rate of the second refill material of the cap structure is greater than 1:

1.

3. The method for forming a semiconductor device as claimed in claim 2, wherein the etching rate ratio is greater than 20:

1.

4. The method of forming a semiconductor device as claimed in claim 1, wherein the step of etching the cover structure includes removing less than 25% of the cover structure.

5. The method of forming a semiconductor device as claimed in claim 2, wherein the step of etching the first refill material to form the recess in the diced metal gate plug further comprises: The interlayer dielectric material is etched to a first depth at a third etch rate; as well as The first refill material is etched to a second depth at a fourth etch rate greater than the third etch rate, and the second depth is greater than the first depth.

6. The method of forming a semiconductor device as claimed in claim 5, wherein the ratio of the third etch rate of the interlayer dielectric material to the fourth etch rate of the first refill material is less than 1:

1.

7. A method for forming a semiconductor device, comprising: A first metal gate is formed on a first semiconductor fin; A first opening is formed through the first metal gate, wherein the step of forming the first opening removes material from the first metal gate; A first dielectric material is filled into the first opening; Planarize the first dielectric material and the first metal gate; The first dielectric material is recessed to form a second opening; A second dielectric material is filled into the second opening; and Planarize the second dielectric material and the first metal gate.

8. The method for forming a semiconductor device as claimed in claim 7, further comprising: A first epitaxial source / drain region is grown on the first semiconductor fin; Forming the first opening through a first portion of the interlayer dielectric layer surrounding the first epitaxial source / drain region, wherein the step of planarizing the second dielectric material and the first metal gate includes planarizing the first portion of the interlayer dielectric layer and the first metal gate; as well as The first portion of the interlayer dielectric layer is etched to expose the first epitaxial source / drain region, and at least a portion of the material of the interlayer dielectric layer between the first epitaxial source / drain region and the second dielectric material in the first portion of the interlayer dielectric layer is removed.

9. The method for forming a semiconductor device as claimed in claim 7, wherein the hardness of the second dielectric material is greater than the hardness of the first dielectric material.

10. The method of forming a semiconductor device as claimed in claim 8, wherein the step of etching the first portion of the interlayer dielectric layer further comprises employing a time-controlled etching process having a first etching rate for the material of the interlayer dielectric layer, a second etching rate for the second dielectric material, and the second etching rate being less than the first etching rate.

11. The method of forming a semiconductor device as claimed in claim 10, wherein the second etch rate is at least twice as small as the first etch rate.

12. The method of forming a semiconductor device as claimed in claim 10, wherein the second etch rate is at least 20 times smaller than the first etch rate.

13. The method of forming a semiconductor device as claimed in claim 8, wherein the step of etching a first portion of the interlayer dielectric layer further comprises removing less than 25% of the second dielectric material in the first portion of the interlayer dielectric layer.

14. The method of forming a semiconductor device as claimed in claim 8, wherein the step of recessing the first dielectric material to form the second opening further comprises using a time-controlled etching process to recess the first dielectric material, and using the time-controlled etching process to recess a second portion of the interlayer dielectric layer separating the first dielectric material from another metal gate, wherein the time-controlled etching process recesses the first dielectric material at a rate at least 10 times greater than the rate at which the second portion of the interlayer dielectric layer is recessed.

15. A semiconductor device, comprising: Multiple metal gate structures are located in an interlayer dielectric layer on a substrate; as well as An isolation structure is located between the metal gate structures, and the isolation structure includes a dielectric cap portion located on a dielectric plug portion, wherein the isolation structure is at least partially buried in the interlayer dielectric layer and electrically isolates and physically separates a source / drain of a first device and a source / drain of a second device in the interlayer dielectric layer, wherein an interface between the dielectric cap portion and the dielectric plug portion of the isolation structure is lower than the upper surface of an epitaxial region covered by a source / drain contact of the first device.

16. The semiconductor device of claim 15, wherein the dielectric cap portion includes a first material, the dielectric plug portion includes a second material, and the first material is different from the second material.

17. The semiconductor device of claim 15, wherein the flat surface of the dielectric cap portion is located in the flat surface of the interlayer dielectric layer.

18. The semiconductor device of claim 16, wherein the first material is harder than the second material.

19. A method for forming a semiconductor device, comprising: Multiple metal gate structures are formed in an interlayer dielectric layer on a substrate; as well as An isolation structure is formed between the metal gate structures, and the isolation structure includes a dielectric cap portion located on a dielectric plug portion, wherein the isolation structure is at least partially buried in the interlayer dielectric layer and electrically isolates and physically separates a source / drain of a first device and a source / drain of a second device in the interlayer dielectric layer, wherein an interface between the dielectric cap portion and the dielectric plug portion of the isolation structure is lower than the upper surface of an epitaxial region covered by a source / drain contact of the first device.

20. The method of forming a semiconductor device as claimed in claim 19, wherein the dielectric cap portion includes a first material, the dielectric plug portion includes a second material, and the first material is different from the second material.

21. The method of forming a semiconductor device as claimed in claim 20, wherein the first material is harder than the second material.

22. The method of forming a semiconductor device as claimed in claim 19, wherein the step of forming the isolation structure forms a flat surface of the dielectric cap portion located in the flat surface of the interlayer dielectric layer.

23. The method of forming a semiconductor device as claimed in claim 19, wherein the step of forming the isolation structure causes the dielectric plug portion to be recessed.

24. The method of forming a semiconductor device as claimed in claim 19, further comprising forming a plurality of contacts to a plurality of source / drain regions of a plurality of adjacent devices separated by the isolation structure.

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