On-chip series power supply system and arithmetic unit, chip, computing power board and computing device using the same

Abstract

The present invention provides an on-chip series power supply system and an arithmetic unit, a chip, a computing power board, and a computing device using the same. The on-chip series power supply system includes two or more voltage domains to be powered, and the voltage domains to be powered are connected in series between a power supply and a ground; two or more isolation regions, the voltage domains to be powered are formed within the isolation regions, and the isolation regions are used to isolate the voltage domains to be powered; the isolation regions are connected in series between the power supply and the ground; a power supply compensation unit, connected between the voltage domains to be powered and the isolation regions, for providing power supply compensation to the voltage domains to be powered; wherein, a voltage stabilization unit is further included, and the voltage stabilization unit is connected in parallel at both ends of each of the isolation regions. The on-chip series power supply system of the present invention can effectively reduce power consumption, lower the design difficulty, save chip area, and reduce production costs.

Description

Technical Field

[0001] The present invention relates to a multi-voltage domain power supply system, and particularly to an on-chip series power supply system for compensating a power supply voltage based on a substrate reference and having a voltage stabilizing unit, and an arithmetic unit, a chip, a computing board and a computing device applying the same. Background Art

[0002] For a new generation of computing devices, a large number of repetitive logic calculation pipelines are required.

[0003] The core of the design of such computing devices lies in the performance power consumption ratio. Higher performance and lower power consumption mean higher efficiency, and at the same time mean that more computing power can be achieved under the same power consumption.

[0004] In addition, a large number of repetitive logic calculations require a large current to be supplied to the computing device, which will result in a large additional power consumption of the computing device in addition to the power consumption required for logic calculations. Therefore, it is necessary to reduce the working current of the computing device so as to reduce its additional power consumption.

[0005] CN206039425U discloses a series power supply circuit. As Figure 1 shown, a plurality of packaging units are serially connected between a power supply terminal VCC and the ground. Each packaging unit respectively includes one or more groups of components. Each group of components includes a chip to be powered and an auxiliary power supply unit connected together. A signal level conversion unit is serially connected between the chips to be powered in two adjacent groups of components. Although this series power supply circuit can supply a low power supply voltage to each chip to be powered, it is for providing series power supply to different packaging units on a printed circuit board and cannot achieve series power supply between different voltage domains inside the chip.

[0006] The multi-supply voltage domain power supply technology is more and more widely applied to a system-on-chip (SoC) and a multi-processor computing structure. In a chip applying the multi-voltage domain technology, the chip usually contains a plurality of independent voltage domains or voltage islands, and the modules under each voltage domain work at an appropriate power supply voltage according to their timing requirements. Generally speaking, for a module with relatively critical timing, it usually works at a high power supply voltage (VDDH) to meet the speed performance requirements of the chip; while for a non-critical circuit module, it works at a low power supply voltage (VDDL) or even a sub-threshold power supply voltage to reduce the power consumption and energy consumption of the chip.

[0007] CN206523836U discloses an on-chip series power supply system. As Figure 2As shown, in the series power supply chip, each unit to be powered can include a chip core, or each unit to be powered can include multiple chip cores connected in parallel. The chip core of each voltage domain includes a P-channel Metal Oxide Semiconductor (PMOS) tube and an N-channel Metal Oxide Semiconductor (NMOS) tube in its circuit. The substrate of the PMOS tube of the chip core of each voltage domain is connected to the power supply voltage or working voltage (VDD) of the voltage domain of this level, and the VDD of the voltage domain of this level is connected to the ground (VSS) of the previous voltage domain. The series power supply chip also includes n deep wells for isolating different voltage domains. These n deep wells are independently arranged and not connected to each other. Each of the n units to be powered is located in a deep well, thereby isolating different voltage domains on the same chip, effectively avoiding short circuits between different voltage domains. Although the internal series power supply system of the chip realizes the series power supply between different voltage domains inside the chip, each voltage domain needs to provide auxiliary voltage sources VDD_1, VDD_2, etc. in addition to the power supply VDD. Not only is the auxiliary voltage source difficult to design, but it also occupies a large chip area and generates high power consumption. Summary of the invention

[0008] In order to solve the above problems, the present invention provides an on-chip series power supply system based on substrate reference, which not only reduces power consumption, but also reduces design difficulty, saves chip area, and reduces production costs.

[0009] In order to achieve the above object, the present invention provides an on-chip series power supply system, comprising:

[0010] Two or more voltage domains to be powered, wherein the voltage domains to be powered are connected in series between a power supply and a ground;

[0011] Two or more isolation regions, the voltage domain to be powered is formed in the isolation region, and the isolation region is used to isolate the voltage domain to be powered;

[0012] The isolation region is connected in series between the power supply and the ground;

[0013] A power compensation unit, connected between the voltage domain to be powered and the isolation area, and used to provide power compensation to the voltage domain to be powered;

[0014] Wherein, it also includes a voltage stabilizing unit, and the voltage stabilizing unit is connected in parallel at both ends of each of the isolation regions.

[0015] The above-mentioned on-chip series power supply system, wherein the power supply compensation unit provides power supply compensation to the voltage domain to be powered by operating in the saturation state.

[0016] The above-mentioned on-chip series power supply system, wherein a first power supply terminal and a first ground terminal are formed at both ends of each of the isolation regions, and the first power supply terminal and / or the first ground terminal are used to provide a reference voltage to the power supply compensation unit.

[0017] The above-mentioned on-chip series power supply system, wherein a second power supply terminal and a second ground terminal are formed at both ends of each of the voltage domains to be powered, and the power supply compensation unit provides power supply compensation to the second power supply terminal and / or the second ground terminal.

[0018] The above-mentioned on-chip series power supply system, wherein, based on the reference voltage, when the voltage change range of the second power supply terminal and / or the second ground terminal exceeds the threshold of the power supply compensation unit, the power supply compensation unit operates in the saturation state.

[0019] The above-mentioned on-chip series power supply system, wherein the power supply compensation unit is a switching transistor.

[0020] The above-mentioned on-chip series power supply system, wherein the switching transistor is a PMOS switching transistor and / or an NMOS switching transistor.

[0021] The above-mentioned on-chip series power supply system, wherein the PMOS switching transistor and / or the NMOS switching transistor are one or more.

[0022] The above-mentioned on-chip series power supply system, wherein one or more semiconductor devices are formed in the voltage domain to be powered, and the second power supply terminal and / or the second ground terminal provide a substrate bias voltage to the semiconductor devices.

[0023] The above-mentioned on-chip series power supply system, wherein the semiconductor devices include PMOS transistors and / or NMOS transistors, the second power supply terminal provides a substrate bias voltage to the PMOS transistors, and the second ground terminal provides a substrate bias voltage to the NMOS transistors.

[0024] The above-mentioned on-chip series power supply system, wherein the voltage stabilizing unit is used to stabilize the voltage of the first power supply terminal and / or the first ground terminal.

[0025] The above-mentioned on-chip series power supply system, wherein the voltage stabilizing unit includes one or more of a resistor, a capacitor, or a diode.

[0026] The above-mentioned in-chip series power supply system, wherein the voltage stabilizing unit is directly connected between the first power supply terminal and the first ground terminal, or is respectively connected between the first power supply terminal and the first ground terminal through an analog switch.

[0027] The above-mentioned in-chip series power supply system, wherein an analog switch is provided between the first ground terminal and the second ground terminal.

[0028] To achieve the above object, the present invention further provides a data operation unit, wherein the data operation unit includes a control circuit, an operation circuit, a storage circuit connected in an interconnected manner, and one or more in-chip series power supply systems, wherein the in-chip series power supply system is any one of the above-mentioned in-chip series power supply systems.

[0029] To achieve the above object, the present invention further provides a chip, wherein the chip includes any one of the above-mentioned data operation units.

[0030] To achieve the above object, the present invention further provides a computing power board for a computing device, wherein the computing power board includes any one of the above-mentioned chips.

[0031] To achieve the above object, the present invention further provides a computing device, including a power supply board, a control board, a connection board, a radiator, and a plurality of computing power boards. The control board is connected to the computing power boards through the connection board. The radiator is arranged around the computing power boards. The power supply board is used to supply power to the connection board, the control board, the radiator, and the computing power boards, wherein the computing power board is any one of the above-mentioned computing power boards.

[0032] By adopting the in-chip series power supply system of the present invention, it is possible to provide a relatively stable working voltage to the voltage domain to be powered without the need for an auxiliary power supply. This not only reduces power consumption, but also reduces the design difficulty, saves chip area, and reduces production costs.

[0033] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but it is not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of an existing series power supply circuit;

[0035] Figure 2 It is a schematic diagram of an existing in-chip series power supply system in a chip;

[0036] Figure 3 It is a schematic diagram of a series power supply circuit structure of the present invention without an in-chip series power supply system;

[0037] Figure 4Schematic diagram of an on-chip series power supply system according to an embodiment of the present invention;

[0038] Figure 5 Schematic diagram of an on-chip series power supply system according to another embodiment of the present invention;

[0039] Figure 6 Schematic diagram of an on-chip series power supply system according to still another embodiment of the present invention;

[0040] Figure 7 Schematic diagram of an on-chip series power supply system according to yet another embodiment of the present invention;

[0041] Figure 8 Schematic diagram of an on-chip series power supply system with a voltage stabilizing unit according to an embodiment of the present invention;

[0042] Figure 9 Schematic diagram of an on-chip series power supply system with a voltage stabilizing unit according to another embodiment of the present invention;

[0043] Figure 10 Schematic diagram of a data operation unit of the present invention;

[0044] Figure 11 Schematic diagram of a chip of the present invention;

[0045] Figure 12 Schematic diagram of a computing power board of the present invention;

[0046] Figure 13 Schematic diagram of a computing device of the present invention.

[0047] Among them, reference numerals:

[0048] 10: Series power supply circuit

[0049] 100: On-chip series power supply system

[0050] 101-1, 101-2,... 101-n: Voltage domains

[0051] 102-1, 102-2,... 102-n: Deep N-wells

[0052] 103-1, 103-2,... 103-n: P-wells

[0053] 104-1, 104-2,... 104-n: N-wells

[0054] 105, 105': Switch transistors

[0055] 106: Body resistance 107: Voltage stabilizing unit

[0056] 108: Analog switch

[0057] VDD1, VDD2, …… VDDn: Power supply terminals of the voltage domain

[0058] VSS1, VSS2, …… VSSn: Ground terminals of the voltage domain

[0059] VPP1, VPP2, …… VPPn: Power supply terminals of the deep N-well

[0060] VBB1, VBB2, …… VBBn: Ground terminals of the deep N-well

[0061] VDD: System power supply GND: System ground

[0062] S: Source terminal D: Drain terminal

[0063] G: Gate terminal B: Substrate terminal

[0064] 700 - Data operation unit 701 - Control circuit

[0065] 702 - Operation circuit 703 - Storage circuit

[0066] 800: Chip 801: Control unit

[0067] 900: Computing power board 1000: Computing device

[0068] 1001: Connection board 1002: Control board

[0069] 1003: Radiator 1004: Power supply board Detailed implementation manners

[0070] The structural principle and working principle of the present invention will be specifically described below with reference to the accompanying drawings:

[0071] In the description and subsequent claims, certain terms are used to refer to specific components. Those of ordinary skill in the art should understand that manufacturers may use different names to refer to the same component. This description and subsequent claims do not use the difference in names as a way to distinguish components, but use the difference in functions of components as the criterion for distinction. Throughout the description, the same reference numerals represent the same elements.

[0072] The terms "comprising" and "including" mentioned throughout the description and subsequent claims are open-ended terms and should be interpreted as "including but not limited to". In addition, the term "connected" herein includes any direct and indirect electrical connection means. Indirect electrical connection means include connection through other devices.

[0073] Figure 3 It is a schematic diagram of the series power supply circuit structure of the present invention without an on-chip series power supply system. As Figure 3As shown, taking the chip substrate as a P-type substrate as an example, there are n voltage domains 101-1, 101-2... 101-n to be powered in the series power supply circuit 10, where n is a positive integer greater than 1. Each voltage domain 101-1, 101-2... 101-n is isolated from other voltage domains through a corresponding deep N-well 102-1, 102-2... 102-n to avoid short circuits between different voltage domains. A certain number of P-wells 103-1, 103-2... 103-n and N-wells 104-1, 104-2... 104-n are respectively formed in the deep N-wells 102-1, 102-2... 102-n.

[0074] PMOS transistors and / or NMOS transistors are formed in each voltage domain 101-1, 101-2... 101-n. If necessary, other types of devices such as resistors and capacitors can also be formed. Among them, PMOS transistors are formed in the N-wells 104-1, 104-2... 104-n, and NMOS transistors are formed in the P-wells 103-1, 103-2... 103-n. PMOS transistors and NMOS transistors are used to implement various functions of the chip.

[0075] The voltage domains 101-1, 101-2... 101-n to be powered are sequentially connected in series between the system power supply VDD and the system ground GND. The power supply terminal VDD1 of the voltage domain 101-1 is connected to the system power supply VDD, the ground terminal VSS1 of the voltage domain 101-1 is connected to the power supply terminal VDD2 of the next-level voltage domain 101-2, the ground terminal VSS2 of the voltage domain 101-2 is connected to the power supply terminal VDD3 of the next-level voltage domain 101-3, and so on in series to the next level. The ground terminal VSSn of the voltage domain 101-n is connected to the system ground GND. Thus, n voltage domains powered in series are formed.

[0076] A PMOS transistor or an NMOS transistor has four ports: S / D / G / B, which are respectively called the source terminal, the drain terminal, the gate terminal, and the substrate terminal. Usually, the substrate terminals of the PMOS transistors in each voltage domain 101-1, 101-2... 101-n are connected to the power supply terminals VDD1, VDD2... VDDn of this voltage domain together with the source terminals, and the substrate terminals of the NMOS transistors are connected to the ground terminals VSS1, VSS2... VSSn of this voltage domain together with the source terminals. When the voltage between the gate terminal and the substrate terminal exceeds the threshold voltage, a conductive channel from the source terminal to the drain terminal is formed in the substrate, enabling carriers to flow in the substrate between the source terminal and the drain terminal, forming an electric current.

[0077] When n voltage domains powered in series are operating normally, the potentials of the power supply terminals VDD1, VDD2... VDDn and the ground terminals VSS1, VSS2... VSSn of each voltage domain basically remain in a stable state. When a large current occurs in one of the n voltage domains powered in series, namely voltage domain 101-m (1 ≤ m ≤ n), due to the resistance of voltage domain 101-m itself, a large voltage difference is formed across the two ends of voltage domain 101-m, which will cause the voltages across the two ends of other voltage domains without large current to be affected, resulting in a drift of the power supply voltage. The drift occurs continuously with the change of the current, and the drift is positively correlated with the magnitude of the current, which may cause the chip to malfunction.

[0078] To avoid the above situation, generally, the method of adding an auxiliary power supply is adopted for improvement, that is, an auxiliary power supply is added to each voltage domain to supply power to the voltage domain. The present invention provides an on-chip series power supply system based on a substrate reference, which can reduce the voltage drift across the two ends of the voltage domain without adding an auxiliary power supply.

[0079] Embodiment 1

[0080] Figure 4 is a schematic diagram of an on-chip series power supply system according to an embodiment of the present invention. As Figure 4 shown, taking the chip substrate as a P-type substrate as an example, n voltage domains 101-1, 101-2... 101-n to be powered are formed in the on-chip series power supply system 100 of the present invention, where n is a positive integer greater than 1. Each voltage domain 101-1, 101-2... 101-n is respectively isolated from different voltage domains through a corresponding deep N-well 102-1, 102-2... 102-n to avoid short circuits between different voltage domains. A certain number of P-wells 103-1, 103-2... 103-n and N-wells 104-1, 104-2... 104-n are respectively formed in the deep N-wells 102-1, 102-2... 102-n.

[0081] PMOS transistors and / or NMOS transistors are formed in each voltage domain 101-1, 101-2... 101-n. If necessary, other types of devices such as resistors and capacitors can also be formed. Among them, the PMOS transistors are formed in the N-wells 104-1, 104-2... 104-n, and the NMOS transistors are formed in the P-wells 103-1, 103-2... 103-n. The PMOS transistors and NMOS transistors are used to implement various functions of the chip.

[0082] Each voltage domain 101-1, 101-2,..., 101-n to be powered is connected in series between the system power supply VDD and the system ground GND in sequence. The power supply terminal VDD1 of the voltage domain 101-1 is connected to the system power supply VDD, the ground terminal VSS1 of the voltage domain 101-1 is connected to the power supply terminal VDD2 of the next-level voltage domain 101-2, the ground terminal VSS2 of the voltage domain 101-2 is connected to the power supply terminal VDD3 of the next-level voltage domain 101-3, and so on in series to the next level. The ground terminal VSSn of the voltage domain 101-n is connected to the system ground GND. Thus, n voltage domains powered in series are formed, and the power supply terminals of each voltage domain 101-1, 101-2,..., 101-n are VDD1, VDD2,..., VDDn respectively, and the ground terminals are VSS1, VSS2,..., VSSn respectively.

[0083] The deep N-wells 102-1, 102-2,..., 102-n are used to achieve isolation between different voltage domains. In addition to forming the above series power supply path, the present invention also uses the body resistance 106 of the P-well and / or N-well to divide the voltage of the system power supply VDD, generating a divided voltage at both ends of the deep N-wells 102-1, 102-2,..., 102-n. Among them, the power supply terminal VPP1 of the deep N-well 102-1 is connected to the system power supply VDD, the ground terminal VBB1 of the deep N-well 102-1 is connected to the power supply terminal VPP2 of the next-level deep N-well 102-2, the ground terminal VBB2 of the deep N-well 102-2 is connected to the power supply terminal VPP3 of the next-level deep N-well 102-3, and so on in series to the next level; the ground terminal VBBn of the deep N-well 102-n is connected to the system ground GND. Deep N-wells are formed that are connected in series in sequence between the system power supply VDD and the ground GND and have relatively stable potential at both ends. The power supply terminals of the deep N-wells 102-1, 102-2,..., 102-n are VPP1, VPP2,..., VPPn respectively, and the ground terminals are VBB1, VBB2,..., VBBn respectively.

[0084] Ideally, the voltages of the power supply terminals VDD1, VDD2,..., VDDn of the voltage domains 101-1, 101-2,..., 101-n are the same as the voltages of the power supply terminals VPP1, VPP2,..., VPPn of the deep N-wells 102-1, 102-2,..., 102-n respectively, and the voltages of the ground terminals VSS1, VSS2,..., VSSn of the voltage domains 101-1, 101-2,..., 101-n are the same as the voltages of the ground terminals VBB1, VBB2,..., VBBn of the deep N-wells 102-1, 102-2,..., 102-n respectively.

[0085] In this embodiment, the source terminal of the PMOS transistor in each voltage domain 101-1, 101-2...101-n is connected to the power supply terminal VDD1, VDD2...VDDn of the voltage domain, and the substrate terminal of the PMOS transistor is connected to the power supply terminal VPP1, VPP2...VPPn of the deep N-well 102-1, 102-2...102-n; the source terminal of the NMOS transistor in each voltage domain 101-1, 101-2...101-n is connected to the ground terminal VSS1, VSS2...VSSn of the voltage domain, and the substrate terminal of the NMOS transistor is connected to the ground terminal VBB1, VBB2...VBBn of the deep N-well 102-1, 102-2...102-n.

[0086] In addition, the on-chip series power supply system 100 of the present invention further includes a power compensation unit, such as a switch transistor 105, which is an NMOS transistor formed in the voltage domains 101-2, 101-3...101-(n-1). Taking the voltage domain 101-2 as an example, the drain terminal D of the switch transistor 105 in the voltage domain 101-2 is connected to the power supply terminal VDD1 of the previous voltage domain 101-1, the source terminal S of the switch transistor 105 is connected to the power supply terminal VDD2 of the current voltage domain 101-2, the gate terminal G of the switch transistor 105 is connected to the power supply terminal VPP2 of the current deep N well 102-2, and the substrate terminal B of the switch transistor 105 is connected to the ground terminal VBB2 of the current deep N well 102-2.

[0087] The gate terminal G and substrate terminal B of the switch transistor 105 are connected to VPP2 and VBB2 respectively. Due to the influence of the gate capacitance and the substrate body capacitance, no current flows between the gate and the substrate, so that the potential of VPP2 remains stable. Ideally, the voltage VPP2 at the gate terminal G of the switch transistor 105 is greater than the voltage VBB2 at the substrate terminal B, thereby forming a conductive channel in the substrate. However, since the voltage VDD1 at the drain terminal D of the switch transistor is greater than the voltage VPP2 at the gate terminal G, the voltage VPP2 at the gate terminal G is the same as the voltage VDD2 at the source terminal S, that is, V d >V g =V s , that is, V gs =0, the conductive channel formed in the substrate is pinched off, and no current flows between the source terminal S and the drain terminal D.

[0088] When the power supply VDD2 of the voltage domain of this level is insufficient, the voltage of VDD2 drops, that is, the voltage of the source terminal S of the switching transistor 105 drops. Since the voltage VPP2 of the gate terminal G remains unchanged, V gs >0 state. Since V ds >V gs , when V gs =Vth When the switch transistor 105 is turned on and operates in the saturation region, the current between the source terminal S and the drain terminal D of the switch transistor 105 is: I DS =[K*(W / L)*(V gs -V th ) 2 ] / 2. At this time, VDD1 at the drain terminal D provides sufficient charge to VDD2 at the source terminal S, and the potential of VDD2 will be clamped at (VPP2-V th ), and will not decrease further.

[0089] Based on the same principle, when the drain terminal D of the switch transistor 105 is connected to the ground terminal VSS1 of the previous voltage domain and the source terminal S is connected to the ground terminal VSS2 of the current voltage domain, the potential of the current voltage domain VSS2 can be clamped at (VSS2-V th ) range.

[0090] Embodiment 2

[0091] Figure 5 FIG. 1 is a schematic diagram of an on-chip series power supply system according to another embodiment of the present invention. Figure 5 As shown, the difference between this embodiment and the first embodiment lies in the different types and connection methods of the switch transistor 105 ′.

[0092] In this embodiment, the on-chip series power supply system 100 also includes a power compensation unit, such as a switch transistor 105', which is a PMOS transistor formed in the voltage domains 101-2, 101-3...101-(n-1). Taking the voltage domain 101-2 as an example, the drain terminal D of the switch transistor 105' in the voltage domain 101-2 is connected to the ground terminal VSS3 of the next-level voltage domain 101-3, the source terminal S of the switch transistor 105' is connected to the ground terminal VSS2 of the current voltage domain 101-2, the gate terminal G of the switch transistor 105' is connected to the ground terminal VBB2 of the current deep N well 102-2, and the substrate terminal B of the switch transistor 105' is connected to the power supply terminal VPP2 of the current deep N well 102-2.

[0093] The gate terminal G and substrate terminal B of the switch transistor 105' are connected to VBB2 and VPP2 respectively. Due to the influence of the gate capacitance and the substrate body capacitance, no current flows between the gate and the substrate, so that the potentials of VBB2 and VPP2 remain stable. Ideally, the voltage VBB2 at the gate terminal G of the switch transistor 105' is lower than the voltage VPP2 at the substrate terminal B, thereby forming a conductive channel in the substrate. However, since the voltage VSS3 at the drain terminal D of the switch transistor 105' is lower than the voltage VBB2 at the gate terminal G, the voltage VBB2 at the gate terminal G is the same as the voltage VSS2 at the source terminal S, that is, V d >Vg = V s , that is, V gs = 0, forming a pinched-off conductive channel in the substrate, and no current flows between the source terminal S and the drain terminal D.

[0094] When an overcurrent is formed in VSS2 of the current stage voltage domain, the potential of VSS2 rises, that is, the voltage of the source terminal S of the switching transistor 105' increases. Since the voltage VBB2 of the gate terminal G remains unchanged, then V gs < 0 state. The threshold voltage of the switching transistor 105' is V th , since V ds > V gs , when V gs = V th , the switching transistor 105' turns on and operates in the saturation region. At this time, the current between the source terminal S and the drain terminal D of the switching transistor 105' is: I DS = [K * (W / L) * (V gs - V th ) 2 / 2. At this time, VSS3 at the drain terminal D supplies sufficient charge to VSS2 at the source terminal S, and the potential of VSS2 will be clamped within the range of (VSS2 + V th ), and will not increase further.

[0095] Based on the same principle, when the drain terminal D of the switching transistor 105' is connected to the power supply terminal VDD3 of the next stage voltage domain and the source terminal S is connected to the power supply terminal VDD2 of the current stage voltage domain, the potential of the power supply terminal VDD2 of the current stage voltage domain can be clamped within the range of (VDD2 + V th ).

[0096] Embodiment 3

[0097] Embodiment 1 and Embodiment 2 only show the case where the power supply compensation unit formed in the same voltage domain is of the same type of switching transistor, that is, the power supply compensation unit is either a PMOS transistor or an NMOS transistor. In different cases, PMOS transistors and NMOS transistors can also be formed simultaneously as switching transistors in each voltage domain.

[0098] Figure 6 is a schematic diagram of an on-chip series power supply system according to another embodiment of the present invention. As Figure 6As shown, taking the m-th voltage domain 101-m of the on-chip series power supply system 100 as an example, a switching transistor 105 and a switching transistor 105' are formed in the voltage domain 101-m. Among them, the switching transistor 105 is an NMOS transistor, and its connection method is the same as that of the switching transistor 105 in the first embodiment; the switching transistor 105' is a PMOS transistor, and its connection method is the same as that of the switching transistor 105' in the second embodiment.

[0099] Embodiment 4

[0100] Embodiment 3 shows a situation where a PMOS transistor and an NMOS transistor are simultaneously formed as switching transistors in the same voltage domain. When only a set of switching transistors 105 and 105' is provided, when a large current change occurs in the adjacent circuit, it can quickly compensate. However, when a large current change occurs in a circuit at a relatively far position, it cannot compensate in time, and it is possible that the power supply voltage of the entire voltage domain changes with the working current, resulting in the abnormal operation of the circuits in the entire voltage domain. In actual design and production, the number of switching transistors can be set to multiple.

[0101] Figure 7 Schematic diagram of the on-chip series power supply system according to another embodiment of the present invention. As Figure 7 shown, a plurality of switching transistors 105 and 105' are formed in each voltage domain 101 of the on-chip series power supply system 100.

[0102] In addition to the area where necessary devices are formed in each voltage domain 101, there is also a certain amount of free area. In order to quickly provide power compensation for adjacent circuits and improve the power compensation ability, as many switching transistors 105 and 105' as possible can be formed in the free area of the voltage domain 101, and the specific number can be determined according to the size of the free area in the voltage domain 101. Among them, the formed plurality of switching transistors 105 and 105' can be arranged evenly or non-uniformly.

[0103] Embodiment 5

[0104] During the actual operation of the circuit, due to the conduction and / or turn-off of transistors, the bulk resistance of the P-well and / or N-well will change, and as a result, the voltages of the power supply terminals VPP1, VPP2... VPPn of the deep N-wells 102-1, 102-2... 102-n and the voltages of the ground terminals VBB1, VBB2... VBBn of the deep N-wells 102-1, 102-2... 102-n will also change accordingly. To ensure the stability of the voltages of VPP1, VPP2... VPPn and VBB1, VBB2... VBBn, it is necessary to ensure that the bulk resistance of the P-well and / or N-well remains relatively constant. A voltage stabilizing unit can be connected in parallel at both ends of the bulk resistance 106 of the P-well and / or N-well.

[0105] Figure 8 Schematic diagram of an on-chip series power supply system with a voltage stabilizing unit according to an embodiment of the present invention. As Figure 8 shown, taking the m-th voltage domain 101-m of the on-chip series power supply system 100 as an example, a voltage stabilizing unit 107 is connected in parallel at both ends of the power supply terminal VPPm and the ground terminal VBBm of the deep N-well 102-m, which is equivalent to connecting a voltage stabilizing unit 107 in parallel at both ends of the bulk resistance of the P-well. The voltage stabilizing unit 107 can be one or more of a resistor, a capacitor, and a diode. The voltage stabilizing unit 107 is not necessary and can be selected to be connected or not at both ends through an analog switch 108.

[0106] Embodiment Six

[0107] During the actual operation process of the circuit, the voltages of the power supply terminals VDD1, VDD2... VDDn and the ground terminals VSS1, VSS2... VSSn of each voltage domain will change, while the voltages of the power supply terminals VPP1, VPP2... VPPn and the ground terminals VBB1, VBB2... VBBn of the deep N-wells remain relatively stable. Ideally, the voltages at the VDD1, VDD2... VDDn terminals are the same as those at the VPP1, VPP2... VPPn, and the voltages at the VSS1, VSS2... VSSn terminals are the same as those at the VBB1, VBB2... VBBn.

[0108] Figure 9 Schematic diagram of an on-chip series power supply system with a voltage stabilizing unit according to another embodiment of the present invention. As Figure 9 shown, taking the m-th voltage domain 101-m of the on-chip series power supply system 100 as an example again, Figure 9 The difference between the embodiment shown and the Figure 8 embodiment shown is that an analog switch 108 is connected between the ground terminal VSSm of the voltage domain 101-m and the ground terminal VBBm of the deep N-well, and whether VSSm and VBBm are connected can be determined by turning on or off the analog switch 108.

[0109] The present invention also provides a data operation unitFigure 10 Schematic diagram of the data operation unit of the present invention. As Figure 10 shown, the data operation unit 700 includes a control circuit 701, an operation circuit 702, a storage circuit 703 connected in parallel, and one or more on-chip series power supply systems 100.

[0110] The present invention also provides a chip, Figure 11 Schematic diagram of the chip of the present invention. As Figure 11 shown, the chip 800 includes a control unit 801 and one or more data operation units 700. The control unit 801 inputs data to the data operation unit 700 and processes the data output by the data operation unit 700.

[0111] The present invention also provides a computing power board, Figure 12 Schematic diagram of the computing power board of the present invention. As Figure 12 shown, each computing power board 900 includes one or more chips 800 for performing hash operations on working data.

[0112] The present invention also provides a computing device, which can be used for any massive operation. Figure 13 Schematic diagram of the computing device of the present invention. As Figure 13 shown, each computing device 1000 includes a connection board 1001, a control board 1002, a radiator 1003, a power supply board 1004, and one or more computing power boards 900. The control board 1002 is connected to the computing power board 900 through the connection board 1001, and the radiator 1003 is arranged around the computing power board 900. The power supply board 1004 is used to supply power to the connection board 1001, the control board 1002, the radiator 1003, and the computing power board 900.

[0113] It should be noted that in the description of the present invention, the orientation or positional relationship indicated by the terms "horizontal", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0114] Although the embodiments of the present invention have been disclosed as above, it is not limited to only the applications listed in the specification and embodiments. It can be fully applied to various fields suitable for the present invention. For those skilled in the art, additional modifications can be easily made. Therefore, without departing from the general concept defined by the claims and the equivalent scope, the present invention is not limited to the specific details and the illustrated examples here.

[0115] In other words, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention. However, these corresponding changes and modifications should all fall within the protection scope of the appended claims of the present invention.

Claims

1. An on-chip series power supply system, characterized in that, Comprising: Two or more voltage domains to be powered, which are connected in series between a power supply and a ground; Two or more isolation regions, within which the voltage domains to be powered are formed, and the isolation regions are used to isolate the voltage domains to be powered; The isolation regions are connected in series between the power supply and the ground, and a first power supply terminal and a first ground terminal are formed at both ends of each isolation region; A power supply compensation unit, connected between the voltage domain to be powered and the isolation region, and the power supply compensation unit includes a switching transistor; Wherein, the first power supply terminal and the first ground terminal of the isolation region generate a reference voltage through body resistance voltage division, and based on the reference voltage, power supply compensation is provided to the voltage domain to be powered when the switching transistor operates in the saturation state; Wherein, a voltage stabilizing unit is further included, which is connected in parallel at both ends of each isolation region, and the voltage stabilizing unit is used to stabilize the voltage of the first power supply terminal and / or the first ground terminal.

2. The on-chip series power supply system according to claim 1, wherein: The first power supply terminal and / or the first ground terminal are used to provide a reference voltage to the power supply compensation unit.

3. The on-chip series power supply system according to claim 2, wherein: A second power supply terminal and a second ground terminal are formed at both ends of each voltage domain to be powered, and the power supply compensation unit provides power supply compensation to the second power supply terminal and / or the second ground terminal.

4. The on-chip series power supply system according to claim 3, characterized in that: Based on the reference voltage, when the voltage change range of the second power supply terminal and / or the second ground terminal exceeds the threshold of the power supply compensation unit, the power supply compensation unit operates in the saturation state.

5. The on-chip series power supply system according to claim 4, characterized in that: The switching transistor is a PMOS switching transistor and / or an NMOS switching transistor.

6. The on-chip series power supply system according to claim 5, wherein: The PMOS switching transistor and / or the NMOS switching transistor is one or more.

7. The on-chip series power supply system according to claim 6, wherein: One or more semiconductor devices are formed in the voltage domain to be powered, and the first power supply terminal and / or the first ground terminal provide a substrate bias voltage to the semiconductor devices.

8. The on-chip series power supply system according to claim 7, wherein: The semiconductor devices include PMOS transistors and / or NMOS transistors, the first power supply terminal provides a substrate bias voltage to the PMOS transistors, and the first ground terminal provides a substrate bias voltage to the NMOS transistors.

9. The on-chip series power supply system according to claim 1, characterized in that: The voltage stabilizing unit includes one or more of a resistor, a capacitor, or a diode.

10. The on-chip series power supply system according to claim 9, wherein: The voltage stabilizing unit is directly connected between the first power supply terminal and the first ground terminal, or is respectively connected between the first power supply terminal and the first ground terminal through an analog switch.

11. The on-chip series power supply system according to claim 10, wherein: An analog switch is provided between the first ground terminal and the second ground terminal.

12. A data operation unit includes a control circuit, an operation circuit, a storage circuit connected in an interconnected manner, and one or more on-chip series power supply systems, and is characterized in that: The on-chip series power supply system is the on-chip series power supply system according to any one of claims 1-11.

13. A chip, characterized in that, Including at least one data operation unit according to any one of claim 12.

14. A computing power board for a computing device, characterized in that, Including a plurality of chips according to any one of claim 13.

15. A computing device, comprising a power supply board, a control board, a connection board, a radiator, and a plurality of computing power boards, wherein the control board is connected to the computing power boards through the connection board, the radiator is disposed around the computing power boards, and the power supply board is configured to supply power to the connection board, the control board, the radiator, and the computing power boards, where The computing power board is the computing power board according to any one of claim 14.

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