Capacitive fingerprint pixel detection circuit and detection method

Abstract

The present invention relates to the technical field of integrated circuit design and fingerprint detection, and in particular to a fingerprint pixel detection circuit and method which can fully self-compensate for the parasitic background capacitance of the surrounding environment and circuit and can well tolerate process deviation and static leakage current, comprising a voltage generator, a switch element, a reference voltage source, a detection electrode, an isolation electrode, an intermediate node, an operational amplifier, a target capacitor, a parasitic capacitor, a switch and a signal control sequence suitable for the operation of the above circuit, in which the pre-charging, resetting, integration and compensation of the signal are mainly completed at each stage of the sequence, and the collection of the fingerprint signal is realized by the transformation of the internal potential, thereby avoiding the introduction of external electrodes and simplifying the application scenario of fingerprint detection; by introducing a special switch and signal control sequence, the negative impact of parasitic capacitance and static leakage current on signal distortion is suppressed to the greatest extent, and high sensitivity and dynamic range are achieved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design and fingerprint detection technology, and in particular to a capacitive fingerprint pixel detection circuit and a detection method. Background Art

[0002] As for the current biometric authentication methods, fingerprint authentication has become the mainstream of current biometric authentication due to its high reliability and cost-effectiveness; and capacitive fingerprint sensors have become the mainstream method of fingerprint authentication due to their small size, fast speed, low power consumption, high detection and ease of use, and have become the focus of current research.

[0003] At present, when a capacitive fingerprint sensor is working, one way is to connect the user's finger to the sensor's driving signal source through an external electrode, forming a detection loop with the sensor's internal circuit. This approach can make the acquisition of fingerprint signals insensitive to the surrounding environment and the parasitic capacitance of the circuit, and obtain high sensitivity and dynamic range. However, due to the introduction of external electrodes, on the one hand, it will complicate the application scenario, and on the other hand, it will directly increase the design complexity and cost of the fingerprint module.

[0004] Another way is to confine all the sensor signals to the inside of the chip, and couple the fingerprint signal by changing the potential of the internal pixel detection electrode. In this way, in order to achieve electrostatic protection of more than 20KV, the thickness of the insulating medium above the sensor detection electrode is required to be greater than 50um. At this time, the fingerprint valley signal has been as small as 0.1fF, which means that the capacitance signal between the detection electrode and the finger is much smaller than the parasitic background capacitance of the detection electrode to the surrounding environment and circuit (usually at the 100fF level). Therefore, to realize a set of the above-mentioned fingerprint acquisition system, it is necessary to achieve maximum compensation for the background parasitic capacitance in order to obtain high sensitivity and dynamic range.

[0005] In addition to the above factors, the objective existence of process mismatch and static leakage current in the integrated circuit manufacturing process will also cause distortion of fingerprint signals. This is also a problem that must be solved in the design of a high-sensitivity and high-dynamic range fingerprint acquisition system.

[0006] Therefore, how to design a capacitive fingerprint pixel circuit and method that is parasitic self-compensating and resistant to process leakage has become our current problem to be solved. Summary of the invention

[0007] The present invention aims to solve the above-mentioned problems.

[0008] Therefore, the first object of the present invention is to provide a capacitive fingerprint pixel detection circuit, which can detect fingerprint signals by internally transforming the potential of the pixel detection electrode without external connection, thereby simplifying the application system.

[0009] To achieve the above object, the present invention provides the following technical solutions: a capacitive fingerprint pixel detection circuit, comprising a voltage generator VPRG_1, a switch element, a reference voltage source REF_1, a reference voltage source REF_2, a detection electrode Top, an isolation electrode Bot, an intermediate node NodeX, an operational amplifier LNA for a signal operation function, a target capacitance Cf is formed between a finger and the detection electrode Top, and a parasitic capacitance Cs is formed between the isolation electrode Bot and the detection electrode Top;

[0010] The switch element comprises a first switch sw1, a second switch sw2, a third switch sw3, a fourth switch sw4, a fifth switch sw5, a sixth switch sw6 and a reset switch sw7, wherein the first switch sw1 to the sixth switch sw6 are all CMOS switches;

[0011] One end of the first switch sw1 and the second switch sw2 and the substrate are commonly connected to the voltage generator VPRG_1, and the other ends are respectively connected to the detection electrode Top and the isolation electrode Bot. The reset switch sw7 is connected across the negative input and output of the operational amplifier LNA. The positive input of the operational amplifier LNA is connected to the reference voltage source REF_1 pin. The isolation electrode Bot is connected to the output of the operational amplifier LNA through the sixth switch sw6. The negative input of the operational amplifier LNA is connected to one end of the fifth switch sw5. The other end of the fifth switch sw5 is connected to the intermediate node NodeX, and the substrate of the fifth switch sw5 is connected to the reference voltage source REF_2 pin. One end of the fourth switch sw4 and the substrate are commonly connected to the intermediate node NodeX, and the other end is connected to the detection electrode Top. One end of the third switch sw3 is connected to the intermediate node NodeX, and the other end and the substrate are commonly connected to the voltage generator VPRG_2.

[0012] Optionally, for the capacitive fingerprint pixel detection circuit, the first switch sw1, the second switch sw2, and the third switch sw3 are all PMOS switches, and the fourth switch sw4, the fifth switch sw5, and the sixth switch sw6 are all NMOS switches.

[0013] Optionally, for the capacitive fingerprint pixel detection circuit, the drain end of the first switch sw1 is connected to the detection electrode Top, the drain end of the second switch sw2 is connected to the isolation electrode Bot, and the source end and substrate of the first switch sw1 and the second switch sw2 are commonly connected to the voltage generator VPRG_1.

[0014] Optionally, for the capacitive fingerprint pixel detection circuit, the source terminal and substrate of the third switch sw3 are commonly connected to the voltage generator VPRG_2, and the drain terminal thereof is connected to the intermediate node NodeX.

[0015] Optionally, for the capacitive fingerprint pixel detection circuit, the source end of the fourth switch sw4 is connected to the detection electrode Top, and the drain end and the substrate are commonly connected to the intermediate node NodeX.

[0016] Optionally, for the capacitive fingerprint pixel detection circuit, the source end of the fifth switch sw5 is connected to the intermediate node NodeX, the drain end thereof is connected to the negative input end of the operational amplifier LNA, and the substrate reference voltage source REF_2 pin thereof is connected.

[0017] Optionally, for the capacitive fingerprint pixel detection circuit, the source end of the sixth switch sw6 is connected to the detection electrode Top, the drain end thereof is connected to the output end of the operational amplifier LNA, and the substrate thereof is grounded.

[0018] The present invention also provides a capacitive fingerprint pixel detection method, comprising the steps of:

[0019] (a) Precharge stage: the first switch sw1, the second switch sw2, the third switch sw3, and the fourth switch sw4 are closed, and the detection electrode Top and the isolation electrode Bot are simultaneously precharged to the voltage V1. At the same time, the intermediate node NodeX and the substrate of the fourth switch sw4 are also precharged to the voltage V1. At this time, the detection electrode Top and the surrounding parasitic nodes are at the same potential, and the reset switch sw7 is closed, and the operational amplifier LNA is in reset mode;

[0020] (b) the first switch sw1, the second switch sw2, the third switch sw3, and the fourth switch sw4 are turned off, and the pre-charging stage ends;

[0021] (c) The fifth switch sw5 and the sixth switch sw6 are closed, and the intermediate node NodeX and the isolation electrode Bot are reset to the reference voltage V2; at the same time, the substrate bias voltage of the third switch sw3 is reduced to V2;

[0022] (d) The reset switch sw7 is opened, and then the fourth switch sw4 is closed. At this time, the parasitic capacitor Cs and the operational amplifier LNA together form an integrator, and the voltage of the detection electrode Top becomes V2;

[0023] (e) The substrate bias of the first switch sw1 and the second switch sw2 and the gate control voltage of the first switch sw1 become V2; finally, all signals related to the target capacitance Cf formed between the finger and the detection electrode Top will fall on the parasitic capacitance Cs, forming a voltage difference with the reference voltage V2; and

[0024] (f) Analyzing the pressure differential.

[0025] In each stage of this method, the focus is on completing the pre-charging, resetting, integration and compensation of the signal. By implementing this sequence, compensation for the surrounding environment and circuit parasitic background capacitance can be achieved, thereby maximizing the collection of the fingerprint net signal. At the same time, by loading a suitable bias voltage at each stage, the leakage current of each node in the signal link is reduced to the lowest possible level, which can maximize the tolerance of the distortion of the fingerprint signal caused by the mismatch of the integrated circuit manufacturing process and the static leakage current, thereby meeting the high requirements for sensitivity and dynamic range.

[0026] The present invention collects fingerprint signals only by changing the internal potential, thereby avoiding the introduction of external electrodes and simplifying the application scenarios of fingerprint detection; by introducing special switches and signal control sequences, the negative impact of parasitic capacitance and static leakage current on signal distortion is suppressed to the greatest extent, achieving high sensitivity and dynamic range. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A circuit diagram of an example of the present invention;

[0028] Figure 2 A schematic diagram of symbols of a P-type MOS switch and an N-type MOS switch used in an example of the present invention;

[0029] Figure 3 Schematic diagram of parasitic capacitance associated with sampling electrode Top in an example of the present invention;

[0030] Figure 4 It is a schematic diagram of the circuit state when the circuit of the embodiment of the present invention is in the pre-charging stage;

[0031] Figure 5 Schematic diagram of the circuit state at the end of the circuit pre-charging stage according to the embodiment of the present invention;

[0032] Figure 6 It is a schematic diagram of the circuit state when the circuit of the embodiment of the present invention is in the reset stage;

[0033] Figure 7It is a schematic diagram of the circuit state when the circuit of the embodiment of the present invention is in the signal integration stage;

[0034] Figure 8 It is a schematic diagram of the circuit state when the circuit of the embodiment of the present invention is in the final parasitic parameter compensation; DETAILED DESCRIPTION

[0035] Embodiments of the present invention will be described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. On the contrary, embodiments of the present invention include all changes, modifications and equivalents that fall within the spirit and connotation of the appended claims.

[0036] like Figure 1 FIG. 2 is a schematic diagram of an embodiment of the present invention. Figure 2 It is a symbolic schematic diagram of a P-type MOS switch and an N-type MOS switch, wherein the first switch sw1, the second switch sw2, and the third switch sw3 are all PMOS switches, and the fourth switch sw4, the fifth switch sw5, and the sixth switch sw6 are all NMOS switches, including a source terminal S, a drain terminal D, a substrate B, and a gate control terminal G; the capacitive fingerprint pixel circuit includes a voltage generator VPRG_1, a voltage generator VPRG_2, a switch element sw, a reference voltage source REF_1, a reference voltage source REF_2, a detection electrode Top, an isolation electrode Bot, an intermediate node NodeX, an operational amplifier LNA for a signal operation function, a target capacitance Cf is formed between a finger and the detection electrode Top, and a parasitic capacitance Cs is formed between the isolation electrode Bot and the detection electrode Top

[0037] As an embodiment of the present invention: the drain ends of the first switch sw1 and the second switch sw2 are connected to the detection electrode Top and the isolation electrode Bot respectively, the source ends and substrates of the first switch sw1 and the second switch sw2 are commonly connected to the voltage generator VPRG_1, the source end and substrate of the third switch sw3 are commonly connected to the voltage generator VPRG_2, and its drain end is connected to the intermediate node NodeX, the source end of the fourth switch sw4 is connected to the detection electrode Top, and its drain end and substrate are commonly connected to the intermediate node NodeX, the source end of the fifth switch sw5 is connected to the intermediate node NodeX, its drain end is connected to the negative input end of the operational amplifier LNA, and its substrate is connected to the reference voltage source REF_2 pin, the source end of the sixth switch sw6 is connected to the detection electrode Top, its drain end is connected to the output end of the operational amplifier LNA, and its substrate is grounded, and the two ends of the reset switch sw7 are respectively connected to the negative input end and the output end of the operational amplifier LNA.

[0038] Figure 3The parasitic background capacitance associated with the detection electrode Top is given, including the parasitic capacitance Cs between the isolation electrode Bot and the parasitic capacitance C between the gate control terminal of the first switch sw1 00 , and the parasitic capacitance C between the substrate of the first switch sw1 01 ; and the parasitic capacitance C between the fourth sw4 gate control terminal 30 , and the parasitic capacitance C between the substrate of the fourth switch sw4 31 However, the presence of these capacitors will have a negative impact on the dynamic range and signal-to-noise ratio of the entire sampling result, and they are parasitic quantities that need to be compensated as much as possible during circuit operation.

[0039] The following provides a switch and signal control sequence suitable for the operation of the above circuit (i.e., a capacitive fingerprint pixel detection method) to solve the above negative effects. In order to simplify the description and facilitate understanding, each voltage generator will be described directly by marking its output value. It can be understood that the values ​​marked below are not intended to be a limitation of the present invention. Other current, voltage and other parameters can be provided according to actual needs. The method includes the following steps:

[0040] (a) Pre-charge stage, such as Figure 4 As shown, the first switch sw1, the second switch sw2, the third switch sw3, and the fourth switch sw4 are closed, and the detection electrode Top and the isolation electrode Bot are simultaneously precharged to a voltage V1, which can be a voltage of 5 to 10V, such as 7V, 8V, etc. At the same time, the intermediate node NodeX together with the substrate of the fourth switch sw4 are also precharged to a voltage V1, which can be a voltage of 5 to 10V, such as 7V, 8V, etc. At this time, the detection electrode Top and the surrounding parasitic nodes are at the same potential, and the reset switch sw7 is closed, and the operational amplifier LNA is in reset mode;

[0041] (b) If Figure 5 As shown, the first switch sw1, the second switch sw2, the third switch sw3, and the fourth switch sw4 are disconnected, and the pre-charging stage ends;

[0042] (c) If Figure 6 As shown, the fifth switch sw5 and the sixth switch sw6 are closed, and the intermediate node NodeX and the isolation electrode Bot are reset to the reference voltage V2, which can be 0.5 to 2V, such as 1V, 1.5V, etc.; at the same time, the substrate bias voltage of the third switch sw3 is reduced to V2, which can be 0.5 to 2V, such as 1V, 1.5V, etc. Since this voltage is the same as the reference voltage in the following integration stage, the leakage current from the node to the signal link is reduced to a minimum state;

[0043] (d) If Figure 7As shown, the reset switch sw7 is disconnected, and then the fourth switch sw4 is closed. At this time, the parasitic capacitor Cs and the operational amplifier LNA together form an integrator, and the parasitic capacitor Cs plays the role of an integrating capacitor. The voltage of the detection electrode Top becomes V2, which can be 0.5 to 2V, such as 1V, 1.5V, etc.;

[0044] (e) If Figure 8 As shown, the substrate bias of the first switch sw1 and the second switch sw2 and the gate control voltage of the first switch sw1 become V2, which can be 0.5 to 2V, such as 1V, 1.5V, etc.; finally, all the signals related to the target capacitance Cf formed between the finger and the detection electrode Top will fall on the integration capacitor, and a voltage difference will be formed between the reference voltage (V2, which can be 0.5 to 2V, such as 1V, 1.5V, etc.); and

[0045] (f) Analyzing the pressure difference. For example, the pressure difference may be sampled by a subsequent ADC to obtain a specific digital value.

[0046] In the above steps, it can be seen that among the several nodes with parasitic capacitances between the detection electrode Top and the isolation electrode Bot, the parasitic capacitance Cs between the detection electrode Top and the isolation electrode Bot is transformed into an integral capacitance, and the parasitic capacitance Cs formed between the first switch sw1 and the detection electrode Top is transformed into an integral capacitance. 00 , C 01 Since all nodes are at V1 at the beginning and at V2 at the end, there is no parasitic charge effect; the capacitance C between the substrate of the fourth switch sw4 31 , since the initial voltage is V1 and the final voltage is V2, V1>V2, there is no parasitic capacitance effect; it can be seen that after this series of switch signal control, except for C 30 In addition, the other parasitic capacitance effects are well self-compensated; in addition, several nodes related to the entire signal chain, including the substrate of the third switch sw3 and the substrate of the first switch sw1, are converted to V2 as early as possible, which is the same as the reference voltage of the integrator, so there is almost no static leakage current.

[0047] It is understandable that, for those skilled in the art in the field of the present invention, corresponding equivalent transformations can be made based on the technical solution and concept of the present invention, and equivalent substitutions without creativity should fall within the scope disclosed by the present invention. In addition to being used in the field of fingerprint detection, the present invention can also be used in applications that require detection of other small signals.

Claims

1. A capacitive fingerprint pixel detection circuit, characterized in that: It includes a voltage generator VPRG_1, a voltage generator VPRG_2, a switch element, a reference voltage source REF_1, a reference voltage source REF_2, a detection electrode Top, an isolation electrode Bot, an intermediate node NodeX, an operational amplifier LNA for a signal operation function, a target capacitance Cf is formed between a finger and the detection electrode Top, and a parasitic capacitance Cs is formed between the isolation electrode Bot and the detection electrode Top; The switch element comprises a first switch sw1, a second switch sw2, a third switch sw3, a fourth switch sw4, a fifth switch sw5, a sixth switch sw6 and a reset switch sw7, wherein the first switch sw1 to the sixth switch sw6 are all CMOS switches; One end of the first switch sw1 and the second switch sw2 and the substrate are commonly connected to the voltage generator VPRG_1, and the other ends are respectively connected to the detection electrode Top and the isolation electrode Bot, the reset switch sw7 is connected across the negative input and output of the operational amplifier LNA, the positive input of the operational amplifier LNA is connected to the reference voltage source REF_1 pin, the isolation electrode Bot and the output of the operational amplifier LNA are connected through the sixth switch sw6, the negative input of the operational amplifier LNA is connected to one end of the fifth switch sw5, the other end of the fifth switch sw5 is connected to the intermediate node NodeX, and the substrate of the fifth switch sw5 is connected to the reference voltage source REF_2 pin, one end of the fourth switch sw4 and the substrate are commonly connected to the intermediate node NodeX, and the other end is connected to the detection electrode Top, one end of the third switch sw3 is connected to the intermediate node NodeX, and the other end and the substrate are commonly connected to the voltage generator VPRG_2; The drain end of the first switch sw1 is connected to the detection electrode Top, the drain end of the second switch sw2 is connected to the isolation electrode Bot, and the source end and substrate of the first switch sw1 and the second switch sw2 are commonly connected to the voltage generator VPRG_1; The source terminal and substrate of the third switch sw3 are commonly connected to the voltage generator VPRG_2, and the drain terminal thereof is connected to the intermediate node NodeX; The source end of the fourth switch sw4 is connected to the detection electrode Top, and the drain end and the substrate thereof are connected to the intermediate node NodeX; The source end of the fifth switch sw5 is connected to the intermediate node NodeX, the drain end thereof is connected to the negative input end of the operational amplifier LNA, and the substrate reference voltage source REF_2 pin thereof is connected; The source end of the sixth switch sw6 is connected to the detection electrode Top, the drain end thereof is connected to the output end of the operational amplifier LNA, and the substrate thereof is grounded.

2. A capacitive fingerprint pixel detection circuit according to claim 1, characterized in that: The first switch sw1 , the second switch sw2 , and the third switch sw3 are all PMOS switches, and the fourth switch sw4 , the fifth switch sw5 , and the sixth switch sw6 are all NMOS switches.

3. A capacitive fingerprint pixel detection method, characterized in that: Includes steps: (a) Precharge stage: the first switch sw1, the second switch sw2, the third switch sw3, and the fourth switch sw4 are closed, and the detection electrode Top and the isolation electrode Bot are simultaneously precharged to the voltage V1. At the same time, the intermediate node NodeX and the substrate of the fourth switch sw4 are also precharged to the voltage V1. At this time, the detection electrode Top and the surrounding parasitic nodes are at the same potential, and the reset switch sw7 is closed, and the operational amplifier LNA is in reset mode. (b) disconnecting the first switch sw1, the second switch sw2, the third switch sw3, and the fourth switch sw4, and the pre-charging stage ends; (c) The fifth switch sw5 and the sixth switch sw6 are closed, and the intermediate node NodeX and the isolation electrode Bot are reset to the reference voltage V2; at the same time, the substrate bias voltage of the third switch sw3 is reduced to V2; (d) The reset switch sw7 is opened, and then the fourth switch sw4 is closed. At this time, the parasitic capacitor Cs and the operational amplifier LNA together form an integrator, and the voltage of the detection electrode Top becomes V2; (e) The substrate bias of the first switch sw1 and the second switch sw2 and the gate control voltage of the first switch sw1 become V2; finally, all signals related to the target capacitance Cf formed between the finger and the detection electrode Top will fall on the parasitic capacitance Cs, forming a voltage difference with the reference voltage V2; as well as (f) Analyzing the pressure differential.

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