Semiconductor package

Abstract

A semiconductor package includes a base wafer including a first substrate and at least one first through-hole electrode extending through the first substrate, and a first semiconductor chip disposed on the base wafer. The first semiconductor chip includes a second substrate and at least one second through-hole electrode extending through the second substrate. The at least one second through-hole electrode is disposed on the at least one first through-hole electrode to electrically connect to the at least one first through-hole electrode. A first diameter of the at least one first through-hole electrode in a first direction is greater than a second diameter of the at least one second through-hole electrode in the first direction.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0135462, filed on November 6, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments relate to semiconductor packages, and more specifically, to semiconductor packages including through-hole electrodes. Background Technology

[0004] In semiconductor packaging, high-bandwidth memory (HBM) can be stacked on a wafer using a wafer-on-wafer (CoW) process. Additionally, through-silicon vias (TSVs), which are electrical connections that pass through the wafer, can be formed on the wafer. As the size of TSVs and the thickness of the wafer decrease while still requiring high speed and high capacity, the wafer may be more susceptible to warpage damage in subsequent processes following the CoW process. Summary of the Invention

[0005] One or more example embodiments provide semiconductor packages with high reliability.

[0006] According to one aspect of an exemplary embodiment, a semiconductor package is provided. The semiconductor package may include: a base wafer including a first substrate and at least one first through-hole electrode extending through the first substrate; and a first semiconductor chip disposed on the base wafer. The first semiconductor chip includes: a second substrate; and at least one second through-hole electrode extending through the second substrate. The at least one second through-hole electrode is disposed on the at least one first through-hole electrode for electrical connection to the at least one first through-hole electrode. A first diameter of the at least one first through-hole electrode in a first direction is greater than a second diameter of the at least one second through-hole electrode in the first direction.

[0007] According to one aspect of another example embodiment, a semiconductor package is provided. The semiconductor package may include: a base wafer including a first substrate and a first through-hole electrode extending through the first substrate; and a semiconductor chip disposed on the base wafer and including a second substrate and a second through-hole electrode extending through the second substrate. A first diameter of the first through-hole electrode in a first direction is different from a second diameter of the second through-hole electrode in the first direction. A first aspect ratio of the first through-hole electrode is equal to or greater than a second aspect ratio of the second through-hole electrode.

[0008] According to one aspect of another example embodiment, a semiconductor package is provided. The semiconductor package may include: a package substrate; an interposer disposed on the package substrate; a base chip including a first substrate and at least one first through-hole electrode extending through the first substrate; a first semiconductor chip disposed on the base chip and including a second substrate and at least one second through-hole electrode extending through the second substrate; and a processor chip disposed on the interposer and spaced apart from the base chip in a first direction. The at least one second through-hole electrode is disposed on the at least one first through-hole electrode for electrical connection to the at least one first through-hole electrode. A first diameter of the at least one first through-hole electrode in the first direction is greater than a second diameter of the at least one second through-hole electrode in the first direction. Attached Figure Description

[0009] The above and / or other aspects will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a cross-sectional view showing a semiconductor package according to an example embodiment;

[0011] Figures 2 to 9 This illustrates the manufacturing process according to an example embodiment. Figure 1 A cross-sectional view of a method for developing semiconductor packaging components;

[0012] Figure 10 This is a cross-sectional view of a semiconductor package according to an example embodiment, wherein the spacing of the through-hole electrodes of the semiconductor chip is substantially equal to the spacing of the through-hole electrodes of the base wafer.

[0013] Figure 11 This is a cross-sectional view of a semiconductor package according to an example embodiment, wherein the spacing of the through-hole electrodes of the semiconductor chip is different from the spacing of the through-hole electrodes of the base wafer; and

[0014] Figure 12 It is a semiconductor package according to an example embodiment. Detailed Implementation

[0015] Figure 1 This is a cross-sectional view showing a semiconductor package 10 according to an example embodiment.

[0016] refer to Figure 1 The semiconductor package 10 may include a plurality of first semiconductor chips 455 and second semiconductor chips 555 sequentially stacked on a base wafer 250. The sidewalls of the plurality of first semiconductor chips 455 and second semiconductor chips 555 may be covered by molded elements 600 on the base wafer 250.

[0017] The base wafer 250 may include a first insulating interlayer 110, a second insulating interlayer 150, and a first conductive bump 180, which are sequentially stacked downwards on the lower surface (or first surface 101) of the first substrate 100. That is, referring to... Figure 1 A first insulating intermediate layer 110 is stacked below the lower surface 101 of the first substrate 100, a second insulating intermediate layer 150 is stacked below the first insulating intermediate layer 110, and a first conductive bump 180 is stacked below the second insulating intermediate layer 150. The base wafer 250 may also include a first through-hole electrode 145 extending through the first substrate 100 and the first insulating intermediate layer 110, a first wiring structure 170 disposed in the second insulating intermediate layer 150, a first passivation layer 210 disposed on the top surface (or second surface 102) of the first substrate 100 and also covering the upper sidewall of the first through-hole electrode 145, and a first conductive pad 220 disposed on the first passivation layer 210 and contacting the upper surface of the first through-hole electrode 145.

[0018] The first substrate 100 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), or III-V compounds, such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), etc. In some example embodiments, the first substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0019] The first substrate 100 may have a first surface (e.g., bottom surface) 101 and a second surface (e.g., top surface) 102 opposite to the first surface 101, and the distance between the first surface 101 and the second surface 102 (i.e., the thickness of the first substrate 100 in the vertical direction substantially perpendicular to the first surface 101) may be a first thickness T1.

[0020] In an example embodiment, circuit elements may be formed beneath a first surface 101 of the first substrate 100, which may be covered by a first insulating intermediate layer 110. That is, circuit elements may be disposed between the first substrate 100 and the first insulating intermediate layer 110. For example, a transistor may be formed between the first substrate 100 and the first insulating intermediate layer 110 as a circuit element. The transistor may include a gate structure beneath the first surface 101 of the first substrate 100 and an impurity region in the lower portion of the first substrate 100 adjacent to the gate structure. However, the embodiments are not limited to this, and for example, diodes, resistors, inductors, capacitors, etc., may be formed as circuit elements between the first substrate 100 and the first insulating intermediate layer 110.

[0021] The first insulating intermediate layer 110 may include oxides (O) 2-For example, silicon oxide (SiO2). A contact plug can be formed through the first insulating intermediate layer 110 to contact the aforementioned impurity region and / or gate structure. The contact plug may include metal, metal nitride, metal silicide, etc.

[0022] The first through-hole electrode 145 may extend through both the first substrate 100 and the first insulating intermediate layer 110 to protrude outward from the second surface 102 of the first substrate 100 (e.g., Figure 1 (As shown, protruding upwards). In an example embodiment, the first through-hole electrode 145 may include a first conductive layer 130 and a first insulating pattern 125 disposed on the outer sidewall of the first conductive layer 130, and may also include a first blocking pattern disposed between the first conductive layer 130 and the first insulating pattern 125.

[0023] The first insulating pattern 125 may include oxides (O) 2- For example, silicon oxide (SiO2), the first conductive layer 130 may include metals such as tungsten (W), copper (Cu), aluminum (Al), etc., and the first blocking pattern may include metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), etc.

[0024] In an example embodiment, the first through-hole electrode 145 can be in the horizontal direction (in Figure 1 In the middle; that is, having a first diameter D1 on a first surface 101 substantially parallel to the first substrate 100, and having a first length L1 in the vertical direction (i.e., the direction substantially perpendicular to the first surface 101).

[0025] As an example embodiment, Figure 1 Six first through-hole electrodes 145 spaced apart from each other are shown; however, the example embodiment is not limited to this and any number of first through-hole electrodes 145 may be formed in the semiconductor package 10.

[0026] The second insulating intermediate layer 150 may include, for example, silicon oxide (SiO2) doped with fluorine (F) or carbon (C), porous SiO2, spin-coated organic polymers, or inorganic polymers, such as hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), etc.

[0027] In an example embodiment, the first wiring structure 170 may include at least one first wiring 165 disposed in the second insulating intermediate layer 150, and at least one first via 160 connected to the first wiring 165 or connecting the first wiring 165 and the first through-hole electrode 145 to each other. Figure 1A first via 160 and a first wiring 165 are shown stacked sequentially below the lower surface of the first through-hole electrode 145. Each of the first wiring 165 and the first via 160 may include metal, metal nitride, metal silicide, etc.

[0028] A first conductive bump 180 may be formed below the second insulating interlayer 150 to contact the lower surface of the first wiring 165. The first conductive bump 180 may comprise a metal (e.g., silver (Ag), copper (Cu), etc.) or an alloy, and may be formed as solder.

[0029] A first passivation layer 210 may be formed on a second surface (i.e., top surface) 102 of the first substrate 100 and may cover the upper portion of the sidewall of the first through-hole electrode 145. The first passivation layer 210 may include oxides and / or nitrides. In an example embodiment, the first passivation layer 210 may include multiple different layers, including a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence.

[0030] The first conductive pad 220 may be formed on the first passivation layer 210 to contact the upper surface of the first through-hole electrode 145. The first conductive pad 220 may include metal, metal nitride, metal silicide, etc.

[0031] Furthermore, a redistribution layer may be formed between the first through-hole electrode 145 and the first conductive pad 220.

[0032] In an example embodiment, the base wafer 250 may include logic devices or controllers. Alternatively, the base wafer 250 may include memory devices, such as dynamic random access memory (DRAM) devices.

[0033] Except that the first semiconductor chip 455 includes a second substrate 300 and a second through-hole electrode 345 instead of the first substrate 100 and the first through-hole electrode 145, the structure of the first semiconductor chip 455 may be substantially the same as or similar to the structure of the base wafer 250.

[0034] More specifically, similar to the base wafer 250 described above, the first semiconductor chip 455 may include a third insulating interlayer 310, a fourth insulating interlayer 350, and a second conductive bump 380, which are stacked downwards sequentially below the lower surface of the second substrate 300. In addition to the second through-hole electrode 345 extending through the second substrate 300 and the third insulating interlayer 310, the first semiconductor chip 455 may also include a second wiring structure 370 disposed in the fourth insulating interlayer 350, a second passivation layer 410 disposed on the second substrate 300 and covering the upper portion of the sidewall of the second through-hole electrode 345, and a second conductive pad 420 disposed on the second passivation layer 410 and contacting the upper surface of the second through-hole electrode 345.

[0035] The second substrate 300 may have a first surface (i.e., lower surface) 301 and a second surface (i.e., upper / top surface) 302 opposite to the first surface 301, and the distance between the first surface 301 and the second surface 302 (i.e., the thickness of the second substrate 300 in the vertical direction (i.e., in the direction perpendicular to the extending direction of the first surface 301 and the second surface 302)) may be a second thickness T2. In an example embodiment, the second thickness T2 may be less than the first thickness T1.

[0036] In an example embodiment, circuit elements may be formed beneath a first surface 301 of the second substrate 300, which may be covered by a third insulating intermediate layer 310. That is, circuit elements may be formed between the second substrate 300 and the third insulating intermediate layer 310. Additionally, contact plugs may be formed through the third insulating intermediate layer 310.

[0037] The first through-hole electrode 345 may extend through the second substrate 300 and the third insulating intermediate layer 310 to protrude from the second surface (i.e., the top surface) 302 of the second substrate 300. In an example embodiment, the second through-hole electrode 345 may include a second conductive layer 330 and a second insulating pattern 325 disposed on the outer sidewall of the second conductive layer 330, and may also include a second blocking pattern between the second conductive layer 330 and the second insulating pattern 325.

[0038] The first through-hole electrode 345 may have a second diameter D2 in the horizontal direction and a second length L2 in the vertical direction. In an example embodiment, the second diameter D2 of the second through-hole electrode 345 may be smaller than the first diameter D1 of the first through-hole electrode 145, and the second length L2 of the second through-hole electrode 345 may be smaller than the first length L1 of the first through-hole electrode 145.

[0039] However, the ratio of the first length L1 to the first diameter D1 (e.g., the first aspect ratio) may be substantially equal to or greater than the ratio of the second length L2 to the second diameter D2 (e.g., the second aspect ratio).

[0040] exist Figure 1 In the example embodiment shown, the semiconductor package 10 includes six second through-hole electrodes 345 spaced apart from each other; however, the example embodiment is not limited to this and any number of multiple second through-hole electrodes 345 may be formed.

[0041] In an example embodiment, the second wiring structure 370 may include at least one second wiring 365 disposed in the fourth insulating intermediate layer 350, and at least one second via 360 connected to the second wiring 365 or connecting the second wiring 365 and the second through-hole electrode 345 to each other.

[0042] In an example embodiment, one or more first semiconductor chips 455 may be stacked on a base wafer 250 in a vertical direction. Figure 1 Three first semiconductor chips 455 are shown stacked on a base wafer 250; however, the example embodiment is not limited to this. For example, the first semiconductor chips 455 may be stacked in seven layers.

[0043] In an example embodiment, the first semiconductor chip 455 may be a memory chip, such as a DRAM chip.

[0044] In addition, multiple first semiconductor chips 455 may be spaced apart from each other in the horizontal direction.

[0045] The second semiconductor chip 555 may be stacked on top of the topmost of the stacked first semiconductor chips 455, or stacked on one of the first semiconductor chips 455. In an example embodiment, the second semiconductor chip 555 may differ from the first semiconductor chip 455 and may not include any through-hole electrodes, and the third substrate 500 in the second semiconductor chip 555 may have a third thickness T3 in the vertical direction. The third thickness T3 of the third substrate 500 may be greater than the second thickness T2 of the second substrate 300 in the first semiconductor chip 455.

[0046] In an example embodiment, the second semiconductor chip 555 may be a memory chip, such as a DRAM chip.

[0047] In an example embodiment, a third adhesion layer 440 may be formed between the base wafer 250 and the bottommost of the plurality of first semiconductor chips 455, between two adjacent first semiconductor chips 445 stacked in the vertical direction, and between the topmost of the plurality of first semiconductor chips 455 and the second semiconductor chip 555. The plurality of first semiconductor chips 455 and the second semiconductor chip 555 can be electrically connected to each other via second conductive pads 420 and second conductive bumps 380.

[0048] In an example embodiment, the molding element 600 may include epoxy molding compound (EMC).

[0049] In an example embodiment, in the semiconductor package 10, the first thickness T1 of the first substrate 100 in the base wafer 250 may be greater than the second thickness T2 of the second substrate 300 in each of the plurality of first semiconductor chips 455 stacked on the first substrate 100, thereby reducing damage to the semiconductor package 10 due to potential warping. Therefore, the semiconductor package 10 can be manufactured with enhanced reliability and less waste and rework.

[0050] The second diameter D2 of the second through-hole electrode 345 disposed in each of the plurality of first semiconductor chips 455 may be smaller than the first diameter D1 of the first through-hole electrode 145 disposed in the base wafer 250, so that the first semiconductor chips 455 may have an increased error margin relative to their positioning in the layout of circuit patterns or wiring.

[0051] Additionally, in the example embodiment, the second aspect ratio of the second through-hole electrode 345 may be substantially equal to or less than the first aspect ratio of the first through-hole electrode 145. Therefore, even if the second through-hole electrode 345 has a relatively small diameter, the characteristics of the second through-hole electrode 345 can be reduced accordingly without deterioration.

[0052] Furthermore, the second thickness T2 of the second substrate 300 in each first semiconductor chip 455 may be less than the first thickness T1 of the first substrate 100 in the base wafer 250, so a greater number of first semiconductor chips 455 may be stacked on the base wafer 250, and the semiconductor package 10 may have increased capacity and enhanced performance.

[0053] Figures 2 to 9 This illustrates the manufacturing process according to an example embodiment. Figure 1 A cross-sectional view of a method for a semiconductor package 10.

[0054] refer to Figure 2 Circuit elements may be formed on the first surface 101 of the first substrate 100 (i.e., Figure 1 The first insulating intermediate layer 110 may be formed on the first surface 101 of the first substrate 100 to cover / insulate the circuit elements.

[0055] For example, a transistor may be formed on a first surface 101 of the first substrate 100 as a circuit element. The transistor may include a gate structure on the first surface 101 of the first substrate 100 and an impurity region at the upper part of the first substrate 100.

[0056] A contact plug can be formed through the first insulating intermediate layer 110 to contact the impurity region and / or the gate structure.

[0057] A first primary through-hole electrode 140 can be formed by partially penetrating through the first substrate 100.

[0058] Specifically, a first etching mask can be used to etch the upper portion of the first insulating intermediate layer 110 and the first substrate 100 to form a first trench. A first insulating layer 120 can be formed on the inner wall of the first trench, the first insulating intermediate layer 110, and the contact plug. A first conductive layer 130 can be formed on the first insulating layer 120 to fill the first trench. The first conductive layer 130 and the first insulating layer 120 can be planarized until the upper surface of the first insulating intermediate layer 110 is exposed to form a first primary through-hole electrode 140 that includes the first insulating layer 120 and the first conductive layer 130 and fills the first trench. The first primary through-hole electrode 140 may also include a first barrier layer between the first conductive layer 130 and the first insulating layer 120.

[0059] A second insulating intermediate layer 150, including the first wiring structure 170 formed therein, may be disposed on the first insulating intermediate layer 110, the contact plug, and the first primary through-hole electrode 140.

[0060] In an example embodiment, the first wiring structure 170 may include at least one first wiring 165 and at least one first via 160, the at least one first via 160 being connected to the first wiring 165 or connecting the first wiring 165 and the first primary through-via electrode 140 to each other. Figure 2 A first via 160 and a first wiring 165 are shown sequentially stacked on a first primary through-hole electrode 140. However, the example embodiment is not limited to a single first wiring 165 and a single first via 160.

[0061] In the example embodiment, the first wiring 165 and the first via 160 can be formed by a dual damascene process or a single damascene process.

[0062] A first conductive bump 180 may be formed on the second insulating intermediate layer 150 to contact the upper surface (or exposed surface) of the first wiring 165.

[0063] refer to Figure 3 A first adhesion layer 190 can be formed on the second insulating intermediate layer 150 and the first wiring 165 to cover the first conductive bump 180, and the first processing substrate 200 can be attached to the first adhesion layer 190.

[0064] The first adhesion layer 190 and the first processing substrate 200 can be stacked sequentially to form a wafer support system (WSS).

[0065] The first substrate 100 can be inverted using a WSS (Wide Screen), so that the second surface 102 of the first substrate 100 faces upwards, as shown in the figure, and a portion of the first substrate 100 adjacent to the second surface 102 can be removed to expose the upper portion of the first primary through-hole electrode 140. This portion of the first substrate 100 can be removed by an etch-back process and / or a polishing process.

[0066] refer to Figure 4 A first passivation layer 210 may be formed on the second surface (i.e., top surface) 102 of the first substrate 100 and the exposed portion of the first primary through-hole electrode 140, and the upper part of the first passivation layer 210 may be planarized until the upper surface of the first conductive layer 130 of the first primary through-hole electrode 140 is exposed.

[0067] Therefore, a portion of the first insulating layer 120 on the first conductive layer 130 of the first initial through-hole electrode 140 can be removed to form a first insulating pattern 125, and a first through-hole electrode 145 including the first conductive layer 130 and the first insulating pattern 125 on the sidewall of the first conductive layer 130 can be formed.

[0068] In an example embodiment, the planarization process can be performed using a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0069] In an example embodiment, the first passivation layer 210 may include a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence.

[0070] refer to Figure 5 A first conductive pad 220 can be formed on the first passivation layer 210 to contact the upper surface of the exposed first through-hole electrode 145.

[0071] A redistribution layer may be further formed between the first through-hole electrode 145 and the first conductive pad 220.

[0072] Through the above process, a base wafer 250 that can be supported by a WSS and may include a first through-hole electrode 145 can be formed.

[0073] In an example embodiment, the first through-hole electrode 145 may have a first diameter D1 in a horizontal direction substantially parallel to the first surface 101 of the first substrate 100, and a first length L1 in a vertical direction substantially perpendicular to the first surface 101 of the first substrate 100. Additionally, the first substrate 100 in the base wafer 250 may have a first thickness T1 in the vertical direction.

[0074] refer to Figure 6 Executable and Reference Figures 2 to 5 The processes shown are substantially the same or similar to those for forming the first semiconductor chip 455.

[0075] That is, circuit elements can be formed on the first surface 301 of the second substrate 300, and a third insulating intermediate layer 310 can be formed on the first surface 301 of the second substrate 300 to cover the circuit elements. Contact plugs can be formed through the third insulating intermediate layer 310 to contact impurity regions and / or gate structures. A second primary through-hole electrode, including a second insulating layer and a second conductive layer 330, can be formed partially through the second substrate 300.

[0076] A fourth insulating intermediate layer 350, which includes a second wiring structure 370, may be formed on the third insulating intermediate layer 310, the contact plug, and the second primary through-hole electrode. The second wiring structure 370 may include at least one second wiring 365 and at least one second via 360.

[0077] A second conductive bump 380 may be formed on the fourth insulating intermediate layer 350 to contact the upper surface of the second wiring 365. A second adhesive layer may be formed on the fourth insulating intermediate layer 350 and the second wiring 365 to cover the second conductive bump 380, and a second processing substrate may be attached to the second adhesive layer. The second processing substrate may be used to invert the second substrate 300 so that the second surface 302 of the second substrate 300 faces upward, and the upper portion of the second substrate 300 adjacent to the second surface 302 may be removed to expose a portion of the second primary through-hole electrode.

[0078] A second passivation layer 410 may be formed on the second surface 302 of the second substrate 300 and the exposed portion of the second primary through-hole electrode, and the upper portion of the second passivation layer 410 may be planarized until the upper surface of the second conductive layer 330, which exposes the second primary through-hole electrode, is exposed. Therefore, a portion of the second insulating layer on the second conductive layer 330 of the second primary through-hole electrode may be removed to form a second insulating pattern 325, and a second through-hole electrode 345 comprising the second conductive layer 330 and the second insulating pattern 325 on the sidewalls of the second conductive layer 330 may be formed. A second conductive pad 420 may be formed on the second passivation layer 410 to contact the upper surface of the second through-hole electrode 345.

[0079] A strip 430 can be formed on the second conductive pad 420 and the second passivation layer 410. The strip 430 can be used to flip the second substrate 300 so that the first surface 301 of the second substrate 300 can face upwards. The second adhesive layer and the second processed substrate can be removed to expose the second conductive bump 380 and the fourth insulating intermediate layer 350.

[0080] A third adhesion layer 440 may be formed on the exposed second conductive bump 380 and the fourth insulating intermediate layer 350.

[0081] Through the above process, a stacked wafer 450 including a second through-hole electrode 345 can be formed on the strip 430, and the upper surface of the stacked wafer 450 can be covered by a third adhesion layer 440.

[0082] In an example embodiment, the second diameter D2 of the second through-hole electrode 345 in the horizontal direction may be smaller than the first diameter D1 of the first through-hole electrode 145, thus allowing for a relatively high error margin relative to their positioning in a circuit pattern or wiring layout.

[0083] In addition, the second length L2 of the second through-hole electrode 345 may be less than the first length L1 of the first through-hole electrode 145, and the second thickness T2 of the second substrate 300 in the stacked wafer 450 may be less than the first thickness T1 of the first substrate 100 in the base wafer 250.

[0084] However, in the example embodiment, the ratio of the first length L1 to the first diameter D1 (i.e., the first aspect ratio) may be substantially equal to or greater than the second aspect ratio, i.e., the ratio of the second length L2 to the second diameter D2. Therefore, even if the second through-hole electrode 345 has a relatively small diameter, the second trench used to form the second primary through-hole electrode can be fully filled with the second conductive layer 330 without any gaps, and the characteristics of the second through-hole electrode 345 may not deteriorate.

[0085] In the example embodiment, reference Figure 7 The stacked wafer 450 can be divided into multiple first semiconductor chips 455 by, for example, a dicing process, and multiple first semiconductor chips 455 can be mounted. Figure 7 Two first semiconductor chips 455 in the plurality of first semiconductor chips 455 are arranged such that the second conductive bump 380 of each of the plurality of first semiconductor chips 455 can contact the upper surface of the first conductive pad 220 of the base wafer 250.

[0086] In an example embodiment, a plurality of first semiconductor chips 455 can be bonded to a base wafer 250 using a thermoforming nonconductive paste (TCNCP) process. Specifically, a second conductive bump 380 of each of the plurality of first semiconductor chips 455 can be positioned to contact a corresponding first conductive pad 220 of the base wafer 250 and pressed at an appropriate attachment temperature, such that the second conductive bump 380 can be attached to the first conductive pad 220. Additionally, a third adhesion layer 440 can be formed between the first semiconductor chips 455 and the base wafer 250 to facilitate attachment of the first semiconductor chips 455 and the base wafer 250 to each other.

[0087] When the first semiconductor chip 455 is mounted onto the base wafer 250, the strip 430 can be removed.

[0088] refer to Figure 8 The additional first semiconductor chip 455 can be further stacked on the initial two first semiconductor chips 455 respectively, and the second semiconductor chip 555 can be stacked on the topmost one of the first semiconductor chips 455.

[0089] Multiple first semiconductor chips 455 (including the topmost one of the first semiconductor chips 455) stacked in the vertical direction and second semiconductor chips 555 can also be bonded to each other via the TCNCP process.

[0090] Figure 8 The illustration shows multiple first semiconductor chips 455 stacked in three layers, and a second semiconductor chip 555 formed on a base wafer 250 in one layer. However, the example embodiment is not limited to this. For example, the multiple first semiconductor chips 455 may be stacked in seven layers, and the second semiconductor chip 555 may be formed in one layer.

[0091] In an example embodiment, unlike the first semiconductor chip 455, the second semiconductor chip 555 may not include any through-hole electrodes disposed therein, and the third thickness T3 of the third substrate 500 in the second semiconductor chip 555 in the vertical direction may be greater than the second thickness T2 of the second substrate 300 in the vertical direction in each of the first semiconductor chips 455.

[0092] refer to Figure 9 A molded element 600 can be formed on the base wafer 250 to cover the first semiconductor chip 455 and the second semiconductor chip 555.

[0093] Return to reference Figure 1 ,from Figure 9 The embodiment shown can remove the molding element 600 until the upper surface of the second semiconductor chip 555 can be exposed, and can remove the first adhesion layer 190 of the WSS and the first processing substrate 200 below the base wafer 250 to form a wafer-on-wafer (CoW) package.

[0094] Various electrical tests can be performed on CoW packages, and during testing, the CoW packages may be damaged due to, for example, warping. However, in the example embodiment, the first thickness T1 of the first substrate 100 in the base wafer 250 may be greater than the second thickness T2 of each of the plurality of first semiconductor chips 455 that may be stacked on the base wafer 250, thus reducing damage to the CoW packages due to warping.

[0095] In addition, the second diameter D2 of the second through-hole electrode 345 in each first semiconductor chip 455 may be smaller than the first diameter D1 of the first through-hole electrode 145 in the base wafer 250, so each first semiconductor chip 455 may have a high degree of freedom in the layout of circuit patterns or wiring.

[0096] The second aspect ratio of the second through-hole electrode 345 may be equal to or less than the first aspect ratio of the first through-hole electrode 145. Therefore, even if the second through-hole electrode 345 has a relatively small diameter, its characteristics may not deteriorate.

[0097] Furthermore, the second thickness T2 of the second substrate 300 in each first semiconductor chip 455 may be less than the first thickness T1 of the first substrate 100 in the base wafer 250, so more first semiconductor chips 455 can be stacked on the base wafer 250, and the CoW package including the first semiconductor chip 455 may have high capacity and high performance.

[0098] Figure 10 This is a cross-sectional view of a semiconductor package 11 according to an exemplary embodiment, wherein the spacing of the through-hole electrodes of the semiconductor chip is substantially equal to the spacing of the through-hole electrodes of the base wafer.

[0099] refer to Figure 10 Multiple first semiconductor chips 455 may be arranged horizontally and spaced apart from each other on a base wafer 250. Two more first semiconductor chips 455 may be stacked vertically on top of each of the first semiconductor chips 455, and a second semiconductor chip 555 may be stacked on top of the topmost of the first semiconductor chips 455. However, the number of first semiconductor chips 455 stacked vertically is not limited to this.

[0100] In the example embodiment, the first thickness T1 of the base wafer 250 may be greater than the second thickness T2 of each of the first semiconductor chips 455. Additionally, the second diameter D2 and second length L2 of the second through-hole electrode 345 may be smaller than the first diameter D1 and first length L1 of the first through-hole electrode 145, respectively. However, the first aspect ratio of the first through-hole electrode 145 may be equal to or greater than the second aspect ratio of the second through-hole electrode 345.

[0101] The second spacing P2 between the second through-hole electrodes 345 can be substantially equal to the first spacing P1 between the first through-hole electrodes 145. That is, the distance between the centers of the corresponding second through-hole electrodes 345 can be substantially equal to the distance between the centers of the corresponding first through-hole electrodes 145.

[0102] Figure 11This is a cross-sectional view of a semiconductor package 12 according to an example embodiment, wherein the spacing of the through-hole electrodes of the semiconductor chip is different from the spacing of the through-hole electrodes of the base wafer.

[0103] refer to Figure 11 The third spacing P3 between adjacent second through-hole electrodes 345 can be smaller than the first spacing P1 between adjacent first through-hole electrodes 145.

[0104] Therefore, more second through-hole electrodes 345 can be formed in the same area, and the integration density of each first semiconductor chip 455 can be enhanced.

[0105] However, a redistribution layer 230 may be formed between the base wafer 250 and the first conductive pad 220 to adjust the position of the first conductive pad 220 so that the first conductive pad 220 can be effectively connected to the second conductive bump 380 of the first semiconductor chip 455.

[0106] The redistribution layer 230 may include metals, metal nitrides, metal silicides, etc.

[0107] Figure 12 It is a semiconductor package 13 according to an example embodiment.

[0108] Semiconductor package 13 may be a high-bandwidth memory (HBM) package and may include a reference package. Figure 1 The semiconductor package 10 shown contains substantially the same or similar components. Therefore, detailed descriptions of the same components are omitted here.

[0109] refer to Figure 12 The semiconductor package may include a package substrate 900, an interposer 800, a base chip 255, a plurality of first semiconductor chips 455, and a second semiconductor chip 555. The semiconductor package 13 may also include a processor chip 700 spaced apart from the base chip 255 on the interposer 800.

[0110] The figure shows a base chip 255 and a plurality of first semiconductor chips 455 and second semiconductor chips 555 sequentially stacked on the base chip 255; however, the example embodiment is not limited thereto. For example, the semiconductor package 13 may include four base chips 255 surrounding a processor chip 700, and a plurality of first semiconductor chips 455 and second semiconductor chips 555 on each base chip 255.

[0111] The packaging substrate 900 may include, for example, a printed circuit board (PCB). External connection terminals 980 may be formed under the packaging substrate 900, so that the semiconductor package can be mounted on the module substrate or motherboard via the external connection terminals 980.

[0112] A third conductive bump 880 may be formed between the packaging substrate 900 and the interposer 800, a first conductive bump 180 may be formed between the interposer 800 and the base chip 255, and a fourth conductive bump 780 may be formed between the interposer 800 and the processor chip 700. Additionally, a second conductive bump 380 may be formed between the base chip 255 and the first semiconductor chip 455, between the first semiconductor chips 455, and between the first semiconductor chip 455 and the second semiconductor chip 555.

[0113] A third wiring 810, a fourth wiring 820, and a fifth wiring 830 may be formed in the interposer layer 800. The third wiring 810 can electrically connect some of the first conductive bumps 180 to some of the third conductive bumps 880, the fourth wiring 820 can electrically connect some of the fourth conductive bumps 780 to some of the third conductive bumps 880, and the fifth wiring 830 can electrically connect some of the first conductive bumps 180 to some of the fourth conductive bumps 780.

[0114] The base chip 255 can be formed by dicing the base wafer 250. Therefore, the base chip 255 may include a first substrate 100, a first through-hole electrode 145, a first wiring structure 170, a first conductive pad 220, and a first passivation layer 210.

[0115] In an example embodiment, the base chip 255 may include a logic chip or a controller chip. Alternatively, the base chip 255 may include a memory chip, such as a DRAM chip.

[0116] Multiple first semiconductor chips 455 can be stacked on the base chip 255 in multiple layers. A second semiconductor chip 555 can be stacked on top of the multiple first semiconductor chips 455.

[0117] The third adhesion layer 440 may be formed between the first semiconductor chip 455 and the base chip 255, between the first semiconductor chips 455, and between the first semiconductor chip 455 and the second semiconductor chip 555.

[0118] In an example embodiment, processor chip 700 may include a graphics processing unit (GPU) chip or a central processing unit (CPU) chip.

[0119] Reference Figure 1 The semiconductor package 10 shown is similar. Figure 12 The semiconductor package 13 in the middle can have high capacity and high performance.

[0120] The semiconductor package according to the example embodiment can have high capacity and high performance, and also improves reliability. Furthermore, the semiconductor package according to the example embodiment can have a high degree of freedom in the layout of circuit patterns or wiring.

[0121] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many variations and modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims.

Claims

1. A semiconductor package comprising: a base wafer comprising: a first substrate; and at least one first through-hole electrode extending through the first substrate; and a first semiconductor chip disposed on the base wafer, the first semiconductor chip comprising: a second substrate; and at least one second through-hole electrode extending through the second substrate, wherein the at least one second through-hole electrode is disposed on the at least one first through-hole electrode to electrically connect to the at least one first through-hole electrode, wherein a first diameter of the at least one first through-hole electrode in a first direction is greater than a second diameter of the at least one second through-hole electrode in the first direction, and wherein a first aspect ratio of the at least one first through-hole electrode is substantially equal to or greater than a second aspect ratio of the at least one second through-hole electrode, the first aspect ratio being a ratio of a first length of the at least one first through-hole electrode in a second direction substantially perpendicular to the first direction to the first diameter, and the second aspect ratio being a ratio of a second length of the at least one second through-hole electrode in the second direction to the second diameter.

2. The semiconductor package of claim 1, wherein, a first thickness of the first substrate in the second direction is greater than a second thickness of the second substrate in the second direction.

3. The semiconductor package of claim 1, wherein, a first length of the at least one first through-hole electrode in the second direction is greater than a second length of the at least one second through-hole electrode in the second direction.

4. A semiconductor package comprising: a base wafer comprising: a first substrate; and a first through-hole electrode extending through the first substrate; and a semiconductor chip disposed on the base wafer, the semiconductor chip comprising: a second substrate; and a second through-hole electrode extending through the second substrate, wherein a first diameter of the first through-hole electrode in a first direction is different from a second diameter of the second through-hole electrode in the first direction, and wherein a first aspect ratio of the first through-hole electrode is equal to or greater than a second aspect ratio of the second through-hole electrode, the first aspect ratio being a ratio of a first length of the first through-hole electrode in a second direction substantially perpendicular to the first direction to the first diameter, and the second aspect ratio being a ratio of a second length of the second through-hole electrode in the second direction to the second diameter.

5. The semiconductor package of claim 4, further comprising: a plurality of first through-hole electrodes comprising the first through-hole electrode, the plurality of first through-hole electrodes spaced apart from one another in the first direction; and a plurality of second through-hole electrodes comprising the second through-hole electrode, the plurality of second through-hole electrodes spaced apart from one another in the first direction, wherein a first pitch of the plurality of first through-hole electrodes is substantially equal to a second pitch of the plurality of second through-hole electrodes.

6. The semiconductor package of claim 5, wherein, The plurality of second through-hole electrodes are respectively disposed on the plurality of first through-hole electrodes to be electrically connected to the plurality of first through-hole electrodes.

7. The semiconductor package of claim 4, further comprising: a plurality of first through-hole electrodes including the first through-hole electrode, the plurality of first through-hole electrodes being spaced apart from each other in the first direction; and a plurality of second through-hole electrodes including the second through-hole electrode, the plurality of second through-hole electrodes being spaced apart from each other in the first direction, wherein a first pitch of the plurality of first through-hole electrodes is different from a second pitch of the plurality of second through-hole electrodes.

8. The semiconductor package of claim 4, wherein, A first thickness of the first substrate in the second direction is greater than a second thickness of the second substrate in the second direction. 9.A semiconductor package comprising: a package substrate; an interposer disposed on the package substrate; a base chip comprising: a first substrate; and at least one first through-hole electrode extending through the first substrate; a first semiconductor chip disposed on the base chip, the first semiconductor chip comprising: a second substrate; and at least one second through-hole electrode extending through the second substrate; and a processor chip disposed on the interposer and spaced apart from the base chip in a first direction, wherein the at least one second through-hole electrode is disposed on the at least one first through-hole electrode to be electrically connected to the at least one first through-hole electrode, wherein a first diameter of the at least one first through-hole electrode in the first direction is greater than a second diameter of the at least one second through-hole electrode in the first direction, and wherein a first aspect ratio of the at least one first through-hole electrode is substantially equal to or greater than a second aspect ratio of the at least one second through-hole electrode, the first aspect ratio being a ratio of a first length of the at least one first through-hole electrode in a second direction substantially perpendicular to the first direction to the first diameter, and the second aspect ratio being a ratio of a second length of the at least one second through-hole electrode in the second direction to the second diameter.

10. The semiconductor package of claim 9, wherein, The base chip comprises a graphics processing unit (GPU) chip or a central processing unit (CPU) chip.

11. The semiconductor package of claim 9, wherein, The base chip comprises a logic device or a controller, and wherein the first semiconductor chip comprises a memory device. 12.The semiconductor package of claim 9, wherein the interposer comprises: first wiring electrically connecting the base chip and the package substrate to each other; second wiring electrically connecting the processor chip and the package substrate to each other; and third wiring electrically connecting the base chip and the processor chip to each other.

13. The semiconductor package of claim 9, wherein, A first thickness of the first substrate in the second direction is greater than a second thickness of the second substrate in the second direction.

14. The semiconductor package of claim 9, wherein, A first length of the at least one first through-hole electrode in the second direction is greater than a second length of the at least one second through-hole electrode in the second direction.

15. The semiconductor package of claim 9, wherein, A first pitch of the at least one first through-hole electrode is substantially equal to a second pitch of the at least one second through-hole electrode.

16. The semiconductor package of claim 9, further comprising: A plurality of first semiconductor chips including the first semiconductor chip, the plurality of first semiconductor chips being stacked in the second direction.

17. The semiconductor package of claim 16, further comprising: A second semiconductor chip disposed on an uppermost first semiconductor chip of the plurality of first semiconductor chips in the second direction, the second semiconductor chip including a third substrate.

18. The semiconductor package of claim 17, wherein, A third thickness of the third substrate in the second direction is greater than a second thickness of the second substrate in the second direction.

19. The semiconductor package of claim 9, further comprising: A plurality of first semiconductor chips including the first semiconductor chip, the plurality of first semiconductor chips being spaced apart from each other on the base chip in the first direction.

20. A semiconductor package comprising: a package substrate; an interposer disposed on the package substrate; a base chip comprising: a first substrate; and at least one first through-hole electrode extending through the first substrate; a first semiconductor chip disposed on the base chip, the first semiconductor chip comprising: a second substrate; and at least one second through-hole electrode extending through the second substrate; and a processor chip disposed on the interposer and spaced apart from the base chip in a first direction, wherein a first diameter of the at least one first through-hole electrode in the first direction is different from a second diameter of the at least one second through-hole electrode in the first direction, and wherein a first aspect ratio of the at least one first through-hole electrode is equal to or greater than a second aspect ratio of the at least one second through-hole electrode, the first aspect ratio being a ratio of a first length of the at least one first through-hole electrode in a second direction substantially perpendicular to the first direction to the first diameter, and the second aspect ratio being a ratio of a second length of the at least one second through-hole electrode in the second direction to the second diameter.

21. The semiconductor package of claim 20, wherein, A first thickness of the first substrate in the second direction is greater than a second thickness of the second substrate in the second direction.

22. The semiconductor package of claim 20, wherein, A first length of the at least one first through-hole electrode in the second direction is greater than a second length of the at least one second through-hole electrode in the second direction.

23. The semiconductor package of claim 20, wherein, A first pitch of the at least one first through-hole electrode is substantially equal to a second pitch of the at least one second through-hole electrode.

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