Protection Circuit of Linear Regulator, Linear Regulation Module and Device

Abstract

The present application relates to a protection circuit, a linear adjustment module and a device of a linear regulator. The protection circuit of the linear regulator includes a current sampling module, an output voltage detection module and a negative feedback control loop; the current sampling module is respectively connected to the gate and the drain of the power PMOS transistor; the acquisition end of the output voltage detection module is used for connecting the output feedback end of the linear regulator; the input end of the negative feedback control loop is respectively connected to the output end of the current sampling module and the output end of the output voltage detection module, and the output end of the negative feedback control loop is used for connecting the gate of the power PMOS transistor. Based on the above structure, by collecting the changes in the output current and output voltage of the power PMOS transistor, the power PMOS transistor is controlled, and at the same time, the output current limiting function and the output short-circuit protection function are realized; based on this, the linear regulator can be protected to work normally within the allowed current limiting range, and when the working conditions are abnormal and the output is short-circuited, it can quickly switch to the short-circuit protection state to avoid chip burnout.

Description

Technical Field

[0001] The present application relates to the technical field of circuit protection, and particularly to a protection circuit for a linear regulator, a linear adjustment module, and a device. Background Art

[0002] In a linear regulator, output current limiting is an important protection function of the chip, which can prevent the chip from burning out due to exceeding the maximum heat dissipation capacity. In the traditional structure, a constant current limiting structure is mostly used to achieve output current limiting, that is, when the output current of the linear regulator exceeds the set current limiting value, the output current will no longer continue to increase, but remain relatively constant.

[0003] The constant current limiting structure can be implemented in various ways, and the circuit structure is relatively simple. However, in the implementation process, the inventor found that there are at least the following problems in the traditional technology: the output voltage in the current limiting state of the constant current limiting structure may be pulled to the ground potential, which is likely to burn out the chip in the case of output short circuit. Summary of the Invention

[0004] Based on this, in view of the problem that the traditional current limiting structure is likely to burn out the chip in the case of output short circuit, it is necessary to provide a protection circuit for a linear regulator, a linear adjustment module, and a device.

[0005] To achieve the above object, on the one hand, an embodiment of the present application provides a protection circuit for a linear regulator, including:

[0006] A current sampling module, configured to collect the output current of the power PMOS transistor of the linear regulator, and perform proportional scaling on the output current to obtain a sampled current; a first collection end of the current sampling module is used to connect to the gate of the power PMOS transistor, and a second collection end of the current sampling module is used to connect to the drain of the power PMOS transistor;

[0007] An output voltage detection module, configured to collect the output voltage of the linear regulator, and perform voltage comparison on the output voltage to obtain a reference current; a collection end of the output voltage detection module is used to connect to the output feedback end of the linear regulator;

[0008] A negative feedback control loop, configured to subtract the sampled current and the reference current, and perform amplification processing on the subtraction result to obtain a negative feedback current, and output the negative feedback current to the gate of the power PMOS transistor; an input end of the negative feedback control loop is respectively connected to an output end of the current sampling module and an output end of the output voltage detection module, and an output end of the negative feedback control loop is used to connect to the gate of the power PMOS transistor.

[0009] In one of the embodiments, the current sampling module includes:

[0010] The first PMOS transistor; the gate of the first PMOS transistor is connected to the first acquisition terminal of the current sampling module, and the source of the first PMOS transistor is used to connect to the voltage source;

[0011] The second PMOS transistor; the source of the second PMOS transistor is connected to the drain of the first PMOS transistor, and the drain of the second PMOS transistor is connected to the output terminal of the current sampling module;

[0012] The third PMOS transistor; the source of the third PMOS transistor is connected to the second acquisition terminal of the current sampling module, and the gate of the third PMOS transistor is connected to the gate of the second PMOS transistor;

[0013] The bias current source; the first end of the bias current source is respectively connected to the gate, the gate and the drain of the third PMOS transistor, and the second end of the bias current source is grounded.

[0014] In one embodiment, the multiple by which the current sampling module scales the output current is M;

[0015] The aspect ratio of the power PMOS transistor is M times that of the first PMOS transistor.

[0016] In one embodiment, the output voltage detection module includes:

[0017] The first NMOS transistor; the gate of the first NMOS transistor is used to connect to the bias voltage, and the source of the first NMOS transistor is grounded;

[0018] The second NMOS transistor; the drain of the second NMOS transistor is connected to the output terminal of the output voltage detection module, the gate of the second NMOS transistor is used to connect to the acquisition terminal of the output voltage detection module, and the source of the second NMOS transistor is connected to the drain of the first NMOS transistor.

[0019] In one embodiment, the negative feedback control loop includes:

[0020] The third NMOS transistor; the drain of the third NMOS transistor is connected to the input terminal of the negative feedback control loop, the gate of the third NMOS transistor is connected to the input terminal of the negative feedback control loop, and the source of the third NMOS transistor is grounded;

[0021] The fourth NMOS transistor; the gate of the fourth NMOS transistor is respectively connected to the input terminal of the negative feedback control loop and the gate of the third NMOS transistor, and the source of the fourth NMOS transistor is grounded;

[0022] The fourth PMOS transistor; the source of the fourth PMOS transistor is used to connect to the voltage source, and the gate and the drain of the fourth PMOS transistor are both connected to the drain of the fourth NMOS transistor;

[0023] The fifth PMOS transistor; the source of the fifth PMOS transistor is used to connect to a voltage source, the gate of the fifth PMOS transistor is respectively connected to the drain of the fourth NMOS transistor, the gate and the drain of the fourth PMOS transistor, and the drain of the fifth PMOS transistor is connected to the output end of the negative feedback control loop.

[0024] On the other hand, an embodiment of the present application also provides a linear adjustment module, including:

[0025] A linear regulator, including a power PMOS transistor and an output feedback terminal connected to the PMOS transistor;

[0026] The protection circuit as described above.

[0027] In one embodiment, the source of the power PMOS transistor is used to connect to a voltage source;

[0028] The linear regulator includes:

[0029] A feedback network; the input end of the feedback network is connected to the drain of the power PMOS transistor through the output feedback terminal, and the output end of the feedback network is connected to the gate of the power PMOS transistor.

[0030] In one embodiment, the feedback network includes:

[0031] An error amplifier; the non-inverting input terminal of the error amplifier is connected to the input end of the feedback network, the inverting input terminal of the error amplifier is used to connect to a reference power source, and the output end of the error amplifier is connected to the gate of the power PMOS transistor.

[0032] In one embodiment, the linear regulator further includes:

[0033] A first resistor; the first end of the first resistor is respectively connected to the drain of the power PMOS transistor and the second acquisition terminal of the current sampling module, and the second end of the first resistor is connected to the output feedback terminal;

[0034] A second resistor; the first end of the second resistor is respectively connected to the second end of the first resistor and the output feedback terminal, and the second end of the second resistor is grounded.

[0035] In one embodiment, a device is further provided, including the linear adjustment module as described above.

[0036] One of the above technical solutions has the following advantages and beneficial effects:

[0037] The protection circuit of the linear regulator includes a current sampling module, an output voltage detection module, and a negative feedback control loop; the first acquisition terminal of the current sampling module is used to connect to the gate of the power PMOS transistor, and the second acquisition terminal of the current sampling module is used to connect to the drain of the power PMOS transistor; the acquisition terminal of the output voltage detection module is used to connect to the output feedback terminal of the linear regulator; the input terminals of the negative feedback control loop are respectively connected to the output terminal of the current sampling module and the output terminal of the output voltage detection module, and the output terminal of the negative feedback control loop is used to connect to the gate of the power PMOS transistor. Based on the above structure, by collecting the changes in the output current and output voltage of the power PMOS transistor, the power PMOS transistor is controlled, and at the same time, the output current limiting function and the output short-circuit protection function are realized; based on this, the linear regulator can be protected to work normally within the allowable current limiting range, and when the working conditions are abnormal and the output is short-circuited, it can quickly switch to the short-circuit protection state to avoid chip burnout caused by instantaneous unexpected over-power operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other objects, features, and advantages of the present application will become clearer through more specific descriptions of the preferred embodiments of the present application shown in the drawings. The same reference numerals in all the drawings indicate the same parts, and the drawings are not deliberately drawn to scale in actual size, with the focus on showing the gist of the present application.

[0039] Figure 1 It is the first schematic structural diagram of the protection circuit in an embodiment;

[0040] Figure 2 It is the second schematic structural diagram of the protection circuit in an embodiment;

[0041] Figure 3 It is the third schematic structural diagram of the protection circuit in an embodiment;

[0042] Figure 4 It is the structural schematic diagram of the linear adjustment module in an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0044] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to another element and integrated with it, or there may be an intermediate element at the same time. The terms "output terminal", "input terminal", "acquisition terminal" and similar expressions used herein are only for the purpose of illustration.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0046] A linear regulator can adjust the current flowing through a load through a transistor, and the voltage obtained by the load is the output voltage of the regulator; the linear regulator can obtain the output voltage through the output feedback terminal, compare the output voltage with the reference voltage inside the regulator, and the generated differential signal is used to control the transistor to form a negative feedback loop. With appropriate compensation, the output voltage can be adjusted down to the target voltage, unaffected by input voltage or load changes, and remain reasonably stable.

[0047] In the output current limiting function of a linear regulator, the constant current limiting structure is prone to burning out the chip in the case of output short circuit, while the fold-back current limiting structure can, after the output current reaches the maximum current limiting value, internally adjust to make the current limiting value decrease as the output voltage decreases, limiting the power of the chip within a controllable range. However, the implementation method of the fold-back current limiting structure is relatively complex, increasing the circuit design difficulty, not conducive to implementation in low-power products, and consuming more static current, thus being limited in low-power applications. For this reason, the embodiments of this application provide a current limiting and short-circuit protection circuit applicable to a linear regulator, which simultaneously realizes the output current limiting function and the output short-circuit protection function by collecting the changes in the output current and output voltage.

[0048] In one embodiment, a protection circuit for a linear regulator is provided, as Figure 1 shown, including:

[0049] A current sampling module, configured to collect the output current of the power PMOS (positive channel MetalOxide Semiconductor) transistor of the linear regulator and perform amplification processing on the output current to obtain a sampled current; the first collection end of the current sampling module is used to connect to the gate of the power PMOS transistor, and the second collection end of the current sampling module is used to connect to the drain of the power PMOS transistor.

[0050] An output voltage detection module, configured to collect the output voltage of the linear regulator and perform voltage comparison on the output voltage to obtain a reference current; the collection end of the output voltage detection module is used to connect to the output feedback terminal of the linear regulator.

[0051] A negative feedback control loop is used to subtract the sampled current from the reference current and amplify the result of the subtraction to obtain a negative feedback current, and output the negative feedback current to the gate of the power PMOS transistor; the input terminals of the negative feedback control loop are respectively connected to the output terminal of the current sampling module and the output terminal of the output voltage detection module, and the output terminal of the negative feedback control loop is used to connect to the gate of the power PMOS transistor.

[0052] Specifically, the linear regulator includes a power PMOS transistor and an output feedback terminal; specifically, the power PMOS transistor serves as a driving device, and the output signal of the power PMOS transistor can be fed back to the feedback network of the linear regulator through the output feedback terminal. At the same time, there is a constant maximum current in the power PMOS transistor. The protection circuit includes at least three parts: a current sampling module, an output voltage detection module, and a negative feedback control loop. The first acquisition terminal of the current sampling module is used to connect to the gate of the power PMOS transistor, and the second acquisition terminal of the current sampling module is used to connect to the drain of the power PMOS transistor; the acquisition terminal of the output voltage detection module is used to connect to the output feedback terminal of the linear regulator; the input terminals of the negative feedback control loop are respectively connected to the output terminal of the current sampling module and the output terminal of the output voltage detection module, and the output terminal of the negative feedback control loop is used to connect to the gate of the power PMOS transistor.

[0053] Among them, based on the above structure, the current sampling module can be used to collect the output current of the power PMOS transistor, that is, to collect the output current of the linear regulator in an accurate manner; at the same time, the current sampling module also scales the output current by a certain ratio to obtain and output a sampled current. Optionally, the current sampling module may mainly be composed of an arithmetic circuit, a transistor, etc., which is not specifically limited here; exemplarily, the current sampling module can reduce the output current by 1000 times based on an arithmetic circuit or a transistor circuit to obtain a sampled current. It should be noted that the scaling ratio of the current sampling module can be adjusted according to actual requirements for the current structure or device parameters, which can meet the requirements of different linear regulators and improve the applicability of the embodiments of the present application.

[0054] The output voltage detection module is used to detect the output voltage of the linear regulator, and take the output voltage as an input signal for voltage comparison, generate and output a reference current. That is, the output voltage can control the change of the reference current. Optionally, the output voltage detection module may mainly be composed of a comparison circuit or transistors, etc., and no specific limitation is made here. It should be noted that the voltage threshold in the voltage comparison process can be adjusted according to actual needs by adjusting the circuit structure or device parameters, which can meet the requirements of different linear regulators and improve the applicability of the embodiments of the present application. Exemplarily, when the output voltage is greater than a preset voltage threshold, a reference current greater than 0 and stable is output, and the specific magnitude of the reference current can be set according to actual needs; when the output voltage is less than the preset voltage threshold, the output reference current is 0; for example, when the linear regulator output is abnormal and enters a short-circuit state, the reference current output by the output voltage detection module can be 0.

[0055] The negative feedback control loop is used to subtract the sampled current signal output by the current sampling module from the reference current output by the output voltage detection module, amplify the subtracted current to obtain a negative feedback current, and transmit it to the gate of the power PMOS transistor. Based on this, the output end of the negative feedback control loop can generate a positive-correlation pull-up effect on the power PMOS gate drive, thereby limiting the power PMOS current and achieving the control effect of negative feedback. Optionally, the negative feedback control loop may mainly be composed of a subtraction current, an amplification circuit or a transistor circuit, and no specific limitation is made here. Exemplarily, when the negative feedback current transmitted by the output end of the negative feedback control loop is greater than or equal to the maximum drive current of the power PMOS transistor, the drive ability of the power PMOS is controlled by the protection circuit. In one example, when the output current of the power PMOS transistor is greater than a preset current limit value (i.e., the maximum output current), the negative feedback current transmitted by the output end of the negative feedback control loop is greater than the maximum drive current of the power PMOS transistor. At this time, the protection circuit and the power PMOS transistor form a complete negative feedback loop, and the output end of the negative feedback control loop generates a pull-up on the gate drive of the power PMOS transistor to limit the current of the power PMOS transistor. In another example, when the output current of the power PMOS transistor is less than the preset current limit value, the negative feedback current transmitted by the output end of the negative feedback control loop is less than the maximum drive current of the power PMOS transistor. At this time, the gate drive ability of the power PMOS transistor is determined by the inside of the linear regulator, and the linear regulator outputs the normal voltage.

[0056] It should be noted that the input end of the negative feedback control loop can be a single port, which is respectively connected to the output end of the current sampling module and the output end of the output voltage detection module; in addition, the input end of the negative feedback control loop can also include at least two ports, one of which is used to connect the output end of the current sampling module, and the other is used to connect the output end of the output voltage detection module.

[0057] It should be noted that in the embodiments of the present application, the input end, output end, and acquisition end mentioned may be fixed interfaces of the module, or may be ports or electrodes of the devices in the module; different devices can be electrically connected by connecting to the same end.

[0058] Based on the above structure, the output current of the power PMOS transistor is reduced by M times to obtain the sampling current, and the negative feedback current is N times the difference between the sampling current and the reference current. Then the maximum output current can be set by M, N, and the reference current, that is, the magnitude of the current limiting and short-circuit current protection of the linear regulator can be set based on the embodiments of the present application. The embodiments of the present application can collect the changes in the output current and output voltage of the power PMOS transistor, and then control the power PMOS transistor, simultaneously realizing the output current limiting function and the output short-circuit protection function; based on this, the linear regulator can be protected to operate normally within the allowed current limiting range, and when the working conditions are abnormal and the output is short-circuited, it can quickly switch to the short-circuit protection state to avoid chip burnout caused by instantaneously unpredictable over-power operation.

[0059] In one embodiment, the first acquisition end of the current sampling module is used to connect to the gate of the power PMOS transistor.

[0060] Specifically, the first acquisition end of the current sampling module is also connected to the gate of the power PMOS transistor, and it can confirm whether the protection circuit is started based on the drive signal of the power PMOS transistor.

[0061] In one embodiment, as Figure 2 shown, the current sampling module includes:

[0062] The first PMOS transistor P1; the gate of the first PMOS transistor P1 is connected to the first acquisition end of the current sampling module, and the source of the first PMOS transistor P1 is used to connect to the voltage source VDD;

[0063] The second PMOS transistor P2; the source of the second PMOS transistor P2 is connected to the drain of the first PMOS transistor P1, and the drain of the second PMOS transistor P2 is connected to the output end of the current sampling module;

[0064] The third PMOS transistor P3; the source of the third PMOS transistor P3 is connected to the second acquisition end of the current sampling module, and the gate of the third PMOS transistor P3 is connected to the gate of the second PMOS transistor P2;

[0065] The bias current source IB; the first end of the bias current source IB is respectively connected to the gate, drain, and gate of the second PMOS transistor P2 and the third PMOS transistor P3, and the second end of the bias current source IB is grounded.

[0066] Specifically, the current sampling module at least includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a bias current source IB. Among them, the gate of the first PMOS transistor P1 is connected to the gate of the power PMOS transistor through the first acquisition terminal of the current sampling module. The source of the first PMOS transistor P1 is connected to the voltage source VDD, and the drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2. The gate of the second PMOS transistor P2 is connected to the gate of the third PMOS transistor P3, and the drain of the second PMOS transistor P2 is connected to the input terminal of the negative feedback control loop through the output terminal of the current sampling module. The source of the third PMOS transistor P3 is connected to the drain of the power PMOS transistor P0 through the second acquisition terminal of the current sampling module. The drain of the third PMOS transistor P3 is connected to the gate of the third PMOS transistor P3 and the first terminal of the bias current source IB; the other end of the bias current source IB is grounded. Based on the above circuit structure, the drain of the second PMOS transistor P2 can also be regarded as the output terminal of the current sampling module.

[0067] It should be noted that in the current sampling module, the first PMOS transistor P1 can be used to determine the scaling factor; the functions of the second PMOS transistor P2 and the third PMOS transistor P3 are to ensure that the drain voltage of the first PMOS transistor P1 is close to the drain voltage V OUT of the power PMOS transistor P0, reduce the current distortion of the first PMOS transistor P1 caused by the substrate bias effect, and further improve the sampling accuracy of the embodiments of the present application. It should be noted that the structure of the current sampling module provided by the embodiments of the present application is simple and the cost is low; on this basis, the performance of the current sampling module can be further improved by adding devices or changing the device type, etc., which will not be listed one by one here.

[0068] In one embodiment, the scaling factor of the output current by the current sampling module is M;

[0069] The aspect ratio of the width to length of the power PMOS transistor is M times that of the first PMOS transistor.

[0070] Specifically, the scaling ratio can be set by setting the aspect ratios of the first PMOS transistor and the power PMOS transistor. The aspect ratio of the width to length of the power PMOS transistor is M times that of the first PMOS transistor. The first PMOS transistor with the corresponding aspect ratio can also be selected based on the scaling ratio and the aspect ratio of the power PMOS transistor. Among them, the aspect ratio mentioned in the embodiments of the present application is the ratio of the width to the length of the conductive channel of the MOS transistor.

[0071] In one embodiment, as Figure 2 shown, the output voltage detection module includes:

[0072] A first NMOS transistor N1; the gate of the first NMOS transistor N1 is used to connect to the bias voltage, and the source of the first NMOS transistor N1 is grounded;

[0073] The second NMOS transistor N2; the drain of the second NMOS transistor N2 is connected to the output terminal of the output voltage detection module, the gate of the second NMOS transistor N2 is used to connect to the acquisition terminal of the output voltage detection module, and the source of the second NMOS transistor N2 is connected to the drain of the first NMOS transistor N1.

[0074] Specifically, the output voltage detection module includes at least the first NMOS transistor N1 and the second NMOS transistor N2. Among them, the gate of the first NMOS transistor N1 is connected to the bias voltage V B , the source of the first NMOS transistor N1 is grounded, and the drain of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2. The gate of the second NMOS transistor N2 obtains the output voltage V FB of the linear regulator through the acquisition terminal of the output voltage detection module, and the drain of the second NMOS transistor N2 is connected to the input terminal of the negative feedback control loop through the output terminal of the output voltage detection module. Based on the above circuit structure, the gate of the second NMOS transistor N2 can be regarded as the acquisition terminal of the output voltage detection module; the drain of the second NMOS transistor N2 can be regarded as the output terminal of the output voltage detection module. That is, in one example, the drain of the second NMOS transistor N2 is electrically connected to the drain of the second PMOS transistor P2.

[0075] It should be noted that the output voltage detection module can control the magnitude of the output reference current I FB according to the voltage signal V REF obtained from the output feedback terminal of the linear regulator (i.e., the output voltage). Exemplarily, when V FB is greater than the threshold voltage of the second NMOS transistor N2, the first NMOS transistor N1 operating in the saturation region generates a stable reference current I B through an external current bias and the voltage signal V REF0 , that is, the reference current output by this module is I REF0 ; when V FB is significantly less than the threshold voltage of the second NMOS transistor N2, the second NMOS transistor N2 is turned off, and the reference current I REF output by this module is zero. Based on this, the embodiment of the present application can quickly obtain the output voltage through the transistor circuit, determine whether the linear regulator is in a short-circuit state, and reduce the complexity and cost of the protection circuit. It should be noted that the structure of the output voltage detection module provided by the embodiment of the present application is simple and the cost is low; on this basis, the performance of the output voltage detection module can be further improved by adding devices or changing the device type, etc., which will not be listed one by one here.

[0076] In one embodiment, as Figure 2 shown, the negative feedback control loop includes:

[0077] The third NMOS transistor N3; the drain of the third NMOS transistor N3 is connected to the input end of the negative feedback control loop, the gate of the third NMOS transistor N3 is connected to the input end of the negative feedback control loop, and the source of the third NMOS transistor N3 is grounded;

[0078] The fourth NMOS transistor N4; the gate of the fourth NMOS transistor N4 is respectively connected to the input end of the negative feedback control loop and the gate of the third NMOS transistor N3, and the source of the fourth NMOS transistor N4 is grounded;

[0079] The fourth PMOS transistor P4; the source of the fourth PMOS transistor P4 is used to connect to the voltage source VDD, and the gate and drain of the fourth PMOS transistor P4 are both connected to the drain of the fourth NMOS transistor N4;

[0080] The fifth PMOS transistor P5; the source of the fifth PMOS transistor P5 is used to connect to the voltage source VDD, the gate of the fifth PMOS transistor P5 is respectively connected to the drain of the fourth NMOS transistor N4, the gate and drain of the fourth PMOS transistor P4, and the drain of the fifth PMOS transistor P5 is connected to the output end of the negative feedback control loop.

[0081] Specifically, the negative feedback control loop at least includes the third NMOS transistor N3, the fourth NMOS transistor N4, the fourth PMOS transistor P4, and the fifth PMOS transistor P5. Among them, the gate of the third NMOS transistor N3 is connected to the drain of the third NMOS transistor N3, the drain of the third NMOS transistor N3 is connected to the input end of the negative feedback control loop, and the source of the third NMOS transistor N3 is grounded. The gate of the fourth NMOS transistor N4 is connected to the gate of the third NMOS transistor N3, the drain of the fourth NMOS transistor N4 is connected to the drain of the fourth PMOS transistor P4, and the source of the third NMOS transistor N3 is grounded. The gate of the fourth PMOS transistor P4 is connected to the drain of the fourth PMOS transistor P4, and the source of the fourth PMOS transistor P4 is connected to the power supply. The gate of the fifth PMOS transistor P5 is connected to the gate of the fourth PMOS transistor P4, the drain of the fifth PMOS transistor P5 is connected to the gate of the power PMOS transistor P0, and the source of the fifth PMOS transistor P5 is connected to the power supply. Based on the above circuit structure, the drain of the third NMOS transistor N3 can be regarded as the input end of the negative feedback control loop; the drain of the fifth PMOS transistor P5 can be regarded as the output end of the negative feedback control loop. In one example, the drain of the third NMOS transistor N3 is electrically connected to the drain of the second PMOS transistor P2 and the drain of the second NMOS transistor N2 respectively.

[0082] It should be noted that the negative feedback control loop can be used to comprehensively judge the sampling current I S and the reference current I REFIn this case, it further determines the driving of the power PMOS transistor P0. Among them, the lengths L of the third NMOS transistor N3 and the fourth NMOS transistor N4 are much larger than the minimum process dimension to reduce the channel length modulation effect and improve the current mirror accuracy. Here, the length L is the length of the conductive channel. It should be noted that the structure of the negative feedback control loop provided by the embodiments of the present application is simple and has low cost; on this basis, the performance of the negative feedback control loop can be further improved by adding devices or changing the device type, etc., which will not be listed one by one here.

[0083] The embodiments of the present application can be implemented based on transistors, with a simple circuit structure, which is easy to be superimposed and implemented on the basis of a conventional current limiting circuit. It can perform current limiting and short circuit protection for a linear regulator and requires extremely low additional static current, and is suitable for low-power application scenarios; in addition, it is also compatible with the CMOS (Complementary Metal Oxide Semiconductor) process.

[0084] In one embodiment, as Figure 3 shown, according to the characteristics of MOS transistors, the output current I OUT of the linear regulator and the sampling current I S output by the current sampling module are related as follows:

[0085] I OUT = M × I S

[0086] In the negative feedback control loop, the input current I FIN and the sampling current I S , reference current I REF are related as follows:

[0087] I FIN = I S - I REF

[0088] The gain from the input current I FIN to the negative feedback current I FOUT of the negative feedback control loop is N, that is:

[0089] I FOUT = N × (I S - I REF )

[0090] The maximum drive current output of the error amplifier EA is I DRV , and the critical condition for judging the effectiveness of the protection circuit is that I FOUT is equal to I DRV . At this time, the driving ability of the power PMOS transistor is controlled by the protection circuit.

[0091] When the linear regulator is in the working state, considering the relationship of the above-mentioned modules, the maximum output current, that is, the current limit, is:

[0092]

[0093] When the output of the linear regulator is abnormal and enters the short-circuit state, the output of the output voltage detection module is zero. At this time, the short-circuit current of the linear regulator is:

[0094]

[0095] It can be seen from the above formula that by adjusting the proportionality coefficients M, N, and the reference current I REF0 the magnitudes of the current limit and short-circuit current protection can be freely set.

[0096] In one embodiment, a linear adjustment module is provided, as Figure 4 shown, including:

[0097] A linear regulator, including a power PMOS transistor and an output feedback terminal connected to the PMOS transistor;

[0098] The protection circuit as described above.

[0099] Specifically, the linear adjustment module includes a linear regulator and a protection circuit connected to the linear regulator. Among them, the specific definition of the protection circuit can refer to the previous discussion and will not be repeated here. The linear regulator may include a PMOS transistor as a driving device and an output feedback terminal for obtaining the output feedback signal of the linear regulator. The linear adjustment module can be used to connect to a chip or be provided on a chip; based on the protection circuit, the linear regulator in the linear adjustment module can work normally within the allowed current limit range, and when the working conditions are abnormal and the output is short-circuited, it can quickly switch to the short-circuit protection state to avoid chip burnout caused by instantaneously unpredictable over-power operation.

[0100] In one embodiment, the source of the power PMOS transistor is used to connect to a voltage source;

[0101] The linear regulator includes:

[0102] A feedback network; the input end of the feedback network is connected to the drain of the power PMOS transistor through the output feedback terminal, and the output end of the feedback network is connected to the gate of the power PMOS transistor.

[0103] Specifically, the linear regulator may further include a feedback network, which may mainly be composed of an operational amplifier and other devices. Multiple feedback circuits can be used to implement this in the embodiments of the present application, and no specific limitation is made here; that is, the embodiments of the present application can be flexibly configured and have strong applicability.

[0104] In one embodiment, the feedback network includes:

[0105] Error amplifier; the non-inverting input terminal of the error amplifier is connected to the input terminal of the feedback network, the inverting input terminal of the error amplifier is used to connect to the reference power supply, and the output terminal of the error amplifier is connected to the gate of the power PMOS transistor.

[0106] Specifically, the feedback network may mainly consist of an error amplifier. By using a simple error amplifier to achieve the output feedback of the linear regulator, the cost and complexity of the embodiments of the present application are reduced.

[0107] In one embodiment, the linear regulator further includes:

[0108] A first resistor; the first end of the first resistor is respectively connected to the drain of the power PMOS transistor and the second acquisition terminal of the current sampling module, and the second end of the first resistor is connected to the output feedback terminal;

[0109] A second resistor; the first end of the second resistor is respectively connected to the second end of the first resistor and the output feedback terminal, and the second end of the second resistor is grounded.

[0110] Specifically, the linear regulator may further include a first resistor for voltage division and a second resistor for grounding.

[0111] In one embodiment, a device is provided, including the linear adjustment module as described above.

[0112] Specifically, the linear adjustment module may be provided in the device chip or on the device substrate.

[0113] The device adopts the above linear adjustment module, which can not only achieve current limiting but also short-circuit protection, improving the safety of the device.

[0114] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0115] The above-described embodiments only represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A protection circuit for a linear regulator, characterized in that Comprising: A current sampling module, configured to collect the output current of the power PMOS transistor of the linear regulator, and perform proportional scaling on the output current to obtain a sampled current; The first collection end of the current sampling module is used to connect to the gate of the power PMOS transistor, and the second collection end of the current sampling module is used to connect to the drain of the power PMOS transistor; An output voltage detection module, configured to collect the output voltage of the linear regulator, and perform voltage comparison on the output voltage to obtain a reference current; When the output voltage is greater than a preset voltage threshold, the reference current is greater than 0 and stable, and when the output voltage is less than the preset voltage threshold, the reference current is 0; the collection end of the output voltage detection module is used to connect to the output feedback end of the linear regulator; A negative feedback control loop, configured to subtract the sampled current and the reference current, and perform amplification processing on the subtraction result to obtain a negative feedback current, and output the negative feedback current to the gate of the power PMOS transistor; the input ends of the negative feedback control loop are respectively connected to the output end of the current sampling module and the output end of the output voltage detection module, and the output end of the negative feedback control loop is used to connect to the gate of the power PMOS transistor.

2. The protection circuit of the linear regulator according to claim 1, wherein The current sampling module includes: A first PMOS transistor; the gate of the first PMOS transistor is connected to the first collection end of the current sampling module, and the source of the first PMOS transistor is used to connect to a voltage source; A second PMOS transistor; the source of the second PMOS transistor is connected to the drain of the first PMOS transistor, and the drain of the second PMOS transistor is connected to the output end of the current sampling module; A third PMOS transistor; the source of the third PMOS transistor is connected to the second collection end of the current sampling module, and the gate of the third PMOS transistor is connected to the gate of the second PMOS transistor; A bias current source; the first end of the bias current source is respectively connected to the gate, the drain of the third PMOS transistor, and the second end of the bias current source is grounded.

3. The protection circuit of the linear regulator according to claim 2, characterized in that, The multiple by which the current sampling module performs proportional scaling on the output current is M; The width-to-length ratio of the power PMOS transistor is M times the width-to-length ratio of the first PMOS transistor.

4. The protection circuit of the linear regulator according to any one of claims 1 to 3, characterized in that The output voltage detection module includes: A first NMOS transistor; the gate of the first NMOS transistor is used to connect to a bias voltage, and the source of the first NMOS transistor is grounded; A second NMOS transistor; the drain of the second NMOS transistor is connected to the output end of the output voltage detection module, the gate of the second NMOS transistor is used to connect to the collection end of the output voltage detection module, and the source of the second NMOS transistor is connected to the drain of the first NMOS transistor.

5. The protection circuit of the linear regulator according to any one of claims 1 to 3, characterized in that, The negative feedback control loop includes: A third NMOS transistor; the drain of the third NMOS transistor is connected to the input end of the negative feedback control loop, the gate of the third NMOS transistor is connected to the input end of the negative feedback control loop, and the source of the third NMOS transistor is grounded; The fourth NMOS transistor; the gate of the fourth NMOS transistor is respectively connected to the input end of the negative feedback control loop and the gate of the third NMOS transistor, and the source of the fourth NMOS transistor is grounded; The fourth PMOS transistor; the source of the fourth PMOS transistor is used to connect to a voltage source, and the gate and drain of the fourth PMOS transistor are both connected to the drain of the fourth NMOS transistor; The fifth PMOS transistor; the source of the fifth PMOS transistor is used to connect to a voltage source, the gate of the fifth PMOS transistor is respectively connected to the drain of the fourth NMOS transistor, the gate and drain of the fourth PMOS transistor, and the drain of the fifth PMOS transistor is connected to the output end of the negative feedback control loop.

6. A linear adjustment module, characterized in that Comprising: A linear regulator, comprising a power PMOS transistor and an output feedback terminal connected to the PMOS transistor; The protection circuit according to any one of claims 1 to 5.

7. The linear adjustment module according to claim 6, wherein The source of the power PMOS transistor is used to connect to a voltage source; The linear regulator comprises: A feedback network; the input end of the feedback network is connected to the drain of the power PMOS transistor through the output feedback terminal, and the output end of the feedback network is connected to the gate of the power PMOS transistor.

8. The linear adjustment module according to claim 7, wherein The feedback network comprises: An error amplifier; the positive input terminal of the error amplifier is connected to the input end of the feedback network, the negative input terminal of the error amplifier is used to connect to a reference power source, and the output end of the error amplifier is connected to the gate of the power PMOS transistor.

9. The linear adjustment module according to any one of claims 6 to 8, characterized in that The linear regulator further comprises: A first resistor; the first end of the first resistor is respectively connected to the drain of the power PMOS transistor, the second acquisition terminal of the current sampling module, and the second end of the first resistor is connected to the output feedback terminal; A second resistor; the first end of the second resistor is respectively connected to the second end of the first resistor and the output feedback terminal, and the second end of the second resistor is grounded.

10. A device, characterized in that, Comprising the linear adjustment module according to any one of claims 6 to 9 provided in the device chip or on the device substrate; the device can achieve current limiting and short-circuit protection by using the linear adjustment module.

Images