Hardware Cache Management Unit (BMU) with keywords

Abstract

A hardware cache management unit (BMU) with keywords is provided. The provided hardware cache management unit includes an allocation-lock unit, a hit-lock unit, a release-unlock unit, a keyword submission unit, and a keyword table; the keyword table includes multiple entries, each entry representing one of the cache units; the allocation-lock unit searches the keyword table for an entry representing an available cache unit and outputs a cache unit index representing the available cache unit; the hit-lock unit outputs the cache unit index corresponding to the entry storing the provided keyword in response to a provided keyword; the unlock-release unit decrements the allocation count field of the entry corresponding to the provided cache unit index in the keyword table in response to the provided cache unit index; and the keyword submission unit records the provided keyword in the entry corresponding to the provided cache unit index in the keyword table in response to the provided keyword and the cache unit index.

Description

Technical Field

[0001] The present application relates to cache management, and in particular, to a hardware cache management unit (BMU) with a keyword. Background Art

[0002] Figure 1 A block diagram of a storage device is shown. Storage device 102 is coupled to a host to provide storage capabilities for the host. The host and solid-state storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and storage device 102 via, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), UFS (Universal Flash Storage), eMMC (embedded MMC (MultiMediaCard)), Ethernet, Fibre Channel, wireless communication networks, and the like. The host can be an information processing device capable of communicating with the storage device in the above manner, such as a personal computer, tablet computer, server, portable computer, network switch, router, cellular phone, personal digital assistant, and the like. The storage device 102 includes an interface 103 , a control unit 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, or the like.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways such as software, hardware, firmware or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit) or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access data in the DRAM 110. The FTL table and / or cached IO command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash memory interface controller (also known as a media interface controller or a flash memory lane controller). The flash memory interface controller is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle" and "ONFI".

[0007] Figure 2 A block diagram showing the control components of a storage device.

[0008] The control component 104 includes a host interface 103 , a front-end processing unit 210 , a processor 240 , a buffer management unit (BMU) 270 , and a media interface controller 106 .

[0009] The control unit 104 is also coupled to a plurality of cache units and an NVM chip. The plurality of cache units are provided by, for example, DRAM. Optionally, the plurality of cache units are implemented within the control unit 104 and are part of the same chip as the control unit 104.

[0010] The front-end processing unit 210 obtains commands (eg, IO commands) provided by the host from the host interface 103 and provides the commands to the processor 240. The processor 240 recognizes the meaning of the commands, processes them accordingly, and operates the media interface controller 106 to access the NVM chip.

[0011] The cache management unit 270 manages the allocation and release of cache units. The cache unit is used to temporarily store data accessed by IO commands, for example, data to be written to the NVM chip by a write command provided by the cache host, and / or cache data read from the NVM chip. The cache management unit of the prior art responds to cache unit allocation requests from the processor 240 or other components (for example, the front-end processing unit 210, the media interface controller 106) at the cache unit granularity, and provides an index of an available cache unit, and responds to a cache unit release request to mark the corresponding cache unit as available. The processor 240 or other components access data using the corresponding cache unit based on the cache unit index obtained from the cache management unit. The cache management unit 270 of the prior art does not care about the content of the data stored in the cache unit, that is, the cache management unit is completely isolated from the content of the cache unit.

[0012] In early chip designs, software implemented the cache management unit (CMU), providing cache management interfaces such as malloc() and free(). However, as chip designs grew in size, more and more cache units were needed, and so too did the number of circuit units that needed to utilize them. If the CMU remained managed by software, the response would be slow. To improve cache efficiency, mainstream chips now implement the CMU entirely through hardware logic circuits. When software needs a cache unit, it requests it from the CMU.

[0013] The cache management unit is implemented in hardware, typically using a FIFO (First In First Out) queue, a BITMAP, or a hybrid of the two. The cache management unit does not require active operation, but instead provides an interface for allocating and releasing cache units, passively responding to allocation and release operations. Summary of the Invention

[0014] Storage devices use cache memory when processing I / O commands. For example, a read command involves reading data from the NVM chip based on the address accessed by the read command, moving it into the cache, and then transferring the cache data to the host. If the host issues multiple read commands accessing the same address, some of the data to be read may already be in the cache. The processor then needs to determine whether the data to be read is in the cache (this is called a cache hit).

[0015] There are two situations for identifying cache unit hits: (1) For a cache unit that has been allocated and not yet released, the processor identifies whether the data associated with the address is in the cache unit by recording the address of the data stored in the cache unit; (2) For a cache unit that has been released, the data therein may or may not be overwritten. If the data is not overwritten, it can still be used to respond to subsequent read commands.

[0016] For the above situation (2), whether the data in the released cache unit has been overwritten can be determined by identifying whether it has been reallocated. When the processor manages the allocation and release of cache units, it can know whether the cache unit has been reallocated. However, when the allocation and release of cache units is managed by the hardware cache management unit (BMU), the cache management unit (BMU) does not tell whether a cache unit has been allocated. At this time, the processor can still access each storage unit and query whether there is hit data from the storage unit. However, even if the processor finds the hit cache unit, during the use of the hit cache unit, the cache management unit (BMU) may still allocate the cache unit to other circuit units, causing the data in the hit cache unit to be overwritten.

[0017] According to the embodiments of the present application, the cache management unit (BMU) is improved. The BMU not only provides cache unit allocation and release, but also provides search for hit cache units. After a cache unit is released, it can be reallocated or used as a hit cache unit before reallocation. This solves the problem that when the processor and other circuit units use the hardware cache management unit (BMU), the released cache unit cannot be used to process cache unit hits, increases the probability of cache unit hits, and thus improves the performance of the storage device.

[0018] According to the first aspect of the present application, a first hardware cache management unit according to the first aspect of the present application is provided, including an allocation-lock unit, a hit-lock unit, a release-unlock unit, a keyword submission unit and a keyword table; the keyword table includes multiple entries, each entry represents one of the cache units; the allocation-lock unit searches for an entry representing an available cache unit from the keyword table and outputs a cache unit index representing the available cache unit; the hit-lock unit outputs the cache unit index corresponding to the entry storing the provided keyword in response to the provided keyword; the unlock-release unit decrements the allocation count field of the entry corresponding to the provided cache unit index in the keyword table in response to the provided cache unit index; the keyword submission unit records the provided keyword in the entry corresponding to the provided cache unit index in the keyword table in response to the provided keyword and cache unit index.

[0019] According to the first hardware cache management unit of the first aspect of the present application, a second hardware cache management unit according to the first aspect of the present application is provided, wherein each entry of the keyword table includes a keyword field, an allocation count field and a dirty flag.

[0020] According to the first or second hardware cache management unit of the first aspect of the present application, a third hardware cache management unit according to the first aspect of the present application is provided, wherein the allocation-locking unit searches for an entry with an allocation count field of 0 from the keyword table, and uses the found entry as an entry representing an available cache unit.

[0021] According to the third hardware cache management unit of the first aspect of the present application, a fourth hardware cache management unit according to the first aspect of the present application is provided, wherein if the allocation-locking unit finds multiple entries with allocation count fields of 0 from the keyword table, one of the found entries is selected as the entry representing the available cache unit.

[0022] According to the third or fourth hardware cache management unit of the first aspect of the present application, a fifth hardware cache management unit according to the first aspect of the present application is provided, wherein the allocation-locking unit increments the reference count field of the entry representing the available cache unit and sets its dirty flag to true.

[0023] According to one of the first to fifth hardware cache management units of the first aspect of the present application, a sixth hardware cache management unit according to the first aspect of the present application is provided, wherein the hit-lock unit outputs a dirty mark as no in response to the provided keyword and stores the cache unit index corresponding to the entry of the provided keyword.

[0024] According to the sixth hardware cache management unit of the first aspect of the present application, a seventh hardware cache management unit according to the first aspect of the present application is provided, wherein the hit-lock unit also marks the dirty entry as no and increments the reference count field of the entry storing the provided keyword.

[0025] According to the sixth or seventh hardware cache management unit of the first aspect of the present application, an eighth hardware cache management unit according to the first aspect of the present application is provided, wherein the hit-lock unit outputs a dirty mark as no in response to the provided keyword and stores the cache unit index corresponding to the entry of the provided keyword, regardless of the value of the reference count field of the entry.

[0026] According to the first to eighth hardware cache management units of the first aspect of the present application, a ninth hardware cache management unit according to the first aspect of the present application is provided, wherein the unlock-release unit decrements the allocation count field of the entry corresponding to the provided cache unit index in the keyword table in response to the provided cache unit index, and ensures that the value of the allocation count field is not less than 0 after decrement.

[0027] According to the ninth hardware cache management unit of the first aspect of the present application, there is provided a tenth hardware cache management unit according to the first aspect of the present application, wherein the unlock-release unit does not update the key field of the entry.

[0028] According to the first to tenth hardware cache management units of the first aspect of the present application, an eleventh hardware cache management unit according to the first aspect of the present application is provided, wherein the keyword submission unit responds to the provided keyword and cache unit index, and also sets the dirty flag of the entry corresponding to the provided cache unit index to no.

[0029] According to the eleventh hardware cache management unit of the first aspect of the present application, a twelfth hardware cache management unit according to the first aspect of the present application is provided, wherein the keyword submission unit, in response to the provided keyword and cache unit index, also sets the dirty flag of one or more entries in the keyword table other than the entry corresponding to the provided cache unit index, which have the same keyword as the provided keyword and have a dirty flag of no to true.

[0030] According to the second aspect of the present application, a first chip according to the second aspect of the present application is provided, comprising a processor and a hardware cache management unit, wherein the hardware cache management unit is one of the first to twelfth hardware cache management units according to the first aspect of the present application.

[0031] According to the first chip of the second aspect of the present application, a second chip according to the second aspect of the present application is provided, wherein the processor executes a program to use the allocation-lock unit, the hit-lock unit, the release-unlock unit and / or the keyword submission unit.

[0032] According to the second chip of the second aspect of the present application, a third chip according to the second aspect of the present application is provided, wherein after the processor executes the program to write data to the cache unit allocated by the allocation-locking unit, it also immediately provides the index of the cache unit and the keyword associated with the written data to the keyword submission unit.

[0033] According to the second or third chip of the second aspect of the present application, a fourth chip according to the second aspect of the present application is provided, wherein the processor, in response to receiving a write command, uses the allocation-locking unit to obtain the index of the available first cache unit, moves the data to be written by the write command to the first cache unit, provides the index of the first cache unit and the address accessed by the write command as a keyword to the keyword submission unit, and also provides the index of the first cache unit to the release-unlocking unit.

[0034] According to the second to fourth chips of the second aspect of the present application, a fifth chip according to the second aspect of the present application is provided, wherein the processor, in response to receiving a read command, provides the address accessed by the read command as a keyword to the hit-lock unit, in response to the hit-lock unit indicating a hit, obtains the index of the second cache unit provided by the hit-lock unit, moves data from the second cache unit to the host in response to the read command, and also provides the index of the second cache unit to the release-unlock unit.

[0035] According to the fourth chip of the second aspect of the present application, a sixth chip according to the second aspect of the present application is provided, wherein in response to the hit-lock unit indicating a miss, the allocation-lock unit is used to obtain the index of the available third cache unit, the data to be read by the read command is moved to the third cache unit, the index of the third cache unit and the address accessed by the read command as the keyword are provided to the keyword submission unit, and the index of the third cache unit is also provided to the release-unlock unit.

[0036] According to the third aspect of the present application, a method for processing IO commands using a first hardware cache management unit according to the third aspect of the present application is provided, wherein the hardware cache management unit is one of the first to twelfth hardware cache management units according to the first aspect of the present application, and the method includes: in response to receiving a write command, using the allocation-locking unit to obtain the index of the available first cache unit, moving the data to be written by the write command to the first cache unit, providing the index of the first cache unit and the address accessed by the write command as a keyword to the keyword submission unit, and also providing the index of the first cache unit to the release-unlocking unit.

[0037] According to the first method of processing IO commands using a hardware cache management unit according to the third aspect of the present application, a second method of processing IO commands using a hardware cache management unit according to the third aspect of the present application is provided, which also includes: in response to receiving a read command, providing the address accessed by the read command as a keyword to the hit-lock unit, in response to the hit-lock unit indicating a hit, obtaining the index of the second cache unit provided by the hit-lock unit, moving data from the second cache unit to the host to respond to the read command, and also providing the index of the second cache unit to the release-unlock unit.

[0038] According to the second method of processing IO commands using a hardware cache management unit according to the third aspect of the present application, a third method of processing IO commands using a hardware cache management unit according to the third aspect of the present application is provided, which also includes: in response to the hit-lock unit indicating a miss, using the allocate-lock unit to obtain the index of the available third cache unit, moving the data to be read by the read command to the third cache unit, providing the index of the third cache unit and the address accessed by the read command as a keyword to the keyword submission unit, and providing the index of the third cache unit to the release-unlock unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0040] Figure 1 is a block diagram of a storage device in the prior art;

[0041] Figure 2 A block diagram showing the control components of a storage device;

[0042] Figure 3A A block diagram of a control component of a storage device according to an embodiment of the present application is shown;

[0043] Figure 3B A block diagram of a cache management unit according to an embodiment of the present application is shown;

[0044] Figure 4 A schematic diagram showing the collaborative operation of a processor and a cache management unit according to an embodiment of the present application; and

[0045] Figures 5A-5C A flowchart of processing IO commands according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0046] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0047] Figure 3A A block diagram of a control component of a storage device according to an embodiment of the present application is shown.

[0048] The control unit 104 includes a host interface 103, a front-end processing unit 310, a processor 340, a buffer management unit (BMU) 370, and a media interface controller 106. Figure 2 3 also includes a key table 375. The cache management unit 370 manages the allocation, deallocation, hit checking, and key updating of cache units.

[0049] Figure 3B A block diagram of a cache management unit according to an embodiment of the present application is shown.

[0050] The cache management unit includes a “hit-lock unit” 372 , an “allocation-lock unit” 374 , a “release-unlock unit” 376 , a “keyword submission unit” 378 and a keyword table 375 .

[0051] The keyword table 375 includes multiple entries, each of which records a "keyword", an "allocation count", a "dirty flag", and an optional "cache unit index". Optionally, the entry does not include a cache unit index, but the position of the entry in the entry table implies the cache unit index, for example, the nth entry in the entry table indicates the nth cache unit. The "keyword" of an entry is information used to identify whether a cache unit is hit according to an embodiment of the present application. For example, a cache unit stores data to be accessed by an IO command, and the corresponding keyword is the address accessed by the IO command. When the data to be accessed by an IO command is filled into a cache unit, the logical address accessed by the IO command is also filled into the entry indicating the cache unit as a keyword. The "allocation count" of an entry indicates the number of times the entry has been referenced. The "dirty flag" of an entry indicates whether the data stored in the cache unit indicated by the entry is available.

[0052] The "hit-lock unit" 372 searches the keyword table 375 for an entry with the same keyword based on the keyword provided, and the "dirty flag" of the entry is no. After the keyword table 375 is initialized, when the cache unit corresponding to the entry has not been allocated, the initial value of the "dirty flag" of the entry is true. If the "hit-lock unit" 372 finds an entry from the keyword table 375, its "dirty flag" is no, and its keyword is the same as the keyword provided to the "hit-lock unit", it is recognized that the cache unit corresponding to the entry has been hit. The "hit-lock unit" 372 uses the corresponding cache unit index as the processing result based on the hit entry. If there is no entry that meets such conditions in the keyword table 375, which means that no cache unit is hit, the "hit-lock unit" 372 will use a specified value that does not represent any cache unit, such as all 0s or all 1s, as the processing result.

[0053] For example, the "hit-lock unit" 372 provides a register to receive a key and stores the result of the processing in another register. Thus, the processor 340 or other circuit units of the control component instruct the "hit-lock unit" 372 to start searching for the cache unit that was hit by writing, for example, a logical address into the register that receives the key, and obtain the search result from another register.

[0054] In response to finding the entry corresponding to the hit cache unit, the "hit-lock unit" 372 also increments (i.e., adds 1) the "allocation count" field of the entry to indicate that the cache unit corresponding to the entry has been used. The incremented value "1" represents the number of entities (processors or circuit units) using the cache unit. This allows the same keyword to be repeatedly provided to the "hit-lock unit" 372 to repeatedly request the "hit-lock unit" 372 to query whether the keyword hits the cache unit. This is very helpful when processing multiple read commands that access the same address at the same time. Since the "hit-lock unit" 372 increments (i.e., adds 1) the "allocation count" field of the entry corresponding to the hit cache unit in response, the value of the "allocation count" field of the entry indicates the number of entities that may use the cache unit or the number of times it has been read. When the value of the "allocation count" field of an entry is not 0, the cache unit of the entry will not be allocated by the "allocation-lock unit" 374.

[0055] According to an embodiment of the present application, the initial value of the "allocation count" of each entry in the keyword table 375 is 0, which also means that the corresponding cache unit is not in use. An entry with a non-zero "allocation count" value indicates that the corresponding cache unit is in use by at least one subject.

[0056] The "allocation-lock unit" 374 searches for an entry with an "allocation count" value of 0 from the keyword table 375 according to the allocation request, and uses the cache unit index corresponding to the entry as the processing result of the allocation request. If there are multiple entries with an "allocation count" value of 0 in the keyword table 375, any one of the multiple entries is selected, and the cache unit index corresponding to the entry is used as the processing result. Optionally, an entry is selected from the multiple entries according to a specified algorithm, and the cache unit index corresponding to the entry is used as the processing result. For example, an entry whose "allocation count" value becomes 0 earlier or earliest among the multiple entries is selected, thereby further improving the probability of the data in the cache unit being used.

[0057] The "allocation-locking unit" 374 also increments (i.e., adds 1) the "allocation count" field of the entry found or selected to indicate that the cache unit corresponding to the entry has been used and should not be allocated again. The "allocation-locking unit" 374 also sets the "dirty flag" of the entry found or selected to true to indicate that the cache unit corresponding to the entry should not be read because data may be written to it at any time (causing the content stored in the cache unit to be unstable). It should be noted that when processing an allocation request, the "allocation-locking unit" 374 does not consider the "dirty flag" of the entry. Therefore, if the "allocation count" value of the entry is 0 and the "dirty flag" is true, the cache unit corresponding to the entry can still be allocated.

[0058] For example, the "allocation-lock unit" 374 provides a register to receive an allocation request and stores the result (cache unit index) in another register. An allocation request has no parameters. The result of the allocation request may be an allocation failure. If no entry that meets the conditions exists in the keyword table 375, the allocation request fails. In response to the allocation request failure, the "allocation-lock unit" 374 sets a specified value that does not represent any cache unit, such as all 0s or all 1s, as the result of the processing.

[0059] The "release-unlock unit" 376 releases the entry in the keyword table 375 corresponding to the cache unit index based on the provided cache unit index. The "release-unlock unit" 376 obtains the entry corresponding to the provided cache unit index from the keyword table 375 and decrements (i.e., reduces by 1) the "allocation count" field of the entry. Optionally, the "release-unlock unit" 376 also avoids reducing the value of the "allocation count" field of the entry to a negative value. For example, it ensures that the minimum value of the "allocation count" field is 0, and does not decrement the "allocation count" field if it is already 0. This prevents the processor 340 or other circuit units from accidentally repeatedly releasing the cache unit index. It is understandable that after the "allocation count" field of the entry is decremented to 0, the "allocation-lock unit" 374 has the opportunity to allocate the cache unit indicated by the entry again. It should be noted that although the "release-unlock unit" 376 decrements the "allocation count" field of the specified entry, it does not change the "key" field of the specified entry. Therefore, even if the "allocation count" field of an entry is decremented to 0, its "key" field still records the previous key, and the data stored in the cache unit indicated by the entry is not overwritten, so the cache unit can still be hit. Then, before the cache unit to which the entry applies is allocated again, it can still be hit by the "hit-lock unit" 372 based on the received key.

[0060] For example, the "release / unlock unit" 376 provides a register to receive a cache unit index. The processor 340 or other circuit units of the control component then write the cache unit index into the register provided by the "release / unlock unit" 376, thereby instructing the "release / unlock unit" 376 to release the entry in the keyword table 375 corresponding to the cache unit index. The "release / unlock unit" 376 may not provide a processing result.

[0061] The "keyword submission unit" 378 records the keyword in the entry corresponding to the cache unit index based on the keyword and cache unit index provided. The "keyword submission unit" 378 also sets the "dirty flag" of the entry to be no. The "keyword submission unit" 378 also uses the provided keyword to query other entries in the keyword table 375 (entries other than the entry corresponding to the provided cache unit index). If one or more "keyword" fields of the other entries are the same as the provided keyword, the "dirty flag" of the one or more other entries found is set to be yes, to ensure that even if there are multiple entries in the keyword table 375 that record the same keyword, only one entry has the "dirty flag" set to no.

[0062] For example, the "keyword submission unit" 378 provides two registers, one for receiving a keyword and the other for receiving a cache unit index. Thus, the processor 340 or other circuit units of the control component can instruct the "keyword submission unit" 378 to update the keyword of the entry corresponding to the cache unit index by writing, for example, a logical address and a cache unit index into the registers receiving the keyword and cache unit index. The "keyword submission unit" 378 may not provide processing results.

[0063] According to an embodiment of the present application, if the processor 340 receives two or more write commands that access the same address, for example, the processor 340 requests the cache management unit 370 to allocate a cache unit (392, 394) for each write command. After moving the data to be written by each write command to the allocated cache unit, the processor 340 provides the address accessed by the write command (denoted as ADDR) to the "keyword submission unit" 378 for each write command that completes the data transfer.

[0064] For example, the processor 340 first instructs the "keyword submission unit" 378 to submit the keyword (K1) to the entry 392 by providing the cache unit index and the keyword (K1). In response, the "keyword submission unit" 378 records the keyword K1 in the "keyword" field of the entry 392 and sets the "dirty flag" of the entry 392 to "no". The "keyword submission unit" 378 also checks whether the keyword fields of other entries have recorded the keyword (K1). The current query result is that no other entry has recorded the keyword (K1). Next, the processor 340 first instructs the "keyword submission unit" 378 to submit the keyword (K1) to the entry 394 by providing the cache unit index and the keyword (K1). In response, the "keyword submission unit" 378 records the keyword K1 in the "keyword" field of the entry 394 and sets the "dirty flag" of the entry 394 to "no". The "keyword submission unit" 378 also checks whether the keyword field of other entries records the keyword (K1). The current query result is that the keyword (K1) is recorded in entry 392, and then the "keyword submission unit" 378 also sets the "dirty mark" of entry 392 to true. In this way, the data stored in the cache unit corresponding to entry 392 is marked as no longer valid. If the "hit-lock unit" 372 of the cache management unit 370 receives the keyword (K1) next, only entry 394 will be hit, and entry 392 will not be hit. This solves the problem of cache unit conflict when processing two or more write commands that access the same address, and can allocate cache units to these write commands. It can also ensure that the correct cache unit is used to respond to subsequent "hit-lock unit" 372 queries on whether the provided keyword hits the cache unit. This also improves the parallelism of the cache management unit 370.

[0065] Figure 4 A schematic diagram showing the collaborative operation of a processor and a cache management unit according to an embodiment of the present application is shown.

[0066] exist Figure 4 In the example of FIG, the processor runs a program to operate the cache management unit 370. Alternatively, other circuit units of the control component operate the cache management unit 370 in a similar manner even if they do not execute a program.

[0067] The program provides multiple programming interfaces, including an allocate cache unit interface 410, a hit check interface 412, a release cache unit interface 414, and a fill cache unit interface 416. The program also includes a command processing module 420. The command processing module 420 is used to process commands and operate the cache management unit 370 using one or more programming interfaces.

[0068] The allocation cache unit interface 410 issues an allocation request to the "allocation-locking unit" 374 of the cache management unit 370 and obtains the cache unit index as the allocation result from the register of the "allocation-locking unit" 374. The allocation cache unit interface 410 also determines whether the allocation result provided by the "allocation-locking unit" 374 indicates that the allocation is successful.

[0069] The hit check interface 412 writes the keyword to be checked to the register of the "hit-lock unit" 372. In the embodiment according to the present application, the keyword is the address to be accessed by the IO command. If there is a cache unit that is hit, the "hit-lock unit" 372 writes the index of the hit cache unit to the register, and the hit check interface 412 obtains the index of the hit cache unit from the register of the "hit-lock unit" 372. The hit check interface 412 also identifies whether the hit result provided by the "hit-lock unit" 372 indicates that a cache unit is hit.

[0070] Understandably, the above Figure 3A and Figure 3B As described, in response to a cache unit being hit, the "hit-lock unit" 372 not only provides the index of the hit cache unit, but also sets the "dirty mark" field of the entry corresponding to the hit cache unit in the keyword table 375 to yes, and increments the "allocation count" field value of the entry to lock the entry to prevent the entry from being allocated again.

[0071] If the hit check interface 412 repeatedly writes the same keyword to be checked to the register of the "hit-lock unit" 372, the same hit cache unit index will be obtained if the keyword table is not updated, and the "hit-lock unit" 372 will increase the "allocation count" field value of the corresponding entry of the hit cache unit in response to each request.

[0072] The release cache unit interface 414 writes the cache unit index to be released to the register of the "release-unlock unit" 376. The "release-unlock unit" 376 only decrements the "allocation count" field value of the entry in the keyword table 375 corresponding to the received cache unit index. The "release-unlock unit" 376 also ensures that the minimum value of the "allocation count" field after decrement is 0. The "release-unlock unit" 376 does not change the other fields of the entry, so that the released cache unit index may still be hit. The cache unit corresponding to the entry with the "allocation count" field being 0 can be reallocated, and it may also be hit before being reallocated.

[0073] If the release cache unit interface 414 repeatedly writes the cache unit index to be released to the register of the "release-unlock unit" 376, the "release-unlock unit" 376 will decrement the "allocation count" field value of the corresponding entry of the hit cache unit in response to each request, and also ensure that the minimum value of the "allocation count" field after decrement is 0.

[0074] The fill cache unit interface 416 writes data to the assigned cache unit and writes the index of the cache unit and the keyword corresponding to the written data (in the embodiment according to the present application, the address) to the register of the "keyword submission unit" 378. The operations of writing data to the cache unit and writing the keyword to the register of the "keyword submission unit" 378 implemented by the fill cache unit interface 416 are implemented together as much as possible. After the data is written to the cache unit, the keyword is written to the register of the "keyword submission unit" 378. This allows the cache management unit 370 to know the keyword associated with the cache unit as soon as data is written to the cache unit and to process subsequent hit requests.

[0075] In response, the "keyword submission unit" 378 also sets the "dirty flag" of the entry in the keyword table 375 corresponding to the cache unit index received by its register to false, indicating that the data stored in the cache unit corresponding to the entry is available. If the keyword table 375 contains other entries with the same "keyword" as the keyword provided to the "keyword submission unit" 378 by the fill cache unit interface 416, the "dirty flag" of these other entries is also set to true, indicating that the data stored in the cache units corresponding to these entries is unavailable.

[0076] After the fill cache unit interface 416 writes data to the allocated cache unit, the "allocation count" field of the entry corresponding to the cache unit is not decremented, that is, the cache unit is not released, so data can be repeatedly written to the allocated cache unit through the fill cache unit interface 416.

[0077] Optionally, the cache management unit 370 also includes a data transfer unit to handle filling or reading the cache unit. The data transfer unit is aware that the data writing process to the cache unit is complete and then writes the index of the cache unit and the key associated with the written data to the register of the "keyword submission unit" 378.

[0078] Figures 5A-5C A flowchart of processing IO commands according to an embodiment of the present application is shown.

[0079] in Figures 5A-5C The processor is e.g. Figure 4 The processor that executes the program, Figures 5A-5C The cache management unit is Figure 4 The cache management unit 370, Figures 5A-5C The storage controller is used to process data movement related to the cache unit (writing data to the cache unit or reading data from the cache unit) (in Figure 4 not shown).

[0080] Figure 5A A flowchart of processing a write command according to an embodiment of the present application is shown.

[0081] When the processor receives the write command, the command processing module 420 calls the allocate cache unit interface 410 (step 510) to request the cache management unit to provide an available cache unit. In response, the cache management unit's "allocate-lock unit" 374 provides the allocate cache unit interface 410 with an index of the available cache unit (step 512).

[0082] The command processing module 420 obtains the available cache unit index from the allocate cache unit interface 410 and calls the fill cache unit interface 416 (step 514). The fill cache unit interface 416 instructs the storage controller to initiate a data move from the host to the allocated cache unit (step 516). In response to the completion of the data move, the fill cache unit interface 416 also provides the cache unit index and key (i.e., the address accessed by the write command) associated with the moved data to the key commit unit 378 (step 518).

[0083] In response to the completion of calling the fill cache unit interface 416, the command processing module 420 then requests the storage controller to read data from the filled cache unit and write the read data to the NVM through the media interface controller (step 520). The storage controller initiates the data transfer from the cache unit to the media interface controller (step 522).

[0084] When necessary (e.g., when the data transfer in step 522 is complete), command processing module 420 also calls release cache unit interface 414 (step 524). Release cache unit interface 414 provides the index of the cache unit to be released to release-unlock unit 376. Release-unlock unit 376 decrements the "allocation count" field of the corresponding entry based on the received cache unit index (step 526). Command processing module 420 may also postpone calling release cache unit interface 414, for example, if command processing module 420 anticipates that the cache unit may be hit in the future.

[0085] Figure 5B A flowchart of processing a read command according to another embodiment of the present application is shown.

[0086] When the processor receives the read command, the command processing module 420 extracts the address to be accessed by the read command as the key and calls the hit check interface 412 (step 530). The "hit-lock unit" 372 recognizes that the key hits the cache unit and provides the index of the hit cache unit to the hit check interface 412 (step 532).

[0087] The command processing module 420 obtains the hit cache unit index from the hit check interface 412 and operates the storage controller to read data from the hit cache unit (step 534). The storage controller initiates data movement from the cache unit to the host (step 536).

[0088] When necessary (e.g., when the data move in step 536 is complete), command processing module 420 also calls release cache unit interface 414 (step 538). Release cache unit interface 414 provides the index of the cache unit to be released to release-unlock unit 376. Release-unlock unit 376 decrements the "allocation count" field of the corresponding entry based on the received cache unit index (step 540). Command processing module 420 may also postpone calling release cache unit interface 414, for example, if command processing module 420 anticipates that the cache unit may be hit in the future.

[0089] Figure 5C A flowchart of processing a read command according to another embodiment of the present application is shown.

[0090] When the processor receives the read command, the command processing module 420 extracts the address to be accessed by the read command as the key and calls the hit check interface 412 (step 550). The "hit-lock unit" 372 recognizes that the key does not hit any cache unit and notifies the hit check interface 412 of the missed cache unit (step 552).

[0091] The command processing module 420 obtains the result of the cache unit miss from the hit check interface 412 and calls the allocate cache unit interface 410 (step 554) to request the cache management unit to provide an available cache unit. In response, the "allocate-lock unit" 374 of the cache management unit provides the index of the available cache unit to the allocate cache unit interface 410 (step 556).

[0092] The command processing module 420 obtains the available cache unit index from the allocate cache unit interface 410, reads data from the NVM chip via the media interface controller, and calls the fill cache unit interface 416 (step 558). The fill cache unit interface 416 instructs the storage controller to move the data read from the NVM chip to the allocated cache unit (step 560). In response to the completion of the data move, the fill cache unit interface 416 also provides the cache unit index and key (i.e., the address accessed by the read command) associated with the moved data to the "key submission unit" 378 (step 562).

[0093] In response to the completion of calling the fill cache unit interface 416, the command processing module 420 operates the storage controller to read the data from the filled cache unit and move it to the host (step 564). The storage controller initiates the data movement from the cache unit to the host (step 566).

[0094] When necessary (e.g., when the data transfer in step 566 is complete), command processing module 420 also calls release cache unit interface 414 (step 568). Release cache unit interface 414 provides the index of the cache unit to be released to release-unlock unit 376. Release-unlock unit 376 decrements the "allocation count" field of the corresponding entry based on the received cache unit index (step 570). Command processing module 420 may also postpone calling release cache unit interface 414, for example, if command processing module 420 anticipates that the cache unit may be hit in the future.

[0095] According to an embodiment of the present application, a storage device is further provided, including a controller and a non-volatile memory chip, wherein the controller executes any one of the processing methods provided in the embodiments of the present application.

[0096] According to an embodiment of the present application, a program stored on a readable medium is also provided, which, when executed by a controller of a storage device, enables the storage device to execute any one of the processing methods provided according to the embodiments of the present application.

[0097] Although preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this application. Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if such changes and modifications fall within the scope of the claims of this application and their equivalents, then this application is intended to include such changes and modifications.

Claims

1. A hardware cache management unit, comprising an allocation-locking unit, a hit-locking unit, a release-unlocking unit, a keyword submission unit, and a keyword table; The keyword table includes a plurality of entries, each entry representing one of the cache units; each entry records a keyword, an allocation count, and a dirty flag; each entry also records a cache unit index, or the position of the entry in the keyword table implies the cache unit index; the keyword of the entry is information used to identify whether the cache unit is hit, the allocation count of the entry indicates the number of times the entry is referenced, and the dirty flag of the entry indicates whether the data stored in the cache unit indicated by the entry is available; The allocation-locking unit searches for an entry representing an available cache unit from the keyword table and outputs a cache unit index representing the available cache unit; The hit-lock unit outputs a cache unit index corresponding to an entry storing the provided keyword in response to the provided keyword; The release-unlock unit decrements the allocation count field of the entry corresponding to the provided cache unit index in the keyword table in response to the provided cache unit index; The keyword submitting unit records the provided keyword in an entry corresponding to the provided cache unit index in the keyword table in response to the provided keyword and the cache unit index.

2. The hardware cache management unit according to claim 1, wherein The allocation-locking unit searches for an entry whose allocation count field is 0 from the keyword table, and uses the found entry as an entry representing an available cache unit.

3. The hardware cache management unit according to claim 2, wherein The allocate-lock unit increments the reference count field of the entry representing the free cache unit and sets its dirty flag to true.

4. The hardware cache management unit according to any one of claims 1 to 3, wherein The hit-lock unit outputs a dirty flag of no in response to the provided keyword and stores a cache unit index corresponding to an entry of the provided keyword.

5. The hardware cache management unit according to claim 4, wherein The hit-lock unit also marks the entry dirty as not and increments the reference count field of the entry storing the supplied key.

6. The hardware cache management unit according to claim 5, wherein The release-unlock unit decrements the allocation count field of the entry corresponding to the provided cache unit index in the keyword table in response to the provided cache unit index, and ensures that the value of the allocation count field is not less than 0 after being decremented.

7. The hardware cache management unit according to claim 6, wherein The keyword committing unit further sets the dirty flag of the entry corresponding to the provided cache unit index to be negative in response to the provided keyword and cache unit index.

8. The hardware cache management unit according to claim 7, wherein In response to the provided keyword and cache unit index, the keyword submission unit also sets the dirty flag of one or more entries in the keyword table other than the entry corresponding to the provided cache unit index, which have the same keyword as the provided keyword and have a dirty flag of no to true.

9. A chip comprising a processor and a hardware cache management unit, wherein the hardware cache management unit is the hardware cache management unit according to any one of claims 1 to 8.

10. A method for processing IO commands using a hardware cache management unit, wherein the hardware cache management unit is the hardware cache management unit according to any one of claims 1 to 8, the method comprising: In response to receiving a write command, the allocation-locking unit is used to obtain the index of the available first cache unit, the data to be written by the write command is moved to the first cache unit, the index of the first cache unit and the address accessed by the write command as the keyword are provided to the keyword submission unit, and the storage controller is requested to read the data from the filled first cache unit. The storage controller initiates data movement from the first cache unit to the media interface controller, and after the data movement is completed, the index of the first cache unit is also provided to the release-unlocking unit.

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