Vertical semiconductor device

Abstract

A vertical semiconductor device is provided. The vertical semiconductor device may include a plurality of channel connection patterns, a lower insulating layer, a supporting layer, a stacked structure, and a channel structure. The channel connection pattern may contact a substrate. The lower insulating layer may be formed on the channel connection pattern. The supporting layer may be formed on the lower insulating layer to be spaced apart from the channel connection pattern. The supporting layer may include polysilicon doped with impurities. The stacked structure may be formed on the supporting layer, and the stacked structure may include an insulating layer and a gate electrode to form a memory cell string. The channel structure may pass through the stacked structure, the supporting layer, and the lower insulating layer. The channel structure may include a charge storage structure and a channel. The channel may contact the channel connection pattern. The charge storage structure and the channel may be arranged to face the gate electrode and the supporting layer. The supporting layer may serve as a gate of a GIDL (gate induced drain leakage) transistor.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2018-0135545 filed on November 7, 2018 in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Apparatuses consistent with example embodiments of inventive concepts relate to vertical semiconductor devices. Background Art

[0003] In a VNAND flash memory device, a gate-induced drain leakage (GIDL) transistor may be formed below a ground select transistor. Holes generated by the gate-induced drain leakage of the GIDL transistor may be used to erase data stored in a memory cell. In order to reduce the erase voltage, the GIDL transistor may need to have a high efficiency of hole generation through the GIDL. In addition, the height of the GIDL transistor may need to be reduced so that the height of the VNAND flash memory device is not substantially increased.

[0004] The information disclosed in this background technology section is known to the inventor before the invention of this application is realized, or is technical information obtained in the process of realizing the invention. Therefore, it may contain information that does not form the prior art known to the public. Summary of the invention

[0005] Various example embodiments are directed to a vertical semiconductor device having excellent electrical characteristics.

[0006] According to example embodiments, a vertical semiconductor device is provided. The vertical semiconductor device may include a plurality of channel connection patterns, a lower insulating layer, a supporting layer, a stacked structure, and a channel structure. The channel connection pattern may contact a substrate. The lower insulating layer may be formed on the channel connection pattern. The supporting layer may be formed on the lower insulating layer to be spaced apart from the channel connection pattern. The supporting layer may include polysilicon doped with impurities. A stacked structure may be formed on the supporting layer, and the stacked structure may include an insulating layer and a gate electrode to form a memory cell string. The channel structure may pass through the stacked structure, the supporting layer, and the lower insulating layer. The channel structure may include a charge storage structure and a channel. The channel may contact the channel connection pattern. The charge storage structure and the channel may be arranged to face the gate electrode and the supporting layer. The supporting layer may serve as a gate of a GIDL (gate induced drain leakage) transistor.

[0007] According to example embodiments, a vertical semiconductor device is provided. The vertical semiconductor device may include a plurality of channel connection patterns, a lower insulating layer, a support layer, a stacked structure, and a channel structure. The channel connection pattern may contact the upper surface of the substrate. The lower insulating layer may be formed on the channel connection pattern and in a portion between the channel connection patterns. The support layer may be formed on the lower insulating layer to be spaced apart from the channel connection pattern. The support layer may include polysilicon doped with impurities. The stacked structure may be formed on the support layer. The stacked structure may include insulating layers and gate electrodes that are repeatedly and alternately stacked. The channel structure may pass through the stacked structure, the support layer, and the lower insulating layer. The channel structure may extend to the upper portion of the substrate. The channel structure may include a charge storage structure and a channel. The channel may contact the channel connection pattern and may have a cylindrical shape. The charge storage structure and the channel may be arranged to face the gate electrode and the support layer. The width of the channel at a level below the upper surface of the support layer may be greater than the width of the sidewall of the channel at a level above the upper surface of the support layer.

[0008] According to example embodiments, a vertical semiconductor device is provided. The vertical semiconductor device may include a lower gate layer, a stacked structure, and a channel structure. The lower gate layer may be spaced apart from a substrate, and the lower gate layer may include polysilicon doped with impurities. The stacked structure may be formed on the lower gate layer. The stacked structure may include an insulating layer and a gate electrode that are repeatedly stacked to form a memory cell string, and the gate electrode may include a metal. The channel structure may pass through the stacked structure and the lower gate layer. The channel structure may extend to an upper portion of the substrate, and the channel structure may include a charge storage structure and a channel having a cylindrical shape. The charge storage structure and the channel may be arranged to face the gate electrode and the lower gate layer. The width of the channel at a level below the upper surface of the lower gate layer may be greater than the width of the sidewall of the channel at a level above the upper surface of the lower gate layer.

[0009] In example embodiments, the vertical semiconductor device may include a support layer to support a structure formed on the support layer, and the support layer may serve as a gate of the GIDL transistor. Therefore, the vertical height of the vertical semiconductor device may be reduced. In addition, in the vertical semiconductor device, the width of the lower portion of the channel may be reduced, thereby improving the electrical characteristics of the GIDL transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 28 represents non-limiting example embodiments as described herein.

[0011] Figures 1 to 3 are cross-sectional views and plan views illustrating a vertical semiconductor device according to example embodiments;

[0012] Figure 4 and Figure 5 are cross-sectional views illustrating a vertical semiconductor device according to example embodiments, respectively;

[0013] Figures 6 to 22 are plan views and cross-sectional views illustrating stages of a method of manufacturing a vertical semiconductor device according to example embodiments;

[0014] Fig.23 and Fig.24 is a cross-sectional view illustrating a vertical semiconductor device according to example embodiments;

[0015] Fig.25 is a cross-sectional view illustrating stages of a method of manufacturing a vertical semiconductor device according to an example embodiment;

[0016] Fig.26 and Fig. 27 is a cross-sectional view illustrating a vertical semiconductor device according to example embodiments; and

[0017] Fig.28 is a cross-sectional view illustrating a vertical semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0018] It will be understood that when an element or layer is referred to as being "on" another element or layer, "above" another element or layer, "on" another element or layer, "connected to" or "bonded to" another element or layer, it may be directly on, directly above, directly on, directly connected to or directly bonded to the other element or layer, or there may be intermediate elements or intermediate layers. In contrast, when an element or layer is referred to as being "directly on" another element or layer, "directly above", "directly on", "directly connected to" or "directly bonded to" another element or layer, there are no intermediate elements or intermediate layers. The same reference numerals always represent the same element. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0019] Hereinafter, a direction substantially parallel to the upper surface of the substrate is defined as a first direction, and a direction substantially perpendicular to the upper surface of the substrate is defined as a vertical direction.

[0020] Figures 1 to 3 are cross-sectional views and plan views illustrating a vertical semiconductor device according to example embodiments. Figure 4 and Figure 5 are cross-sectional views illustrating vertical semiconductor devices according to example embodiments, respectively.

[0021] Figure 1 and Figure 2 is a cross-sectional view, Figure 3 It is a floor plan. Figure 2 yes Figure 1 Magnified view of portion "A".

[0022] Figure 1 is along Figure 3 Specifically, Figure 1 , portions of a common source line, a channel structure, and a dummy channel structure are shown.

[0023] Reference Figure 1 , Figure 2 and Figure 3 , the vertical semiconductor device may include a channel connection pattern 158a, a lower insulating layer 106, a support layer 108, a stack structure 172, and a channel structure 190 formed on a substrate 100. In addition, the vertical semiconductor device may include a common source line 182, a spacer 180, and a dummy channel structure 190a.

[0024] The substrate 100 may include a semiconductor material such as silicon, germanium, silicon germanium, or a III-V semiconductor compound such as GaP, GaAs, GaSb, etc. In example embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0025] In example embodiments, a pad layer 101 may be formed on a portion of an upper surface of the substrate 100. The pad layer 101 may include an insulating material. For example, the pad layer 101 may include an oxide, such as silicon oxide.

[0026] The channel connection pattern 158a may be electrically connected to the channel 136 and the substrate 100. Therefore, at least a portion of the channel connection pattern 158a may directly contact the substrate 100. In example embodiments, the entire lower surface of the channel connection pattern 158a may contact the upper surface of the substrate 100. The channel connection pattern 158a may include polysilicon doped with impurities. The impurities doped in the channel connection pattern 158a may be N-type impurities such as phosphorus, arsenic, etc.

[0027] In example embodiments, the channel connection pattern 158a may include a first opening 112a and a second opening 112b. For example, the first opening 112a may correspond to a portion of a trench for forming a common source line, and the second opening 112b may correspond to a portion for forming a dummy channel structure. The width of the first opening 112a may be greater than the width of the second opening 112b.

[0028] The channel connection pattern 158a may be spaced apart from the support layer 108 in a vertical direction. Therefore, the channel connection pattern 158a may not be electrically connected to the support layer 108.

[0029] In some example embodiments, Figure 5 As shown in , the channel connection pattern 158a may include only the first opening 112a in the portion of the trench for forming the common source line. That is, the channel connection pattern 158a may not include the second opening for forming the dummy channel structure.

[0030] A lower insulating layer 106 may be formed on the channel connection patterns 158a to fill a space between the channel connection patterns 158a. The lower insulating layer 106 may include, for example, silicon oxide.

[0031] In example embodiments, the lower insulating layer 106 may be formed on the channel connection pattern 158a to fill the first opening 112a and the second opening 112b. Therefore, the upper surface of the lower insulating layer 106 may have a relatively low height at a portion of the first opening 112a, so that a recess may be formed at the upper surface of the lower insulating layer 106.

[0032] The support layer 108 may be formed on the lower insulating layer 106. When the recess is formed at the upper surface of the lower insulating layer 106, the recess may also be formed on the upper portion of the support layer 108. That is, the recess may be formed on a portion of the upper surface of the lower insulating layer 106 under which the first opening 112a is formed.

[0033] When a first gap as a space for forming the channel connection pattern 158a is formed by an etching process, the support layer 108 may support a structure formed on the support layer 108. Therefore, the support layer 108 may include a material having a high etching selectivity with respect to a material that will be easily etched in the etching process for forming the first gap. For example, the support layer 108 may include a material having a high etching selectivity with respect to silicon nitride.

[0034] In an example embodiment, a GIDL transistor for erasing data stored in a memory cell may be formed at the lowest portion of a cell string. The GIDL transistor forces GIDL to be generated, and thus holes paired with electrons may be generated at a gate portion of the GIDL transistor. In addition, holes may be injected into a channel of the cell string to generate a reverse bias, so that the stored data in the memory cell may be erased.

[0035] In an example embodiment, the support layer 108 may be or be used as a gate electrode of the lowest transistor of the cell string. That is, the support layer 108 may be formed or configured to be used as a gate electrode of a GIDL transistor. Therefore, the support layer 108 may have conductivity. In addition, the thickness of the support layer 108 in the vertical direction may be substantially equal to the channel length of the GIDL transistor. Therefore, the electrical characteristics of the GIDL transistor may be controlled by adjusting the thickness of the support layer 108 in the vertical direction. For example, the thickness of the support layer 108 in the vertical direction may be greater than the thickness of each gate electrode 170 formed above the support layer 108 in the vertical direction.

[0036] In example embodiments, the support layer 108 may include polysilicon doped with impurities. The support layer 108 may include, for example, polysilicon doped with N-type impurities such as phosphorus, arsenic, etc. In example embodiments, the impurities included in the support layer 108 may be substantially the same as the impurities included in the channel connection pattern 158a.

[0037] As described above, the support layer 108 and the gate electrode of the GIDL transistor are not formed separately, and one polysilicon layer can serve as both the support layer 108 and the gate electrode of the GIDL transistor. Therefore, the height of the VNAND flash memory device in the vertical direction can be reduced. In addition, malfunctions and / or defects caused by the increase in the height of the VNAND flash memory device in the vertical direction can be reduced.

[0038] The filling insulating pattern 110 may be further formed to fill the recess of the supporting layer 108. An upper surface of the filling insulating pattern 110 and an upper surface of the supporting layer 108 may be flat and coplanar with each other.

[0039] A stack structure 172 may be formed on the support layer 108 and the filling insulating pattern 110. The stack structure 172 may include alternately and repeatedly stacked insulating layers 120 and gate electrodes 170. Each gate electrode 170 included in the stack structure 172 may serve as or may be configured to serve as a gate electrode of one of a ground selection transistor, a cell transistor, and a cell selection transistor.

[0040] For example, at least one gate electrode 170a formed at the lowest portion of the stack structure 172 may serve as a gate electrode of a ground selection transistor, and at least one gate electrode 170 formed at the highest portion of the stack structure 172 may serve as a gate electrode of a cell selection transistor. The gate electrode 170 disposed between the gate electrode of the ground selection transistor and the gate electrode of the cell selection transistor may serve as a gate electrode of the cell transistor.

[0041] The gate electrode 170 may include a material different from that of the supporting layer 108. That is, the material of the gate electrode of the GIDL transistor may be different from that of the gate electrode 170 of the transistor formed above the GIDL transistor.

[0042] In example embodiments, the gate electrode 170 may include a barrier layer (not shown) and a gate conductive layer. The gate conductive layer may include a metal having good step coverage and low resistance. The gate conductive layer may include a metal such as tungsten, titanium, tantalum, platinum, etc., and the barrier layer may include a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, etc.

[0043] The channel structure 190 may penetrate the stack structure 172, the support layer 108, and the lower insulating layer 106, and may extend into the upper surface of the substrate 100. Thus, the channel structure 190 may contact the substrate 100.

[0044] The channel structure 190 may be formed in a channel hole 126a (refer to Figure 8 )middle.

[0045] In example embodiments, the channel hole 126a may have an inclined sidewall so that the width of the channel hole 126a may gradually decrease from an upper portion of the channel hole 126a toward a lower portion of the channel hole 126a. Therefore, the channel structure 190 may also have an inclined sidewall so that the width of the channel structure 190 may gradually decrease from an upper portion of the channel structure 190 toward a lower portion of the channel structure 190.

[0046] In some example embodiments, Figure 4 As shown in FIG. 1 , the sidewall slope of the channel hole 126a may become larger at a portion adjacent to the support layer 108, so that the inclined sidewall of the channel hole 126a may be curved at a portion adjacent to the support layer 108. Therefore, the channel hole 126a may have a relatively small width at a level below the support layer 108.

[0047] The channel structure 190 may include a charge storage structure 135, a channel 136, and a filling pattern 138. The channel structure 190 may further include a capping pattern 140 formed at an upper portion of the channel hole 126a. The capping pattern 140 may contact the channel 136.

[0048] The charge storage structure 135 may include a tunnel insulating pattern 134, a charge storing pattern 132, and a blocking pattern 130 which may be sequentially stacked on an outer wall of a channel 136. The tunnel insulating pattern 134 and the blocking pattern 130 may include silicon oxide, and the charge storing pattern 132 may include silicon nitride.

[0049] The charge storage structure 135 may be formed on an upper sidewall of the channel hole 126a, which is located at a level higher than the channel connection pattern 158a. In addition, a portion of the charge storage structure 135 may remain at a portion of the channel hole 126a extending into the substrate 100.

[0050] In example embodiments, the channel 136 may have a cylindrical shape in the channel hole 126a. In example embodiments, the channel 136 may have a tapered cylindrical shape in the channel hole 126a, the diameter of which becomes smaller in a downward direction. Hereinafter, example embodiments describe a channel having a tapered cylindrical shape. The channel 136 may contact the charge storage structure 135 and the channel connection pattern 158a.

[0051] In example embodiments, the bottom of the inner space of the channel 136 may be disposed at a level between the upper surface of the support layer 108 and the lower surface of the lowermost gate electrode 170a. The thickness of the lower portion of the channel 136 having the tapered cylindrical shape in the vertical direction may be greater than the thickness of the sidewall of the channel 136 in the lateral direction.

[0052] The lower portion of the channel 136 may fill the lower portion of the channel hole 126a below the upper surface of the support layer 108, and the upper portion of the channel 136 may be conformally formed on the sidewall of the channel hole 126a. The width of the lower portion of the channel 136 in the lateral direction may be greater than the thickness of the sidewall of the channel 136 in the lateral direction.

[0053] The lower portion of the channel 136 may be electrically connected to the substrate 100 through the channel connection pattern 158a. The contact portion between the channel 136 and the channel connection pattern 158a may be located at a level below the lower surface of the support layer 108. In addition, at the contact portion between the channel 136 and the channel connection pattern 158a, the charge storage structure 135 may be removed.

[0054] The lower portion of the channel 136 may serve as a channel region of the GIDL transistor. In addition, the upper portion of the channel 136 may serve as a channel region of the ground selection transistor, the cell transistor, and the cell selection transistor. Therefore, the channels 136 of the ground selection transistor, the cell transistor, and the cell selection transistor, and the channel 136 of the GIDL transistor may have different shapes and different widths. The lower portion of the channel 136 serving as the channel region of the GIDL transistor may have a pillar shape.

[0055] In example embodiments, the lower portion of the channel 136, which is a channel region of the GIDL transistor, may be doped with impurities. That is, a portion of the channel 136 below the lowermost gate electrode 170a may be selectively doped with impurities. However, the upper portion of the channel 136 may not be doped with impurities. The impurities doped in the lower portion of the channel 136 may be N-type impurities such as phosphorus, arsenic, etc. The impurities may be substantially the same as the impurities doped in the channel connection pattern 158a.

[0056] In the polysilicon formed as the channel 136, the grain size at the wide portion of the polysilicon is larger than the grain size at the narrow portion of the polysilicon. As the grain size of the polysilicon increases, the diffusion of impurities can be easily controlled. Therefore, impurities can be fully doped at the lower portion of the channel 136 having a relatively wide width and a large grain size, but impurities are not doped in the upper portion of the channel 136 having a relatively narrow width and a small grain size. Therefore, the GIDL current generated at the GIDL transistor can be increased, and thus the erase voltage of the stored data in the memory cell can be reduced.

[0057] A filling pattern 138 may be formed on the trench 136 to fill the trench hole 126a. The filling pattern 138 may include an insulating material. The insulating material may include, for example, silicon oxide.

[0058] The capping pattern 140 may include, for example, polysilicon. The capping pattern 140 may serve as a pad for contacting an upper wiring (not shown).

[0059] The dummy channel structure 190a may pass through the stacked structure 172, the support layer 108, and the lower insulating layer 106, and may extend to the upper portion of the substrate 100. The dummy channel structure 190a may be formed in a dummy channel hole ( Figure 8 In example embodiments, the dummy channel hole 126b may have an inclined sidewall such that the width may gradually decrease from an upper portion of the dummy channel hole toward a lower portion of the dummy channel hole. Therefore, the dummy channel structure 190a may also have an inclined sidewall such that the width may gradually decrease from an upper portion of the dummy channel structure 190a toward a lower portion of the dummy channel structure 190a.

[0060] The dummy channel structure 190a may include a charge storing structure 135, a dummy channel 136a, and a filling pattern 138. In addition, a capping pattern 140 may be formed at an upper portion of the dummy channel hole 126b, and the capping pattern 140 may contact the dummy channel 136a.

[0061] In example embodiments, the dummy channel structure 190a may pass through the lower insulating layer 106 in the second opening 112b and may extend to the substrate 100. In example embodiments, the dummy channel 136a may not contact the channel connection pattern 158a. The lower sidewall of the dummy channel structure 190a may contact the lower insulating layer 106. Therefore, the dummy channel structure 190a may be electrically isolated from the substrate 100. The dummy channel structure 190a may not operate as an actual memory cell. In addition, the dummy channel structure 190a may not be electrically connected to the channel structure 190. Therefore, even if a failure and / or damage of the dummy channel structure 190a occurs, the channel structure 190 will not be electrically affected.

[0062] In some example embodiments, Figure 5 As shown in FIG. 1 , the dummy channel structure 190a may have a shape substantially the same as that of the channel structure 190. In this case, the dummy channel 136a included in the dummy channel structure 190a may contact the channel connection pattern 158a.

[0063] Common source line 182 may pass through stack structure 172, support layer 108, and lower insulating layer 106 so that at least a portion of a bottom of common source line 182 may contact an upper surface of substrate 100. In addition, common source line 182 may extend in a first direction.

[0064] The stack structure 172 and the support layer 108 may be formed between the common source lines 182. Therefore, the support layer 108 and the stack structure 172 may have a line shape extending in the first direction.

[0065] The common source line 182 may include, for example, a barrier metal layer (not shown) and a metal pattern. The barrier metal layer may include metal nitrides such as tungsten nitride, titanium nitride, tantalum nitride, etc. The metal pattern may include a metal with low resistance such as tungsten, titanium, tantalum, platinum, etc.

[0066] A spacer 180 including an insulating material may surround a sidewall of the common source line 182. In example embodiments, the insulating material may include silicon oxide.

[0067] The stack structure 172 and the support layer 108 may contact the spacer 180. Therefore, the gate electrode 170 and the common source line 182 included in the stack structure 172 may be electrically isolated by the spacer 180, and the support layer 108 and the common source line 182 may also be electrically isolated by the spacer 180.

[0068] In example embodiments, the common source line 182 may pass through the lower insulating layer 106 in the first opening 112a and may extend to the substrate 100. Thus, the common source line 182 disposed in the first opening 112a may be spaced apart from the channel connection pattern 158a.

[0069] In the vertical semiconductor device, the support layer 108 can be used as the gate electrode of the GIDL transistor, so that the height of the vertical semiconductor device can be reduced. In addition, the width of the channel region of the GIDL transistor can be increased. Therefore, the GIDL current generated at the GIDL transistor can be increased, and thus the erase voltage of the stored data in the memory cell can be reduced.

[0070] Figures 6 to 22 are plan views and cross-sectional views illustrating stages of a method of fabricating a vertical semiconductor device according to example embodiments.

[0071] Reference Figure 6 and Figure 7 , a pad layer 101 may be formed on the substrate 100 , a first sacrificial pattern 104 may be formed on the pad layer 101 , and a lower insulating layer 106 and a supporting layer 108 may be sequentially formed on the first sacrificial pattern 104 and the pad layer 101 .

[0072] The pad layer 101 may include silicon oxide.

[0073] The first sacrificial pattern 104 may be formed by depositing a first sacrificial layer on the pad layer 101 and patterning the first sacrificial layer. In example embodiments, in the patterning process, the first sacrificial layer disposed at a portion in the trench for forming a common source line and the first sacrificial layer disposed at a portion for forming a dummy channel structure may be removed to form the first sacrificial pattern 104. In this case, the first sacrificial pattern 104 may include a first opening 112a at a portion in the trench for forming a common source line and a second opening 112b at a portion for forming a dummy channel structure. The width of the first opening 112a may be greater than the width of the second opening 112b.

[0074] In some example embodiments, in the patterning process, the first sacrificial layer disposed at a portion in the trench for forming the common source line may be removed to form the first sacrificial pattern 104. In this case, the first sacrificial pattern 104 may include a first opening 112a at a portion in the trench for forming the common source line. However, the second opening 112b may not be formed at a portion for forming the dummy channel structure. Therefore, when a subsequent process is performed in the same manner on the first sacrificial pattern 104 including only the first opening 112a, the shape of the dummy channel structure may be substantially the same as the shape of the channel structure. Therefore, it is possible to manufacture Figure 5 The semiconductor device shown in FIG.

[0075] The first sacrificial pattern 104 may include a material having a high etch selectivity with respect to each of silicon oxide and polysilicon. For example, the first sacrificial pattern 104 may include silicon nitride.

[0076] A lower insulating layer 106 may be formed on the first sacrificial pattern 104 to fill the first opening 112a and the second opening 112b. The lower insulating layer 106 may include, for example, silicon oxide. In example embodiments, an upper surface of the lower insulating layer 106 may be relatively lowered in the first opening 112a and the second opening 112b, so that an upper surface of the lower insulating layer 106 may have a recess at a portion corresponding to the first opening 112a and the second opening 112b.

[0077] The support layer 108 may be formed to support a structure stacked on the support layer 108 during a subsequent removal process of the first sacrificial pattern 104. Therefore, the support layer 108 may include a material having a high etch selectivity with respect to each of silicon oxide and silicon nitride.

[0078] In addition, the support layer 108 may serve as or may be configured to serve as a gate electrode of a GIDL transistor formed at the lowermost portion of the cell string. Therefore, the support layer 108 may have conductivity. In example embodiments, the support layer 108 may include polysilicon doped with N-type impurities such as phosphorus, arsenic, etc.

[0079] Since the support layer 108 is formed on the upper surface of the lower insulating layer 106 including the recess, the upper surface of the support layer 108 may also have the recess. The recess may be disposed to face the first opening 112a and the second opening 112b.

[0080] In example embodiments, the filling insulating pattern 110 may be formed to fill the recess formed on the support layer 108. Upper surfaces of the filling insulating pattern 110 and the support layer 108 may be flat and coplanar with each other. The filling insulating pattern 110 may include, for example, silicon oxide.

[0081] Then, the insulating layers 120 and the second sacrificial layers 122 may be alternately and repeatedly formed on the support layer 108 and the filling insulating patterns 110. The first insulating interlayer 124 may be formed on the uppermost insulating layer 120.

[0082] The second sacrificial layer 122 may form gate electrodes of a ground selection transistor, a cell transistor, and a cell selection transistor through a subsequent process. As the thickness of the second sacrificial layer 122 increases, the height of the semiconductor device in a vertical direction may increase. Therefore, in example embodiments, the thickness of each of the second sacrificial layers 122 may be less than the thickness of the support layer 108 as the gate electrode of the GIDL transistor.

[0083] In example embodiments, the insulating layer 120 and the first insulating interlayer 124 may include an oxide, eg, silicon oxide, and the second sacrificial layer 122 may include a nitride, eg, silicon nitride.

[0084] Reference Figure 8 and Fig.10 , the first insulating interlayer 124 , the insulating layer 120 , the second sacrificial layer 122 , the support layer 108 , the lower insulating layer 106 , the first sacrificial pattern 104 , and the pad layer 101 may be isotropically etched to form the channel holes 126 a and the dummy channel holes 126 b .

[0085] The channel hole 126a and the dummy channel hole 126b may be formed to extend into a portion below the upper surface of the substrate 100. Therefore, bottoms of the channel hole 126a and the dummy channel hole 126b may be lower than the upper surface of the substrate 100.

[0086] In example embodiments, each of the channel hole 126 a and the dummy channel hole 126 b may have an inclined sidewall such that a width of each of the channel hole 126 a and the dummy channel hole 126 b may gradually decrease from an upper portion thereof toward a lower portion thereof.

[0087] In some example embodiments, Fig. 9 As shown in , the sidewall slope of each of the channel hole 126a and the dummy channel hole 126b may be increased at a portion adjacent to the support layer 108, so that the inclined sidewall of each of the channel hole 126a and the dummy channel hole 126b may be curved at a portion adjacent to the support layer 108. Therefore, each of the channel hole 126a and the dummy channel hole 126b may have a relatively small width below the support layer 108. In this case, the manufacturing method can be performed by performing subsequent processes in the same manner. Figure 4 The semiconductor device shown in FIG.

[0088] In an example embodiment, the channel hole 126a may serve as a space for forming a channel structure constituting a memory cell string, and the dummy channel hole 126b may serve as a space for forming a dummy channel structure constituting a dummy cell string. The channel hole 126a may pass through the first sacrificial pattern 104, and thus, the first sacrificial pattern 104 may be exposed by the lower sidewall of the channel hole 126a. At the same time, the dummy channel hole 126b may pass through a portion of the second opening 112b between the first sacrificial patterns 104, so that the lower insulating layer 106 may be exposed by the lower sidewall of the dummy channel hole 126b. That is, the first sacrificial pattern 104 may not be exposed by the sidewall of the dummy channel hole 126b.

[0089] In some example embodiments, the channel structure and the dummy channel structure may be formed to have substantially the same shape. In this case, the first sacrificial pattern 104 may not include the second opening 112b. Therefore, each of the channel hole 126a and the dummy channel hole 126b may pass through the first sacrificial pattern 104, so that the first sacrificial pattern 104 may be exposed by the lower sidewalls of the channel hole 126a and the dummy channel hole 126b.

[0090] Reference Fig.11 , a charge storage structure 135 , a channel 136 , and a filling pattern 138 may be formed in each of the channel hole 126 a and the dummy channel hole 126 b .

[0091] Specifically, a charge storage structure layer may be formed on the sidewalls and bottoms of the channel hole 126a and the dummy channel hole 126b and on the upper surface of the first insulating interlayer 124. The charge storage structure layer may include a first blocking layer, a charge storage layer, and a tunnel insulating layer stacked in sequence. For example, the first blocking layer, the charge storage layer, and the tunnel insulating layer may include silicon oxide, silicon nitride, and silicon oxide, respectively.

[0092] A channel layer may be conformally formed on the charge storage structure layer. The channel layer may include undoped polysilicon.

[0093] Each of the channel hole 126a and the dummy channel hole 126b may include a lower portion at a level below the bottom of the lowermost second sacrificial layer 122 and an upper portion at a level above the bottom of the lowermost second sacrificial layer 122. The channel layers formed on the lower sidewalls having a relatively small width of each of the channel hole 126a and the dummy channel hole 126b may contact each other. Therefore, the channel layer in each of the channel hole 126a and the dummy channel hole 126b may have a folded shape. The channel layer may fill the lower portion of each of the channel hole 126a and the dummy channel hole 126b. That is, the channel layer formed on the tunnel insulating layer may have a tapered cylindrical shape formed along the inner surface of the channel hole 126a and the dummy channel hole 126b. The bottom of the inner space of the channel layer having a tapered cylindrical shape may be set at a level between the upper surface of the support layer 108 and the lower surface of the lowermost second sacrificial layer 122.

[0094] In example embodiments, the thickness of the lowermost insulating layer 120 between the upper surface of the support layer 108 and the lowermost second sacrificial layer 122 may be formed to be greater than the thickness of other insulating layers 120 thereon. In this case, the margin (or range) of the portion where the upper surface of the folded portion of the channel layer is located may be increased.

[0095] Thereafter, a filling insulating layer may be formed on the channel layer to fill the remaining portions of the channel hole 126a and the dummy channel hole 126b. Then, the filling insulating layer, the channel layer, and the charge storage structure layer may be planarized until the upper surface of the first insulating interlayer 124 may be exposed.

[0096] Thus, a charge storage structure 135 and a channel 136 may be formed on the sidewalls of the channel hole 126a and the dummy channel hole 126b and on the upper surface of the substrate 100, and a filling pattern 138 may be formed on the channel 136 to fill the inner space of the channel 136. The charge storage structure 135 may include a blocking pattern 130, a charge storage pattern 132, and a tunnel insulating pattern 134.

[0097] As described above, the bottom of the inner space of the channel 136 may be located at a level between the upper surface of the support layer 108 and the lowermost second sacrificial layer 122. Therefore, the width of the folded portion of the channel 136 may be greater than the width of the upper portion of the channel 136 above the folded portion. Since the support layer 108 serves as or is configured to serve as a gate electrode of the GIDL transistor, the folded portion of the channel 136 may serve as or may be configured to serve as a channel region of the GIDL transistor.

[0098] At the same time, the portion of the channel 136 contacting the second sacrificial layer 122 may not be folded. Therefore, the channel 136 of the ground selection transistor, the cell transistor and the cell selection transistor, and the channel 136 of the GIDL transistor may have different shapes and different widths. That is, the width of the channel 136 at a level below the upper surface of the support layer 108 may be greater than the width of the sidewall of the channel 136 having a tapered cylindrical shape. In addition, the thickness of the bottom of the channel 136 may be greater than the thickness of the sidewall of the channel 136.

[0099] Reference Fig.12 , the filling pattern 138 and the upper portions of the trench 136 may be removed to form a recess, and a capping pattern 140 may be formed in the recess. The capping pattern 140 may include, for example, polysilicon.

[0100] A second insulating interlayer 146 may be formed on the first insulating interlayer 124 and the capping pattern 140 .

[0101] Reference Fig.13 The first and second insulating interlayers 124 and 146, the second sacrificial layer 122, the insulating layer 120, the support layer 108, and the lower insulating layer 106 may be anisotropically etched to form a trench 148 therethrough. The trench 148 may extend in a first direction.

[0102] In example embodiments, the bottom of the groove 148 may expose the upper surface of the first sacrificial pattern 104. In addition, a portion of the bottom of the groove 148 may expose the surface of the substrate 100. That is, the groove 148 formed at the first opening 112a may expose the surface of the substrate 100.

[0103] Reference Fig.14, a first spacer 150 may be formed on a sidewall of the trench 148. The first spacer 150 may include, for example, polysilicon.

[0104] The first spacer 150 may cover the second sacrificial layer 122 and the support layer 108 exposed by the sidewalls of the trench 148. Therefore, the second sacrificial layer 122 and the support layer 108 may not be exposed by the trench 148.

[0105] Reference Fig.15 and Fig.16 , the first sacrificial pattern 104 exposed by the bottom of the trench 148 may be removed. At this time, the oxide or polysilicon other than the first sacrificial pattern 104 may not be removed. Therefore, an initial first gap 156 may be formed at a portion where the first sacrificial pattern 104 is removed. The bottom of the lower insulating layer 106 and a portion of the sidewall of the blocking pattern 130 may be exposed through the initial first gap 156.

[0106] In example embodiments, the first sacrificial pattern 104 may be removed by a wet etching process. In example embodiments, although the initial first gap 156 may be formed by a wet etching process, the structure formed on the support layer 108 may be supported by the support layer 108, the lower insulating layer 106, the channel structure 190, and the dummy channel structure 190a.

[0107] Reference Fig.17 , the barrier pattern 130, the charge storage pattern 132, and the tunnel insulating pattern 134 exposed by the initial first gap 156 may be wet-etched. Thus, the outer wall of the lower portion of the channel 136 may be partially exposed. In addition, in the etching process of the barrier pattern 130 and the tunnel insulating pattern 134, the pad layer 101 formed on the substrate 100 may be removed together. The initial first gap 156 may be transformed into a first gap 156a exposing the substrate 100 through the etching process.

[0108] The wet etching process may be an isotropic etching process. Thus, the portion of the charge storage structure 135 directly exposed by the initial first gap 156 may be etched, and then the charge storage structure 135 may be further etched in the vertical direction. In this case, the charge storage structure 135 on the sidewall of the support layer 108 may not be removed but may be retained. Thus, the channel 136, the charge storage structure 135, and the support layer 108 may be sequentially stacked in the lateral direction. At the same time, a portion of the substrate 100 may be exposed by the first gap 156a formed by partially etching the charge storage structure 135.

[0109] In example embodiments, the charge storage structure 135 formed in the dummy channel hole 126b may be covered by the lower insulating layer 106 and may not be exposed. Therefore, the charge storage structure 135 in the dummy channel hole 126b may not be removed through an etching process.

[0110] Reference Fig.18 A channel connection layer 158 may be formed to fill the first gap 156 a. The channel connection layer 158 may also be formed on the sidewall and bottom of the trench 148 and on the upper surface of the second insulating interlayer 146 .

[0111] The channel connection layer 158 may include polysilicon doped with impurities. The channel connection layer 158 may be doped with N-type impurities such as phosphorus, arsenic, and the like.

[0112] Reference Fig.19 , the channel connection layer 158 may be partially removed to form a channel connection pattern 158 a filling only the first gap 156 a .

[0113] In example embodiments, the channel connection layer 158 formed at the trench 148 and the second insulating interlayer 146 may be etched through an etch-back process to form a channel connection pattern 158 a .

[0114] When the channel connection pattern 158 a is formed, the channel 136 may be electrically connected to the substrate 100 .

[0115] The channel connection pattern 158a may directly contact the lower portion of the channel 136, so that the impurities included in the channel connection pattern 158a may diffuse to the lower portion of the channel 136 during a subsequent process performed under a heated atmosphere. Therefore, the impurities included in the channel connection pattern 158a may diffuse to the channel region of the GIDL transistor, so that the channel region of the GIDL transistor may be doped with the impurities. Therefore, the impurities doped in the lower portion of the channel 136 may be substantially the same as the impurities doped in the channel connection pattern 158a.

[0116] However, impurities may not be doped into the channel regions of the ground selection transistor and the transistor formed above the ground selection transistor. Therefore, impurities included in the channel connection pattern 158a may be controlled so that the impurities do not excessively diffuse upward.

[0117] The width of the polysilicon at the folded portion of the channel 136 may be greater than the width of the polysilicon at other portions, and thus the grain size of the polysilicon at the folded portion may be greater than the grain size of the polysilicon at other portions. Therefore, impurities may be sufficiently doped into the lower portion of the channel 136 corresponding to the folded portion, and the upper portion of the channel 136 may not be doped or may be less doped. Therefore, the GIDL current generated at the GIDL transistor may increase, and thus, the erase voltage of the data stored in the memory cell may be reduced.

[0118] A channel structure 190 may be formed in the channel hole 126a, and a dummy channel structure 190a may be formed in the dummy channel hole 126b. The dummy channel 136a included in the dummy channel structure 190a may be electrically isolated from the substrate 100. Therefore, the dummy channel structure 190a may not operate as an actual memory cell. The dummy channel structure 190a may not be electrically connected to the channel structure 190. Therefore, even if a malfunction or damage of the dummy channel structure 190a occurs, the channel structure 190 will not be affected.

[0119] Reference Fig. 20 , the second sacrificial layer 122 exposed by the trench 148 may be removed to form a second gap 160 between the insulating layers 120. A portion of the outer wall of the barrier pattern 130 may be exposed by the second gap 160. The removal process of the second sacrificial layer 122 may be a wet etching process.

[0120] Reference Fig.21 A second barrier layer (not shown) may be formed along surfaces of the trench 148 and the second gap 160 , and a gate electrode layer may be formed on the second barrier layer to fill the second gap 160 .

[0121] In example embodiments, the gate electrode layer may include a barrier layer (not shown) and a gate conductive layer stacked in sequence. The gate conductive layer may include a metal with low resistance, such as tungsten, titanium, tantalum, and platinum, and the barrier layer may include a metal nitride, such as tungsten nitride, titanium nitride, and tantalum nitride.

[0122] Thereafter, the gate electrode layer may be partially removed. Thus, the gate electrode 170 may be formed in the second gap 160. In example embodiments, the gate electrode layer formed in the trench 148 may be removed. The removal process may be a wet etching process. The gate electrode 170 may extend in the first direction.

[0123] That is, the ground selection transistor, the cell transistor, and the gate electrode 170 of the cell selection transistor may include metal. On the other hand, the support layer 108 as the gate electrode of the GIDL transistor may include polysilicon.

[0124] Reference Fig. 22, a spacer layer may be formed on the sidewalls of the trench 148, and the spacer layer may be anisotropically etched to expose the substrate 100 at the bottom of the trench 148. Thus, a spacer 180 may be formed on the sidewalls of the trench 148. The spacer 180 may include, for example, silicon oxide.

[0125] Thereafter, a conductive layer may be formed on the second insulating interlayer 146 to fill the trench 148. The conductive layer may be planarized until the upper surface of the second insulating interlayer 146 may be exposed to form a common source line 182. The common source line 182 may include, for example, a barrier metal layer and a metal pattern. The barrier metal layer may include a metal nitride, for example, tungsten nitride, titanium nitride, tantalum nitride, etc. In addition, the metal pattern may include a metal having a low resistance, for example, tungsten, titanium, tantalum, platinum, etc.

[0126] Although not shown, an upper insulating interlayer may be formed on the second insulating interlayer 146, the common source line 182, and the spacer 180. Then, a wiring may be formed to be electrically connected to each of the capping pattern 140, the common source line 182, and the gate electrode 170.

[0127] Fig.23 and Fig.24 is a cross-sectional view illustrating a vertical semiconductor device according to example embodiments.

[0128] Fig.24 yes Fig.23 Magnified view of portion "B".

[0129] In addition to the channel connection pattern and the shape of the channel, Fig.23 and Fig.24 The vertical semiconductor device shown in FIG. Figure 1 The vertical semiconductor devices shown are substantially the same, and therefore, detailed descriptions of the same elements may be omitted.

[0130] Reference Fig.23 and Fig.24 , a lower portion of the channel 136 may contact the channel connection pattern 158 a so that the channel 136 may be electrically connected to the substrate 100 .

[0131] A contact portion between the channel 136 and the channel connection pattern 158a may be disposed at a level below the bottom of the support layer 108. That is, the contact portion may correspond to a lower portion of the channel 136.

[0132] A portion of the charge storage structure 135 formed at a contact portion between the channel 136 and the channel connection pattern 158 a may be removed.

[0133] In example embodiments, the width of the channel 136 at the contact portion between the channel 136 and the channel connection pattern 158a may be smaller than the width of the channel 136 at portions above and below the channel connection pattern 158a. That is, the sidewall of the channel 136 may be curved or recessed at the channel portion contacting the channel connection pattern 158a.

[0134] Fig.25 are cross-sectional views illustrating stages of a method of fabricating a vertical semiconductor device according to example embodiments.

[0135] A method of manufacturing a vertical semiconductor device may include the following steps: Figures 6 to 22 The processes shown are substantially the same or similar processes. Therefore, a detailed description of the method may be omitted.

[0136] First, you can perform a reference Figures 6 to 17 Then, refer to Fig.25 , the exposed sidewalls of the channel 136 may be further etched. Therefore, the width of the channel 136 at the etched portion may be relatively reduced. The etching process may include a wet etching process.

[0137] The exposed sidewalls of the trench 136 may be further etched so that surface damage included in the trench 136 may be removed by the etching process.

[0138] Afterwards, you can perform a reference Figures 18 to 22 Therefore, it is possible to manufacture Fig.23 and Fig.24 The semiconductor device shown in FIG.

[0139] Fig.26 and Fig. 27 is a cross-sectional view illustrating a vertical semiconductor device according to example embodiments.

[0140] Fig. 27 yes Fig.26 Magnified view of portion “C” in FIG.

[0141] In addition to the shape of the channel, Fig.26 and Fig. 27 The vertical semiconductor device shown in FIG. Figure 1 The vertical semiconductor devices shown are identical. Therefore, detailed description of identical elements may be omitted.

[0142] Reference Fig.26 and Fig. 27 , the channel 136 may have a tapered cylindrical shape.

[0143] In example embodiments, the bottom and sidewalls of the channel 136 may have substantially the same thickness. That is, the polysilicon layer corresponding to the lower portion of the channel 136 may not be folded. Therefore, the bottom of the inner space of the channel 136 may be disposed at a level below the upper surface of the support layer 108.

[0144] A method of manufacturing a vertical semiconductor device may include the following steps: Figures 6 to 22 The processes shown are substantially the same or similar processes. However, when performing the reference Fig.11 During the process shown, the channel layer may be formed on the tunnel insulating layer in the channel hole 126a and the dummy channel hole 126b to have a uniform thickness. The channel layer may not be folded in the lower portion of each of the channel hole 126a and the dummy channel hole 126b, so that the channel layer may not fill the lower portion of the channel hole 126a and the dummy channel hole 126b.

[0145] Fig.28 is a cross-sectional view illustrating a vertical semiconductor device according to example embodiments.

[0146] The vertical semiconductor device may have a cell-on-periphery (COP) structure in which a peripheral circuit is formed under a memory cell.

[0147] Reference Fig.28 , a circuit pattern as a peripheral circuit may be formed on the lower substrate 200. A lower insulating interlayer 220 may be formed to cover the circuit pattern. In addition, a lower wiring 210 electrically connected to the circuit pattern may be formed.

[0148] The lower substrate 200 may include a field region and an active region, an isolation pattern is formed on the field region, and no isolation pattern is formed on the active region.

[0149] The circuit pattern may include a transistor 202 , a resistor, a capacitor, etc. The transistor 202 may include a gate, a source, and a drain.

[0150] The lower wiring 210 may be formed in the lower insulating interlayer 220. The uppermost surface of the lower insulating interlayer 220 may be flat.

[0151] The base layer 100a may be formed on the lower insulating interlayer 220. The base layer 100a may include, for example, polysilicon. In example embodiments, the base layer 100a may serve as an upper substrate.

[0152] Figures 1 to 3 The structure shown in FIG. 1 may be formed on the base layer 100 a .

[0153] In some example embodiments, Figure 4 , Figure 5 , Fig.23 and Fig.26One of the structures shown in FIG. 1 may be formed on the base layer 100 a .

[0154] The vertical semiconductor device may have a COP structure, so that a horizontal region of a substrate for forming a peripheral circuit may not be required. Therefore, a highly integrated vertical semiconductor device may be manufactured.

[0155] The above is an explanation of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.

Claims

1. A vertical semiconductor device, comprising: A plurality of channel connection patterns contacting the upper surface of the substrate; a lower insulating layer formed on the plurality of channel connection patterns and in spaces between the plurality of channel connection patterns; a support layer formed on the lower insulating layer to be spaced apart from the plurality of channel connection patterns, the support layer comprising polysilicon doped with impurities; a stacked structure formed on the support layer, wherein an insulating layer and a gate electrode are stacked in the stacked structure; and The channel structure passes through the stack structure, the support layer and the lower insulating layer and extends to the upper part of the substrate, the channel structure includes a charge storage structure and a channel, wherein the channel structure is formed in a channel hole that passes through the stacked structure, the support layer and the lower insulating layer and extends to the upper portion of the substrate, wherein the channel has a cylindrical shape, and a lower portion of the channel completely fills a lower portion of the channel hole below an upper surface of the support layer, Wherein, the channel contacts the channel connection pattern, Wherein, the charge storage structure and the channel are arranged to face the gate electrode and the support layer, wherein a lower portion of the channel is arranged to face the support layer and the charge storage structure, and the support layer is configured to serve as a gate of a gate-induced drain leakage transistor, and The channel structure further includes a filling pattern formed on the channel to fill only an upper portion of the channel hole located above the upper surface of the support layer.

2. The vertical semiconductor device according to claim 1, wherein: A gate electrode formed over the support layer includes a metal, and The support layer is the only layer in the vertical semiconductor device that serves as the gate of the gate-induced drain leakage transistor.

3. The vertical semiconductor device according to claim 1, wherein: The channel connection pattern includes polysilicon doped with impurities.

4. The vertical semiconductor device according to claim 1, wherein: A charge storage structure is formed on an upper portion of a sidewall of the channel hole disposed at a higher level than the channel connection pattern, and Wherein, the channel contacts the charge storage structure and the channel connection pattern.

5. The vertical semiconductor device according to claim 1, wherein: The bottom of the inner space of the channel having the cylindrical shape is located at a level between the upper surface of the support layer and the bottom of the lowermost gate electrode among the gate electrodes, and the cylindrical shape is a tapered cylindrical shape.

6. The vertical semiconductor device according to claim 1, wherein: The width of the channel at a level below the upper surface of the support layer is greater than the width of the sidewalls of the channel.

7. The vertical semiconductor device according to claim 1, wherein: The thickness of the bottom of the trench is greater than the width of the sidewalls of the trench.

8. The vertical semiconductor device according to claim 1, wherein: The channel hole has an inclined sidewall such that a width of the channel hole gradually decreases from an upper portion of the channel hole toward a lower portion of the channel hole.

9. The vertical semiconductor device according to claim 1, wherein: A channel at a level below a lowermost gate electrode among the gate electrodes is doped with impurities, and Therein, the channel at the lowest gate electrode or at a level above the lowest gate electrode is not doped with impurities or is less doped with impurities than the channel at a level below the lowest gate electrode.

10. The vertical semiconductor device of claim 1, further comprising: a common source line passing through the stack structure, the support layer and the lower insulating layer, and contacting a portion of the substrate; as well as The spacer includes an insulating material, and the spacer surrounds the sidewall of the common source line.

11. The vertical semiconductor device of claim 10, wherein: The support layer contacts the spacers on the sidewalls of the common source line, and The support layer and the common source line are electrically isolated from each other by a spacer.

12. The vertical semiconductor device of claim 10, wherein: An upper surface of the support layer includes a recess, and the common source line passes through the recess. 13 . The vertical semiconductor device of claim 1 , the charge storage structure comprising a tunnel insulating pattern, a charge storage pattern, and a blocking pattern sequentially stacked from an outer wall of the channel.

14. The vertical semiconductor device of claim 1, further comprising a dummy channel structure passing through the stack structure, the support layer, and the lower insulating layer and extending to an upper portion of the substrate, in, The dummy channel structure includes a charge storage structure and a channel that is not electrically connected to the channel connection pattern.

15. A vertical semiconductor device, comprising: A plurality of channel connection patterns contacting the upper surface of the substrate; a lower insulating layer formed on the plurality of channel connection patterns and in spaces between the plurality of channel connection patterns; a support layer formed on the lower insulating layer to be spaced apart from the plurality of channel connection patterns, the support layer comprising polysilicon doped with impurities; a stacked structure formed on the support layer, wherein an insulating layer and a gate electrode are stacked in the stacked structure; and A channel structure passes through the stack structure, the support layer and the lower insulating layer and extends to the upper portion of the substrate, the channel structure includes a charge storage structure and a channel, the channel contacts the channel connection pattern and has a cylindrical shape, wherein the channel structure is formed in a channel hole that passes through the stacked structure, the support layer and the lower insulating layer and extends to the upper portion of the substrate, wherein the lower portion of the channel completely fills the lower portion of the channel hole below the upper surface of the support layer, Wherein, the charge storage structure and the channel are arranged to face the gate electrode and the support layer, The lower portion of the channel is arranged to face the support layer and the charge storage structure. wherein the width of the channel at a level below the upper surface of the support layer is greater than the width of the sidewall of the channel at a level above the upper surface of the support layer, and The channel structure further includes a filling pattern formed on the channel to fill only an upper portion of the channel hole located above the upper surface of the support layer.

16. The vertical semiconductor device of claim 15, wherein: A gate electrode formed over the support layer includes a metal, and Therein, the support layer is configured to function as a gate-induced drain leakage transistor.

17. The vertical semiconductor device of claim 15, wherein: The bottom of the inner space of the channel having the cylindrical shape is located at a level between the upper surface of the support layer and the bottom of the lowermost gate electrode, and the cylindrical shape is a tapered cylindrical shape.

18. The vertical semiconductor device of claim 15, wherein: A channel at a level below a lowermost gate electrode among the gate electrodes is doped with impurities.

19. The vertical semiconductor device of claim 15, further comprising: a common source line passing through the stack structure, the support layer and the lower insulating layer, and contacting a portion of the substrate; as well as The spacer includes an insulating material, and the spacer surrounds the sidewall of the common source line.

20. A vertical semiconductor device, comprising: A lower gate layer is formed above the substrate, the lower gate layer is spaced apart from the substrate, and the lower gate layer includes polysilicon doped with impurities; a stack structure formed on the lower gate layer, wherein an insulating layer and a gate electrode are stacked in the stack structure to form a memory cell string, and the gate electrode comprises a metal; and A channel structure passes through the stack structure and the lower gate layer and extends to the upper portion of the substrate, the channel structure comprising a charge storage structure and a channel having a cylindrical shape, wherein the channel structure is formed in a channel hole that passes through the stack structure, the lower gate layer and the lower insulating layer and extends to the upper portion of the substrate, wherein the channel has a cylindrical shape, and a lower portion of the channel completely fills a lower portion of the channel hole below an upper surface of the lower gate layer, Wherein, the charge storage structure and the channel are arranged to face the gate electrode and the lower gate layer, Wherein, the lower portion of the channel is arranged to face the lower gate layer and the charge storage structure, wherein a width of the channel at a level below the upper surface of the lower gate layer is greater than a width of a sidewall of the channel at a level above the upper surface of the lower gate layer, and The channel structure further includes a filling pattern formed on the channel to fill only an upper portion of the channel hole located above an upper surface of the lower gate layer. 21 . The vertical semiconductor device of claim 20 , wherein the channel at a level below a lowermost gate electrode among the gate electrodes is selectively doped with impurities.

22. The vertical semiconductor device of claim 20, further comprising: A channel connection pattern is formed on the substrate, the channel connection pattern contacts the upper surface of the substrate and the channel, and the channel connection pattern is spaced apart from the lower gate layer; as well as A lower insulating layer is formed between the channel connection pattern and the lower gate layer.

23. The vertical semiconductor device of claim 20, wherein: The lower gate layer is configured to structurally support the stack structure, and includes a material having an etching selectivity with respect to silicon oxide and silicon nitride.

24. The vertical semiconductor device of claim 20, wherein: The lower gate layer is configured to function as a gate-induced drain leakage transistor, and The thickness of the lower gate layer in the vertical direction is equal to the channel length of the gate-induced drain leakage transistor. 25 . The vertical semiconductor device of claim 20 , the memory cell string comprising a ground selection transistor, a cell transistor, and a cell selection transistor.

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