Organic light emitting diode display device

Abstract

A display device is provided, which may include a first substrate, a pixel, a contact electrode, and a side electrode. The pixel may overlap with the first surface of the first substrate. The contact electrode may be electrically connected to the pixel. The first surface of the contact electrode may overlap with the first surface of the first substrate. The side electrode may be arranged to protrude from the first substrate. The first surface of the side electrode may directly contact the second surface of the contact electrode. The second surface of the contact electrode may not be parallel to the first surface of the contact electrode.

Description

Technical Field

[0001] The technical field relates to an organic light emitting diode display device. Background Art

[0002] Modern display devices include liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices. It is desirable that the display device has a maximum display area and a minimum non-display area.

[0003] The display device may include electrodes for connecting to an external device so as to receive a signal from the external device. In order to accommodate the electrodes, the display device may have an undesirably large non-display area. Summary of the invention

[0004] Some embodiments may relate to a display device, for example, an organic light emitting diode (OLED) display device including a side electrode.

[0005] According to some example embodiments, an OLED display device includes a lower substrate, a plurality of sub-pixel structures, an upper substrate, a pad electrode, and a side electrode. The lower substrate has a display area and a peripheral area surrounding the display area. The sub-pixel structure is disposed in the display area and on the lower substrate. The upper substrate is disposed on the sub-pixel structure. The pad electrode is disposed in the peripheral area between the lower substrate and the upper substrate, and one side surface of the pad electrode is exposed. The side electrode is disposed on one side surface of the upper substrate and the lower substrate, and contacts one side surface of the pad electrode.

[0006] In example embodiments, the side electrode may protrude from one side surface of the lower substrate and the upper substrate in the first direction.

[0007] In example embodiments, a size of the lower substrate may be the same as a size of the upper substrate, and the lower substrate and the upper substrate may overlap each other.

[0008] In example embodiments, the side electrode may include a first metal layer contacting the pad electrode and a second metal layer disposed on the first metal layer.

[0009] In example embodiments, the second metal layer may have a lower resistance than the first metal layer, and the first metal layer may have a greater adhesive force than the second metal layer.

[0010] In example embodiments, the first metal layer may include at least one selected from titanium (Ti), molybdenum (Mo), nickel (Ni), tantalum (Ta), and neodymium (Nd).

[0011] In example embodiments, the second metal layer may include at least one selected from among silver (Ag), copper (Cu), aluminum (Al), and gold (Au).

[0012] In example embodiments, the side electrode may further include a third metal layer disposed on the second metal layer, and a mechanical strength of the third metal layer may be greater than a mechanical strength of each of the first metal layer and the second metal layer.

[0013] In example embodiments, the pad electrode may extend in one direction from the peripheral region into the display region and may be electrically connected to the sub-pixel structure.

[0014] In example embodiments, the pad electrodes may include first to n-th pad electrodes (where n is an integer greater than 2). The first to n-th pad electrodes may be spaced apart from each other and may be arranged along the second direction in the peripheral region.

[0015] In example embodiments, the side electrodes may include first to m-th side electrodes (where m is an integer greater than 2), and the first to m-th side electrodes may make contact with first to n-th pad electrodes, respectively.

[0016] In example embodiments, the OLED display device may further include first to p-th organic patterns (where p is an integer greater than 1). A k-th organic pattern (where k is an integer between 1 and p) among the first to p-th organic patterns may be disposed between an h-th side electrode and an h+1-th side electrode (where h is an integer between 1 and m) among the first to m-th side electrodes.

[0017] In an example embodiment, the OLED display device may further include a plurality of semiconductor elements, each of which may include an active layer disposed on a lower substrate, a gate insulating layer disposed on the active layer, a gate electrode disposed on the gate insulating layer, an insulating interlayer disposed on the gate electrode, and a source electrode and a drain electrode disposed on the insulating interlayer.

[0018] In example embodiments, the pad electrode may include a first pad electrode pattern disposed on the lower substrate and a second pad electrode pattern disposed on the first pad electrode pattern.

[0019] In example embodiments, the first pad electrode pattern and the gate electrode may be simultaneously formed using the same material, and the source and drain electrodes and the second pad electrode pattern may be simultaneously formed using the same material.

[0020] In example embodiments, the gate insulating layer and the insulating interlayer may not be disposed under the pad electrode.

[0021] In example embodiments, the OLED display device may further include a sealing member disposed between the lower substrate and the upper substrate in the peripheral region.

[0022] In example embodiments, the sealing member may cover at least a portion of the pad electrode.

[0023] In example embodiments, one side surface of the sealing member may not be in contact with the side electrode in a portion where the sealing member is in contact with the pad electrode.

[0024] In example embodiments, each sub-pixel structure may include a plurality of lower electrodes disposed on a lower substrate, a plurality of light emitting layers respectively disposed on the lower electrodes, and an upper electrode disposed on the light emitting layers.

[0025] Embodiments may relate to a display device. The display device may include a first substrate, a pixel, a contact electrode, and a side electrode. The pixel may overlap with the first surface of the first substrate. The contact electrode may be electrically connected to the pixel. The first surface of the contact electrode may overlap with the first surface of the first substrate. The side electrode may be arranged to protrude from the first substrate. The first surface of the side electrode may be parallel to the second surface of the contact electrode and directly contact the second surface of the contact electrode. The second surface of the contact electrode may be perpendicular to the first surface of the contact electrode and not parallel to the first surface of the contact electrode. The side electrode may cover the second surface of the contact electrode.

[0026] The first surface of the side electrode may be parallel to the second surface of the first substrate. The second surface of the first substrate may be perpendicular to the first surface of the first substrate and not parallel to the first surface of the first substrate.

[0027] The display device may include a second substrate. The contact electrode may be disposed between a first surface of the first substrate and a first surface of the second substrate. The second surface of the first substrate may be coplanar with a second surface of the second substrate and may be coplanar with a second surface of the contact electrode.

[0028] The side electrode may include the following elements: a first metal layer directly contacting the contact electrode; and a second metal layer disposed on the first metal layer. The first metal layer may be disposed between the contact electrode and the second metal layer.

[0029] The second metal layer may have a lower resistance than the first metal layer. The first metal layer may have a greater adhesive force than the second metal layer.

[0030] The first metal layer may include at least one of titanium (Ti), molybdenum (Mo), nickel (Ni), tantalum, (Ta), and neodymium (Nd).

[0031] The second metal layer may include at least one of silver (Ag), copper (Cu), aluminum (Al), and gold (Au).

[0032] The side electrode may further include a third metal layer disposed on the second metal layer. The second metal layer may be disposed between the first metal layer and the third metal layer. The mechanical strength of the third metal layer may be greater than each of the mechanical strength of the first metal layer and the mechanical strength of the second metal layer.

[0033] The material of the contact electrode may be the same as at least one of a material of a gate electrode of the pixel and a material of a drain electrode of the pixel.

[0034] The display device may include a second substrate. The contact electrode may be disposed between the first surface of the first substrate and the first surface of the second substrate, and may be disposed closer to the first substrate than the second substrate. The first surface of the side electrode may be parallel to the second surface of the second substrate and directly contact the second surface of the second substrate.

[0035] The first surface of the side electrode may be parallel to the second surface of the first substrate and directly contact the second surface of the first substrate.

[0036] The display device may include an organic member directly contacting the second face of the side electrode. The second face of the side electrode may be perpendicular to the first face of the side electrode and not parallel to the first face of the side electrode.

[0037] The pixel may include a transistor. The transistor may include a first transistor electrode and a second transistor electrode. The contact electrode may include a first conductive layer and a second conductive layer. The first conductive layer may be disposed between the first substrate and the second conductive layer. The material of the first conductive layer may be the same as the material of the first transistor electrode. The material of the second conductive layer may be the same as the material of the second transistor electrode.

[0038] The first transistor electrode may be a gate electrode. The second transistor electrode may be a drain electrode.

[0039] The first conductive layer may be parallel to the first substrate and directly contact the first substrate. The gate electrode may be separated from the first substrate.

[0040] The display device may include the following elements: a gate insulating layer disposed between the first transistor electrode and the first substrate; and an insulating interlayer disposed between the first transistor electrode and the second transistor electrode. Both the gate insulating layer and the insulating interlayer may be separated from the contact electrode.

[0041] The display device may include the following elements: a second substrate; and a sealing member disposed between the first substrate and the second substrate, directly contacting the second substrate, and directly contacting the contact electrode.

[0042] The sealing member may partially cover the contact electrode, and may partially expose the contact electrode.

[0043] The sealing member may directly contact the first face of the side electrode.

[0044] The contact electrode may include a first conductive layer and a second conductive layer. The first conductive layer may be disposed between the first substrate and the second conductive layer. The sealing member may be narrower than the first conductive layer and wider than the second conductive layer in a direction parallel to the first surface of the first substrate.

[0045] According to the embodiment, a non-display area of ​​a display device can be minimized. In the embodiment, a display device can be easily electrically connected to an external device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a plan view illustrating an organic light emitting diode (OLED) display device according to example embodiments.

[0047] Figure 2 is a diagram showing electrical connections to Figure 1 Block diagram of external devices of an OLED display device.

[0048] Figure 3 is a diagram showing a method of including Figure 1 A perspective view of a pad electrode in an OLED display device.

[0049] Figure 4 is a perspective view showing an OLED display device according to an example embodiment.

[0050] Figure 5 According to an example embodiment, Figure 1 A cross-sectional view taken along line II′.

[0051] Figure 6 is a diagram showing a method of including Figure 5 A cross-sectional view (or side view) of a side electrode in an OLED display device.

[0052] Figure 7 is a diagram showing a method of including Figure 1 A circuit diagram of OLEDs and transistors in an OLED display device.

[0053] Figure 8 is a side view showing an OLED display device according to example embodiments.

[0054] Fig. 9 is a plan view showing an OLED display device according to example embodiments.

[0055] Fig.10 According to an example embodiment, Fig. 9 A cross-sectional view taken along line II-II′.

[0056] Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19is a diagram illustrating a structure formed in a method of manufacturing an OLED display device according to example embodiments. DETAILED DESCRIPTION

[0057] Example embodiments are described with reference to the accompanying drawings.

[0058] Although the terms "first", "second", etc. can be used here to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, without departing from the teaching of one or more embodiments, the first element can be referred to as the second element. The description of the element being referred to as the "first" element may not require or imply the existence of the second element or other elements. The terms "first", "second", etc. can also be used here to distinguish different classes or groups of elements. For simplicity, the terms "first", "second", etc. can respectively represent "first class (or first group)", "second class (or second group)", etc.

[0059] The term "conductive" may mean "electrically conductive". The term "connected" may mean "electrically connected". The term "insulated" may mean "electrically insulated". The term "pattern" may mean "member". The term "pad electrode" may mean "contact electrode". The term "electrode" may mean "electrode group". The term "sub-pixel structure" may mean "display element". The term "semiconductor element" may mean "transistor". "Pixel" may include a display element and a transistor. The term "contact" may mean "directly mechanically / physically in contact" or "directly mechanically / physically in contact". The description that a first surface directly contacts a second surface may mean that the first surface is parallel to the second surface and directly contacts the second surface. The description that an element may include a series of materials may mean that the element may include at least one of the materials. The description that an element may be formed using a series of materials may mean that the element may be formed using at least one of the materials.

[0060] Figure 1 is a plan view illustrating an organic light emitting diode (OLED) display device according to example embodiments. Figure 2 is used to describe electrical connections to Figure 1 Block diagram of external devices of an OLED display device. Figure 3 It is used to describe the Figure 1 A perspective view of a pad electrode in an OLED display device. Figure 4 is a perspective view showing an OLED display device according to an example embodiment. For example, for ease of description, Figure 3 The OLED display device 100 is shown except for the side electrodes 470 . Figure 5 According to an example embodiment, Figure 1 A cross-sectional view taken along line II′.

[0061] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 , the OLED display device 100 may include a lower substrate 110, a sub-pixel structure 200, an upper substrate 410, a sealing member 390, a pad electrode 430 (or a contact electrode 430), a side electrode 470, etc. The OLED display device 100 and / or the lower substrate 110 may have a display area 10 and a peripheral area 20. The peripheral area 20 may surround the display area 10.

[0062] Sub-pixel structure 200 (eg, Figure 5 The sub-pixel structure 200 shown in FIG. 1 may be disposed in the display region 10. An image may be displayed in the display region 10 through / by the sub-pixel structure 200. Wiring (e.g., gate signal wiring, data signal wiring, gate initialization signal wiring, initialization voltage wiring, light emission signal wiring, power supply wiring, etc.) may be disposed in the peripheral region 20.

[0063] like Figure 1 and Figure 3 As shown in FIG. 1 , a plurality of pad electrodes 430 may be disposed in the peripheral region 20. In example embodiments, the pad electrode 430 may be interposed between the lower substrate 110 and the upper substrate 410, and one side surface of each pad electrode 430 may be exposed by the sealing member 390. Each pad electrode 430 may extend from the peripheral region 20 into the display region 10 and may be electrically connected to one or more of the sub-pixel structures 200. The pad electrode 430 may be connected to at least some of the wirings disposed in the display region 10.

[0064] In example embodiments, since the pad electrode 430 is disposed between the lower substrate 110 and the upper substrate 410, and the coplanar side surfaces of the pad electrode 430 are exposed by the sealing member 390, the face of the lower substrate 110 may be coplanar with the coplanar side surfaces of the pad electrode 430 and may be coplanar with the face of the upper substrate 410, and the size of the lower substrate 110 may be equal to the size of the upper substrate 410. Since the lower substrate 110 does not protrude beyond the upper substrate 410 in a plan view of the OLED display device 100, the non-display area of ​​the OLED display device 100 may be minimized.

[0065] like Figure 1 and Figure 4As shown in , the side electrode 470 may be disposed on one side surface of each of the substrates 110 and 410. Each side electrode 470 may be in direct contact with one side surface of a corresponding one of the pad electrodes 430. The side electrodes 470 may respectively completely cover the coplanar side surfaces of the pad electrodes 430 so that the pad electrodes 430 are not exposed. The side electrode 470 may protrude from / protrude beyond one side of each of the substrates 110 and 410 in the first direction D1. The side of each of the substrates 110 and 410 may be coplanar with the coplanar side surfaces of the pad electrodes 430.

[0066] The pad electrode 430 may include first to n-th pad electrodes (where n is an integer greater than 2), and the first to n-th pad electrodes may be spaced apart from each other and arranged along a second direction D2 perpendicular to the first direction D1. The side electrode 470 may include first to m-th side electrodes (where m is an integer greater than 2), and the first to m-th side electrodes may be in direct contact with the first to n-th pad electrodes, respectively, where m may be equal to n.

[0067] Reference Figure 1 , Figure 2 , Figure 3 and Figure 4 , the side electrode 470 may be electrically connected to the external device 101. For example, the external device 101 may generate a gate signal, a data signal, a gate initialization signal, an initialization voltage, a light emitting signal, a power source, etc. The external device 101 may be electrically connected to the OLED display device 100 through the side electrode 470, the pad electrode 430, wiring, a flexible printed circuit board (FPCB), etc., and may provide the gate signal, the data signal, the gate initialization signal, the initialization voltage, the light emitting signal, the power source, etc. to the OLED display device 100. For example, a first portion of the FPCB may be in direct contact with the side electrode 470, and a second portion of the FPCB opposite to the first portion may be in direct contact with the external device 101. A driving integrated circuit may be mounted in the FPCB.

[0068] like Figure 3 , Figure 4 and Figure 5 As shown in , the sealing member 390 may be disposed in the peripheral region 20 between the lower substrate 110 and the upper substrate 410. The sealing member 390 may be disposed along the peripheral region 20, and may have a substantially hollow rectangular shape in a plan view of the OLED display device 100. In example embodiments, the sealing member 390 may cover at least a portion of each pad electrode 430 in the peripheral region 20. One side surface of the sealing member 390 may be in direct contact with the side electrode 470, and may be coplanar with a coplanar side surface of the pad electrode 430.

[0069] In a conventional OLED display device, a pad electrode is disposed in a pad region on a lower substrate, and the lower substrate is longer than an upper substrate so that the pad electrode is in direct contact with the FPCB. The lower substrate protrudes beyond the upper substrate, and the pad electrode is disposed in a protruding portion of the lower substrate. Due to the pad region of the lower substrate, a conventional OLED display device has a relatively large non-display area (e.g., a peripheral area).

[0070] The OLED display device 100 according to example embodiments does not need to protrude beyond the pad area of ​​the upper substrate 410. Advantageously, the non-display area of ​​the OLED display device 100 may be minimized.

[0071] In example embodiments, the pad electrode 430 and the side electrode 470 are disposed only in the first portion of the peripheral region 20. In embodiments, the pad electrode 430 and the side electrode 470 may be disposed in the second portion, the third portion, and / or the fourth portion of the peripheral region 20. The second portion may be opposite to the first portion, and the third portion and the fourth portion may be located between the first portion and the second portion.

[0072] In an example embodiment, Figure 1 Each of the display area 10 and the peripheral area 20 shown in FIG. 1 has a quadrilateral shape. In an embodiment, each of the display area 10 and the peripheral area 20 may have one or more of a triangular shape, a diamond shape, a polygonal shape, a circular shape, a motion track shape, an elliptical shape, etc.

[0073] Figure 6 It is shown that the Figure 5 A cross-sectional view (or side view) of a side electrode in an OLED display device.

[0074] Reference Figure 5 and Figure 6 , the OLED display device 100 may include a lower substrate 110, a semiconductor element 250 (or a transistor 250), a pad electrode 430, a planarization layer 270, a sub-pixel structure 200, a pixel defining layer 310, a sealing member 390, an upper substrate 410, a side electrode 470, etc. The semiconductor element 250 may include an active layer 130, a gate insulating layer 150, a gate electrode 170, an insulating interlayer 190, a source electrode 210, and a drain electrode 230, and the sub-pixel structure 200 may include a lower electrode 290, a light emitting layer 330, and an upper electrode 340. The pad electrode 430 may include a first pad electrode pattern 431 and a second pad electrode pattern 432, and the side electrode 470 may include a first metal layer 471, a second metal layer 472, and a third metal layer 473.

[0075] The lower substrate 110 may include a display region 10 and a peripheral region 20. For example, a portion of an image may be displayed in the display region 10 through / by the subpixel structure 200 and the semiconductor element 250, and the lower substrate 110 and the upper substrate 410 may be sealed in the peripheral region 20 through / by the sealing member 390.

[0076] The lower substrate 110 including a transparent or opaque insulating material may be provided. The lower substrate 110 may include or may be at least one of a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, and the like.

[0077] The lower substrate 110 may include / be a flexible transparent substrate, such as a flexible transparent resin substrate (e.g., a polyimide substrate). The polyimide substrate may include a first polyimide layer, a barrier film layer, a second polyimide layer, etc. For example, the lower substrate 110 may have a structure in which the first polyimide layer, the barrier film layer, and the second polyimide layer are sequentially stacked on a rigid glass substrate. In the method for manufacturing the OLED display device 100, after an insulating layer (e.g., a buffer layer) is disposed on the second polyimide layer of the polyimide substrate, an upper structure (e.g., a semiconductor element 250, a sub-pixel structure 200, etc.) may be formed on the insulating layer. After the upper structure is formed on the insulating layer, the rigid glass substrate on which the polyimide substrate is formed may be removed. Because the polyimide substrate is relatively thin and soft, it is difficult to directly form the upper structure on the polyimide substrate. The upper structure is formed on the polyimide substrate and the rigid glass substrate, and then the polyimide substrate can be used as the lower substrate 110 after removing the rigid glass substrate.

[0078] A buffer layer (not shown) may be disposed on the entire lower substrate 110. The buffer layer may prevent metal atoms and / or impurities from diffusing from the lower substrate 110 into the semiconductor element 250 and the sub-pixel structure 200. In addition, the buffer layer may control the rate of heat transfer in the crystallization process for forming the active layer 130, thereby obtaining a substantially uniform active layer 130. In addition, the buffer layer may improve the surface flatness of the lower substrate 110 when the surface of the lower substrate 110 is relatively irregular. Depending on the type of the lower substrate 110, at least two buffer layers may be disposed on the lower substrate 110, or no buffer layer may be disposed. For example, the buffer layer may include an organic material or an inorganic material.

[0079] The active layer 130 may be disposed in the display region 10 on the lower substrate 110. The active layer 130 may include a metal oxide semiconductor, an inorganic semiconductor (eg, amorphous silicon, polycrystalline silicon, etc.), an organic semiconductor, or the like.

[0080] The gate insulating layer 150 may be disposed on the active layer 130. The gate insulating layer 150 may cover the active layer 130 in the display area 10 on the lower substrate 110, and may be disposed in the entire display area 10 on the lower substrate 110. In example embodiments, the gate insulating layer 150 may not be disposed in the peripheral area 20 on the lower substrate 110. In some example embodiments, the gate insulating layer 150 may be disposed in the entire display area 10 and the peripheral area 20 on the lower substrate 110. The gate insulating layer 150 may fully cover the active layer 130 on the lower substrate 110, and may have a substantially flat upper surface without steps around the active layer 130. Alternatively, the gate insulating layer 150 may cover the active layer 130 on the lower substrate 110, and may be disposed to a substantially uniform thickness along the contour of the active layer 130. The gate insulating layer 150 may include a silicon compound, a metal oxide. For example, the gate insulating layer 150 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ), Silicon Carbonitride (SiC x N y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), tantalum oxide (TaO x ), hafnium oxide (HfO x )、ZrO x ), titanium oxide (TiO x ) etc.

[0081] The gate electrode 170 may be disposed on a portion of the gate insulating layer 150 under which the active layer 130 is positioned. The gate electrode 170 may include at least one of a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in appropriate combinations. In some example embodiments, the gate electrode 170 may have a multilayer structure including a plurality of layers.

[0082] The first pad electrode pattern 431 may be disposed in the peripheral region 20 on the lower substrate 110. A first portion (e.g., one side surface) of the first pad electrode pattern 431 may be aligned / coplanar with the outermost surface of the OLED display device 100, and a second portion of the first pad electrode pattern 431 opposite to the first portion may extend from the peripheral region 20 into the display region 10. For example, the second portion of the first pad electrode pattern 431 may be connected to one of a gate signal wiring, a data signal wiring, a power wiring, a gate initialization signal wiring, an initialization voltage wiring, and a light emitting signal wiring. One of a gate signal, a data signal, a power supply, a gate initialization signal, an initialization voltage, and a light emitting signal generated by an external device 101 may be provided to the sub-pixel structure 200 through the FPCB, the side electrode 470, the second pad electrode pattern 432, and the first pad electrode pattern 431. The first pad electrode pattern 431 may include at least one of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. For example, the first pad electrode pattern 431 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum alloy, aluminum nitride (AlN x ), silver alloy, tungsten nitride (WN x ), copper alloy, molybdenum alloy, titanium nitride (TiN x ), chromium nitride (CrN x ), Tantalum Nitride (TaN x ), strontium ruthenium oxide (SRO), zinc oxide (ZnO x )、Indium Tin Oxide (ITO), Tin Oxide (SnO x ), indium oxide (InO x ), gallium oxide (GaO x ), indium zinc oxide (IZO), etc. These may be used alone or in appropriate combination. The first pad electrode pattern 431 may have a multi-layer structure including a plurality of layers.

[0083] The insulating interlayer 190 may be disposed on the gate electrode 170. The insulating interlayer 190 may cover the gate electrode 170 in the display region 10 on the gate insulating layer 150, and may be disposed on the entire gate insulating layer 150. In example embodiments, the insulating interlayer 190 may not be disposed in the peripheral region 20 on the lower substrate 110. In some example embodiments, the gate insulating layer 150 may be disposed in the entire display region 10 and the peripheral region 20 on the lower substrate 110, except for a portion where the first pad electrode pattern 431 contacts the second pad electrode pattern 432. The insulating interlayer 190 may fully cover the gate electrode 170 on the gate insulating layer 150, and may have a substantially flat upper surface without a step around the gate electrode 170. The insulating interlayer 190 may cover the gate electrode 170 on the gate insulating layer 150, and may be disposed to a substantially uniform thickness along the contour of the gate electrode 170. The insulating interlayer 190 may include a silicon compound, a metal oxide, or the like.

[0084] The source electrode 210 and the drain electrode 230 may be disposed in the display region 10 on the insulating interlayer 190. The source electrode 210 may be connected to (or directly contact) the source region of the active layer 130 via a contact hole formed by removing the first portion of the gate insulating layer 150 and the insulating interlayer 190. The drain electrode 230 may be connected to the drain region of the active layer 130 via a contact hole formed by removing the second portion of the gate insulating layer 150 and the insulating interlayer 190. Each of the source electrode 210 and the drain electrode 230 may include at least one of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in an appropriate combination. Each of the source electrode 210 and the drain electrode 230 may have a multilayer structure including a plurality of layers. The semiconductor element 250 may include an active layer 130, a gate insulating layer 150, a gate electrode 170, an insulating interlayer 190, a source electrode 210, and a drain electrode 230.

[0085] In example embodiments, the OLED display device 100 includes one transistor (eg, semiconductor element 250). In embodiments, the OLED display device 100 may include at least two semiconductor elements and at least one capacitor.

[0086] The semiconductor element 250 may have a top gate structure. The semiconductor element 250 may have a bottom gate structure and / or a double gate structure.

[0087] The second pad electrode pattern 432 may be disposed in the peripheral region 20 on the first pad electrode pattern 431. A first portion (e.g., one side surface) of the second pad electrode pattern 432 may be aligned / coplanar with the outermost surface of the OLED display device 100, and a second portion of the second pad electrode pattern 432 opposite to the first portion may be disposed within the sealing member 390. Optionally, the second portion of the second pad electrode pattern 432 may extend from the peripheral region 20 into the display region 10. The second pad electrode pattern 432 may include at least one of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in an appropriate combination. In an example embodiment, the second pad electrode pattern 432, the source electrode 210, and the drain electrode 230 may be formed simultaneously using the same material. The second pad electrode pattern 432 may have a multilayer structure including a plurality of layers. The pad electrode 430 may include a first pad electrode pattern 431 and a second pad electrode pattern 432. One side surface of the first pad electrode pattern 431 and one side surface of the second pad electrode pattern 432 may be defined as one side surface of the pad electrode 430.

[0088] The planarization layer 270 may be provided in the display region 10 on the insulating interlayer 190, the source electrode 210, and the drain electrode 230. For example, the planarization layer 270 may be provided with a high thickness to fully cover the source electrode 210 and the drain electrode 230 on the insulating interlayer 190. The planarization layer 270 may have a substantially flat upper surface, and a planarization process may be further performed on the planarization layer 270 to achieve a flat upper surface of the planarization layer 270. A portion of the upper surface of the drain electrode 230 may be exposed via a contact hole formed by removing a portion of the planarization layer 270. The planarization layer 270 may include an organic material or an inorganic material. In example embodiments, the planarization layer 270 may include one or more organic materials such as polyimide, epoxy resin, acryl resin, polyester, photoresist, polyacryl resin, polyimide resin, polyamide resin, siloxane resin, etc.

[0089] The lower electrode 290 may be disposed in the display region 10 on the planarization layer 270. The lower electrode 290 may directly contact the drain electrode 230 via the contact hole of the planarization layer 270, and may be electrically connected to the semiconductor element 250. The lower electrode 290 may include at least one of a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in an appropriate combination. The lower electrode 290 may have a multilayer structure including a plurality of layers.

[0090] The pixel defining layer 310 may be disposed on a portion of the lower electrode 290 and a portion of the planarization layer 270 in the display region 10. The pixel defining layer 310 may cover both side portions of the lower electrode 290 and may expose a portion of the upper surface of the lower electrode 290. The pixel defining layer 310 may include an organic material or an inorganic material. In example embodiments, the pixel defining layer 310 may include an organic material.

[0091] The light emitting layer 330 may be disposed in the display region 10 on the lower electrode 290 exposed by the pixel defining layer 310. The light emitting layer 330 may be formed using at least one of the light emitting materials capable of producing light of different colors (e.g., red light, blue light, green light, etc.) according to the sub-pixel structure 200. In an embodiment, the light emitting layer 330 may generally produce white light by stacking a plurality of light emitting materials capable of producing light of different colors such as red light, green light, blue light, etc. A color filter may be disposed on the light emitting layer 330 (e.g., to overlap with the light emitting layer 330 in the lower surface or upper surface of the upper substrate 410). The color filter may include at least one selected from a red color filter, a green color filter, and a blue color filter. Optionally, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include at least one of a photosensitive resin, a color photoresist, and the like.

[0092] The upper electrode 340 may be disposed in the display region 10 on the pixel defining layer 310 and the light emitting layer 330. The upper electrode 340 may include at least one of a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in a suitable combination. The upper electrode 340 may have a multilayer structure including a plurality of layers. The sub-pixel structure 200 may include a lower electrode 290, a light emitting layer 330, and an upper electrode 340.

[0093] The sealing member 390 may be disposed in the peripheral region 20 on the pad electrode 430. The sealing member 390 may be disposed in the peripheral region 20 between the lower substrate 110 and the upper substrate 410. The upper surface of the sealing member 390 may be in direct contact with the lower surface of the upper substrate 410, and the lower surface of the sealing member 390 may be in contact with a portion of the first pad electrode pattern 431 and the second pad electrode pattern 432. In an example embodiment, a first portion (e.g., one side surface) of the sealing member 390 may be aligned / coplanar with the outermost surface of the OLED display device 100, and a second portion of the sealing member 390 opposite to the first portion may be disposed within the OLED display device 100. The sealing member 390 may include glass frit or the like. The sealing member 390 may additionally include a photocurable material. For example, the sealing member 390 may include a compound such as an organic material and a photocurable material. After one or more of ultraviolet rays, laser beams, visible light, etc. are irradiated into the compound, the compound may be cured, and thus the sealing member 390 may be obtained. The photocurable material included in the sealing member 390 may include at least one of epoxy acrylate-based resin, polyester acrylate-based resin, polyurethane acrylate-based resin, polybutadiene acrylate-based resin, silicon acrylate-based resin, alkyl acrylate-based resin, and the like.

[0094] For example, the laser may be irradiated into a compound such as an organic material and a photocurable material. In response to the irradiation of the laser light, the state of the compound (e.g., the sealing member 390) may change from a solid state to a liquid state. The liquid compound may be cured to a solid state after a predetermined time. After the state of the compound changes, the compound may seal the lower substrate 110 and the upper substrate 410.

[0095] In example embodiments, the sealing member 390 has a quadrilateral shape with a width of the upper surface smaller than that of the lower surface. For example, the sealing member 390 may have at least one of a trapezoidal shape, a square shape, a quadrilateral shape with a width of the upper surface larger than that of the lower surface, and the like.

[0096] The upper substrate 410 may be disposed on the sealing member 390 and the upper electrode 340. The upper substrate 410 and the lower substrate 110 may include substantially the same material. For example, the upper substrate 410 may include / be at least one of a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, and the like. In some example embodiments, the upper substrate 410 may include a transparent inorganic material or a flexible plastic. For example, the upper substrate 410 may include / be a flexible transparent resin substrate. In order to increase the flexibility of the OLED display device 100, the upper substrate 410 may have a stacking structure in which at least one inorganic layer and at least one organic layer are alternately stacked. The stacking structure may include a first inorganic layer, an organic layer, and a second inorganic layer. For example, a first inorganic layer having flexibility may be disposed along the contour of the upper electrode 340, and an organic layer having flexibility may be disposed on the first inorganic layer. A second inorganic layer having flexibility may be disposed on the organic layer. That is, the stacking structure may correspond to a thin film encapsulation structure that directly contacts the upper electrode 340.

[0097] The side electrode 470 may be disposed in the outermost surface of the OLED display device 100. For example, one side surface of the lower substrate 110, one side surface of the upper substrate 410, one side surface of the pad electrode 430, and one side surface of the sealing member 390 may directly contact the face of the side electrode 470. The side electrode 470 may be directly and electrically connected to the pad electrode 430. The side electrode 470 may protrude beyond / from one or more of the lower substrate 110, the pad electrode 430, the sealing member 390, and the upper substrate 410 in the first direction D1.

[0098] like Figure 6 As shown in , the side electrode 470 may have a first surface S1 and a second surface S2 opposite to the first surface S1, and may include a first metal layer 471, a second metal layer 472, and a third metal layer 473. The first surface S1 may contact the pad electrode 430, and the second surface S2 may directly contact the FPCB. In an embodiment, the side electrode 470 may include the first metal layer 471 and the second metal layer 472 without including the third metal layer 473.

[0099] The first metal layer 471 may contact the pad electrode 430 and may include a metal having a relatively high metal adhesion. For example, the first metal layer 471 may be mainly composed of at least one of Ti, Mo, Ni, Ta, Nd, and the like.

[0100] The second metal layer 472 may be disposed on the first metal layer 471 and may include a metal having a relatively low resistance. For example, the second metal layer 472 may be mainly composed of at least one of Au, Ag, Cu, Al, and the like.

[0101] The third metal layer 473 may be disposed on the second metal layer 472 and may include a metal having a relatively high mechanical strength. The third metal layer 473 may protect the second metal layer 472. For example, the third metal layer 473 may be mainly composed of at least one of Ti, Mo, titanium alloy, molybdenum alloy, etc., and may have a metal having a Mohs hardness of 5 or more. In the process for manufacturing the OLED display device 100, the space between the pad electrodes 430 may be relatively small, and the area of ​​one side surface of the pad electrode 430 (e.g., the surface where the pad electrode 430 contacts the side electrode 470) may be relatively small. The first metal layer 471 having a relatively high metal adhesion may be in direct contact with one side surface of the corresponding pad electrode 430. In order to reduce the resistance of the side electrode 470, the second metal layer 472 having a relatively low resistance may be disposed on the first metal layer 471. In order to protect the second metal layer 472 from external impact, the third metal layer 473 having a relatively high mechanical strength may be disposed on the second metal layer 472.

[0102] Since the OLED display device 100 includes the side electrode 470 , the FPCB may be easily electrically connected to the pad electrode 430 .

[0103] Figure 7 It is shown that the Figure 1 OLED and transistor circuit diagram in the OLED display device 100. For example, the OLED display device 100 may include a plurality of PIXELs, and each PIXEL may be Figure 7 The circuit diagram shown in FIG.

[0104] Reference Figure 7 , the OLED display device 100 may include an OLED (eg, Figure 5 corresponding to the sub-pixel structure 200), a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6 and a seventh transistor TR7, a storage capacitor CST, a gate signal GW wiring, a data signal DATA wiring, a high power ELVDD wiring, a low power ELVSS wiring, a gate initialization signal GI wiring, an initialization voltage VINT wiring, a light-emitting signal EM wiring and a diode initialization signal GB wiring, etc.

[0105] The OLED may emit light based on the driving current ID. The OLED may include a first terminal and a second terminal. In an example embodiment, the second terminal of the OLED receives a low power source ELVSS. The low power source ELVSS may be generated from an external device 101 and may be provided to at least one side electrode 470 (refer to FIG. 1 ) among the plurality of side electrodes 470 through the FPCB. Figure 2 , Figure 4 and Figure 6 ). That is, the low power ELVSS may be provided to the low power ELVSS wiring through the pad electrode 430 contacting the side electrode 470, and the low power ELVSS applied to the low power ELVSS wiring may be provided to the second terminal of the OLED. For example, the first terminal of the OLED is an anode terminal, and the second terminal of the OLED is a cathode terminal. Alternatively, the first terminal of the OLED may be a cathode terminal, and the second terminal of the OLED may be an anode terminal. In an example embodiment, the anode terminal of the OLED may be connected to the Figure 5 The cathode terminal of the OLED may correspond to the lower electrode 290. Figure 5 Corresponding to the upper electrode 340.

[0106] The first transistor TR1 may include a gate terminal, a first terminal, and a second terminal. In an example embodiment, the first terminal of the first transistor TR1 is a source terminal, and the second terminal of the first transistor TR1 is a drain terminal. Alternatively, the first terminal of the first transistor TR1 may be a drain terminal, and the second terminal of the first transistor TR1 may be a source terminal.

[0107] The driving current ID may be generated by the first transistor TR1. In an example embodiment, the first transistor TR1 operates in a saturation region. The first transistor TR1 may generate the driving current ID based on a voltage difference between a gate terminal and a source terminal, and the grayscale may be implemented based on the amount of the driving current ID generated by the first transistor TR1. Alternatively, the first transistor TR1 operates in a linear region. In this case, the grayscale may be implemented based on the amount of time during which the first transistor TR1 provides the driving current ID to the OLED within a frame.

[0108] The second transistor TR2 may include a gate terminal, a first terminal, and a second terminal. The gate signal GW may be applied to the gate terminal of the second transistor TR2. The first terminal of the second transistor TR2 may receive the data signal DATA. The data signal DATA may be generated from the external device 101 and may be transmitted through the FPCB (see the combination Figure 2 , Figure 4 and Figure 6The data signal DATA may be provided to the data signal DATA wiring through the pad electrode 430 in contact with the side electrode 470, and the data signal DATA applied to the data signal DATA wiring may be provided to the second transistor TR2. The second terminal of the second transistor TR2 may be connected to the first terminal of the first transistor TR1. In an example embodiment, the first terminal of the second transistor TR2 is a source terminal, and the second terminal of the second transistor TR2 is a drain terminal. Alternatively, the first terminal of the second transistor TR2 may be a drain terminal, and the second terminal of the second transistor TR2 may be a source terminal.

[0109] The second transistor TR2 may provide the data signal DATA to the first terminal of the first transistor TR1 when the gate signal GW is activated. The second transistor TR2 operates in a linear region.

[0110] The third transistor TR3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the third transistor TR3 may receive a gate signal GW. The first terminal of the third transistor TR3 may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 may be connected to the second terminal of the first transistor TR1. For example, the gate signal GW may be generated from the external device 101 (or a gate driver), and the gate signal GW may be provided to at least one side electrode 470 (refer to FIG. 1 ) among the plurality of side electrodes 470 through the FPCB. Figure 2 , Figure 4 and Figure 6 ). The gate signal GW may be provided to the gate signal GW wiring through the pad electrode 430 in contact with the side electrode 470, and the gate signal GW applied to the gate signal GW wiring may be provided to the gate terminal of the third transistor TR3. In example embodiments, the first terminal of the third transistor TR3 is a source terminal, and the second terminal of the third transistor TR3 is a drain terminal. Alternatively, the first terminal of the third transistor TR3 may be a drain terminal, and the second terminal of the third transistor TR3 may be a source terminal.

[0111] The third transistor TR3 may connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1 when the gate signal GW is activated. The third transistor TR3 may operate in the linear region. The third transistor TR3 may form a diode connection of the first transistor TR1 when the gate signal GW is activated. The voltage difference between the first terminal of the first transistor TR1 and the gate terminal of the first transistor TR1 corresponding to the threshold voltage of the first transistor TR1 may occur due to the diode connection of the first transistor TR1. As a result, the sum voltage of the data signal DATA provided to the first terminal of the first transistor TR1 and the voltage difference (i.e., the threshold voltage) may be applied to the gate terminal of the first transistor TR1 when the gate signal GW is activated. The data signal DATA may be compensated as much as the threshold voltage of the first transistor TR1. The compensated data signal DATA may be applied to the gate terminal of the first transistor TR1. Because the influence of the threshold voltage of the first transistor TR1 is reduced, the uniformity of the drive current ID may be improved.

[0112] An input terminal of the initialization voltage VINT wiring to which the initialization voltage VINT is applied is connected to the first terminal of the fourth transistor TR4 and the first terminal of the seventh transistor TR7, and an output terminal of the initialization voltage VINT wiring is connected to the second terminal of the fourth transistor TR4 and the first terminal of the storage capacitor CST. For example, the initialization voltage VINT may be generated from the external device 101, and the initialization voltage VINT may be provided to at least one side electrode 470 among the plurality of side electrodes 470 through the FPCB (refer to Figure 2 , Figure 4 and Figure 6 The initialization voltage VINT may be supplied to the initialization voltage VINT wiring through the pad electrode 430 contacting the side electrode 470 , and the initialization voltage VINT applied to the initialization voltage VINT wiring may be supplied to the first terminal of the fourth transistor TR4 and the first terminal of the seventh transistor TR7 .

[0113] The fourth transistor TR4 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fourth transistor TR4 may receive a gate initialization signal GI. For example, the gate initialization signal GI may be generated from the external device 101, and the gate initialization signal GI may be provided to at least one side electrode 470 among the plurality of side electrodes 470 through the FPCB (refer to Figure 2 , Figure 4 and Figure 6). The gate initialization signal GI may be provided to the gate initialization signal GI wiring through the pad electrode 430 in contact with the side electrode 470, and the gate initialization signal GI applied to the gate initialization signal GI wiring may be provided to the gate terminal of the fourth transistor TR4. In addition, the initialization voltage VINT may be applied to the first terminal of the fourth transistor TR4. The second terminal of the fourth transistor TR4 may be connected to the gate terminal of the first transistor TR1. In an example embodiment, the first terminal of the fourth transistor TR4 is a source terminal, and the second terminal of the fourth transistor TR4 is a drain terminal. Alternatively, the first terminal of the fourth transistor TR4 may be a drain terminal, and the second terminal of the fourth transistor TR4 may be a source terminal.

[0114] The fourth transistor TR4 may apply an initialization voltage VINT to the gate terminal of the first transistor TR1 when the gate initialization signal GI is activated. The fourth transistor TR4 may operate in a linear region. The fourth transistor TR4 may initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT when the gate initialization signal GI is activated. In an example embodiment, the voltage level of the initialization voltage VINT is sufficiently lower than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame. The initialization voltage VINT may be applied to the gate terminal of the first transistor TR1 as a P-channel metal oxide semiconductor (PMOS) type transistor. In some example embodiments, the voltage level of the initialization voltage VINT is sufficiently higher than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame. The initialization voltage VINT may be applied to the gate terminal of the first transistor TR1 as an N-channel metal oxide semiconductor (NMOS) type transistor.

[0115] In an example embodiment, the gate initialization signal GI is the same as the gate signal GW advanced by one horizontal period. For example, the gate initialization signal GI applied to the PIXEL located in the nth row (where n is an integer of 2 or greater) among the plurality of PIXELs included in the OLED display device 100 may be substantially the same as the gate signal GW applied to the PIXEL located in the n-1th row among the plurality of PIXELs. By applying the activated gate signal GW to the PIXEL located in the n-1th row among the PIXELs, the activated gate initialization signal GI may be applied to the PIXEL located in the nth row among the PIXELs. As a result, when the data signal DATA is applied to the PIXEL located in the n-1th row among the PIXELs, the gate terminal of the first transistor TR1 included in the PIXEL located in the nth row among the PIXELs may be initialized to the initialization voltage VINT.

[0116] The fifth transistor TR5 may include a gate terminal, a first terminal, and a second terminal. The light emitting signal EM may be applied to the gate terminal of the fifth transistor TR5. The high power source ELVDD may be applied to the first terminal of the fifth transistor TR5. The second terminal of the fifth transistor TR5 may be connected to the first terminal of the first transistor TR1.

[0117] The fifth transistor TR5 may apply the high power ELVDD to the first terminal of the first transistor TR1 when the light emitting signal EM is activated. On the other hand, the fifth transistor TR5 does not apply the high power ELVDD when the light emitting signal EM is not activated. The fifth transistor TR5 may operate in a linear region. The fifth transistor TR5 may apply the high power ELVDD to the first terminal of the first transistor TR1 when the light emitting signal EM is activated, so that the first transistor TR1 generates a driving current ID. In addition, the fifth transistor TR5 does not apply the high power ELVDD when the light emitting signal EM is not activated, so that the data signal DATA applied to the first terminal of the first transistor TR1 is applied to the gate terminal of the first transistor TR1. The high power ELVDD may be generated from the external device 101, and the gate signal GW may be provided to at least one side electrode 470 (refer to FIG. 4 ) among the plurality of side electrodes 470 through the FPCB. Figure 2 , Figure 4 and Figure 6 ). The high power ELVDD may be supplied to the high power ELVDD wiring through the pad electrode 430 in contact with the side electrode 470, and the high power ELVDD applied to the high power ELVDD wiring may be supplied to the first terminal of the fifth transistor TR5. In an example embodiment, the first terminal of the fifth transistor TR5 is a source terminal, and the second terminal of the fifth transistor TR5 is a drain terminal. Optionally,

[0118] A first terminal of the fifth transistor TR5 may be a drain terminal, and a second terminal of the fifth transistor TR5 may be a source terminal.

[0119] The sixth transistor TR6 (eg, Figure 5 The semiconductor element 250 of the embodiment may include a gate terminal, a first terminal, and a second terminal. The light emitting signal EM may be applied to the gate terminal of the sixth transistor TR6. The first terminal of the sixth transistor TR6 may be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6 may be connected to the first terminal of the OLED. The light emitting signal EM may be generated from the external device 101 (or the gate driver), and the light emitting signal EM may be provided to at least one side electrode 470 (refer to the side electrode 470) among the plurality of side electrodes 470 through the FPCB. Figure 2 , Figure 4 and Figure 6). The light emitting signal EM may be provided to the light emitting signal EM wiring through the pad electrode 430 contacting the side electrode 470, and the light emitting signal EM applied to the light emitting signal EM wiring may be provided to the gate terminal of the fifth transistor TR5 and the gate terminal of the sixth transistor TR6. In example embodiments, the first terminal of the sixth transistor TR6 is a source terminal, and the second terminal of the sixth transistor TR6 is a drain terminal. In some example embodiments, the first terminal of the sixth transistor TR6 may be a drain terminal, and the second terminal of the sixth transistor TR6 may be a source terminal.

[0120] The sixth transistor TR6 may provide the driving current ID generated by the first transistor TR1 to the OLED when the light emitting signal EM is activated. The sixth transistor TR6 may operate in a linear region. The sixth transistor TR6 may provide the driving current ID generated by the first transistor TR1 to the OLED when the light emitting signal EM is activated, so that the OLED emits light. In addition, the sixth transistor TR6 may electrically disconnect the first transistor TR1 from the OLED when the light emitting signal EM is not activated, so that the compensated data signal DATA applied to the second terminal of the first transistor TR1 is applied to the gate terminal of the first transistor TR1.

[0121] The seventh transistor TR7 may include a gate terminal, a first terminal, and a second terminal. A diode initialization signal GB may be applied to the gate terminal of the seventh transistor TR7. An initialization voltage VINT may be applied to the first terminal of the seventh transistor TR7. The second terminal of the seventh transistor TR7 may be connected to the first terminal of the OLED. In an example embodiment, the first terminal of the seventh transistor TR7 is a source terminal, and the second terminal of the seventh transistor TR7 is a drain terminal. Alternatively, the first terminal of the seventh transistor TR7 may be a drain terminal, and the second terminal of the seventh transistor TR7 may be a source terminal.

[0122] The seventh transistor TR7 may apply the initialization voltage VINT to the first terminal of the OLED when the diode initialization signal GB is activated. The seventh transistor TR7 may operate in a linear region. The seventh transistor TR7 may initialize the first terminal of the OLED to the initialization voltage VINT when the diode initialization signal GB is activated.

[0123] Optionally, the gate initialization signal GI and the diode initialization signal GB are substantially the same signal. The initialization operation of the gate terminal of the first transistor TR1 may not affect the initialization operation of the first terminal of the OLED. The initialization operation of the gate terminal of the first transistor TR1 and the initialization operation of the first terminal of the OLED may be independent of each other. Therefore, the gate initialization signal GI is used as the diode initialization signal GB, thereby improving production efficiency.

[0124] The storage capacitor CST may include a first terminal and a second terminal, and may be connected between the high power ELVDD wiring and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the high power ELVDD wiring. The storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1 when the gate signal GW is not activated. The light emitting signal EM may be activated when the gate signal GW is not activated (for example, the portion where the gate signal GW is not activated may include the portion where the light emitting signal EM is activated). The driving current ID generated by the first transistor TR1 may be provided to the OLED when the light emitting signal EM is activated. Therefore, the driving current ID generated by the first transistor TR1 may be provided to the OLED based on the voltage level maintained by the storage capacitor CST.

[0125] Figure 8 4 is a side view showing an OLED display device according to an example embodiment. In addition to the organic pattern 490 (or organic member 490), Figure 8 The OLED display device 500 shown in FIG. Figures 1 to 7 The configuration of the OLED display device 100 described above is substantially the same or similar to that of the OLED display device 100. Figure 8 In the example above, you can avoid repeating the reference Figures 1 to 7 A detailed description of elements that are described are substantially the same or similar.

[0126] Reference Figures 1 to 7 as well as Figure 8 The OLED display device 500 may include a lower substrate 110, a semiconductor element 250, a pad electrode 430, a planarization layer 270, a sub-pixel structure 200, a pixel defining layer 310, a sealing member 390, an upper substrate 410, a side electrode 470, an organic pattern 490, and the like.

[0127] The pad electrode 430 may include first to n-th pad electrodes (where n is an integer greater than 2), the first to n-th pad electrodes may be spaced apart from each other and arranged along the second direction D2 in the peripheral region 20. The side electrode 470 may include first to m-th side electrodes (where m is an integer greater than 2), the first to m-th side electrodes may be in direct contact with the first to n-th pad electrodes, respectively, where m may be equal to n. The organic pattern 490 may include first to p-th organic patterns (where p is an integer greater than 1), and a k-th organic pattern among the first to p-th organic patterns may be disposed between an h-th side electrode and an h+1-th side electrode among the first to m-th side electrodes, where k is an integer between 1 and p, and h is an integer between 1 and m.

[0128] After the organic layer is completely formed in the outermost surface of the OLED display device 500, the organic pattern 490 may be formed by patterning the organic layer. The organic pattern 490 may expose the pad electrode 430. A metal layer may be formed on the outermost surface of the OLED display device 500 and the organic pattern 490. After the metal layer is formed, the side electrode 470 may be formed by patterning the metal layer. The organic pattern 490 may include at least one of polyimide, siloxane, and the like.

[0129] Fig. 9 is a plan view showing an OLED display device according to an example embodiment, Fig.10 It is along Fig. 9 In addition to the shape of the sealing member 390, Fig. 9 and Fig.10 The OLED display device 700 shown in FIG. Figures 1 to 7 The elements of the OLED display device 100 described above are substantially the same or similar elements. Fig. 9 and Fig.10 In the example above, you can avoid repeating the reference Figures 1 to 7 A detailed description of elements that are described are substantially the same or similar.

[0130] Reference Fig. 9 and Fig.10 , the OLED display device 700 may include a lower substrate 110, a semiconductor element 250, a pad electrode 430, a planarization layer 270, a sub-pixel structure 200, a pixel defining layer 310, a sealing member 390, an upper substrate 410, a side electrode 470, etc. The sealing member 390 may include a first sealing pattern 391 and a second sealing pattern 392. The pad electrode 430 may include a first pad electrode pattern 431 and a second pad electrode pattern 432, and the side electrode 470 may include a first metal layer 471, a second metal layer 472, and a third metal layer 473.

[0131] The sealing member 390 may be disposed in the peripheral region 20 on the lower substrate 110. For example, a portion of the peripheral region 20 where the pad electrode 430 is disposed is defined as a first peripheral region, and a portion of the peripheral region 20 where the pad electrode 430 is not disposed is defined as a second peripheral region.

[0132] like Fig.10As shown in , the peripheral area 20 shown on the right side of the display area 10 may correspond to the first peripheral area, and the peripheral area 20 shown on the left side of the display area 10 may correspond to the second peripheral area. In example embodiments, the first seal pattern 391 (or the first seal member / portion 391) may be disposed in the first peripheral area on the lower substrate 110, and the second seal pattern 392 (or the second seal member / portion 392) may be disposed in the second peripheral area on the lower substrate 110. The first seal pattern 391 may contact the pad electrode 430 and the side electrode 470, and the shape of the cross section of the first seal pattern 391 may be different from the shape of the cross section of the second seal pattern 392. For example, a portion of the upper substrate 410, a portion of the lower substrate 110, and a portion of the pad electrode 430 located in the first peripheral area may be removed so that the side electrode 470 contacts the pad electrode 430, and the outermost portion of the first seal pattern 391 may have a flat side surface. At the same time, the outermost portion of the second seal pattern 392 may have an inclined side surface. The side surface of the first seal pattern 391 may not be symmetrical, and the side surface of the second seal pattern 392 may be symmetrical.

[0133] Figures 11 to 19 is a diagram showing a structure formed in a method of manufacturing an OLED display device according to an example embodiment. For example, Figures 11 to 16 is a cross-sectional view corresponding to an OLED display device, Fig.17 and Fig.18 is a side view corresponding to the OLED display device. In addition, Fig.19 is a perspective view corresponding to an OLED display device.

[0134] Reference Fig.11 , a lower substrate 110 including a transparent or opaque insulating material may be provided. The lower substrate 110 may be formed using at least one of a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, etc. Alternatively or additionally, the lower substrate 110 may be formed using a flexible transparent material.

[0135] A buffer layer (not shown) may be formed on the entire lower substrate 110. The buffer layer may prevent diffusion of metal atoms / impurities from the lower substrate 110. The buffer layer may control the rate of heat transfer in a crystallization process for forming an active layer, thereby obtaining a substantially uniform active layer. In addition, the buffer layer may improve the surface flatness of the lower substrate 110 when the surface of the lower substrate 110 is relatively irregular. Depending on the type of the lower substrate 110, at least two buffer layers may be provided on the lower substrate 110, or no buffer layer may be formed. For example, an organic material or an inorganic material may be used to form the buffer layer. An active layer 130 may be formed in the display area 10 on the lower substrate 110.

[0136] Reference Fig.12 , a gate insulating layer 150 may be formed on the active layer 130. The gate insulating layer 150 may cover the active layer 130 in the display area 10 on the lower substrate 110, and the gate insulating layer 150 may be formed in the entire display area 10 on the lower substrate 110. In example embodiments, the gate insulating layer 150 may not be formed in the peripheral area 20 on the lower substrate 110. In some example embodiments, the gate insulating layer 150 may be formed in the entire display area 10 and the peripheral area 20 on the lower substrate 110. The gate insulating layer 150 may fully cover the active layer 130 on the lower substrate 110, and may have a substantially flat upper surface without steps around the active layer 130. The gate insulating layer 150 may cover the active layer 130 on the lower substrate 110, and may be formed to a substantially uniform thickness along the contour of the active layer 130. The gate insulating layer 150 may include at least one of a silicon compound, a metal oxide, and the like. SiO may be used. x 、SiN x 、SiO x N y 、SiO x C y 、SiC x N y 、AlO x 、AlN x 、TaO x , HfO x 、ZrO x 、TiO x At least one of the above mentioned materials forms the gate insulating layer 150 .

[0137] The gate electrode 170 may be formed on a portion of the gate insulating layer 150, and the gate electrode 170 may overlap the active layer 130. The gate electrode 170 may be formed using at least one of a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in an appropriate combination. The first gate electrode 170 may have a multilayer structure including a plurality of layers.

[0138] The initial first pad electrode pattern 1431 may be formed in the peripheral region 20 and on the lower substrate 110. The initial first pad electrode pattern 1431 may be formed using at least one of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. For example, the initial first pad electrode pattern 1431 may include Au, Ag, Al, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, W, Cu, Mo, Sc, Nd, Ir, aluminum alloy, AlN x , Silver alloy, WN x , copper alloy, molybdenum alloy, TiN x CrNx 、TaN x 、SRO x 、ZnO x 、ITO、SnO x 、InO x 、GaO x , IZO, etc. These may be used alone or in appropriate combination. In example embodiments, the initial first pad electrode pattern 1431 and the gate electrode 170 may be simultaneously formed using the same material. For example, after forming the initial first electrode layer on the entire lower substrate 110, the gate electrode 170 and the initial first pad electrode pattern 1431 may be simultaneously formed by selectively etching the initial first electrode layer. The initial first pad electrode pattern 1431 may have a multilayer structure including a plurality of layers.

[0139] Reference Fig.13 , an insulating interlayer 190 may be formed on the gate electrode 170. The insulating interlayer 190 may cover the gate electrode 170 in the display region 10 on the gate insulating layer 150, and may be formed on the entire gate insulating layer 150. In example embodiments, the insulating interlayer 190 may not be formed in the peripheral region 20 on the lower substrate 110. In some example embodiments, the gate insulating layer 150 may be formed in the entire display region 10 and the peripheral region 20 on the lower substrate 110 except for a portion where the initial first pad electrode pattern 1431 is formed. The insulating interlayer 190 may fully cover the gate electrode 170 on the gate insulating layer 150, and may have a substantially flat upper surface without a step around the gate electrode 170. The insulating interlayer 190 may cover the gate electrode 170 on the gate insulating layer 150, and may be formed to a substantially uniform thickness along the contour of the gate electrode 170. The insulating interlayer 190 may be formed using a silicon compound, a metal oxide, or the like.

[0140] The source electrode 210 and the drain electrode 230 may be formed in the display area 10 and on the insulating interlayer 190. The source electrode 210 may directly contact the source region of the active layer 130 via a contact hole formed by removing the first portion of the gate insulating layer 150 and the insulating interlayer 190. The drain electrode 230 may directly contact the drain region of the active layer 130 via a contact hole formed by removing the second portion of the gate insulating layer 150 and the insulating interlayer 190. Each of the source electrode 210 and the drain electrode 230 may be formed using at least one of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in an appropriate combination. Each of the source electrode 210 and the drain electrode 230 may have a multilayer structure including a plurality of layers. Thus, a semiconductor element 250 including an active layer 130, a gate insulating layer 150, a gate electrode 170, an insulating interlayer 190, a source electrode 210, and a drain electrode 230 may be formed.

[0141] An initial second pad electrode pattern 1432 may be formed in the peripheral region 20 and on the initial first pad electrode pattern 1431. The initial second pad electrode pattern 1432 may be formed using at least one of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in appropriate combinations. In an example embodiment, the initial second pad electrode pattern 1432, the source electrode 210, and the drain electrode 230 may be simultaneously formed using the same material. For example, after forming the initial second electrode layer on the lower substrate 110, the initial second pad electrode pattern 1432, the source electrode 210, and the drain electrode 230 may be simultaneously formed by selectively etching the initial second electrode layer. The initial second pad electrode pattern 1432 may have a multilayer structure including a plurality of layers. Thus, an initial pad electrode 1430 including the initial first pad electrode pattern 1431 and the initial second pad electrode pattern 1432 may be formed.

[0142] Reference Fig.14 , a planarization layer 270 may be formed in the display area 10 and on the insulating interlayer 190, the source electrode 210, and the drain electrode 230. The planarization layer 270 may have a sufficient thickness to fully cover the source electrode 210 and the drain electrode 230 on the insulating interlayer 190. The planarization layer 270 may have a substantially flat upper surface, and a planarization process may be further performed on the planarization layer 270 to achieve a flat upper surface of the planarization layer 270. A portion of the upper surface of the drain electrode 230 may be exposed via a contact hole formed by removing a portion of the planarization layer 270. The planarization layer 270 may include an organic material or an inorganic material. In example embodiments, the planarization layer 270 may be formed using an organic material such as at least one of polyimide, epoxy-based resin, acryl-based resin, polyester, photoresist, polyacryl-based resin, polyimide-based resin, polyamide-based resin, siloxane-based resin, and the like.

[0143] The lower electrode 290 may be formed in the display region 10 and on the planarization layer 270. The lower electrode 290 may directly contact the drain electrode 230 via the contact hole of the planarization layer 270 and may be electrically connected to the semiconductor element 250. The lower electrode 290 may be formed using at least one of a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in an appropriate combination. The lower electrode 290 may have a multilayer structure including a plurality of layers.

[0144] A pixel defining layer 310 may be formed in the display region 10 and on a portion of the lower electrode 290 and a portion of the planarization layer 270. The pixel defining layer 310 may cover both side portions of the lower electrode 290 and may expose a portion of the upper surface of the lower electrode 290. The pixel defining layer 310 may include an organic material or an inorganic material. In example embodiments, the pixel defining layer 310 may be formed using an organic material.

[0145] The light emitting layer 330 may be formed in the display area 10 and on the lower electrode 290 exposed by the pixel defining layer 310. The light emitting layer 330 may be formed using at least one of the light emitting materials capable of generating light of different colors (e.g., red light, blue light, green light, etc.) according to the sub-pixel structure 200. The light emitting layer 330 may generally generate white light by stacking a plurality of light emitting materials capable of generating light of different colors such as red light, green light, blue light, etc. In this case, a color filter may be formed on the light emitting layer 330. The color filter may include at least one selected from a red color filter, a green color filter, and a blue color filter. The color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may be formed using a photosensitive resin, a color photoresist, etc.

[0146] The upper electrode 340 may be formed in the display area 10 and on the pixel defining layer 310 and the light emitting layer 330. The upper electrode 340 may be formed using at least one of a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in a suitable combination. The upper electrode 340 may have a multilayer structure including a plurality of layers. Thus, a sub-pixel structure 200 including a lower electrode 290, a light emitting layer 330, and an upper electrode 340 may be formed.

[0147] Reference Fig.15 , an initial sealing member 1390 may be formed in the peripheral region 20 and on the initial pad electrode 1430. The lower surface of the initial sealing member 1390 may be in direct contact with a portion of the initial first pad electrode pattern 1431 and the initial second pad electrode pattern 1432. The initial sealing member 1390 may be formed using glass frit or the like. The initial sealing member 1390 may include a photocurable material. For example, the initial sealing member 1390 may include a compound such as an organic material and a photocurable material. After one or more of ultraviolet rays, laser beams, visible light, etc. are irradiated into the compound, the compound may be cured, and thus the initial sealing member 1390 may be obtained. The photocurable material included in the initial sealing member 1390 may include at least one of epoxy acrylate resin, polyester acrylate resin, polyurethane acrylate resin, polybutadiene acrylate resin, silicone acrylate resin, alkyl acrylate resin, and the like.

[0148] An upper substrate 410 may be formed on the initial sealing member 1390 and the upper electrode 340. The upper substrate 410 and the lower substrate 110 may include substantially the same material. For example, the upper substrate 410 may be formed using at least one of a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, and the like. In some example embodiments, the upper substrate 410 may include a transparent inorganic material or a flexible plastic. In an embodiment, after the initial sealing member 1390 is formed on the upper substrate 410, the upper substrate 410 and the initial sealing member 1390 may be connected to the lower substrate 110.

[0149] After forming the upper substrate 410, laser may be irradiated on the initial sealing member 1390. In response to the irradiation of the light of the laser, the state of the initial sealing member 1390 may be changed from solid to liquid. The liquid initial sealing member 1390 may be cured to a solid state after a predetermined time. After the state of the initial sealing member 1390 is changed, the initial sealing member 1390 may seal the lower substrate 110 and the upper substrate 410.

[0150] After the upper substrate 410 and the lower substrate 110 are sealed, Fig.15 Line III-III′ shown in FIG. 4 removes a portion of the upper substrate 410 , a portion of the lower substrate 110 , a portion of the preliminary sealing member 1390 , and a portion of the preliminary pad electrode 1430 located in the first peripheral region.

[0151] Reference Fig.16 After removing a portion of the upper substrate 410, a portion of the lower substrate 110, a portion of the preliminary sealing member 1390, and a portion of the preliminary pad electrode 1430 located in the first peripheral region, a sealing member 390 and a pad electrode 430 including a first pad electrode pattern 431 and a second pad electrode pattern 432 may be formed.

[0152] A first portion (eg, one side surface) of the first pad electrode pattern 431 may be aligned / coplanar with the outermost surface of the sealing member 390 , and a second portion of the first pad electrode pattern 431 opposite the first portion may extend from the peripheral region 20 into the display region 10 .

[0153] A first portion (e.g., one side surface) of the second pad electrode pattern 432 may be aligned / coplanar with the outermost surface of the sealing member 390, and a second portion of the second pad electrode pattern 432 opposite to the first portion may be formed within the sealing member 390. Alternatively, the second portion of the second pad electrode pattern 432 may extend from the peripheral region 20 into the display region 10 along the first direction D1.

[0154] A first portion (eg, one side surface) of the sealing member 390 may be aligned / coplanar with the outermost surface of each of the substrates 110 and 410 , and a second portion of the sealing member 390 opposite to the first portion may be located within the OLED display device 500 .

[0155] Reference Fig.17 , an organic layer 1490 is formed on the outermost surface of one or more of the sealing member 390, the pad electrode 430, the lower substrate 110, and the upper substrate 410. The organic layer 1490 may cover one side surface of each pad electrode 430 exposed by the sealing member 390. The organic layer 1490 may include polyimide, siloxane, or the like.

[0156] Reference Fig.18 After forming the organic layer 1490, an organic pattern 490 may be formed by patterning the organic layer 1490. The organic pattern 490 may expose the pad electrode 430. After forming the organic pattern 490, a metal layer may be formed on the outermost surfaces of the pad electrode 430 and the sealing member 390 exposed by the organic pattern 490.

[0157] Reference Fig.19 , after forming the metal layer, a side electrode 470 located between the organic patterns 490 may be formed between the organic patterns 490. The side electrode 470 may directly contact the corresponding side surface of the pad electrode 430 and may be electrically connected to the corresponding pad electrode 430. The side electrode 470 may protrude from / protrude beyond the outermost surface of one or more of the sealing member 390, the pad electrode 430, the lower substrate 110, and the upper substrate 410 in the first direction D1.

[0158] The side electrodes 470 may include Figure 6 4. The first metal layer 471, the second metal layer 472, and the third metal layer 473 are shown in FIG.

[0159] The first metal layer 471 may contact the pad electrode 430 and may be formed using a metal having relatively high metal adhesion. For example, the first metal layer 471 may be mainly composed of at least one of Ti, Mo, Ni, Ta, Nd, and the like.

[0160] The second metal layer 472 may be formed on the first metal layer 471 and may be formed using a metal having relatively low resistance. For example, the second metal layer 472 may be mainly composed of at least one of Au, Ag, Cu, Al, and the like.

[0161] The third metal layer 473 may be formed on the second metal layer 472, and may be formed using a metal having relatively high mechanical strength. The third metal layer 473 may protect the second metal layer 472. For example, the third metal layer 473 may be mainly composed of at least one of Ti, Mo, a titanium alloy, a molybdenum alloy, etc., and may have a metal having a Mohs hardness of 5 or more. The OLED display device 500 may have a minimal non-display area.

[0162] The embodiments may be applied to various display devices including organic light emitting diode display devices, for example, vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, etc.

[0163] The above is an explanation of example embodiments and is not to be construed as limiting. Although some example embodiments have been described, many modifications are possible in the example embodiments. All modifications are intended to be included within the scope defined in the claims.

Claims

1. A display device, comprising: first base; pixels, overlapping the first surface of the first substrate; a contact electrode electrically connected to the pixel, wherein a first surface of the contact electrode overlaps the first surface of the first substrate; and a side electrode, arranged to protrude from the first substrate in a direction parallel to the first surface of the first substrate, wherein the first surface of the side electrode directly contacts the second surface of the contact electrode, wherein the second surface of the contact electrode is not parallel to the first surface of the contact electrode, Wherein, the side electrode includes: a first metal layer, directly contacting the contact electrode; a second metal layer, arranged on the first metal layer in the direction, the resistance of the second metal layer is lower than the resistance of the first metal layer, and the adhesion force of the first metal layer is greater than the adhesion force of the second metal layer; and a third metal layer, arranged on the second metal layer in the direction, the mechanical strength of the third metal layer is greater than each of the mechanical strength of the first metal layer and the mechanical strength of the second metal layer.

2. The display device according to claim 1, wherein: The first surface of the side electrode is parallel to the second surface of the first substrate, and wherein the second surface of the first substrate is not parallel to the first surface of the first substrate.

3. The display device according to claim 1, further comprising a second substrate, wherein: The contact electrode is disposed between the first surface of the first substrate and the first surface of the second substrate, wherein the second surface of the first substrate is coplanar with the second surface of the second substrate and coplanar with the second surface of the contact electrode.

4. The display device according to claim 1, wherein: The first metal layer includes at least one of titanium, molybdenum, nickel, tantalum and neodymium, and wherein the second metal layer includes at least one of silver, copper, aluminum and gold.

5. The display device according to claim 1, wherein: A material of the contact electrode is the same as at least one of a material of a gate electrode of the pixel and a material of a drain electrode of the pixel.

6. The display device according to claim 1, further comprising a second substrate, wherein: The contact electrode is arranged between the first surface of the first substrate and the first surface of the second substrate, and is arranged closer to the first substrate than the second substrate, wherein the first surface of the side electrode directly contacts the second surface of the second substrate, and wherein the first surface of the side electrode directly contacts the second surface of the first substrate.

7. The display device according to claim 1, further comprising an organic member directly contacting the second surface of the side electrode, wherein: The second surface of the side electrode is not parallel to the first surface of the side electrode.

8. The display device according to claim 1, wherein: The pixel includes a transistor, wherein the transistor includes a first transistor electrode and a second transistor electrode, wherein the contact electrode includes a first conductive layer and a second conductive layer, wherein the first conductive layer is arranged between the first substrate and the second conductive layer, wherein the material of the first conductive layer is the same as the material of the first transistor electrode, wherein the material of the second conductive layer is the same as the material of the second transistor electrode, wherein the first transistor electrode is a gate electrode, wherein the second transistor electrode is a drain electrode, wherein the first conductive layer directly contacts the first substrate, and wherein the gate electrode is separated from the first substrate.

9. The display device according to claim 8, further comprising: a gate insulating layer, disposed between the first transistor electrode and the first substrate; and an insulating interlayer disposed between the first transistor electrode and the second transistor electrode, wherein the gate insulating layer and the insulating interlayer are both separated from the contact electrode.

10. The display device according to claim 1, further comprising: Second base; and a sealing member disposed between the first substrate and the second substrate, directly contacting the second substrate and directly contacting the contact electrode, The sealing member partially covers the contact electrode and partially exposes the contact electrode, wherein the sealing member directly contacts the first surface of the side electrode.

11. The display device according to claim 10, wherein: The contact electrode includes a first conductive layer and a second conductive layer, wherein the first conductive layer is disposed between the first substrate and the second conductive layer, and wherein the sealing member is narrower than the first conductive layer and wider than the second conductive layer in the direction.

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