Low-voltage sensor system and its offset cancellation method

Abstract

The present invention discloses a low-voltage sensor system and a method for eliminating offset thereof. The low-voltage sensor system includes: a Hall device for detecting an external magnetic field signal and converting it into a Hall voltage signal; an offset elimination circuit for eliminating the offset voltage in the Hall voltage signal and outputting a modulation signal; a comparison module for comparing the modulation signal with a reference voltage signal; a digital processing module for outputting a control signal according to the comparison result; and an output driving module for outputting a driving signal according to the control signal. Among them, the offset elimination circuit includes: an amplification unit for eliminating the offset voltage generated by itself and generating an amplified signal; a sample and hold unit for eliminating the offset voltage of the Hall device itself in the amplified signal and outputting a modulation signal; and a timing control unit. Thereby, it ensures the normal operation of the system circuit within a wide voltage range, reduces or even eliminates the saturation situation caused by offset in the circuit under low voltage, and at the same time reduces the cost.

Description

Technical Field

[0001] The present invention relates to the field of Hall switches, and particularly to a low-voltage sensor system and a method for eliminating offset thereof. Background Art

[0002] CMOS integrated Hall sensors have been widely used in industrial control, automobiles, intelligent instruments and meters, consumer electronics and other fields to detect magnetic fields due to their many advantages such as low cost, low power consumption, high integration level, and strong anti-interference ability. However, the Hall voltage generated by CMOS Hall sensors is very weak, and there are large offset voltages and flicker noises in the system. The design of the signal processing circuit for eliminating offset and noise is very crucial.

[0003] The offset in Hall sensors mainly comes from two aspects: the offset voltage of the Hall disk and the offset voltage of the signal processing circuit. Compared with the weak output voltage of the Hall disk, the offset voltage of the Hall disk is very large and can easily submerge the Hall voltage. If the Hall voltage is to be accurately identified, effective measures must be taken to eliminate the offset voltage of the Hall disk.

[0004] In a sensor system, if the system operating voltage is low, the amplified DC offset can easily saturate the circuit, completely blocking the useful AC signal and causing abnormal functions of the Hall system. Currently, the following two general methods are used to eliminate the offset in Hall systems: one is the rotating current method combined with a sample-and-hold circuit; the other is the chopper technique combined with the ADC digital feedback offset compensation method. The rotating current method is a method that uses one or more Hall disks and periodically changes the power supply voltage and the output node direction, combined with a sample-and-hold circuit, to eliminate the offset of the Hall system. However, in the system, due to the fact that the front-stage offset voltage will be amplified, it is easy to cause the operational amplifier output to saturate under the low-voltage working state. Therefore, this structure is only applicable to the case where the voltage is relatively high and the system gain is not very high. The method of eliminating offset by ADC loop compensation can well eliminate the offset, but its structure is complex and not suitable for low-cost consumer products. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a low-voltage sensor system and a method for eliminating offset thereof, which can effectively eliminate the offset voltage and noise in the system when the system is in a low operating voltage condition.

[0006] On the one hand, the present invention provides a low-voltage sensor system, which includes:

[0007] A Hall device, which detects an external magnetic field signal and converts the magnetic field signal into a Hall voltage signal;

[0008] An offset elimination circuit, which is used to eliminate the offset voltage in the Hall voltage signal and output a modulated signal;

[0009] A comparison module, connected to the offset cancellation circuit, compares the modulation signal with a reference voltage signal;

[0010] A digital processing module, connected to the comparison module, outputs a control signal according to the comparison result of the comparison module; and

[0011] An output driving module, connected to the digital processing module, outputs a driving signal according to the control signal,

[0012] wherein, the offset cancellation circuit includes:

[0013] An amplification unit, connected to the Hall device, is used to eliminate the offset voltage generated by the amplification unit itself and generate an amplified signal;

[0014] A sample and hold unit, connected to the amplification unit, is used to eliminate the offset voltage of the Hall device itself in the amplified signal and perform sample and hold, and output the modulation signal;

[0015] A timing control unit, connected to the Hall device, the amplification unit and the sample and hold unit, provides a plurality of clock signals.

[0016] Preferably, the amplification unit includes:

[0017] A first-stage amplifier unit, connected to the Hall device, is used to eliminate the offset voltage generated by the first-stage amplifier unit and generate an amplified signal.

[0018] Preferably, the first-stage amplifier unit includes: a first amplifier, a second amplifier, a first resistor, a second resistor and a third resistor,

[0019] The non-inverting input terminals of the first amplifier and the second amplifier are respectively connected to the output terminal of the Hall device, a third resistor is connected between the inverting input terminals of the first amplifier and the second amplifier, the first resistor is connected between the inverting input terminal and the output terminal of the first amplifier, and the second resistor is connected between the inverting input terminal and the output terminal of the second amplifier.

[0020] Preferably, the amplification unit further includes:

[0021] A second-stage amplifier unit, connected to the first-stage amplifier unit and the sample and hold unit, is used to realize gain amplification of the amplified signal.

[0022] Preferably, the second-stage amplifier unit includes: a third amplifier, a fourth amplifier, a fourth resistor, a fifth resistor and a sixth resistor,

[0023] Among them, the non-inverting input terminals of the third amplifier and the fourth amplifier are respectively connected to the output terminals of the first amplifier and the second amplifier. A sixth resistor is connected between the inverting input terminals of the first amplifier and the second amplifier. The fourth resistor is connected between the inverting input terminal and the output terminal of the third amplifier. The fifth resistor is connected between the inverting input terminal and the output terminal of the fourth amplifier.

[0024] The output terminals of the third amplifier and the fourth amplifier are connected to the sample-and-hold unit to output the amplified amplified signal.

[0025] Preferably, the amplification unit further includes:

[0026] A first capacitor, connected between the output terminal of the first amplifier and the non-inverting input terminal of the third amplifier;

[0027] A second capacitor, connected between the output terminal of the second amplifier and the non-inverting input terminal of the fourth amplifier.

[0028] Preferably, the amplification unit further includes a first switch to a fourth switch;

[0029] Among them, the first switch and the second switch are connected in series between the non-inverting input terminals of the first amplifier and the second amplifier and are controlled by the first clock signal. The middle node of the first switch and the second switch receives a preset voltage;

[0030] The third switch and the fourth switch are connected in series between the non-inverting input terminals of the third amplifier and the fourth amplifier and are controlled by the second clock signal. The middle node of the third switch and the fourth switch receives a common-mode input signal.

[0031] Preferably, the non-inverting input terminal of the comparison module receives the reference voltage signal, and the inverting input terminal is connected to the sample-and-hold unit to compare the modulation signal with the reference voltage signal and output a control signal.

[0032] Preferably, the multiple clock signals include: a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal.

[0033] Among them, the timing control unit provides the third clock signal and the fourth clock signal to the Hall device, provides the first clock signal and the second clock signal to the amplification unit, and provides the third clock signal, the fourth clock signal, and the fifth clock signal to the sample-and-hold unit.

[0034] Preferably, when the third clock signal, the fourth clock signal, and the fifth clock signal are at a low level, and the first clock signal and the second clock signal are at a high level, the offset voltage generated by the first-stage amplifier unit is obtained and stored in the first capacitor and the second capacitor.

[0035] Preferably, when the first clock signal, the second clock signal, the fourth clock signal, and the fifth clock signal are at a low level, and the third clock signal is at a high level, the Hall device outputs a first Hall voltage signal.

[0036] The first-stage amplifier unit outputs its own generated offset voltage and the first Hall voltage signal, which cancel out the offset voltage stored in the first capacitor and the second capacitor, generates a first amplified signal and outputs it to the sample-and-hold unit.

[0037] Preferably, when the second clock signal is at a low level and the first clock signal is at a high level, the first-stage amplifier unit is in a short-circuit state.

[0038] Preferably, when the first clock signal, the second clock signal, the third clock signal, and the fifth clock signal are at a low level, and the fourth clock signal is at a high level, the Hall device outputs a second Hall voltage signal.

[0039] The first-stage amplifier unit outputs its own generated offset voltage and the second Hall voltage signal, which cancel out the offset voltage stored in the first capacitor and the second capacitor, generates a second amplified signal, and outputs it to the sample-and-hold unit.

[0040] Wherein, the second Hall voltage signal has a polarity opposite to that of the first Hall voltage signal.

[0041] Preferably, when the second clock signal, the third clock signal, and the fourth clock signal are at a low level, and the first clock signal and the fifth clock signal are at a high level, the sample-and-hold unit subtracts the first amplified signal and the second amplified signal, eliminates the offset voltage of the Hall device itself to generate the modulation signal and outputs it to the comparison module.

[0042] Preferably, the digital processing module is further connected to the timing control unit for controlling the timing control unit to periodically output the first clock signal to the fifth clock signal.

[0043] Preferably, the digital processing module includes a latch, and the latch is connected to the output end of the comparison module for latching the comparison result of the comparison module.

[0044] Preferably, the amplification gain values of the first amplifier and the second amplifier are the same, and the resistance values of the first resistor and the second resistor are the same.

[0045] Preferably, the amplification gain values of the third amplifier and the fourth amplifier are the same, the resistance values of the fourth resistor and the fifth resistor are the same, and the capacitance values of the first capacitor and the second capacitor are the same.

[0046] Preferably, the first-stage amplifier unit and / or the second-stage amplifier unit is an instrumentation amplifier unit.

[0047] Preferably, the amplification unit further includes a third-stage amplifier unit, and the third-stage amplifier unit is connected between the second-stage amplifier unit and the sample-and-hold unit.

[0048] On the other hand, the present invention provides a method for offset cancellation of a low-voltage sensor system. The low-voltage sensor system includes a Hall device and an offset cancellation circuit. The offset cancellation method includes:

[0049] Storing the offset voltage generated by the offset cancellation circuit;

[0050] Detecting an external magnetic field signal and converting the magnetic field signal into a Hall voltage signal;

[0051] Canceling the offset voltage generated by the offset cancellation circuit in the Hall voltage signal and generating an amplified signal;

[0052] Canceling the offset voltage of the Hall device itself in the amplified signal and performing sample-and-hold to output a modulated signal;

[0053] Generating a drive signal according to the modulated signal.

[0054] Preferably, the step of generating a drive signal according to the modulated signal includes:

[0055] Comparing the modulated signal with a reference voltage signal and outputting a comparison result;

[0056] Generating a control signal according to the comparison result;

[0057] Generating a drive signal according to the control signal.

[0058] Preferably, the offset cancellation method further includes:

[0059] Providing a plurality of clock signals, and the plurality of clock signals at least include: a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal.

[0060] Preferably, before the step of detecting an external magnetic field signal and converting the magnetic field signal into a Hall voltage signal, the following steps are further included:

[0061] When the third clock signal, the fourth clock signal, and the fifth clock signal are at a low level, and the first clock signal and the second clock signal are at a high level, obtain the offset voltage generated by the low-voltage sensor system and store it.

[0062] Preferably, the step of eliminating the offset voltage generated by the low-voltage sensor system in the Hall voltage signal and generating an amplified signal includes:

[0063] When the first clock signal, the second clock signal, the fourth clock signal, and the fifth clock signal are at a low level, and the third clock signal is at a high level, obtain a first Hall voltage signal;

[0064] Output the offset voltage generated by the low-voltage sensor system and the first Hall voltage signal, cancel them out with the stored offset voltage, generate a first amplified signal and output it.

[0065] Preferably, the step of eliminating the offset voltage generated by the low-voltage sensor system in the Hall voltage signal and generating an amplified signal further includes:

[0066] When the first clock signal, the second clock signal, the third clock signal, and the fifth clock signal are at a low level, and the fourth clock signal is at a high level, obtain a second Hall voltage signal;

[0067] Output the offset voltage generated by the low-voltage sensor system and the second Hall voltage signal, cancel them out with the stored offset voltage, generate a second amplified signal and output it.

[0068] Wherein, the second Hall voltage signal has the opposite polarity to the first Hall voltage signal.

[0069] Preferably, the step of eliminating the offset voltage of the Hall device itself in the amplified signal, performing sample and hold, and outputting a modulation signal includes:

[0070] When the second clock signal, the third clock signal, and the fourth clock signal are at a low level, and the first clock signal and the fifth clock signal are at a high level, perform a subtraction process on the amplified first amplified signal and second amplified signal, eliminate the offset voltage of the Hall device itself, generate the modulation signal and output it.

[0071] Preferably, the control signal is further used to control the periodic output of the first clock signal to the fifth clock signal.

[0072] Preferably, the step of generating a control signal according to the comparison result includes:

[0073] Latch the comparison result between the modulation signal and the reference voltage signal.

[0074] The beneficial effects of the present invention are as follows: By using the timing control signal, when the Hall device is not working, the first-stage amplifier unit stores the offset voltage generated by itself on the capacitor. When the Hall device is working, the first-stage amplifier unit neutralizes the operational amplifier offset voltage with the operational amplifier offset voltage stored on the capacitor to eliminate the offset voltage generated by itself. At the same time, the sample and hold unit eliminates the offset voltage of the Hall device itself, enabling the system to effectively eliminate the offset signal at low voltage without causing saturation of the offset signal, ensuring the normal function of the system and improving the accuracy of the sensor system.

[0075] In the present invention, the solution to the offset voltage in the low-voltage sensor system is mainly achieved in the first-stage amplifier unit after the Hall device, which is different from the prior art that processes at the backend of the amplification unit.

[0076] The low-voltage sensor system proposed by the present invention is applicable to the working state of low voltage. For a system that conventionally solves the offset signal without restricting the working voltage, the offset signal is likely to cause saturation at high working voltage, which is not conducive to the elimination of the offset signal.

[0077] The low-voltage sensor system proposed by the present invention realizes the system gain through multiple-stage operational amplifiers, mainly to prevent the saturation problem caused by the offset of the first-stage operational amplifier itself at low voltage due to excessive system gain; the role of the first-stage operational amplifier in the multiple-stage operational amplifiers is to eliminate the offset, and the subsequent operational amplifiers mainly play the role of gain amplification.

[0078] At the same time, the system structure is simple, which can effectively reduce costs and improve the competitiveness of products. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer.

[0080] Figure 1 Shows the circuit block diagram of the low-voltage sensor system provided according to an embodiment of the present invention;

[0081] Figure 2 Shows Figure 1 The structural schematic diagram of the low-voltage sensor system in

[0082] Figure 3 Shows the flowchart of the offset elimination method provided according to an embodiment of the present invention;

[0083] Figure 4 Shows Figure 1 The timing working diagram of the timing control unit in DETAILED DESCRIPTION OF THE EMBODIMENTS

[0084] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0086] Below, the present invention will be described in detail with reference to the drawings.

[0087] Figure 1 and Figure 2 show a circuit block diagram and a schematic circuit structure diagram of a low-voltage sensor system provided according to an embodiment of the present invention. As Figure 1 and Figure 2 shown, an embodiment of the present invention provides a low-voltage sensor system 100, including a Hall device 10, an offset cancellation circuit 20, a comparison module 30, a digital processing module 40, and an output driving module 50. Among them, the Hall device 10 is used to detect an external magnetic field signal, convert the magnetic field signal into a Hall voltage signal (with an offset voltage), and then output it. The offset cancellation circuit 20 is used to cancel the offset voltage in the Hall voltage signal and output a modulation signal Vo. The comparison module 30 is connected to the offset cancellation circuit 20 to compare the modulation signal Vo with a reference voltage signal Vref. The digital processing module 40 is connected to the comparison module 30 and outputs a control signal according to the comparison result of the comparison module 30. The output driving module 50 is connected to the digital processing module 40 and outputs a driving signal Vout according to the control signal.

[0088] The offset cancellation circuit 20 includes: an amplification unit 21, a sample and hold unit 22, and a timing control unit 23. Among them, the amplification unit 21 is connected to the Hall device 10 and is used to cancel the offset voltage generated by the amplification unit 21 itself and generate an amplified signal. The sample and hold unit 22 is connected to the amplification unit 21 and is used to cancel the offset voltage of the Hall device 10 itself in the amplified signal and perform sample and hold, and output the modulation signal Vo. The timing control unit 23 is connected to the Hall device 10, the amplification unit 21, and the sample and hold unit 22 and is used to provide a plurality of clock signals. Among them, the Hall voltage signal with an offset voltage is the input voltage VIN of the amplification unit 21 connected to the Hall device 10.

[0089] In this embodiment, the timing control unit 23 is connected to the Hall device 10, the amplification unit 21, and the sample and hold unit 22, and is used to provide the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, and the fifth clock signal CLK5 thereto. Specifically, the timing control unit 23 provides the third clock signal CLK3 and the fourth clock signal CLK4 to the Hall device 10, provides the first clock signal CLK1 and the second clock signal CLK2 to the amplification unit 21, and provides the third clock signal CLK3, the fourth clock signal CLK4, and the fifth clock signal CLK5 to the sample and hold unit 22;

[0090] The Hall device 10 is used to detect an external magnetic field signal and, under the control of the third clock signal CLK3 and the fourth clock signal CLK4, convert the magnetic field signal into a Hall voltage signal (with an offset voltage) and then output it.

[0091] The amplification unit 21 is connected to the Hall device 10 and the timing control unit 23, and under the control of the first clock signal CLK1 and the second clock signal CLK2, eliminates the offset voltage generated by the amplification unit 21 in the Hall voltage signal and generates an amplified signal.

[0092] The sample and hold unit 22 is connected to the amplification unit 21 and the timing control unit 23, and under the control of the third clock signal CLK3, the fourth clock signal CLK4, and the fifth clock signal CLK5, after sampling and holding the amplified signal, eliminates the offset voltage of the Hall device 10 itself in the amplified signal and outputs a modulation signal Vo.

[0093] The comparison module 30 compares the modulation signal with a reference voltage signal Vref, the digital processing module 40 outputs a control signal according to the comparison result, and the output driving module 50 outputs a driving signal Vout according to the control signal, thereby realizing the gain and output of the magnetic field signal.

[0094] Furthermore, the digital processing module 40 is also connected to the timing control unit 23 and is used to control the timing control unit to periodically output the first clock signal CLK1 to the fifth clock signal CLK5. Among them, the output period of the first clock signal CLK1 to the fifth clock signal CLK5 can be, for example, several seconds to more than ten seconds, and is not limited in this embodiment and can be adjusted and set according to actual requirements.

[0095] Further, the amplification unit 21 includes: a first-stage amplifier unit IA1 connected to the Hall device 10. The first-stage amplifier unit IA1 includes: a first operational amplifier OTA1, a second operational amplifier OTA2, a first resistor R11, a second resistor R12, and a third resistor R13. The non-inverting input terminals of the first operational amplifier OTA1 and the second operational amplifier OTA2 are respectively connected to the output terminal of the Hall device 10. A third resistor R13 is connected between the inverting input terminals of the first operational amplifier OTA1 and the second operational amplifier OTA2. The first resistor R11 is connected between the inverting input terminal and the output terminal of the first operational amplifier OTA1. The second resistor R12 is connected between the inverting input terminal and the output terminal of the second operational amplifier OTA2.

[0096] Further, the amplification unit 21 further includes: a second-stage amplifier unit IA2 connected between the first-stage amplifier unit IA1 and the sample-and-hold unit 22. The second-stage amplifier unit IA2 includes: a third operational amplifier OTA3, a fourth operational amplifier OTA4, a fourth resistor R21, a fifth resistor R22, and a sixth resistor R23. The non-inverting input terminal of the third operational amplifier OTA3 is connected to the output terminal of the first operational amplifier OTA1. The non-inverting input terminal of the fourth operational amplifier OTA4 is connected to the output terminal of the second operational amplifier OTA2. A sixth resistor R23 is connected between the inverting input terminals of the third operational amplifier OTA3 and the fourth operational amplifier OTA4. The fourth resistor R21 is connected between the inverting input terminal and the output terminal of the third operational amplifier OTA3. The fifth resistor R22 is connected between the inverting input terminal and the output terminal of the fourth operational amplifier OTA4. The output terminals of the third operational amplifier OTA3 and the fourth operational amplifier OTA4 are both connected to the sample-and-hold unit 22 to output the amplified signal.

[0097] Further, the amplification unit 21 further includes: a first capacitor C1 and a second capacitor C2. The first capacitor C1 is connected between the output terminal of the first operational amplifier OTA1 and the non-inverting input terminal of the third operational amplifier OTA3. The second capacitor C2 is connected between the output terminal of the second operational amplifier OTA2 and the non-inverting input terminal of the fourth operational amplifier OTA4.

[0098] Further, the amplification unit 21 further includes: a first switch K1 and a second switch K2 connected in series between the non-inverting input terminal of the first amplifier OTA1 and the non-inverting input terminal of the second amplifier OTA2, and a third switch K3 and a fourth switch K4 connected in series between the non-inverting input terminal of the third amplifier OTA3 and the non-inverting input terminal of the fourth amplifier OTA4. Among them, the first switch K1 and the second switch K2 are controlled by a first clock signal CLK1, and the middle node of the first switch K1 and the second switch K2 is connected to a specific voltage VDD / 2. The third switch K3 and the fourth switch K4 are controlled by a second clock signal CLK2, and the middle node of the third switch K3 and the fourth switch K4 is connected to a common-mode input signal VCM. Among them, the specific voltage VDD / 2 and the common-mode input signal VCM can be designed according to actual requirements.

[0099] Further, the sample-and-hold unit 22 includes: a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, a ninth switch K9, a tenth switch K10, an eleventh switch K11, a twelfth switch K12, as well as a third capacitor C3 and a fourth capacitor C4. Among them, the fifth switch K5 and the sixth switch K6 are connected in series between the output terminal of the third amplifier OTA3 and the non-inverting input terminal of the comparison module 30. The seventh switch K7 and the eighth switch K8 are connected in series between the output terminal of the fourth amplifier OTA4 and the connection port of the specific voltage VDD / 2. The ninth switch K9 and the tenth switch K10 are connected in series between the output terminal of the fourth amplifier OTA4 and the non-inverting input terminal of the comparison module 30. The eleventh switch K11 and the twelfth switch K12 are connected in series between the output terminal of the third amplifier OTA3 and the connection port of the specific voltage VDD / 2. The third capacitor C3 is connected between the middle connection node of the fifth switch K5 and the sixth switch K6 and the middle connection node of the seventh switch K7 and the eighth switch K8. The fourth capacitor C4 is connected between the middle connection node of the ninth switch K9 and the tenth switch K10 and the middle connection node of the eleventh switch K11 and the twelfth switch K12.

[0100] Further, the fifth switch K5 and the seventh switch K7 are controlled by a third clock signal CLK3, the ninth switch K9 and the eleventh switch K11 are controlled by a fourth clock signal CLK4, and the sixth switch K6, the eighth switch K8, the tenth switch K10, and the twelfth switch K12 are controlled by a fifth clock signal CLK5, so as to control the sample-and-hold unit 22 to eliminate the offset voltage of the Hall device 10 itself in the amplified signal and output a modulation signal Vo.

[0101] In this embodiment, the amplification unit 21 includes two-stage amplifier units IA1 and IA2. The non-inverting input can significantly increase the input impedance of the circuit and reduce the attenuation of the circuit to weak input signals. The differential input enables the circuit to only amplify the differential-mode signal, while only following the common-mode input signal VCM, improving the common-mode rejection ratio (CMRR) in the amplification unit. In this way, in the amplification unit 21, when the CMRR requirement remains unchanged, the accuracy matching requirements for the first resistor R11, the second resistor R12, the third resistor R13, the fourth resistor R21, the fifth resistor R22, and the sixth resistor R23 can be significantly reduced, so that the amplification unit 21 has better common-mode rejection ability. Among them, the amplification gain values of the first amplifier OTA1 and the second amplifier OTA2 are the same, and the resistance values of the first resistor R11 and the second resistor R12 are the same. The amplification gain values of the third amplifier OTA3 and the fourth amplifier OTA4 are the same, the resistance values of the fourth resistor R21 and the fifth resistor R22 are the same, and the capacitance values of the first capacitor C1 and the second capacitor C2 are the same.

[0102] It should be noted here that the method for solving the offset voltage in the system in the present invention is mainly realized in the first-stage amplifier unit after the Hall device, which is different from the method in the prior art of eliminating the offset voltage at the backend of the amplification unit.

[0103] In addition, the amplification unit 21 in this embodiment includes but is not limited to two-stage amplifier units. The system gain is realized in two stages mainly to prevent the problem of saturation caused by the offset of the first-stage amplifier unit itself at low operating voltages. It is also feasible to realize it in three or more stages. The offset voltage of the operational amplifier is eliminated through the first-stage amplifier unit and the output capacitor connected thereto. The subsequent amplifier units play the role of gain amplification through reasonable gain design and have no effect on eliminating the offset signal.

[0104] In this embodiment, the non-inverting input terminal of the comparison module 30 receives the reference voltage signal Vref. The non-inverting input terminal is connected to the sample and hold unit 22 to compare the modulation signal with the reference voltage signal Vref. Further, the digital processing module 40 is a logic digital processing module, which logically processes the above comparison result and generates a control signal to be output to the output driving module 50. Further, the digital processing module 40 includes a latch (not shown), which is connected to the output terminal of the comparison module 30 and is used to latch the comparison result of the comparison module 30.

[0105] Further, the above-mentioned first-stage amplifier unit IA1 and second-stage amplifier unit IA2 are instrumentation amplifier units.

[0106] Further, when the first clock signal CLK1 is at a high level and the second clock signal CLK2 is at a low level, the first-stage amplifier unit IA1 is in a short-circuit state.

[0107] In the embodiment provided by the present invention, when the Hall device 10 is not working, when the second clock signal CLK2 is at a high level, the low-voltage sensor system 100 stores the offset charge representing the offset voltage Vos of the first-stage amplifier unit IA1 in the first capacitor C1 at the output end of the first amplifier OTA1 and the second capacitor C2 at the output end of the second amplifier OTA2; when controlled by the third clock signal CLK3 and the fourth clock signal CLK4, the Hall device 10 adopts the rotating current method to output a Hall voltage signal. After modulation, a Hall voltage signal with a periodically changing polarity but constant magnitude and the offset voltage Vos of the first-stage amplifier unit IA1 are amplified together; at this time, the polarity and magnitude of the offset voltage Vos1 of the Hall device 10 itself remain unchanged, and the Hall voltage signal including the offset voltage Vos1 of the Hall device 10 and the offset voltage Vos of the first-stage amplifier unit IA1 enters the offset cancellation circuit 20. The offset voltage Vos of the first-stage amplifier unit IA1 is subtracted from the offset voltage existing on the first capacitor C1 and the second capacitor C2 before, and the offset of the first-stage amplifier unit IA1 is eliminated; when the fifth clock signal CLK5 is at a high level, the Hall voltage signal and the offset voltage Vos1 of the Hall device 10 are processed by addition and subtraction in the sample and hold unit 22 to obtain a modulation signal Vo. Finally, the modulation signal Vo (i.e., the Hall voltage signal after offset cancellation) is compared with the reference voltage signal Vref, and the comparison result is output.

[0108] The low-voltage sensor system proposed by the present invention is applicable to a circuit system that works at a low operating voltage and the conventional method for solving the offset signal does not limit the operating voltage. Its offset signal is prone to saturation at a high operating voltage, which is not conducive to the elimination of the offset signal. This application can effectively eliminate the offset signal and will not cause saturation of the offset signal, and can improve the accuracy of the sensor system.

[0109] Figure 3 The flowchart showing the offset cancellation method provided by the embodiment of the present invention is as Figure 3 shown. The offset cancellation method of the low-voltage sensor system provided by the embodiment of the present invention includes:

[0110] Step S110: Store the offset signal generated by the amplification unit;

[0111] Step S120: Detect an external magnetic field signal and convert the magnetic field signal into a Hall voltage signal; in step S120, the offset voltage generated by the amplification unit in the Hall voltage signal is eliminated and an amplified signal is generated;

[0112] Step S130: Eliminate the offset voltage of the Hall device itself in the amplified signal through the sample and hold unit, and output a modulation signal;

[0113] Step S140: Compare the modulation signal with the reference voltage signal and output the comparison result;

[0114] Step S150: Generate a control signal according to the comparison result;

[0115] Step S160: Generate a drive signal according to the control signal.

[0116] In order to avoid the saturation of the system caused by the offset of the first-stage amplifier unit IA1 and the offset of the Hall device 10 itself at low operating voltages, in the embodiments provided by the present invention, it is achieved through two-stage amplification gains. The gain of the first-stage amplifier unit IA1 is A1, and the gain of the second-stage amplifier unit IA2 is A2. Then the total gain of the system is A1*A2. In this way, in the first-stage amplifier unit IA1, the offset of the first-stage amplifier unit IA1 is eliminated by using the above method.

[0117] The amplification unit 21 includes a first-stage amplifier unit IA1 and a second-stage amplifier unit IA2. The first-stage amplifier unit IA1 includes a first amplifier OTA1 and a second amplifier OTA2, and a pair of proportional resistors R11 and R13; the second-stage amplifier unit IA2 includes a third amplifier OTA3 and a fourth amplifier OTA4, and a pair of proportional resistors R21 and R23. The gains of the two-stage amplifier units IA1 and IA2 are respectively:

[0118] A1 = (2R13 / R11 + 1); (1)

[0119] A2 = (2R23 / R21 + 1); (2)

[0120] In order to eliminate the saturation effect caused by the offset of the first-stage amplifier unit IA1 and the Hall device 10 at low voltages, the Hall device 10 combines the rotating current method and the self-zeroing technique. Generally, the working principle of the rotating current method is that the Hall device 10 periodically interchanges the connection modes of the four contact ends of the Hall disk. After each group of clocks, the DC Hall signal is modulated into a signal with periodically reversed polarity but unchanged amplitude, while the offset voltage remains unchanged in terms of polarity and amplitude.

[0121] Figure 4 Show Figure 1 The timing diagram of the timing digital processing module in.

[0122] Next, in combination with Figures 2 to 4 , the offset cancellation method of the low-voltage sensor system provided by the embodiments of the present invention will be further described in detail.

[0123] Specifically, the process of eliminating the offset voltage is as follows:

[0124] At time T1, the Hall device 10 is in a sleep state; when the second clock signal CLK2 is at a high level, the first switch K1 and the second switch K2 are closed and conducting, and the third switch K3 and the fourth switch K4 are closed and conducting. At this time, the first clock signal CLK1 is at a high level state. Using the operational amplifier output offset cancellation method, the offset voltage Vos of the first-stage amplifier unit IA1 is stored in the first capacitor C1 and the second capacitor C2 connected to the output end of the first-stage amplifier unit IA1, thereby realizing the automatic zeroing of the Hall device 10. The offset charges stored in the first capacitor C1 and the second capacitor C2 are both:

[0125] Qoff = Vos * A1 * C1; (3)

[0126] At time T2, the Hall device 10 switches to the working state. The Hall device 10 is controlled by the third clock signal CLK3 and the fourth clock signal CLK4 provided by the timing control unit 23. At this time, the third clock signal CLK3 turns to a high level, the first switch K1 and the second switch K2 are opened, and the third switch K3 and the fourth switch K4 are opened. The output voltage of the Hall device 10 is Vsig + Vos1, where Vsig is the Hall voltage signal without the offset voltage, and Vos1 is the offset voltage of the Hall device itself. Then the input voltage of the first-stage amplifier unit IA1 is:

[0127] VIN1 = Vsig + Vos1 + Vos; (4)

[0128] Where VIN1 represents the input voltage of the first-stage amplifier unit IA1 under the control of CLK3; Vos1 is the offset voltage of the Hall device, and Vos is the offset voltage of the first-stage amplifier unit IA1. After the input voltage VIN1 is amplified by the first-stage amplifier unit IA1, it is stored on the first capacitor C1 and the second capacitor C2 at the output end. At this time, the charge on the capacitor is:

[0129] Q2 = Q1 = A1 * VIN1 * C1; (5)

[0130] Combined with formula (4), we get:

[0131] Q1 = A1 * (Vsig + Vos1 + Vos) * C1 (6)

[0132] Then, after canceling with the previously stored offset charge, the offset voltage Vos of the first-stage amplifier unit IA1 is eliminated for the first time. Combining with formula (3), the output of the first-stage amplifier unit IA1 is:

[0133] VOUT1 * C1 = Q1 - Qoff = A1 * (Vsig + Vos1) * C1 (7)

[0134] In Equation (7), VOUT1 represents the output signal after the signal is amplified by the first-stage amplifier unit IA1 under the control of CLK3; then, after being amplified by the second-stage amplifier unit IA2, it is stored in the capacitor C3 in the sample-and-hold unit 22.

[0135] At time T3, the first clock signal CLK1 is in the high-level state, the first switch K1 and the second switch K2 are closed and conducting, and the third switch K3 and the fourth switch K4 are open. The first-stage amplifier unit IA1 is short-circuited, which can prevent voltage mutations caused by phase conversion in the first amplifier OTA1 and the second amplifier OTA2 in the first-stage amplifier unit IA1 during the rotating current method, such as the spike pulse of the capacitor C1.

[0136] At time T4, the fourth clock signal CLK4 is in the high-level state, and the output signal of the Hall device 10 changes direction. At this time, the output voltage of the Hall device 10 is (-Vsig + Vos1), so the input voltage of IA1 is:

[0137] VIN2 = -Vsig + Vos1 + Vos (8)

[0138] In Equation (8), VIN2 represents the input voltage of the first-stage amplifier unit IA1 under the control of CLK4; the input voltage VIN2 of the first-stage amplifier unit IA1 has the opposite polarity to the input voltage VIN1 in Equation (4). The input voltage of the Hall device 10 during normal operation is amplified by the first-stage amplifier unit IA1 to be A1 * VIN2. After being canceled with the charge value stored on the capacitor connected to the output terminal of the first-stage amplifier unit IA1, combined with Equation (8), its output value is:

[0139] VOUT2 * C1 = A1 * VIN2 * C1 - A1 * C1 * Vos

[0140] = A1 * (-Vsig + Vos1) * C1 (9)

[0141] Thus, the offset voltage Vos of the first-stage amplifier unit IA1 is eliminated.

[0142] In Equation (9), VOUT2 represents the output signal amplified by the amplification unit 21 under the control of CLK4; VOUT2 is amplified by the IA2 circuit and stored in the capacitor C4 of the sample-and-hold unit 22.

[0143] At time T5, in the sample and hold unit 22, the charges in capacitor C3 and capacitor C4 are subtracted, and the offset voltage Vos1 of the Hall device 10 itself is eliminated, and the output is (modulation signal Vo) 2A1*A2*Vsig, where the sizes of capacitor C3 and capacitor C4 are the same; finally, the modulation signal Vo is compared with the reference voltage signal, and the comparison result is processed by the digital processing module 40 through logical control and transmitted to the output driving module 50 as a control signal.

[0144] During the operation of this system, the Hall voltage signal is amplified by the amplification unit 21 to eliminate the offset voltage (i.e., the offset voltage of the first-stage amplifier unit IA1) Vos of the offset elimination circuit 20, and then amplified. After passing through the sample and hold unit 22, the offset voltage Vos1 of the Hall device caused by temperature, process, mechanical stress, etc. is eliminated. Then, in the comparison module 30, the modulation signal Vo (i.e., the processed Hall voltage signal) is compared with the set reference voltage signal Vref. According to the comparison result, it is determined whether the output driving module 50 changes its state, and the output is latched by a latch, so that the output of the Hall device can maintain its original state in the sleep state, and the system can still operate normally under low voltage.

[0145] Among them, the clock widths of the first clock signal CLK1 and the second clock signal CLK2 are related to the offset elimination working time of the output signals VOUT1 and VOUT2 in the offset elimination circuit, and satisfy the settling time of each instrumentation amplifier circuit; the clock widths of the third clock signal CLK3 and the fourth clock signal CLK4 are determined by the time for the Hall device 10 to process the external magnetic field signal, and the fifth clock signal CLK5 is related to the settling time of the comparison module 30, and the settling time of the comparison module 30 is much longer than the settling time of the comparison module 30.

[0146] It should be noted that in the description of the present invention, it should be understood that the terms "upper", "lower", "inner", etc. indicating the orientation or positional relationship are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the components or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present invention.

[0147] In addition, in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the presence of additional identical elements in the process, method, article or device including the said element.

[0148] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly illustrating the present invention, rather than limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A low-voltage sensor system, characterized in that, Comprising: A Hall device that detects an external magnetic field signal and converts the magnetic field signal into a Hall voltage signal; An offset cancellation circuit for canceling the offset voltage in the Hall voltage signal and outputting a modulation signal; A comparison module connected to the offset cancellation circuit for comparing the modulation signal with a reference voltage signal; A digital processing module connected to the comparison module for outputting a control signal according to the comparison result of the comparison module; And An output driving module connected to the digital processing module for outputting a driving signal according to the control signal, The offset cancellation circuit includes: An amplification unit connected to the Hall device for canceling the offset voltage generated by the amplification unit itself and generating an amplified signal; A sample and hold unit connected to the amplification unit for canceling the offset voltage of the Hall device itself in the amplified signal and performing sample and hold to output the modulation signal; A timing control unit connected to the Hall device, the amplification unit and the sample and hold unit for providing a plurality of clock signals, Wherein, the amplification unit includes a first-stage amplifier unit and a second-stage amplifier unit. The first-stage amplifier unit is connected to the Hall device. The first-stage amplifier unit and the output capacitor connected thereto cancel the offset voltage generated by the amplification unit itself. The second-stage amplifier unit is connected to the first-stage amplifier unit and the sample and hold unit for realizing gain amplification of the amplified signal, The offset cancellation circuit uses a timing control signal. When the Hall device is not working, the first-stage amplifier unit stores the offset voltage generated by itself on the capacitor. When the Hall device is working, the first-stage amplifier unit neutralizes the operational amplifier offset voltage with the operational amplifier offset voltage stored on the capacitor to cancel the offset voltage generated by itself.

2. The low-pressure sensor system according to claim 1, wherein The first-stage amplifier unit includes: a first amplifier, a second amplifier, a first resistor, a second resistor and a third resistor, The non-inverting input terminals of the first amplifier and the second amplifier are respectively connected to the output terminal of the Hall device. A third resistor is connected between the inverting input terminals of the first amplifier and the second amplifier. The first resistor is connected between the inverting input terminal and the output terminal of the first amplifier. The second resistor is connected between the inverting input terminal and the output terminal of the second amplifier.

3. The low-pressure sensor system according to claim 1, wherein The second-stage amplifier unit includes: a third amplifier, a fourth amplifier, a fourth resistor, a fifth resistor and a sixth resistor, Wherein, the non-inverting input terminals of the third amplifier and the fourth amplifier are respectively connected to the output terminals of the first amplifier and the second amplifier. A sixth resistor is connected between the inverting input terminals of the first amplifier and the second amplifier. The fourth resistor is connected between the inverting input terminal and the output terminal of the third amplifier. The fifth resistor is connected between the inverting input terminal and the output terminal of the fourth amplifier, The output terminals of the third amplifier and the fourth amplifier are connected to the sample and hold unit to output the amplified amplified signal.

4. The low-voltage sensor system according to claim 3, characterized in that, The amplification unit further includes: A first capacitor connected between the output terminal of the first amplifier and the non-inverting input terminal of the third amplifier; A second capacitor is connected between the output terminal of the second amplifier and the non-inverting input terminal of the fourth amplifier.

5. The low-pressure sensor system according to claim 4, wherein The amplification unit further includes a first switch, a second switch, a third switch, and a fourth switch; Wherein, the first switch and the second switch are connected in series between the first amplifier and the non-inverting input terminal of the second amplifier, and are controlled by a first clock signal. A middle node of the first switch and the second switch receives a preset voltage; The third switch and the fourth switch are connected in series between the non-inverting input terminal of the third amplifier and the non-inverting input terminal of the fourth amplifier, and are controlled by a second clock signal. A middle node of the third switch and the fourth switch receives a common-mode input signal.

6. The low-pressure sensor system according to claim 1, characterized in that, The non-inverting input terminal of the comparison module receives the reference voltage signal, and the inverting input terminal is connected to the sample-and-hold unit to compare the modulation signal with the reference voltage signal and output a control signal.

7. The low-pressure sensor system according to claim 4, characterized in that, The plurality of clock signals include: a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal, Wherein, the timing control unit provides the third clock signal and the fourth clock signal to the Hall device, provides the first clock signal and the second clock signal to the amplification unit, and provides the third clock signal, the fourth clock signal, and the fifth clock signal to the sample-and-hold unit.

8. The low-pressure sensor system according to claim 7, wherein, When the third clock signal, the fourth clock signal, and the fifth clock signal are at a low level, and the first clock signal and the second clock signal are at a high level, the offset voltage generated by the first-stage amplifier unit is obtained and stored in the first capacitor and the second capacitor.

9. The low-pressure sensor system according to claim 7, wherein, When the first clock signal, the second clock signal, the fourth clock signal, and the fifth clock signal are at a low level, and the third clock signal is at a high level, the Hall device outputs a first Hall voltage signal. The first-stage amplifier unit outputs its own generated offset voltage and the first Hall voltage signal, which cancel out the offset voltage stored in the first capacitor and the second capacitor, generates a first amplified signal and outputs it to the sample-and-hold unit.

10. The low-pressure sensor system according to claim 7, characterized in that, When the second clock signal is at a low level and the first clock signal is at a high level, the first-stage amplifier unit is in a short-circuit state.

11. The low-pressure sensor system according to claim 9, wherein When the first clock signal, the second clock signal, the third clock signal, and the fifth clock signal are at a low level, and the fourth clock signal is at a high level, the Hall device outputs a second Hall voltage signal. The first-stage amplifier unit outputs its own generated offset voltage and the second Hall voltage signal, which cancel out the offset voltage stored in the first capacitor and the second capacitor, generates a second amplified signal, and outputs it to the sample-and-hold unit. Wherein, the second Hall voltage signal has a polarity opposite to that of the first Hall voltage signal.

12. The low-pressure sensor system according to claim 11, wherein, When the second clock signal, the third clock signal, and the fourth clock signal are at a low level, and the first clock signal and the fifth clock signal are at a high level, the sample-and-hold unit subtracts the first amplified signal and the second amplified signal, eliminates the offset voltage of the Hall device itself to generate the modulation signal and outputs it to the comparison module.

13. The low-pressure sensor system according to claim 1, wherein, The digital processing module is also connected to the timing control unit, and is configured to control the timing control unit to periodically output a first clock signal to a fifth clock signal.

14. The low-pressure sensor system according to claim 1, wherein The digital processing module includes a latch, and the latch is connected to the output end of the comparison module for latching the comparison result of the comparison module.

15. The low-voltage sensor system according to claim 2, wherein The amplification gain values of the first amplifier and the second amplifier are the same, and the resistance values of the first resistor and the second resistor are the same.

16. The low-voltage sensor system according to claim 4, characterized in that, The amplification gain values of the third amplifier and the fourth amplifier are the same, the resistance values of the fourth resistor and the fifth resistor are the same, and the capacitance values of the first capacitor and the second capacitor are the same.

17. The low-pressure sensor system according to claim 1, wherein The first-stage amplifier unit and / or the second-stage amplifier unit is an instrumentation amplifier unit.

18. The low-pressure sensor system according to claim 1, characterized in that, The amplification unit further includes at least a third-stage amplifier unit, and the third-stage amplifier unit is connected between the second-stage amplifier unit and the sample-and-hold unit.

19. A method for offset cancellation of a low-voltage sensor system, the low-voltage sensor system including a Hall device and an offset cancellation circuit, characterized in that, Including: Storing the offset voltage generated by the offset cancellation circuit; Detecting an external magnetic field signal and converting the magnetic field signal into a Hall voltage signal; Canceling the offset voltage generated by the offset cancellation circuit in the Hall voltage signal and generating an amplified signal; Canceling the offset voltage of the Hall device itself in the amplified signal, performing sample-and-hold, and outputting a modulation signal; Generating a drive signal according to the modulation signal.

20. The offset cancellation method according to claim 19, wherein, The step of generating a drive signal according to the modulation signal includes: Comparing the modulation signal with a reference voltage signal and outputting a comparison result; Generating a control signal according to the comparison result; Generating a drive signal according to the control signal.

21. The offset cancellation method according to claim 19, characterized in that, Further including: Providing a plurality of clock signals, and the plurality of clock signals at least include: a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal.

22. The offset cancellation method according to claim 21, wherein Before the step of detecting an external magnetic field signal and converting the magnetic field signal into a Hall voltage signal, further including: When the third clock signal, the fourth clock signal, and the fifth clock signal are at a low level, and the first clock signal and the second clock signal are at a high level, obtaining the offset voltage generated by the low-voltage sensor system and storing it.

23. The offset cancellation method according to claim 22, wherein The step of canceling the offset voltage generated by the low-voltage sensor system in the Hall voltage signal and generating an amplified signal includes: When the first clock signal, the second clock signal, the fourth clock signal, and the fifth clock signal are at a low level, and the third clock signal is at a high level, obtaining a first Hall voltage signal; Outputting the offset voltage generated by the low-voltage sensor system and the first Hall voltage signal, canceling them with the stored offset voltage, generating a first amplified signal and outputting it.

24. The offset cancellation method according to claim 23, wherein, The step of canceling the offset voltage generated by the low-voltage sensor system in the Hall voltage signal and generating an amplified signal further includes: When the first clock signal, the second clock signal, the third clock signal, and the fifth clock signal are at a low level, and the fourth clock signal is at a high level, obtaining a second Hall voltage signal; Outputting the offset voltage generated by the low-voltage sensor system and the second Hall voltage signal, canceling them with the stored offset voltage, generating a second amplified signal and outputting it. Among them, the second Hall voltage signal has a polarity opposite to that of the first Hall voltage signal.

25. The offset cancellation method according to claim 24, wherein The step of eliminating the offset voltage of the Hall device itself in the amplified signal, performing sample and hold, and outputting a modulation signal includes: When the second clock signal, the third clock signal, and the fourth clock signal are at a low level, and the first clock signal and the fifth clock signal are at a high level, perform a subtraction process on the amplified first amplified signal and second amplified signal to eliminate the offset voltage of the Hall device itself to generate the modulation signal and output it.

26. The offset cancellation method according to claim 21, wherein The control signal is further used to control the periodic output of the first clock signal to the fifth clock signal.

27. The offset cancellation method according to claim 20, characterized in that The step of generating a control signal according to the comparison result includes: Latch the comparison result between the modulation signal and the reference voltage signal.

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