Memory controller, operation method thereof, and memory system

Abstract

A memory controller with improved data reliability, a memory system including the memory controller, and a method for operating the memory controller are provided. The memory controller includes an error correction code (ECC) circuit configured to perform error detection on a codeword read from a memory device; and a processor configured to set at least one memory chip among a plurality of memory chips as an indicator chip, monitor error occurrence in the indicator chip based on a result of the error detection, and output reliability degradation information indicating reliability degradation of the memory device based on the monitoring result.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0139398 filed on November 13, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a memory controller, and more particularly, to a memory controller having improved data reliability, a memory system including the memory controller, and a method of operating the memory controller. Background Art

[0004] As nonvolatile memory devices, flash memory and resistive memory such as phase change RAM (PRAM), nano floating gate memory (NFGM), polymer RAM (PoRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM) and resistive RAM (RRAM) are known. The resistive memory has the nonvolatile characteristics of the flash memory, and the flash memory has the high-speed characteristics of the dynamic random access memory (DRAM).

[0005] As write cycles and / or erase cycles increase, the life of the resistive memory may be shortened. In this case, the reliability of the resistive memory may be degraded because data is not written to the resistive memory or data stored in the resistive memory is lost. In the event that data is lost while the resistive memory is being used, the performance of the entire system employing the resistive memory may be degraded. Summary of the invention

[0006] The inventive concept provides a memory controller capable of reducing the possibility of data loss and / or improving data reliability, a memory system including the memory controller, and a method of operating the memory controller.

[0007] According to one aspect of the inventive concept, there is provided a memory controller, comprising: an error correction code (ECC) circuit configured to perform error detection on a codeword read from a memory device; and a processor configured to set at least one memory chip among a plurality of memory chips as an indicator chip, monitor error occurrence in the indicator chip based on a result of the error detection, and output reliability degradation information indicating reliability degradation of the memory device based on a result of the monitoring.

[0008] According to another aspect of the inventive concept, there is provided a memory system comprising: a memory module including a plurality of memory chips mounted on a module board; and a memory controller configured to control memory operations of the plurality of memory chips of the memory module, set at least one memory chip of the plurality of memory chips as an indicator chip, and when it is determined that an error has occurred in the indicator chip based on a result of error detection of a code word read from the memory module, output reliability degradation information indicating that reliability degradation of the memory module has occurred.

[0009] According to another aspect of the inventive concept, a method for operating a memory controller is provided, the method comprising setting at least one memory chip among a plurality of memory chips as an indicator chip; monitoring error occurrence in the indicator chip based on a result of error detection of a code word read from a memory device; and, when an error occurs in the indicator chip, outputting reliability degradation information indicating reliability degradation of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a memory system including a memory device according to an example embodiment;

[0012] Figure 2A and Figure 2B It is shown that the Figure 1 A circuit diagram of an example of a memory cell array in a memory area of ​​;

[0013] Figure 3 It is shown Figure 1 A block diagram of an embodiment of a reliability determiner;

[0014] Figure 4 is a block diagram illustrating a memory system according to an example embodiment;

[0015] Figure 5 is a flowchart of a method of operating a memory controller according to an example embodiment;

[0016] Figures 6 to 9B are diagrams showing various embodiments for setting an indicator chip;

[0017] Fig.10 and Fig.11 is a flowchart illustrating an operation for outputting reliability degradation information according to an example embodiment;

[0018] Fig.12 and Fig.13is a diagram illustrating a method of operating a memory controller according to another modified example embodiment;

[0019] Fig.14 is a block diagram illustrating a memory system according to another modified example embodiment;

[0020] Fig.15 is a block diagram illustrating a memory system according to another modified example embodiment; and

[0021] Fig.16 is a block diagram illustrating an implementation of a memory controller according to example embodiments. DETAILED DESCRIPTION

[0022] Figure 1 is a block diagram showing a memory system including a memory device according to an example embodiment. In an example embodiment, the memory device 200 may be referred to as a resistive memory device because the memory device 200 includes a resistive memory cell. Alternatively, in an example embodiment, the memory device 200 may include various types of memory cells. Since the memory cells are arranged in an area where a plurality of first signal lines and a plurality of second signal lines intersect each other, the memory device 200 may be referred to as a cross-point memory device. In the following example embodiments, it will be assumed that the memory device 200 is a resistive memory device. However, the example embodiments may be applied to various types of memory devices whose reliability may deteriorate as write and / or erase cycles increase. For example, the example embodiments may be applied to various types of memory devices, such as volatile memory devices and flash memory devices.

[0023] Can be implemented in various forms Figure 1 . For example, the memory device 200 may be a device implemented as a single memory chip. Alternatively, the memory device 200 may be defined as a device including a plurality of memory chips.

[0024] refer to Figure 1 , the memory system 10 may include a memory controller 100 and a memory device 200. The memory device 200 may include a plurality of memory areas, for example, a first memory area 210_1 to an N-th memory area 210_N. The memory controller 100 may control memory operations for the first memory area 210_1 to the N-th memory area 210_N. For example, data of a specific unit may be written to the first memory area 210_1 to the N-th memory area 210_N in a distributed manner, or data of a specific unit may be read from the first memory area 210_1 to the N-th memory area 210_N.

[0025] According to example embodiments, the memory device 200 includes a plurality of memory chips, and each of the first to Nth memory regions 210_1 to 210_N may correspond to a memory chip. Each memory chip may include a memory cell array for storing data and a peripheral circuit (not shown) for performing a memory operation, such as a write / read circuit and a control logic.

[0026] According to example embodiments, the memory device 200 may include a memory module in which a plurality of memory chips are mounted on a module board. Alternatively, the memory device 200 may include a semiconductor package including a plurality of memory chips, the memory chips may be stacked in a die form within the semiconductor package, and each of the first to Nth memory regions 210_1 to 210_N may be a memory chip included in the semiconductor package.

[0027] Alternatively, the memory device 200 may include one semiconductor chip including a plurality of semiconductor layers. In this case, each of the first to N-th memory regions 210_1 to 210_N may be a semiconductor layer. Alternatively, when the memory device 200 includes one semiconductor layer and the semiconductor layer includes a memory cell array including a plurality of cell blocks, each of the first to N-th memory regions 210_1 to 210_N may be a cell block.

[0028] The memory controller 100 may include a processor 110, an error correction code (ECC) circuit 120, and / or a reliability determiner 130. Based on the control of the processor 110, the memory controller 100 may control memory operations using a hardware, software, and combination thereof based scheme.

[0029] The memory controller 100 may control the memory device 200 to read data stored in the memory device 200 or write data to the memory device 200 in response to a write / read request from the host. Specifically, the memory controller 100 may provide an address ADDR, a command CMD, and / or a control signal CTRL to the memory device 200, thereby controlling a program (or write) operation, a read operation, and an erase operation for the memory device 200. In addition, data DATA to be written and data DATA to be read may be transmitted and received between the memory controller 100 and the memory device 200.

[0030] Although not shown, the memory controller 100 may include a RAM, a host interface, and / or a memory interface. The RAM may be used as an operating memory for the processor 110. The processor 110 may control all operations of the memory controller 100. The host interface may include a protocol for performing data exchange between the host and the memory controller 100. For example, the memory controller 100 may be configured to communicate with an external device (e.g., a host) via various interface protocols, such as USB, MMC, PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, SCSI, ESDI, and Integrated Drive Electronics (IDE).

[0031] Each of the first to N-th memory regions 210_1 to 210_N may include a plurality of memory cells (not shown) respectively disposed in regions where a plurality of first signal lines and a plurality of second signal lines intersect each other. According to example embodiments, the first signal lines may be a plurality of bit lines, and the second signal lines may be a plurality of word lines. Each of the memory cells may be a single-level cell (SLC) (each single-level cell stores one bit of data) or a multi-level cell (MLC), each multi-level cell storing at least 2 bits of data.

[0032] When one bit of data is written into one memory cell, the memory cell may have two resistance distributions according to the written data. Alternatively, when two bits of data are written into one memory cell, the memory cell may have four resistance distributions according to the written data. In another embodiment, in the case of a three-level cell (TLC) (where three bits of data are stored in one memory cell), the memory cell may have eight resistance distributions according to the written data. However, the inventive concept is not limited thereto. In another embodiment, the memory cell may include a memory cell in which each memory cell is capable of storing four or more bits of data.

[0033] The first memory region 210_1 to the Nth memory region 210_N may include resistance memory cells each including a variable resistance element (not shown). For example, when the variable resistance element is a phase change material (GST, Ge-Sb-Te) and its resistance changes according to temperature, the resistance memory device may be a PRAM. In another example, when the variable resistance element includes a top electrode, a bottom electrode, and a composite metal oxide therebetween, the resistance memory device may be an RRAM. In another example, when the variable resistance element includes an upper electrode having a magnet, a lower electrode having a magnet, and a dielectric therebetween, the resistance memory device may be an MRAM.

[0034] The memory controller 100 may include an ECC circuit 120 for performing error detection and correction operations on data read from the memory device 200, and may provide the host with error-corrected read data. According to an example embodiment, the ECC circuit 120 may generate parity data through an ECC encoding process using normal data from the host, wherein the normal data and the parity data may constitute a codeword. In other words, the memory controller 100 may perform data write and read operations in units of codewords. In the following embodiments, the terms data DATA and codeword may be used interchangeably.

[0035] According to example embodiments, the reliability determiner 130 may determine the possibility of reliability degradation of the memory device 200 and output reliability degradation information Info_F according to the result of the determination. For example, the reliability determiner 130 may include an indicator setter 131, and the indicator setter 131 may be configured to set a memory region having relatively low reliability (or short life) among the first to N-th memory regions 210_1 to 210_N as an indicator.

[0036] Assuming that the first memory area is set as an indicator, the data DATA read from the first memory area having a relatively short life is more prone to error than the data DATA read from other memory areas. For example, before an error occurs in the data DATA read from other memory areas, an error may first occur in the data DATA read from the first memory area. The reliability determiner 130 monitors the occurrence of an error in the data DATA read from the first memory area, and may output reliability degradation information Info_F indicating that the reliability of the memory device 200 is degraded (or the life of the memory device 200 has ended) according to the monitoring result.

[0037] For example, the reliability determiner 130 may output the reliability degradation information Info_F by monitoring the error occurrence rate or bit error rate (BER) of the data DATA read from the first memory area. For example, the reliability determiner 130 may output the reliability degradation information Info_F when an error occurs in the data DATA read from the first memory area. Alternatively, the reliability determiner 130 may count the number of errors of the data DATA read from the first memory area, and output the reliability degradation information Info_F according to whether the error occurrence frequency exceeds a specific reference value. Alternatively, when the number of errors occurring in the data DATA of a specific size read from the first memory area exceeds a reference number, the reliability determiner 130 may output the reliability degradation information Info_F. Alternatively, the reliability determiner 130 may compare the error occurrence frequency of the data DATA read from the first memory area with the error occurrence frequency of other memory areas, and output the reliability degradation information Info_F based on the result of the comparison.

[0038] From the first memory area 210_1 to the Nth memory area 210_N, the indicator may be set in various ways. For example, the reliability of each of the first memory area 210_1 to the Nth memory area 210_N may be measured by a test process during the manufacturing process, and information indicating the reliability (e.g., life information) may be stored in the memory device 200. The memory controller 100 may set at least one memory area having relatively low reliability from the first memory area 210_1 to the Nth memory area 210_N as an indicator based on the life information provided from the memory device 200. Alternatively, the memory controller 100 may determine a relatively unreliable memory area from the first memory area 210_1 to the Nth memory area 210_N by controlling the memory device 200, or the memory controller 100 may artificially degrade the reliability of any memory area from the first memory area 210_1 to the Nth memory area 210_N. In addition, at least one memory area from the first memory area 210_1 to the Nth memory area 210_N may be set as an indicator by various methods.

[0039] For example, when the memory device 200 is a device including a plurality of memory chips, at least one memory chip may be set as an indicator, and the memory chip set as an indicator may be referred to as an indicator chip.

[0040] The memory controller 100 can predict the possibility that actual data may actually be lost from the memory device 200 and provide the reliability degradation information Info_F to the host HOST before the data may actually be lost. Therefore, information indicating that the memory device 200 needs to be replaced can be provided to the user at an appropriate time.

[0041] In the above-described embodiment, the degradation of the reliability of the memory device 200 may be described as degradation or failure of the endurance of the memory device 200 , and thus the memory controller 100 may be described as monitoring the error occurrence of the indicator chip and outputting endurance failure information.

[0042] According to example embodiments, the possibility of data loss can be predicted in a memory device (e.g., a resistive memory) in which sudden data loss may occur when a write and / or erase cycle is performed, and the possibility of data loss is notified to a host, and thus data reliability can be improved. In addition, a method of counting the number of write and / or erase operations can be used as a method of determining the reliability of a plurality of memory regions of the memory device 200. According to example embodiments, it is not necessary to provide a counter for determining the life of a memory region, and thus an increase in area or an increase in power consumption due to the implementation of a counter can be avoided.

[0043] The memory controller 100 and the memory device 200 may be implemented as separate semiconductor devices. Alternatively, the memory controller 100 and the memory device 200 may be integrated into one semiconductor device. For example, the memory controller 100 and the memory device 200 may be integrated into a single semiconductor device and constitute a memory card. For example, the memory controller 100 and the memory device 200 may be integrated into a single semiconductor device and constitute a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM / SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, MMCmicro, etc.), an SD card (e.g., SD, mini SD, micro SD, etc.), a universal flash memory (UFS), etc. In another example, the memory controller 100 and the memory device 200 may be integrated into a single semiconductor device and constitute a solid state disk / drive (SSD).

[0044] Figure 2A and Figure 2B It is shown that the Figure 1 A circuit diagram of an example of a memory cell array in a memory area of ​​. Figure 2A and Figure 2B In FIG. 1 , a case where the resistance memory cell includes a PRAM is exemplified.

[0045] For example, the memory cell array of the first memory area 210_1 may be a two-dimensional memory cell array having a horizontal structure, and may include a plurality of word lines WL1 to WLn, a plurality of bit lines BL1 to BLm, and a plurality of memory cells MC. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells arranged in rows and columns. Here, according to an embodiment, the number of word lines WL, the number of bit lines BL, and the number of memory cells MC may vary. However, the inventive concept is not limited thereto. According to another embodiment, the memory cell array of the first memory area 210_1 may be a vertical three-dimensional memory cell array.

[0046] According to some example embodiments, each of the memory cells MC may include a variable resistance element R and a switch element SW. Here, the variable resistance element R may be referred to as a variable resistance material, and the switch element SW may be referred to as a selection element.

[0047] In some example embodiments, the variable resistance element R may be connected between one of the bit lines BL1 to BLm and the switch element SW, and the switch element SW may be connected between the variable resistance element R and one of the word lines WL1 to WLn. However, the inventive concept is not limited thereto, and the switch element SW may be connected between one of the bit lines BL1 to BLm and the variable resistance element R, and the variable resistance element R may be connected to the switch element SW and one of the word lines WL1 to WLn.

[0048] The switch element SW may be connected between any one of the word lines WL1 to WLn and the variable resistance element R, and may control current supply to the variable resistance element R according to voltages applied to the word line and the bit line connected to the switch element SW. Figure 2A It is shown that the switching element SW is a diode, but it is merely an embodiment. According to some example embodiments, the switching element SW may be changed to another switchable element.

[0049] refer to Figure 2B , the memory cell MC may include a variable resistance element R and a switch element SW. The switch element SW may be implemented using various elements such as a transistor, a diode, etc. The variable resistance element R may include a phase change film 11 (the phase change film 11 includes a mixture of germanium, antimony, and tellurium (GST, Ge-Sb-Te)), an upper electrode 12 on the phase change film 11, and a lower electrode 13 under the phase change film 11.

[0050] The upper electrode 12 and the lower electrode 13 may include various metals, metal oxides or metal nitrides. The upper electrode 12 and the lower electrode 13 may include aluminum (Al), copper (Cu), titanium nitride (TiN), titanium aluminum nitride (TiN), x Al y Nz ), iridium (Ir), platinum (Pt), silver (Ag), gold (Au), polysilicon, tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), nickel (Ni), cobalt (Co), chromium (Cr), antimony (Sb), iron (Fe), molybdenum (Mo), palladium (Pd), tin (Sn), zirconium (Zr), zinc (Zn), iridium oxide (IrO 2 ), strontium oxide zirconate (StZrO 3 )wait.

[0051] The phase change film 11 may include a bipolar resistance memory material or a unipolar resistance memory material. The bipolar resistance memory material may be programmed to a set state or a reset state according to the polarity of the current, and may include a perovskite-based material. The unipolar resistance memory material may be programmed to a set state or a reset state by a current of the same polarity, and may include a transition metal oxide such as NiO. x or TiO x .

[0052] The GST material can be programmed between an amorphous state with a relatively high resistivity and a crystalline state with a relatively low resistivity. The GST material can be programmed by heating the GST material. Based on the magnitude and time of heating the GST material, the GST material can remain in the amorphous state or the crystalline state. The high resistivity and the low resistivity can be represented by programmed logical values ​​0 and 1, respectively, and can be detected by measuring the resistivity of the GST material. Conversely, the high resistivity and the low resistivity can be represented by programmed logical values ​​1 and 0, respectively.

[0053] exist Figure 2B In the embodiment, when the write current I is applied to the memory cell MC, the write current I flows through the lower electrode 13. When the write current I is applied to the memory cell MC for a very short time, the film adjacent to the lower electrode 13 is heated by Joule heat. At this time, due to the difference in the heating profile, a part of the phase change film 11 becomes a crystalline state (or a set state) or an amorphous state (or a reset state).

[0054] Figure 3 It is shown Figure 1 1 is a block diagram of an embodiment of a reliability determiner 130.

[0055] refer to Figure 1 and Figure 3 , the reliability determiner 130 may include an indicator setter 131, an error region determiner 132 and / or a reliability determination logic 133. The indicator setter 131 may set at least one memory region of the first to Nth memory regions 210_1 to 210_N as an indicator according to the above-described embodiments.

[0056] The error region determiner 132 may determine a memory region (or a location of a memory region) where an error occurs during a memory operation for the memory device 200. For example, error detection and correction are performed for a codeword read from the first memory region 210_1 to the Nth memory region 210_N of the memory device 200, and the error region determiner 132 may determine a region where an error occurs by referring to a result of error detection from the ECC circuit 120. For example, a plurality of bits constituting a codeword may be stored in a distributed manner in the first memory region 210_1 to the Nth memory region 210_N, and the location of a memory region where an error occurs in the first memory region 210_1 to the Nth memory region 210_N may be determined by detecting bits having an error. The error region determiner 132 may output error location information Info_P according to a result of the determination.

[0057] The reliability determination logic 133 may receive the indicator position information Info_I indicating the memory area corresponding to the indicator from the indicator setter 131, and simultaneously receive the error position information Info_P from the error area determiner 132. In addition, the reliability determination logic 133 may output the reliability degradation information Info_F indicating whether the reliability of the memory device 200 is degraded based on the indicator position information Info_I and the error position information Info_P. For example, as described above, the reliability determination logic 133 may determine the error occurrence frequency in the memory area corresponding to the indicator based on the indicator position information Info_I and the error position information Info_P, and may also determine whether the error occurrence frequency exceeds a specific reference value Nref. In addition, the reliability determination logic 133 may output the reliability degradation information Info_F according to the result of the determination. In various examples, when the error occurrence frequency in the memory area corresponding to the indicator exceeds a specific reference value, the reliability determination logic 133 may output the reliability degradation information Info_F indicating the reliability degradation of the memory device 200 (or the end of the life of the memory device 200).

[0058] Can be implemented in various forms Figure 3 The various components shown in the figure perform corresponding functions. For example, Figure 3 The various components shown in may be implemented as hardware circuits or software including programs that can be executed by processor 110. Alternatively, Figure 3 The various components shown in may be implemented as a combination of hardware and software.

[0059] Hereinafter, various implementations of a memory system according to example embodiments will be described. In addition, it will be assumed in the following embodiments that the memory device is a memory module including a plurality of memory chips. However, the memory device may be implemented in various other forms as described above.

[0060] Figure 4 is a block diagram illustrating a memory system according to example embodiments.

[0061] refer to Figure 4 , the memory system 300 may include a memory controller 310 and a memory module 320. The memory controller 310 may include an ECC circuit 311 and / or a reliability determiner 312. Figure 4 Although not shown in FIG. 3 , the memory controller 310 may also include various other components for controlling memory operations, such as a processor, a host I / F, and a memory I / F.

[0062] The memory module 320 may include a plurality of memory chips mounted on a module board. For example, the memory module 320 may include a first memory chip 321_1 to an Nth memory chip 321_N. In addition, according to the above-described embodiment, the reliability determiner 312 may set at least one memory chip among the first memory chip 321_1 to the Nth memory chip 321_N as an indicator chip. Figure 4 , an example of setting the Nth memory chip 321_N as an indicator chip is shown. For example, the reliability determiner 312 may set the indicator chip based on the reliability information about the first memory chip 321_1 to the Nth memory chip 321_N from the memory module 320, or set the indicator chip through a test operation for the first memory chip 321_1 to the Nth memory chip 321_N or a number of pseudo programming operations for a specific memory chip. Although Figure 4 It is shown that the Nth memory chip 321_N storing the parity data Parity corresponds to an indicator chip, but normal data may be stored in the Nth memory chip 321_N.

[0063] The ECC circuit 311 of the memory controller 310 may generate parity data Parity through an ECC encoding operation, and a codeword including normal data DATA and the parity data Parity may be stored in a distributed manner in the first to Nth memory chips 321_1 to 321_N. In addition, the codeword may be read from the first to Nth memory chips 321_1 to 321_N and provided to the ECC circuit 311. The ECC circuit 311 may perform an error detection operation through an ECC decoding operation and provide the result thereof to the reliability determiner 312.

[0064] The reliability determiner 312 may determine whether an error has occurred in the Nth memory chip 321_N corresponding to the indicator chip based on information about the indicator chip set therein and the error detection result from the ECC circuit 311. When an error has occurred in a memory chip other than the Nth memory chip 321_N, the reliability determiner 312 may determine that since an error has occurred in a memory chip having relatively high reliability and a long life, there is no influence on the reliability of the memory module 320. On the other hand, when an error has occurred in the Nth memory chip 321_N corresponding to the indicator chip, the reliability determiner 312 may determine that the error has occurred due to the short life of the memory module 320, and therefore, the reliability determiner 312 may output reliability degradation information Info_F.

[0065] according to Figure 4 According to some example embodiments shown in , it is not necessary to provide a counter for counting the number of write and / or erase operations to manage the lifespan of a plurality of memory chips mounted on the memory module 320, and by setting a memory chip with relatively low reliability as an indicator chip and monitoring it, the possibility of data reliability degradation can be notified to the host before the end of the lifespan of the memory module 320. In other words, before the data stored in the memory chip is actually lost, it can be determined in advance that the lifespan of the memory module 320 is about to end by the indicator chip with a relatively short lifespan, and the reliability degradation information Info_F can be provided to the host to urge the user to replace the memory module 320.

[0066] In some of the above-mentioned example embodiments, the memory module 320 may be implemented in the form of a single in-line memory module (SIMM) or a dual in-line memory module (DIMM). In addition, the memory module 320 may correspond to various types of DIMMs. For example, various types of DIMMs such as FB-DIMMs and LR-DIMMs may be applied to the memory module 320. Alternatively, the memory module 320 may correspond to a non-volatile DIMM (NVDIMM) including a non-volatile memory (e.g., a flash memory (not shown)) to compensate for the problem of data loss when the power of the volatile memory is turned off.

[0067] In addition, as an example of various types of modules, when the memory module 320 includes a PRAM as a resistive memory, the memory module 320 may be referred to as a P_DIMM. Example embodiments may also be applied to various other types of modules. For example, when the memory module 320 includes a cross-point memory chip having a three-dimensional resistive memory cell, the memory module 320 may be referred to as a cross-point (XPoint) DIMM (or 3D cross-point DIMM).

[0068] Figure 5 is a flowchart of a method of operating a memory controller according to example embodiments.

[0069] refer to Figure 5 , the memory controller can control memory operations for multiple memory chips, determine a memory chip with relatively low reliability (or relatively short life) from the memory chips, and set at least one memory chip as an indicator chip according to the determination result (operation S11).

[0070] The memory controller may read the codeword from the memory chip and detect an error through an ECC decoding process for the codeword (operation S12). In addition, by detecting the position of an error bit from a plurality of bits included in the codeword, the memory controller may determine a memory chip in which an error has occurred.

[0071] Based on the information about the memory chip in which an error has occurred (or is detected) and the information about the indicator chip previously stored therein, the memory controller may determine whether the memory chip in which an error has occurred (or is detected) corresponds to the indicator chip (operation S13). When the memory chip in which an error has occurred (or is detected) is not the indicator chip, it may be repeatedly determined whether an error has occurred in the indicator chip for the next read codeword.

[0072] When a memory chip in which an error has occurred (or detected) corresponds to an indicator chip, it can be determined whether the error occurrence frequency in the indicator chip exceeds a specific reference value (operation S14). In addition, when the error occurrence frequency exceeds a specific reference value, the memory controller can output reliability degradation information (operation S15). The operation for determining whether the reference value is exceeded and the operation for outputting reliability degradation information according to the example embodiment can be implemented by various methods. For example, reliability degradation information can be output whenever an error occurs in the indicator chip. Alternatively, reliability degradation information can be output when the errors that occur continuously in the indicator chip exceed the reference value. Alternatively, reliability degradation information can be output when the error occurrence frequency in the indicator chip exceeds a specific reference value during a certain number of read operations. In addition, various other methods can be used to set other criteria for outputting reliability degradation information.

[0073] Figure 6 is a block diagram illustrating a memory system according to a modified example embodiment. Figure 6 A case where the indicator chip is set based on reliability information previously stored in the memory module is shown.

[0074] refer to Figure 6, the memory system 400 may include a memory controller 410 and a memory module 420. The memory module 420 may include first to Nth memory chips 421_1 to 421_N, and may set at least one memory chip as an indicator chip under the control of the memory controller 410.

[0075] For example, the performance of each of the first to N-th memory chips 421_1 to 421_N may be tested during the manufacturing process of the memory module 420, and the reliability of the first to N-th memory chips 421_1 to 421_N may be determined based on the results of the tests (e.g., the number of write and / or erase operations with guaranteed reliability is determined). Moreover, life information (or reliability information) based on the results of the tests may be stored in the memory module 420. The reliability information Info_Reli 1 to Info_Reli N from the memory module 420 may be provided to the memory controller 410 during the initial operation of the memory system 400.

[0076] The memory controller 410 may include a reliability determiner 411, and the reliability determiner 411 may include an indicator setter 411_1. The indicator setter 411_1 may set at least one memory chip as an indicator chip in the memory module 420 based on the reliability information Info_Reli 1 to Info_Reli N. Figure 6 An example in which the second memory chip 421_2 is set as an indicator chip according to the result of determining the reliability information Info_Reli 1 to Info_Reli N is shown.

[0077] The indicator setter 411_1 may store information Info_Chip2 indicating that the second memory chip 421_2 corresponds to the indicator chip according to the setting result, and output reliability degradation information by comparing a memory chip in which an error has occurred among the first to Nth memory chips 421_1 to 421_N with the information Info_Chip2 during a read operation for the memory module 420 .

[0078] Figure 7 is a flowchart of a method of operating a memory controller according to a modified example embodiment. Figure 7 An example of setting the indicator chip through an initial test operation for a memory module is shown.

[0079] When the memory system including the memory controller and the memory module is initially operated (operation S21), various information about the memory operation can be sent and received between the memory controller and the memory module. In addition, the memory controller can perform an initial test operation on the memory chip of the memory module (operation S22). For example, the memory controller can write a specific test mode to the memory chip, read the test mode, and determine the reliability of the memory chip by an error detection operation for the test mode. For example, the memory controller can determine the bit error rate (BER) of each of the memory chips through the initial test operation (operation S23), and can determine the memory chip with relatively low reliability by determining the BER. In addition, one or more memory chips with relatively high BER can be set as indicator chips (operation S24).

[0080] According to some example embodiments, even when life information about a memory chip is not stored in a memory module, a memory chip with relatively low reliability may be determined through an initial test operation of a memory controller, and an operation for setting an indicator chip may be performed based on the determined result.

[0081] although Figure 7 An example of setting the indicator chip based on BER is shown, but the example embodiment is not limited thereto, and the indicator chip may be set based on various criteria. For example, the error occurrence frequency may be detected with respect to a plurality of memory chips, and the memory chip corresponding to the highest error occurrence frequency may be set as the indicator chip. As described above, Figure 1 and Figure 3 A reliability determiner 130, Figure 4 The reliability determiner 312 and Figure 6 The functionality of the reliability determiner 411 may be implemented in the processor 110, or as separate hardware and / or processor / software components.

[0082] Figure 8 is a flowchart of a method of operating a memory controller according to another modified example embodiment. Figure 8 An example is shown in which a memory chip having artificially deteriorated reliability is set as an indicator chip based on control of a memory controller.

[0083] refer to Figure 8, the memory controller may control memory operations of a memory module including a plurality of memory chips, for example, a pseudo programming operation for writing dummy data having an arbitrary pattern into the plurality of memory chips. According to example embodiments, when there is no information about a memory chip having relatively low reliability among the plurality of memory chips, the memory controller may perform an artificial control operation for degrading the reliability of at least one of the memory chips and set the memory chip having degraded reliability as an indicator.

[0084] For example, the memory controller may select one or more memory chips from a plurality of memory chips (operation S31), and perform a plurality of pseudo programming operations on the selected memory chips (operation S32). The pseudo programming operation may be repeatedly performed until the life of the selected memory chip is slightly degraded, and the memory controller may set the memory chip on which the pseudo programming operation is performed as an indicator chip (operation S33).

[0085] When the pseudo programming operation is performed multiple times on the first memory chip in the memory chips, the write count of the first memory chip becomes greater than the write counts of the other memory chips. Therefore, the first memory chip may have a shorter life than the other memory chips. Moreover, by setting the first memory chip as an indicator chip, the possibility of data loss in the memory module can be reduced.

[0086] Fig. 9A and Fig. 9B is a block diagram illustrating a method of operating a memory controller according to another modified example embodiment. Fig. 9A and Fig. 9B The case where interleaving is applied to operations for writing and reading codewords and the case where interleaving is not applied are respectively shown.

[0087] refer to Fig. 9A , the memory system 500A may include a memory controller 510A and a memory module 520A. The memory controller 510A may include an ECC circuit 511A, a reliability determiner 512A and / or an interleaver 513A. The ECC circuit 511A and the reliability determiner 512A may perform operations that are the same as or similar to the operations according to the above-described embodiments, thereby outputting reliability degradation information according to the example embodiment. In addition, the memory module 520A may include a first memory chip 521A_1 to an N-th memory chip 521A_N, and the reliability of the first memory chip 521A_1 to the N-th memory chip 521A_N may be determined according to the above-described embodiments, and it is assumed that the second memory chip 521A_2 corresponds to a memory chip with relatively low reliability (relatively short life).

[0088] The memory controller 510A may store the codeword including normal data and parity data in the first memory chip 521A_1 to the Nth memory chip 521A_N of the memory module 520A. At this time, the interleaver 513A may interleave a plurality of bits of the codeword to normalize the position of the error bit, and the interleaved bits of the codeword may be stored in the first memory chip 521A_1 to the Nth memory chip 521A_N. For example, the parity data Parity 1 in the first codeword may be stored in the Nth memory chip 521A_N, and the normal data DATA1_1 and DATA1_2 may be stored in other memory chips. On the other hand, the parity data Parity 2 in the second codeword may be stored in the second memory chip 521A_2, and the normal data DATA2_1 and DATA2_2 may be stored in other memory chips.

[0089] exist Fig. 9A In some example embodiments shown in , when interleaving is applied to the memory module 520A, the usage frequencies of the first memory chip 521A_1 to the Nth memory chip 521A_N can become similar to each other. For example, even when normal data is only partially changed in one codeword, parity data corresponding to the normal data is changed together. Therefore, the usage frequency (or write count) of the memory chip storing parity data can be increased compared to other memory chips. However, due to Fig. 9A In the illustrated embodiment, the usage frequencies of the first to N-th memory chips 521A_1 to 521A_N are similar to each other, so the second memory chip 521A_2 having relatively low reliability (relatively short life) may be set as an indicator chip.

[0090] refer to Fig. 9B, the memory system 500B may include a memory controller 510B and a memory module 520B, the memory controller 510B may include an ECC circuit 511B and / or a reliability determiner 512B, and the memory module 520B may include a first memory chip 521B_1 to an Nth memory chip 521B_N. The memory controller 510B may store bits at a specific position of a codeword in a specific memory chip of the memory module 520B, and interleaving is not applied when the codeword is stored in the memory module 520B. For example, the parity data of the codeword may be fixedly stored in the Nth memory chip 521B_N of the memory module 520B. For example, the parity data Parity1 in the first codeword may be stored in the Nth memory chip 521B_N, and the normal data DATA1_1 and DATA1_2 may be stored in other memory chips. In addition, the parity data Parity 2 in the second codeword may be stored in the Nth memory chip 521B_N, and the normal data DATA2_1 and DATA2_2 may be stored in other memory chips.

[0091] As described above, the Nth memory chip 521B_N storing parity data Parity 1 and Parity 2 is used more frequently than other memory chips, so the life of the Nth memory chip 521B_N may be shorter than the life of other memory chips. Therefore, the memory controller 510B may determine the Nth memory chip 521B_N to store parity data Parity 1 and Parity 2, and set the Nth memory chip 521B_N as an indicator chip. In addition, by performing an error detection operation on a read codeword, the frequency of error occurrence in the Nth memory chip 521B_N may be monitored, and reliability degradation information according to the above embodiment may be output based on this.

[0092] Fig.10 and Fig.11 is a flowchart illustrating an operation for outputting reliability degradation information according to an example embodiment. Fig.10 An example of outputting reliability degradation information based on BER is shown, and Fig.11 An example of outputting reliability degradation information based on the error occurrence frequency of the indicator chip compared with the error occurrence frequency of the normal memory chip is shown.

[0093] refer to Fig.10 , a code word may be read by a read operation on a memory module including a plurality of memory chips, and an error detection operation on the code word may be performed (operation S41). In addition, it may be determined whether an error has occurred in the indicator chip by comparing pre-stored information about the indicator chip with a memory chip in which an error has occurred (operation S42).

[0094] When an error has occurred in the indicator chip, the number of errors occurring in data of a specific size may be detected, and it may be determined whether the number of detected errors exceeds a specific threshold value (operation S43). When the number of detected errors is equal to or less than a reference value, it may be determined that the reliability of the memory module has not deteriorated. On the other hand, when the number of detected errors exceeds the reference value, it may be determined that the reliability of the memory module has deteriorated, and thus reliability degradation information may be output (operation S44).

[0095] refer to Fig.11 , an error detection operation on a codeword read from a memory module including a plurality of memory chips may be performed (operation S51), and information about an error occurrence in the memory chip (e.g., error information) may be stored in a memory controller (operation S52). In addition, the reliability of the memory module may be periodically determined, and it may be determined whether it corresponds to the reliability determination timing (operation S53).

[0096] At the reliability determination timing, by referring to the error information stored in the memory controller, the error occurrence frequency of the indicator chip can be compared with the error occurrence frequency of the normal memory chip (operation S54). For example, a comparison value can be calculated as a result of comparing the error occurrence frequency of the indicator chip with the error occurrence frequency of the normal memory chip, and it can be determined whether the comparison value exceeds a specific reference value (operation S55). When the comparison value exceeds the specific reference value, reliability degradation information can be output (operation S56).

[0097] Reliability degradation information may be output based on various criteria other than the method described in the above embodiment. In other words, the characteristics of error occurrence in the indicator chip are determined, and whether to output reliability degradation information may be controlled based on various criteria. For example, when the error occurrence frequency of the indicator chip is greater than the error occurrence frequency of other memory chips among the plurality of memory chips by a specific ratio, reliability degradation information may be output.

[0098] Fig.12 and Fig.13 is a diagram illustrating a method of operating a memory controller according to another modified example embodiment.

[0099] refer to Fig.12, the memory system 600 may include a memory controller 610 and a memory module 620. The memory controller 610 may include an ECC circuit 611 and / or a reliability determiner 612, and the reliability determiner 612 may include an indicator setting and / or modifying circuit 612_1. In addition, the memory module 620 may include a first memory chip 621_1 to an Nth memory chip 621_N. Fig.12 An example is shown in which the (N-1)th memory chip 621_(N-1) is set as an indicator chip. According to the above embodiment, the (N-1)th memory chip 621_(N-1) may correspond to a memory chip having the lowest reliability in the memory module 620 or a memory chip in which parity data of codeword data is fixedly stored.

[0100] Each of the first to N-th memory chips 621_1 to 621_N includes a plurality of cell blocks for storing data. For example, the (N-1)th memory chip 621_(N-1) may include first to K-th cell blocks BLK 1 to BLK K. According to example embodiments, the first to K-th cell blocks BLK 1 to BLK K of the (N-1)th memory chip 621_(N-1) may be used sequentially or together, and an operation for determining a location of an error to output reliability degradation information according to example embodiments may be performed on a cell block basis.

[0101] According to an example embodiment, when the first cell block BLK 1 of the (N-1)th memory chip 621_(N-1) may be set as an indicator region, it may be monitored whether an error has occurred in the first cell block BLK 1. When an error has occurred in the first cell block BLK 1, reliability degradation information may be output according to the various standards in the above-described embodiments, and the indicator setting and / or modifying circuit 612_1 may set another cell block of the (N-1)th memory chip 621_(N-1) as an indicator region. In addition, when an error occurrence in the changed indicator region is monitored and the error occurrence frequency in the changed indicator region exceeds a specific reference value, another cell block may be set as an indicator region.

[0102] Now refer to Fig.13 describe Fig.12. The first cell block BLK 1 of the (N-1)th memory chip 621_(N-1) may be set as an indicator region (operation S61), and it may be determined whether the error occurrence frequency of the first cell block BLK 1 exceeds a preset reference value (operation S62). When the error occurrence frequency in the first cell block BLK 1 exceeds the reference value, first reliability degradation information may be output (operation S63), and, as another cell block of the (N-1)th memory chip 621_(N-1), the second cell block BLK 2 may be set as an indicator region (operation S64).

[0103] Then, it can be determined whether the error occurrence frequency in the second cell block BLK2 set as the indicator area exceeds the preset reference value (operation S65), and when the error occurrence frequency in the second cell block BLK2 exceeds the reference value, the second reliability degradation information can be output (operation S66). In addition, in the same aspect as the above operation, another cell block of the (N-1)th memory chip 621_(N-1) can be set as the indicator area, the error occurrence of the Kth cell block BLKK of the (N-1)th memory chip 621_(N-1) set as the indicator area can be monitored, and when the error occurrence frequency of the Kth cell block BLK K exceeds the preset reference value, the Kth reliability degradation information can be output (operation S67).

[0104] According to the above-described example embodiments, the degree of reliability degradation can be classified into multiple stages and determined. For example, when the first reliability degradation information is output, the user can determine that the reliability is degraded in any one of the K cell blocks of the indicator chip, and when the second reliability degradation information is output thereafter, the user can determine that the reliability of the two cell blocks of the indicator chip is degraded. Thereafter, when the reliability degradation information for the last K-th cell block BLK K is output, the reliability degradation of all cell blocks of the indicator chip can be determined. Based on this, the need to replace the memory module can be determined in multiple stages.

[0105] Fig.14 is a block diagram illustrating a memory system according to another modified example embodiment.

[0106] refer to Fig.14 , the memory system 700 may include a memory controller 710 and a memory module 720. The memory controller 710 may include an ECC circuit 711 and / or a reliability determiner 712, and the reliability determiner 712 may include an indicator setting and / or modifying circuit 712_1. In addition, the memory module 720 may include a first memory chip 721_1 to an Nth memory chip 721_N. Fig.14An example of setting the Nth memory chip 721_N as the indicator chip during the initial indicator chip setting operation is shown. In addition, according to example embodiments, a memory chip storing parity data may be set as an indicator chip, wherein the first parity data Parity 1 included in the first codeword may be stored in the Nth memory chip 721_N, and the normal data DATA1_1 to DATA1_(N-1) included in the first codeword may be stored in other memory chips.

[0107] According to the above embodiment, the occurrence of errors in the Nth memory chip 721_N corresponding to the indicator chip can be monitored, and reliability degradation information can be output according to the monitoring result. In addition, as the reliability of the Nth memory chip 721_N deteriorates, the memory chip storing parity data can be changed, and the memory chip storing parity data can be set as the indicator chip again. Fig.14 In the illustrated example, the memory chip storing parity data is changed to the (N-1)th memory chip 721_(N-1), and thus the indicator chip is changed to the (N-1)th memory chip 721_(N-1).

[0108] According to the above-mentioned change of the indicator chip, the second parity data Parity 2 included in the second codeword can be stored in the (N-1)th memory chip 721_(N-1), and the normal data DATA2_1 to DATA2_(N-1) can be stored in other memory chips. In addition, the error occurrence in the (N-1)th memory chip 721_(N-1) corresponding to the indicator chip can be monitored by an error detection operation on the second codeword read from the memory module 720. When an error occurs in the (N-1)th memory chip 721_(N-1), reliability degradation information can be output according to the above-mentioned embodiment. Moreover, similar to the above-mentioned embodiment, the indicator chip can be changed to another memory chip.

[0109] according to Fig.14 Some of the example embodiments shown in Fig.12 and Fig.13 The embodiment similarly determines the degree of reliability in multiple stages. For example, when reliability degradation information is output multiple times by changing the indicator chip, compared with the case where reliability degradation information is output once, it can be determined that the reliability of the memory module 720 is further deteriorated, and the user can determine the need to replace the memory module 720 by referring to the degree of reliability degradation.

[0110] although Fig.14Some example embodiments are shown in which a memory chip storing parity data is changed and an indicator chip is changed based on the change of the memory chip, but the example embodiments are not necessarily limited thereto. For example, a memory chip with relatively low reliability may be determined by reliability information from the memory module 720 or a test operation or a pseudo programming operation of the memory controller 710, wherein the memory chip with the lowest reliability may be set as the initial indicator chip, and a memory chip with the second lowest reliability may be changed to the indicator chip.

[0111] on the other hand, Fig.14 The embodiment shown in can be combined with the above Fig.12 and Fig.13 For example, the Nth memory chip 721_N may include a plurality of unit blocks, and an error occurrence monitoring operation and a reliability degradation information output operation may be performed on each unit block, and after outputting reliability degradation information according to a result of monitoring one or more unit blocks of the Nth memory chip 721_N, the indicator chip may be changed to the (N-1)th memory chip 721_(N-1).

[0112] Fig.15 is a block diagram showing a memory system according to another modified example embodiment. Fig.15 , an example of performing ECC encoding and decoding processing within a memory module is shown.

[0113] refer to Fig.15 , the memory system 800 may include a memory controller 810 and a memory module 820. The memory controller 810 may include a reliability determiner 811, and the reliability determiner 811 may include an indicator setter 811_1. In addition, the memory module 820 may include a first memory chip 821_1 to an N-th memory chip 821_N, and may further include a buffer chip 822 including an ECC circuit 822_1. The buffer chip 822 may be mounted on the memory module 820 to perform various functions, and may include a storage circuit (not shown) for temporarily storing commands and addresses through communication with the memory controller 810. In addition, the ECC circuit 822_1 of the buffer chip 822 may generate parity data using normal data from the memory controller 810, and may also generate an error detection result Res_ECC by an ECC decoding process of a codeword read out from the first memory chip 821_1 to the N-th memory chip 821_N of the memory module 820.

[0114] The reliability determiner 811 may set at least one memory chip among the first memory chip 821_1 to the Nth memory chip 821_N as an indicator chip, and may receive an error detection result Res_ECC when receiving a codeword from the memory module 820. The reliability determiner 811 may include information about the memory chip set as the indicator chip, and may determine the location of the memory chip where an error has occurred by using the error detection result Res_ECC. In addition, the reliability determiner 811 may monitor the error occurrence frequency in the indicator chip and output reliability degradation information according to the above-mentioned embodiment. As described above, Figure 1 , Figure 4 , Figure 6 , Fig. 9A , Fig. 9B , Fig.12 , Fig.14 and Fig.15 The functionality of the memory controllers 100, 310, 410, 510A, 510B, 610, 710, 810 may be implemented in the processor 110, or as separate hardware and / or processor / software components.

[0115] Fig.16 is a block diagram illustrating an implementation of a memory controller according to example embodiments.

[0116] refer to Fig.16 , the memory controller 900 may include a processor 910, a RAM 920, a host interface (I / F) 930, a memory interface (I / F) 940, an ECC circuit 950, and / or a reliability determiner 960. According to an example embodiment, the memory controller 900 may be a device included in an application processor (AP) (not shown) that may be implemented as a system on a chip. The reliability determiner 960 may also include an indicator setter 961, an error region determiner 962, and / or a reliability determination logic 963.

[0117] The processor 910 may include a central processing unit or a microprocessor, and may control all operations of the memory controller 900. For example, the processor 910 may be configured to drive software or firmware for controlling the memory controller 900, wherein the software or firmware may be loaded into the RAM 920 and driven. The RAM 920 may be used as an operating memory, a cache memory, or a buffer memory of the processor 910. In the RAM 920, write data to be written to a memory device may be temporarily stored, and read data read from a memory device may also be temporarily stored.

[0118] The host interface 930 interfaces with the host and receives a request for a memory operation from the host. For example, the host interface 930 may receive various requests for reading and writing data from the host HOST, and in response, generate various internal signals for memory operations of the memory device.

[0119] The memory interface 940 may provide an interface between the memory controller 900 and a memory device (not shown). For example, write data may be sent to the memory device via the memory interface 940 and read data may be received from the memory device via the memory interface 940. In addition, the memory interface 940 may provide commands and addresses to the memory device, and may also receive various information from the memory device and provide it to the memory controller 900.

[0120] The ECC circuit 950 may perform an error detection operation according to the above-described embodiment. For example, the ECC circuit 950 may receive a codeword from a memory module including a plurality of memory chips controlled by the memory controller 900 and perform an error detection operation on the codeword. In addition, the error detection result of the ECC circuit 950 may be provided to the reliability determiner 960.

[0121] The indicator setter 961 can set at least one memory chip among the plurality of memory chips as an indicator chip according to the above-mentioned embodiment, and can also perform an operation for changing the indicator chip. In addition, the error area determiner 962 can determine the memory chip in which an error has occurred based on the error detection result, and the reliability determination logic 963 can determine whether to output reliability degradation information based on the information about the indicator chip and the information about the memory chip in which an error has occurred.

[0122] The various functions that can be performed by the reliability determiner 960 can be implemented in hardware, software, or a combination of hardware and software. For example, when the setting of the indicator chip and the output of the reliability degradation information are implemented in hardware, these functions can be performed by a hardware circuit provided in the reliability determiner 960. Alternatively, when the setting of the indicator chip and the output of the reliability degradation information are implemented in software, a program provided inside or outside the reliability determiner 960 can be loaded into the RAM 920, and the corresponding function can be performed when the processor 910 executes the corresponding program. As described above, Fig.16 The functionality of one or more blocks in the EMBODIMENTS may be implemented as one or more hardware / memory and / or processor / software / memory components.

[0123] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory controller configured to control memory operations of a memory device including a plurality of memory chips, the memory controller comprising: an error correction code (ECC) circuit configured to perform error detection on code words read from the memory device; as well as A processor is configured to perform an initial test operation on the plurality of memory chips, set at least one memory chip with relatively low reliability among the plurality of memory chips as an indicator chip based on a result of performing the initial test operation, monitor error occurrence in the indicator chip based on a result of the error detection, and output reliability degradation information indicating reliability degradation of the memory device based on the monitored error occurrence in the indicator chip.

2. The memory controller according to claim 1, in, The processor is configured to receive lifespan information about the plurality of memory chips from the memory device, and set at least one memory chip having a relatively short lifespan among the plurality of memory chips as the indicator chip.

3. The memory controller according to claim 1, in, The processor is configured to receive a test result on the plurality of memory chips during an initial operation of the memory device, and set at least one memory chip having a relatively large bit error rate among the plurality of memory chips as the indicator chip.

4. The memory controller according to claim 1, in, The memory controller is configured to perform a plurality of dummy programming operations on at least one memory chip of the plurality of memory chips, and The processor is configured to set at least one memory chip on which a dummy program operation is performed as the indicator chip.

5. The memory controller according to claim 1, in, The memory controller is configured to write parity data included in the codeword to the at least one memory chip having relatively low reliability among the plurality of memory chips.

6. The memory controller according to claim 1, in, The processor is configured to output the reliability degradation information when an error occurs in the indicator chip.

7. The memory controller according to claim 1, in, The processor is configured to output the reliability degradation information when an error occurrence frequency in the indicator chip exceeds a predetermined reference value.

8. The memory controller according to claim 1, in, The processor is configured to output the reliability degradation information when an error occurrence frequency of the indicator chip is greater than an error occurrence frequency of other memory chips among the plurality of memory chips by a predetermined ratio.

9. The memory controller according to claim 1, in, The processor is further configured to output first information indicating a location of a memory chip in which an error has occurred among the plurality of memory chips based on a result of the error detection; outputting second information indicating the memory chip set as the indicator chip; as well as An error occurrence in the indicator chip is monitored based on the first information and the second information, and the reliability degradation information is output.

10. The memory controller according to claim 1, in, The processor is configured to set a first memory chip having the lowest reliability among the plurality of memory chips as the indicator chip, and After outputting the reliability degradation information in response to an error in the first memory chip, the processor is further configured to change the indicator chip to a second memory chip having a second lowest reliability among the plurality of memory chips.

11. The memory controller according to claim 1, in, A first memory chip among the plurality of memory chips is provided as the indicator chip, the first memory chip including a plurality of cell blocks, and The processor is configured to set a first cell block among the plurality of cell blocks as an indicator region, and when an error occurs in the first cell block, output the reliability degradation information and change the indicator region to a second cell block among the plurality of cell blocks.

12. A memory system comprising: A memory module including a plurality of memory chips mounted on a module board; as well as a memory controller configured to perform an initial test operation on the plurality of memory chips, control memory operations of the plurality of memory chips of the memory module, and set at least one memory chip having relatively low reliability among the plurality of memory chips as an indicator chip based on a result of performing the initial test operation, and When it is determined that an error has occurred in the indicator chip based on a result of error detection of a code word read from the memory module, reliability degradation information indicating that reliability of the memory module has deteriorated is output.

13. The memory system according to claim 12, in, The memory controller comprises: an error correction code (ECC) circuit configured to perform the error detection on the codeword; and A processor is configured to monitor the indicator chip for an error occurrence.

14. The memory system according to claim 12, in, The memory controller writes parity data included in the codeword into a first memory chip among the plurality of memory chips and sets the first memory chip as the indicator chip.

15. The memory system according to claim 14, in, The memory controller outputs the reliability degradation information when an error occurrence frequency in the first memory chip exceeds a predetermined reference value.

16. The memory system according to claim 12, in, Each of the plurality of memory chips of the memory module includes lifetime information, and The memory controller receives lifespan information about the plurality of memory chips from the memory module, and sets at least one memory chip having a relatively short lifespan among the plurality of memory chips as the indicator chip.

17. The memory system according to claim 12, in, Each of the plurality of memory chips includes a resistance memory cell implemented in a two-dimensional structure or a three-dimensional structure.

18. The memory system according to claim 12, in, The memory module includes a buffer chip, the buffer chip includes an error correction code (ECC) circuit, the error correction code circuit is configured to perform the error detection on the codeword read from the memory module, and The memory controller is configured to determine whether an error has occurred in the indicator chip based on a result of error detection from the buffer chip.

19. A method of operating a memory controller, the memory controller being configured to control memory operations of a memory device including a plurality of memory chips, the method comprising: performing an initial test operation on the plurality of memory chips, setting at least one memory chip having relatively low reliability among the plurality of memory chips as an indicator chip based on a result of performing the initial test operation; monitoring an error occurrence in the indicator chip based on a result of an error detection of a codeword read from the memory device; as well as When an error occurs in the indicator chip, reliability degradation information indicating that reliability of the memory device has been degraded is output.

20. The method according to claim 19, in, When an error occurs in a memory chip other than the indicator chip, the reliability degradation information is not output.

21. The method according to claim 19, in, A first memory chip of the plurality of memory chips stores parity data included in the codeword, and The first memory chip is set as the indicator chip.

22. The method according to claim 19, in, In outputting the reliability degradation information, when the error occurrence frequency in the indicator chip exceeds a predetermined reference value, the reliability degradation information is output.

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