Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device includes the following steps: forming a first sacrificial core on a first region of a lower structure and forming a second sacrificial core on a second region of the lower structure; forming a first spacer on a sidewall of the first sacrificial core and forming a second spacer on a sidewall of the second sacrificial core; forming a protection pattern covering the second spacer and the second sacrificial core on the second region of the lower structure; removing the first sacrificial core from the first region; and etching the lower structure using the first spacer on the first region and the second sacrificial core and the second spacer on the second region.

Description

[0001] Cross-references to related art

[0002] Korean Patent Application No. 10-2018-0137287, titled “Method of Manufacturing a Semiconductor Device,” filed on November 9, 2018, in the Korean Intellectual Property Office is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a method of manufacturing a semiconductor device. Background Art

[0004] As semiconductor devices become increasingly highly integrated, the size of patterns forming these devices is becoming increasingly smaller. Due to the optical resolution limitations of the photolithography equipment used to form these patterns, there are limitations on forming fine patterns. Therefore, methods for forming fine patterns have been proposed. Summary of the Invention

[0005] According to an example embodiment, a method for manufacturing a semiconductor device includes: forming a first sacrificial core on a first region of a lower structure and forming a second sacrificial core on a second region of the lower structure; forming a first spacer on a sidewall of the first sacrificial core and forming a second spacer on a sidewall of the second sacrificial core; forming a protective pattern covering the second spacer and the second sacrificial core on the second region of the lower structure; removing the first sacrificial core from the first region; and etching the lower structure using the first spacer on the first region and the second sacrificial core and the second spacer on the second region.

[0006] According to an example embodiment, a method for manufacturing a semiconductor device includes: preparing a lower structure having a first region, a second region, and a third region; forming a first sacrificial core having a first width on the first region, forming a second sacrificial core having a second width on the second region, and forming a third sacrificial core having a third width greater than the first width and the second width on the third region; forming a first spacer on the first region of the lower structure, forming a first mask structure including the second sacrificial core and the second spacer on the second region of the lower structure, and forming a second mask structure including the third sacrificial core and the third spacer on the third region of the lower structure; and etching the lower structure using the first spacer, the first mask structure, and the second mask structure.

[0007] According to an example embodiment, a method for manufacturing a semiconductor device includes the following steps: stacking a lower sacrificial layer and an upper sacrificial layer on a lower structure having a first region, a second region, and a third region; forming a first upper sacrificial core on the first region and a second upper sacrificial core on the second region by etching the upper sacrificial layer; forming a first spacer on a sidewall of the first upper sacrificial core and a sidewall of the second upper sacrificial core; removing the first upper sacrificial core and the second upper sacrificial core; forming a photoresist pattern having a width wider than that of the first upper sacrificial core on the third region; etching the lower sacrificial layer by using the first spacer and the photoresist pattern as an etching mask to form a first lower sacrificial core on the first region, a second lower sacrificial core on the second region, and a third lower sacrificial core on the third region; forming a second spacer on a sidewall of the first lower sacrificial core, a sidewall of the second lower sacrificial core, and a sidewall of the third lower sacrificial core; forming a protection pattern covering the second region and the third region; removing the first lower sacrificial core formed on the first region; and etching the lower structure using the second spacer on the first region, the second lower sacrificial core and the second spacer on the second region, and the third lower sacrificial core and the second spacer on the third region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 and Figure 2 respectively illustrate a plan view and a cross-sectional view of a semiconductor device manufactured by a method according to example embodiments;

[0010] Figures 3 to 8 cross-sectional views illustrating stages in a method of manufacturing a semiconductor device according to example embodiments;

[0011] Figures 9 to 14 cross-sectional views showing stages in a method of manufacturing a semiconductor device according to example embodiments; and

[0012] Figures 15 to 23 Cross-sectional views illustrating stages in a method of fabricating a semiconductor device according to example embodiments are shown. DETAILED DESCRIPTION

[0013] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0014] Figure 1 and Figure 2 are a plan view and a cross-sectional view illustrating a semiconductor device manufactured by a method of manufacturing a semiconductor device according to example embodiments. Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0015] Reference Figure 1 and Figure 2 The substrate 101 may include a first region R1, a second region R2, and a third region R3. The first region R1 may be a region in which a core transistor having a fin field effect transistor (FinFET) structure is formed. The second region R2 may be a region in which an I / O transistor having a FinFET structure and / or a laterally diffused MOSFET (LDMOS) transistor having a FinFET structure is formed, the I / O transistor and / or the laterally diffused MOSFET transistor using a voltage higher than that of the core transistor. The third region R3 may be a region in which a planar transistor is formed.

[0016] A first active region AT1 extending in one direction may be formed on the first region R1 of the substrate 101, a second active region AT2 extending in one direction may be formed on the second region R2, and at least a single third active region AT3 extending in one direction may be formed on the third region R3. Figure 1 As shown, the first active area AT1, the second active area AT2 and the third active area AT3 may extend in the same direction (eg, along the Y direction). Figure 1 In a different manner as shown, the first active area AT1 , the second active area AT2 , and the third active area AT3 may extend in different directions from each other.

[0017] The first active area AT1 may be a first active fin, and the second active area AT2 may be a second active fin. The first active area AT1 may be arranged at a first pitch Pa, and the second active area AT2 may be arranged at a second pitch Pb greater than the first pitch Pa. The second width Wb of the second active area AT2 may be greater than the first width Wa of the first active area AT1, and the third width Wc of the third active area AT3 may be greater than the second width Wb of the second active area AT2. The second width Wb of the second active area AT2 may be greater than twice the first width Wa of the first active area AT1. The second spacing Sb of the second active area AT2 may be equal to the first spacing Sa of the first active area AT1, or may be greater than the first spacing Sa of the first active area AT1. Figure 1 As shown, the first pitch Pa is equal to the sum of the first width Wa and the first spacing Sa of a single first active area AT1 (i.e., the spacing between two adjacent first active areas AT1), and the second pitch Pb is equal to the sum of the second width Wb and the second spacing Sb of a single second active area AT2 (i.e., the spacing between two adjacent second active areas AT2).

[0018] like Figure 2As shown, a device isolation layer 103 may be formed between adjacent first to third active areas AT1, AT2, and AT3. Upper portions of the first to third active areas AT1, AT2, and AT3 may protrude above the upper surface of the device isolation layer 103. The device isolation layer 103 may cover side surfaces of lower portions of the first to third active areas AT1, AT2, and AT3.

[0019] A first gate structure GS1 may be formed on the first region R1 of the substrate 101, a second gate structure GS2 may be formed on the second region R2, and a third gate structure GS3 may be formed on the third region R3. The first gate structure GS1 may extend in a direction intersecting the first active region AT1, the second gate structure GS2 may extend in a direction intersecting the second active region AT2, and the third gate structure GS3 may extend in a direction intersecting the third active region AT3. For example, the first gate structure GS1, the second gate structure GS2, and the third gate structure GS3 may extend along the X direction.

[0020] The first gate structure GS1 may be arranged at a fourth pitch Pd, and the second gate structure GS2 may be arranged at a fifth pitch Pe that is greater than the fourth pitch Pd. The second width We of the second gate structure GS2 may be greater than the first width Wd of the first gate structure GS1, and the third width Wf of the third gate structure GS3 may be greater than the second width We of the second gate structure GS2. The second width We of the second gate structure GS2 may be greater than twice the first width Wd of the first gate structure GS1. The second spacing Se of the second gate structure GS2 may be equal to the first spacing Sd of the first gate structure GS1, or may be greater than the first spacing Sd of the first gate structure GS1. In example embodiments, the first gate structure GS1 and the second gate structure GS2 may have equal widths and spacings to each other.

[0021] The source / drain regions may be formed on both sides (e.g., opposite sides) of the first, second, and third gate structures GS1, GS2, and GS3 (e.g., each of the first, second, and third gate structures GS1, GS2, and GS3). The source / drain regions may be grown from the first, second, and third active areas AT1, AT2, and AT3 using a selective epitaxial growth (SEG) process, or may be formed in upper regions of the first, second, and third active areas AT1, AT2, and AT3 using an ion implantation process.

[0022] The first gate structure GS1 includes a first gate insulating layer IN1 and a first gate electrode layer GE1, the second gate structure GS2 includes a second gate insulating layer IN2 and a second gate electrode layer GE2, and the third gate structure GS3 includes a third gate insulating layer IN3 and a third gate electrode layer GE3.

[0023] The thickness of the second gate insulating layer IN2 may be greater than that of the first gate insulating layer IN1. The thickness of the third gate insulating layer IN3 may be greater than that of the first gate insulating layer IN1. Each of the first gate insulating layer IN1, the second gate insulating layer IN2, and the third gate insulating layer IN3 may include, for example, silicon oxide, silicon oxynitride, a high-k oxide, or a combination thereof. The high-k oxide may be, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), Hafnium Oxide (HfO2), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ) and praseodymium oxide (Pr2O3).

[0024] Each of the first gate electrode layer GE1, the second gate electrode layer GE2, and the third gate electrode layer GE3 may include, for example, a metal, a metal nitride, doped polysilicon, or a combination thereof. In example embodiments, the first gate electrode layer GE1, the second gate electrode layer GE2, and the third gate electrode layer GE3 may include, for example, at least one of titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), aluminum titanium carbide (TiAlC), tungsten nitride (WCN), and tungsten (W).

[0025] According to example embodiments, since the width of the second active area AT2 of the second region R2 is further increased compared to the width of the first active area AT1 of the first region R1, the reliability of hot carrier immunity (HCI) of an I / O transistor having a FinFET structure or a laterally diffused MOSFET (LDMOS) transistor having a FinFET structure using a voltage higher than that of a core transistor can be improved.

[0026] Figures 3 to 8 are cross-sectional views illustrating stages in a method of manufacturing a semiconductor device according to example embodiments. Figures 3 to 8 The cross-sectional view in Figure 2 Cross-sectional view in .

[0027] Reference Figure 3 , on the substrate 101, a hard mask layer 115, a sacrificial layer 121 and an anti-reflective layer 125 may be formed in sequence.

[0028] The substrate 101 may include a first region R1, a second region R2, and a third region R3. The first region R1 may be a region in which a core transistor having a FinFET structure is formed. The second region R2 may be a region in which an I / O transistor having a FinFET structure that utilizes a higher voltage than the core transistor or a laterally diffused MOSFET (LDMOS) transistor having a FinFET structure is formed. The third region R3 may be a region in which a planar transistor is formed.

[0029] The substrate 101 may be a semiconductor substrate, such as a silicon wafer, or a silicon-on-insulator (SOI) substrate.

[0030] The hard mask layer 115 may be made of a silicon-containing material (eg, silicon oxide (SiO x ), silicon oxynitride (SiON), silicon nitride (Si x N y ) or polysilicon), a carbon-containing material (eg, an amorphous carbon layer (ACL) or a spin-on hard mask (SOH)), and at least one of a metal. For example, the hard mask layer 115 may include multiple layers.

[0031] The sacrificial layer 121 may include, for example, at least one of polysilicon, an amorphous carbon layer (ACL), and a spin-on hard mask (SOH). The sacrificial layer 121 may be between the hard mask layer 115 and the anti-reflective layer 125.

[0032] The anti-reflection layer 125 may be at least one layer for preventing light reflection during a photolithography process. The anti-reflection layer 125 may be formed of, for example, a silicon oxynitride (SiON) film.

[0033] The hard mask layer 115 , the sacrificial layer 121 , and the anti-reflective layer 125 may be formed using, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), spin coating, etc. A baking process or a curing process may be additionally performed depending on the material.

[0034] Then, a photoresist may be formed on the anti-reflection layer 125. A photoresist pattern 180, for example, in the form of lines spaced apart from each other, may be formed on the anti-reflection layer 125 using a photolithography process.

[0035] The first pattern of the photoresist pattern 180 may be formed on the first region R1 to have a first spacing S1 therebetween while having a first width W1. The first pattern of the photoresist pattern 180 may be formed on the first region R1 at a first pitch P1. The first pitch P1 may be defined as the sum of the first width W1 and the first spacing S1.

[0036] The second pattern of the photoresist pattern 180 may be formed on the second region R2 with a second spacing S2 therebetween and a second width W2. The second pattern of the photoresist pattern 180 may be formed on the second region R2 with a second pitch P2. The second pitch P2 may be defined as the sum of the second width W2 and the second spacing S2. The second width W2 may be different from the first width W1. The second spacing S2 may be different from the first spacing S1.

[0037] The third pattern of the photoresist pattern 180 may be formed on the third region R3 while having a third width W3. Figure 8 The first width W1 is determined by the spacing Sa between the first active regions AT1 to be formed. The spacing Sa between the first active regions AT1 to be formed can be narrower than the resolution limit of existing photolithography equipment on the market.

[0038] Reference Figure 4 , the anti-reflective layer 125 and the sacrificial layer 121 may be anisotropically etched using the photoresist pattern 180 as an etching mask. Thus, a first sacrificial core SC1 may be formed on the first region R1, a second sacrificial core SC2 may be formed on the second region R2, and a third sacrificial core SC3 may be formed on the third region R3. The first sacrificial core SC1 may be formed on the first region R1 with a first width W1 and a first spacing S1 therebetween, i.e., a first pitch P1. The second sacrificial core SC2 may be formed on the second region R2 with a second width W2 and a second spacing S2 therebetween, i.e., a second pitch P2. The third sacrificial core SC3 may have a third width W3 on the third region R3. The third width W3 of the third sacrificial core SC3 may be greater than each of the first width W1 of the first sacrificial core SC1 and the second width W2 of the second sacrificial core SC2.

[0039] Reference Figure 5 , spacers 150 may be formed on the sidewalls of the first sacrificial core SC1, the sidewalls of the second sacrificial core SC2, and the sidewalls of the third sacrificial core SC3. Thus, a first mask structure SM1 may be formed on the first region R1, a second mask structure SM2 may be formed on the second region R2, and a third mask structure SM3 may be formed on the third region R3. Each of the first mask structure SM1, the second mask structure SM2, and the third mask structure SM3 may include a lower sacrificial layer 121, a lower anti-reflective layer 125, and a pair of spacers 150.

[0040] In detail, a spacer material layer may be formed to conformally cover the first, second, and third sacrificial cores SC1, SC2, and SC3. An etch-back process may then be performed to form spacers 150 on opposing sidewalls of each of the first, second, and third sacrificial cores SC1, SC2, and SC3.

[0041] It can be considered that the first active area (AT1, see Figure 8 The thickness of the spacer material layer is determined based on the width Wa of the first active region AT1, that is, the thickness of the spacer 150. The width Wa of the first active region AT1 to be formed can be narrower than the resolution limit of existing photolithography equipment on the market.

[0042] The spacer material layer may be formed of a material having an etch selectivity relative to the material of the sacrificial layer 121. For example, when the sacrificial layer 121 is formed of one of polysilicon, an amorphous carbon layer (ACL), and a spin-on hard mask (SOH), the spacer material layer may be formed of silicon oxide or silicon nitride. The spacer material layer may be formed using atomic layer deposition (ALD).

[0043] Reference Figure 6 A protection pattern 182 covering the second region R2 and the third region R3 may be provided. The protection pattern 182 may be formed of, for example, a photoresist material. The protection pattern 182 covers the second mask structure SM2 of the second region R2 and the third mask structure SM3 of the third region R3, so that the first mask structure SM1 may be exposed on the first region R1.

[0044] Next, the first sacrificial core SC1 may be removed from the exposed first region R1 so that the spacers 150 may remain on the hard mask layer 115 of the first region R1. The spacers 150 may be arranged on the first region R1 to be spaced apart from each other by a distance equal to the first width W1 of the first sacrificial core SC1.

[0045] Reference Figure 7 , the protective pattern 182 may be removed. Then, the hard mask layer 115 may be anisotropically etched using the spacer 150 on the first region R1, the second mask structure SM2 on the second region R2, and the third mask structure SM3 on the third region R3 as etching masks. While the hard mask layer 115 may be anisotropically etched, a portion or all of the spacer 150, the second mask structure SM2, and the third mask structure SM3 may be consumed.

[0046] Reference Figure 8The substrate 101 can be anisotropically etched using the patterned hard mask layer 115 as an etch mask to form a first active area AT1 on the first region R1 of the substrate 101, a second active area AT2 on the second region R2, and a third active area AT3 on the third region R3. The first active area AT1 can be a first active fin, while the second active area AT2 can be a second active fin. The second width Wb of the second active area AT2 can be greater than the first width Wa of the first active area AT1, and the third width Wc of the third active area AT3 can be greater than the second width Wb of the second active area AT2. The second width Wb of the second active area AT2 can be greater than twice the first width Wa of the first active area AT1. The second spacing Sb of the second active areas AT2 can be equal to or greater than the first spacing Sa of the first active areas AT1.

[0047] In example embodiments, when the first width W1 of the first sacrificial core SC1 may be equal to the second width W2 of the second sacrificial core SC2, and the width Ws of the spacer 150 may be equal to the first width W1 of the first sacrificial core SC1, the second width Wb of the second active area AT2 may be equal to three times the first width Wa of the first active area AT1. In other words, referring to Figures 7 and 8 , the second width Wb of each of the second active areas AT2 ( Figure 8 ) may be equal to the second width W2 of the second sacrificial core SC2 and the second sacrificial core SC2 ( Figure 7 ) on the sidewall of the two spacers 150 of the sum of the two widths Ws ( Figure 7 ).

[0048] After the anisotropic etching of the substrate 101 is completed, a portion of the hard mask layer 115 may remain on the first to third active areas AT1, AT2, and AT3. A device isolation layer 103 may be formed to allow the upper portions of the first to third active areas AT1, AT2, and AT3 to protrude. Specifically, the space between adjacent first to third active areas AT1, AT2, and AT3 may be filled with the device isolation layer 103. The hard mask layer 115 remaining on the first to third active areas AT1, AT2, and AT3 may be removed, and then a portion of the device isolation layer 103 may be etched to a predetermined depth to allow the upper portions of the first to third active areas AT1, AT2, and AT3 to protrude.

[0049] According to example embodiments, first to third active regions AT1, AT2, and AT3 having different widths may be simultaneously formed in first to third regions R1, R2, and R3, and the width of second active region AT2 may be increased in second region R2 in which an I / O transistor having a FinFET structure or a lateral diffused MOSFET (LDMOS) transistor having a FinFET structure that utilizes a higher voltage than a core transistor is formed. Consequently, the reliability of hot carrier immunity (HCI) of the I / O transistor or the lateral diffused MOSFET (LDMOS) transistor may be improved.

[0050] Figures 9 to 14 are cross-sectional views illustrating stages in a method of manufacturing a semiconductor device according to example embodiments. Figures 9 to 14 The cross-sectional view in Figure 2 sectional view of .

[0051] Reference Figure 9 On the substrate 101, a gate insulating layer 111, a gate conductive layer 113, a hard mask layer 116, a sacrificial layer 121, and an anti-reflective layer 125 may be sequentially formed. Then, a photoresist may be formed on the sacrificial layer 121, and then a photoresist pattern 184 may be formed in the form of lines using a photolithography process.

[0052] The first pattern of the photoresist pattern 184 may be formed on the first region R1, with a fourth spacing S4 therebetween, and with a fourth width W4. The first pattern of the photoresist pattern 184 may be formed on the first region R1 with a fourth pitch P4. The second pattern of the photoresist pattern 184 may be formed on the second region R2, with a fifth spacing S5 therebetween, and with a fifth width W5. The second pattern of the photoresist pattern 184 may be formed on the second region R2 with a fifth pitch P5. The fifth width W5 may be different from the fourth width W4. The fifth spacing S5 may be different from the fourth spacing S4. The third pattern of the photoresist pattern 184 may be formed on the third region R3, and have a sixth width W6. It may be considered that the first gate pattern (GT1, see Figure 14 The fourth width W4 is determined by the spacing Sd between the first gate patterns GT1 to be formed. The spacing Sd between the first gate patterns GT1 to be formed can be narrower than the resolution limit of existing photolithography equipment on the market.

[0053] Reference Figure 10The anti-reflective layer 125 and the sacrificial layer 121 may be anisotropically etched using the third photoresist pattern 184 as an etching mask to form a fourth sacrificial core SC4 on the first region R1, a fifth sacrificial core SC5 on the second region R2, and a sixth sacrificial core SC6 on the third region R3. The fourth sacrificial core SC4 may be formed on the first region R1 with a fourth width W4 and a fourth spacing S4 (i.e., a fourth pitch P4). The fifth sacrificial core SC5 may be formed on the second region R2 with a fifth width W5 and a fifth spacing S5 (i.e., a fifth pitch P5). The sixth sacrificial core SC6 may have a sixth width W6 on the third region R3. The sixth width W6 of the sixth sacrificial core SC6 may be greater than the fourth width W4 of the fourth sacrificial core SC4 and the fifth width W5 of the fifth sacrificial core SC5.

[0054] Reference Figure 11 , spacers 150 may be formed on the sidewalls of the fourth sacrificial core SC4, the sidewalls of the fifth sacrificial core SC5, and the sidewalls of the sixth sacrificial core SC6. Thus, a fourth mask structure SM4 may be formed on the first region R1, a fifth mask structure SM5 may be formed on the second region R2, and a sixth mask structure SM6 may be formed on the third region R3. Each of the fourth mask structure SM4, the fifth mask structure SM5, and the sixth mask structure SM6 may include a sacrificial layer 121, an anti-reflective layer 125, and the pair of spacers 150.

[0055] In detail, a spacer material layer may be formed to conformally cover the fourth, fifth, and sixth sacrificial cores SC4, SC5, and SC6. An etch-back process may then be performed to form spacers 150 on sidewalls of the fourth, fifth, and sixth sacrificial cores SC4, SC5, and SC6.

[0056] Considering the first gate pattern (GT1, see Figure 14 The thickness of the spacer material layer is determined based on the width Wd of the first gate patterns GT1, that is, the thickness of the spacer 150. The width Wd between the first gate patterns GT1 to be formed may be narrower than the resolution limit of existing photolithography equipment on the market.

[0057] Reference Figure 12 , a protection pattern 186 covering the second region R2 and the third region R3 may be provided. The protection pattern 186 may be formed of, for example, a photoresist material. The protection pattern 186 covers the fifth mask structure SM5 of the second region R2 and the sixth mask structure SM6 of the third region R3, and exposes the fourth mask structure SM4.

[0058] By removing the fourth sacrificial core SC4, the spacers 150 remaining on the hard mask layer 115 of the first region R1 may be provided. The spacers 150 may be arranged at a pitch equal to the fourth width W4 of the fourth sacrificial core SC4.

[0059] Reference Figure 13 The hard mask layer 116 may be anisotropically etched using the spacer 150 on the first region R1, the fifth mask structure SM5 on the second region R2, and the sixth mask structure SM6 on the third region R3 as etching masks. While the hard mask layer 116 may be anisotropically etched, a portion or all of the spacer 150, the fifth mask structure SM5, and the sixth mask structure SM6 may be consumed.

[0060] Reference Figure 14 The gate conductive layer 113 and the gate insulating layer 111 can be anisotropically etched using the patterned hard mask layer 116 as an etching mask to form a first gate pattern GT1 on the first region R1 of the substrate 101, a second gate pattern GT2 on the second region R2, and a third gate pattern GT3 on the third region R3. The second width We of the second gate pattern GT2 can be greater than the first width Wd of the first gate pattern GT1, and the third width Wf of the third gate pattern GT3 can be greater than the second width We of the second gate pattern GT2. The second width We of the second gate pattern GT2 can be greater than twice the first width Wd of the first gate pattern GT1. The second spacing Se of the second gate pattern GT2 can be equal to the first spacing Sd of the first gate pattern GT1, or can be greater than the first spacing Sd of the first gate pattern GT1.

[0061] According to example embodiments, first to third gate patterns GT1, GT2, and GT3 having different widths may be simultaneously formed in the first to third regions R1, R2, and R3. The first to third gate patterns GT1, GT2, and GT3 may be replaced by gate replacement processing. Figure 1 and Figure 2 The first to third gate structures GS1, GS2 and GS3.

[0062] Figures 15 to 23 are cross-sectional views illustrating stages in a method of manufacturing a semiconductor device according to example embodiments. Figures 15 to 23 The cross-sectional view in Figure 2 sectional view of .

[0063] Reference Figure 15 , on the substrate 101 , a hard mask layer 115 , a sacrificial layer 121 , an anti-reflective layer 125 , an upper sacrificial layer 141 , and an upper anti-reflective layer 145 may be formed in sequence.

[0064] The substrate 101 may be a semiconductor substrate, such as a silicon wafer, or a silicon-on-insulator (SOI) substrate.

[0065] The hard mask layer 115 may be made of a silicon-containing material (eg, silicon oxide (SiO x), silicon oxynitride (SiON), silicon nitride (Si x N y ) or polysilicon), a carbon-containing material (eg, an amorphous carbon layer (ACL) or a spin-on hard mask (SOH)), and at least one of a metal. For example, the hard mask layer 115 may include multiple layers.

[0066] Each of the sacrificial layer 121 and the upper sacrificial layer 141 may include, for example, at least one of polysilicon, an amorphous carbon layer (ACL), and a spin-on hard mask (SOH).

[0067] The anti-reflection layer 125 and the upper anti-reflection layer 145 may be layers for preventing light reflection during a photolithography process. The anti-reflection layer 125 and the upper anti-reflection layer 145 may be formed of, for example, a silicon oxynitride (SiON) film.

[0068] The hard mask layer 115, the sacrificial layers 121 and 141, and the anti-reflective layers 125 and 145 may be formed using, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), spin coating, etc. A baking process or a curing process may be additionally performed depending on the material. A photoresist may then be formed on the upper sacrificial layer 141, and a first photoresist pattern 190 in the form of lines may then be formed using a photolithography process.

[0069] The substrate 101 may include a first region R1′, a second region R2′, and a third region R3′. The first region R1′ may be a region where a core transistor is formed, the second region R2′ may be a region where an I / O transistor or a laterally diffused MOSFET (LDMOS) transistor utilizing a higher voltage than the core transistor is formed, and the third region R3′ may be a region where a planar transistor is formed.

[0070] The first pattern of the first photoresist pattern 190 may be formed on the first region R1' at a first spacing S11 and have a first width W11. The first pattern of the first photoresist pattern 190 may be formed on the first region R1' at a first pitch P11. The first pitch P11 may be defined as the sum of the first width W11 and the first spacing S11. The second pattern of the first photoresist pattern 190 may be formed on the second region R2' at a second spacing S12 and have a second width W12. The second pattern of the first photoresist pattern 190 may be formed on the second region R2' at a second pitch P12. The second pitch P12 may be defined as the sum of the second width W12 and the second spacing S12. The second width W12 may be different from the first width W11. The second spacing S12 may be different from the first spacing S11.

[0071] Reference Figure 16The upper anti-reflective layer 145 and the upper sacrificial layer 141 may be anisotropically etched using the first photoresist pattern 190 as an etching mask to form a first upper sacrificial core SC1' on the first region R1' and a second upper sacrificial core SC2' on the second region R2'. The first upper sacrificial core SC1' may be formed on the first region R1' with a first width W11 and a first spacing S11 (i.e., a first pitch P11). The second upper sacrificial core SC2' may be formed on the second region R2' with a second width W12 and a second spacing S12 (i.e., a second pitch P12).

[0072] Reference Figure 17 , first spacers 155 may be disposed on sidewalls of the first and second upper sacrificial cores SC1' and SC2'. Specifically, a first spacer material layer may be formed conformally covering the first and second upper sacrificial cores SC1' and SC2', and then an etch-back process may be performed to form the first spacers 155 on the sidewalls of the first and second upper sacrificial cores SC1' and SC2'.

[0073] It can be considered that the first active area (AT1', see Figure 23 The thickness of the first spacer material layer is determined by the spacing Sa' between the first active areas AT1' to be formed. The spacing Sa' between the first active areas AT1' to be formed can be narrower than the resolution limit of existing photolithography equipment on the market.

[0074] The first spacer material layer may be formed of a material having an etch selectivity relative to the material of the upper sacrificial layer 141. For example, when the upper sacrificial layer 141 may be formed of, for example, polysilicon, an amorphous carbon layer (ACL), and a spin-on hard mask (SOH), the first spacer material layer may be formed of, for example, silicon oxide or silicon nitride. The first spacer material layer may be formed using atomic layer deposition (ALD).

[0075] Reference Figure 18 The first upper sacrificial core SC1' and the second upper sacrificial core SC2' may be selectively removed relative to the first spacer 155, thereby providing the first spacer 155 remaining solely on the sacrificial layer 121. Furthermore, a second photoresist pattern 192 having a third width W13 wider than the first width W11 of the first upper sacrificial core SC1' may be formed on the third region R3'. The third width W13 of the second photoresist pattern 192 may ultimately determine the width Wc' of the third active region AT3'. In this regard, the width W13 of the second photoresist pattern 192 may be adjusted, thereby freely adjusting the width Wc' of the third active region AT3'.

[0076] Reference Figure 19, a first lower sacrificial core SC1″ may be formed on the first region R1′, a second lower sacrificial core SC2″ may be formed on the second region R2′, and a third lower sacrificial core SC3″ may be formed on the third region R3′. The anti-reflective layer 125 and the sacrificial layer 121 may be etched using the first spacer 155 and the second photoresist pattern 192 as etching masks. Therefore, on the hard mask layer 115, a first lower sacrificial core SC1″, a second lower sacrificial core SC2″, and a third lower sacrificial core SC3″ may be formed. The first lower sacrificial core SC1″ and the second lower sacrificial core SC2″ may be formed at positions corresponding to the position of the first spacer 155, and the third lower sacrificial core SC3″ may be formed at positions corresponding to the position of the second photoresist pattern 192.

[0077] The first lower sacrificial core SC1” may be formed on the first region R1’ at a fourth spacing S1’ while having a fourth width W1’. The first lower sacrificial core SC1” may be formed at a fourth pitch P1’. The second lower sacrificial core SC2” may be formed on the second region R2’ at a fifth spacing S2’ while having a fifth width W2’. The second lower sacrificial core SC2” may be formed at a fifth pitch P2’. The third lower sacrificial core SC3” may have a sixth width W3’ greater than the fourth width W1’ and the fifth width W2’.

[0078] Reference Figure 20 , a second spacer 150 may be formed on the sidewalls of the first lower sacrificial core SC1”, the sidewalls of the second lower sacrificial core SC2”, and the sidewalls of the third lower sacrificial core SC3”. Therefore, a first mask structure SM1’ may be formed on the first region R1’, a second mask structure SM2’ may be formed on the second region R2’, and a third mask structure SM3’ may be formed on the third region R3’. Each of the first mask structure SM1’, the second mask structure SM2’, and the third mask structure SM3’ may include a lower sacrificial layer 121, a lower anti-reflection layer 125, and a pair of second spacers 150.

[0079] In detail, a second spacer material layer may be formed conformally covering the first lower sacrificial core SC1”, the second lower sacrificial core SC2”, and the third lower sacrificial core SC3”, and then an etch-back process may be performed to form a second spacer 150 on the sidewalls of the first lower sacrificial core SC1”, the sidewalls of the second lower sacrificial core SC2”, and the sidewalls of the third lower sacrificial core SC3”.

[0080] It can be considered that the first active area (AT1', see Figure 23 The thickness of the second spacer material layer is determined by the width Wa' of the first active region AT1', that is, the width Ws' of the second spacer 150. The width Wa' of the first active region AT1' to be formed can be smaller than the resolution limit of existing photolithography equipment on the market.

[0081] The second spacer material layer may be formed of a material having an etch selectivity relative to the material of the sacrificial layer 121. For example, when the sacrificial layer 121 may be formed of one of polysilicon, an amorphous carbon layer (ACL), and a spin-on hard mask (SOH), the second spacer material layer may be formed of silicon oxide or silicon nitride. The second spacer material layer may be formed using atomic layer deposition (ALD).

[0082] Reference Figure 21 A protection pattern 194 covering the second region R2' and the third region R3' may be provided. The protection pattern 194 may be formed of, for example, a photoresist material. The protection pattern 194 covers the second mask structure SM2' of the second region R2' and the third mask structure SM3' of the third region R3', and exposes the first mask structure SM1'.

[0083] By removing the first lower sacrificial core SC1 ″, second spacers 150 may be provided remaining on the hard mask layer 115 of the first region R1 ′. The second spacers 150 may be arranged at a pitch equal to the fourth width W1 ′ of the first lower sacrificial core SC1 ″.

[0084] Reference Figure 22 The hard mask layer 115 may be anisotropically etched using the second spacers 150 on the first region R1', the second mask structure SM2' on the second region R2', and the third mask structure SM3' on the third region R3' as etching masks. While the hard mask layer 115 may be anisotropically etched, a portion or all of the second spacers 150, the second mask structure SM2', and the third mask structure SM3' may be consumed.

[0085] Reference Figure 23 The substrate 101 may be anisotropically etched using the patterned hard mask layer 115 as an etching mask to form a first active area AT1′ on the first region R1′, a second active area AT2′ on the second region R2′, and a third active area AT3′ on the third region R3′ of the substrate 101. After the anisotropic etching of the substrate 101 is completed, a portion of the hard mask layer 115 may remain on the first to third active areas AT1′, AT2′, and AT3′.

[0086] The device isolation layer 103 may be formed to allow the upper portions of the first to third active regions AT1', AT2', and AT3' to protrude. Specifically, the spaces between the first to third active regions AT1', AT2', and AT3' may be filled with the device isolation layer 103. The hard mask layer 115 remaining on the first to third active regions AT1', AT2', and AT3' may be removed, and then a portion of the device isolation layer 103 may be etched to a predetermined depth to allow the upper portions of the first to third active regions AT1', AT2', and AT3' to protrude.

[0087] In summary and review, example embodiments provide a method for manufacturing a semiconductor device capable of forming fine patterns having different widths. That is, according to example embodiments, a semiconductor device including fine patterns (e.g., active regions and gate patterns) having different widths (e.g., a semiconductor device including active fins located in a region where an I / O transistor or a lateral diffused MOSFET (LDMOS) can be formed that are wider than active fins in a region where a core transistor can be formed) can be manufactured without removing a mandrel. In other words, fine patterns having different widths can be formed simultaneously using the same mandrel (i.e., by utilizing spacers formed on the sides of the mandrel as a mask for the wider pattern). Therefore, a single mandrel and two spacers on its sidewalls can be used as an etching mask for a dry etching process, thereby improving the manufacturing process and providing a semiconductor device with excellent reliability.

[0088] Example embodiments are disclosed herein, and although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, unless otherwise indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a first sacrificial core on the first region of the lower structure and forming a second sacrificial core on the second region of the lower structure, wherein the first sacrificial core and the second sacrificial core have the same width; forming a first spacer on a sidewall of the first sacrificial core and forming a second spacer on a sidewall of the second sacrificial core; forming a protection pattern covering the second spacer and the second sacrificial core located on the second region of the lower structure; removing the first sacrificial core from the first region; as well as The lower structure is etched using a first spacer on the first region and a second sacrificial core and a second spacer on the second region to form a first active region having a first width in the first region and a second active region having a second width in the second region, wherein the second width is greater than the first width.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The lower structure includes a semiconductor substrate.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The second width is greater than twice the first width.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The lower structure includes a gate conductive layer, and The step of etching the lower structure comprises: forming a first gate pattern having a third width in the first region, and A second gate pattern having a fourth width greater than the third width is formed in the second region.

5. The method for manufacturing a semiconductor device according to claim 4, wherein The fourth width is greater than twice the third width.

6. The method for manufacturing a semiconductor device according to claim 1, wherein A width of each of the first spacer and the second spacer is equal to a width of the first sacrificial core.

7. The method for manufacturing a semiconductor device according to claim 1, wherein The forming of the first and second sacrificial cores includes forming a third sacrificial core on a third region of the lower structure such that a width of the third sacrificial core is wider than each of a width of the first and second sacrificial cores.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The step of forming the first spacer on the sidewall of the first sacrificial core and forming the second spacer on the sidewall of the second sacrificial core includes forming a third spacer on the sidewall of the third sacrificial core.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The step of forming a protection pattern covering the second spacer and the second sacrificial core located on the second region of the lower structure includes forming a protection pattern covering the third spacer and the third sacrificial core located on the third region.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The step of etching the lower structure includes etching the lower structure using a first spacer on the first region, a second sacrificial core and a second spacer on the second region, and a third sacrificial core and a third spacer on the third region.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The lower structure includes a semiconductor substrate, and The step of etching the lower structure comprises: A third active region having a third width greater than the second width is formed in the third region.

12. The method for manufacturing a semiconductor device according to claim 10, wherein: The lower structure includes a gate conductive layer, and The step of etching the lower structure comprises: forming a first gate pattern having a fourth width in the first region, forming a second gate pattern having a fifth width greater than the fourth width in the second region, and A third gate pattern having a sixth width greater than the fifth width is formed in the third region.

13. A method for manufacturing a semiconductor device, the method comprising the steps of: preparing a lower structure having a first region, a second region, and a third region; forming a first sacrificial core having a first width on the first region, forming a second sacrificial core having a second width on the second region, and forming a third sacrificial core having a third width greater than the first width and the second width on the third region, the first width being equal to the second width; forming a first spacer on the first region of the lower structure, forming a first mask structure including the second sacrificial core and the second spacer on the second region of the lower structure, and forming a second mask structure including the third sacrificial core and the third spacer on the third region of the lower structure; as well as etching the lower structure using the first spacer, the first mask structure, and the second mask structure to form a first active region in the first region and a second active region wider than the first active region in the second region, The steps of forming the first spacer, the first mask structure and the second mask structure include: forming the first spacer on the sidewall of the first sacrificial core, forming the second spacer on the sidewall of the second sacrificial core, and forming the third spacer on the sidewall of the third sacrificial core; forming a protection pattern covering the first mask structure on the second area and the second mask structure on the third area; removing the first sacrificial core from the first region; and The protective pattern is removed.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The lower structure includes a semiconductor substrate, The first active regions have a pitch equal to the first width and have a width equal to a width of the first spacer, The second active region has a pitch equal to the second width and has a width greater than a width of the first active region, and The step of etching the lower structure further comprises: A third active region is formed, wherein the width of the third active region is greater than the width of the second active region.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: A width of each of the first spacer, the second spacer, and the third spacer is equal to the first width.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The lower structure includes a semiconductor substrate, The first active region has the first width, The width of the second active region is equal to three times the first width, and The step of etching the lower structure further comprises: A third active region is formed in the third area, and a width of the third active region is greater than a width of the second active region.

17. A method for manufacturing a semiconductor device, the method comprising the steps of: stacking a lower sacrificial layer and an upper sacrificial layer on the lower structure having the first region, the second region, and the third region; forming a first upper sacrificial core on the first region and forming a second upper sacrificial core on the second region by etching the upper sacrificial layer; forming first spacers on sidewalls of the first upper sacrificial core and sidewalls of the second upper sacrificial core; removing the first upper sacrificial core and the second upper sacrificial core; forming a photoresist pattern on the third region, the photoresist pattern having a width wider than that of the first upper sacrificial core; forming a first lower sacrificial core on the first region, a second lower sacrificial core on the second region, and a third lower sacrificial core on the third region by etching the lower sacrificial layer using the first spacer and the photoresist pattern as an etching mask; forming second spacers on sidewalls of the first lower sacrificial core, sidewalls of the second lower sacrificial core, and sidewalls of the third lower sacrificial core; forming a protection pattern covering the second region and the third region; removing a first lower sacrificial core formed on the first region; as well as The lower structure is etched using the second spacer on the first region, the second lower sacrificial core and the second spacer on the second region, and the third lower sacrificial core and the second spacer on the third region.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: The lower structure includes a semiconductor substrate, and The step of etching the lower structure comprises: forming a first active region having a first width in the first region, forming a second active region having a second width greater than the first width in the second region, and A third active region having a third width greater than the second width is formed in the third region.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The second width is greater than twice the first width.

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